JP2008084499A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which two kind of data regions for high speed access and for large capacity are set in one chip. <P>SOLUTION: The device is the semiconductor memory device constituted by arranging NAND strings in which a plurality of electrically rewritable non-volatile memory cells are connected in series, the device has a first data region and a second data region which has smaller capacity than that of the first data region and achieves high speed random access. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device in which two types of data areas for high-speed access and large-capacity storage are set.

  The demand for NAND flash memory is increasing as the use of large-capacity data such as images and moving images increases in mobile devices. A recent flash memory can store more information with a small chip area by a multi-value technology capable of storing 2-bit information in one memory cell.

  The NAND flash memory has a cell current that is one tenth of that of the NOR type, and is not suitable for high-speed random access. For this reason, the data transfer rate is increased by reading the data into the buffer and outputting it serially, so that it can be adapted to a high-speed system via a buffer memory such as a DRAM.

  In the conventional NAND flash memory, cell information is read by selectively causing inversion of the latch depending on whether or not the charge in the sense amplifier / latch is discharged by turning the cell on / off. For this reason, it takes time in microseconds to access and read the memory cell.

  Further, in the multi-value technique, the word line voltage at the time of reading cannot be sufficiently increased with respect to the threshold value of the memory cell, so that the memory cell current is only about several hundred nA. In order to improve the reading performance of the NAND flash memory, it is necessary to sense a small current at high speed.

  As a sense amplifier that senses a minute cell current at high speed, a latch-type current detection sense amplifier that differentially amplifies a difference between cell currents of a memory cell and a reference cell has been proposed (see Patent Document 1).

  Currently, portable devices have a configuration in which program data such as OS is stored in a NOR flash memory capable of high-speed random access, and large-capacity file data such as images and music data is stored in a NAND flash memory. I'm taking it. Since a program such as an OS is not frequently rewritten, a NOR flash memory having a slow writing speed is used as a ROM. However, since random access is fast, it is directly connected to a CPU and directly executes code.

  For large-capacity file data such as images and music data, a NAND flash memory capable of high-speed writing is suitable. However, since random access of the NAND flash memory takes about 20 μs, it is impossible to execute a code by directly connecting to the CPU.

  Therefore, when code data is stored in the NAND flash memory, the data is once copied to a memory such as a DRAM and the code is executed therefrom. The NAND flash memory control unit performs data input / output transfer, converts the logical address specified from the outside into the physical address of the memory, encodes the data read from the memory by the ECC circuit, and generates an error. It has a function to make corrections.

  However, the two-chip configuration of the NOR flash memory and the NAND flash memory increases the cost and leads to an increase in mounting area. Therefore, it is desired that high-speed random access is possible in one chip and that a large amount of data can be stored.

  Normally, the NAND flash memory performs sequential access using a sector of a predetermined bit as an access unit. For this reason, the NAND flash memory cannot cope with random access to the memory required when the CPU executes a program such as an OS. When using a NAND flash memory instead of the NOR flash memory, it is necessary to transfer a program such as an OS stored in the NAND flash memory to the DRAM once, and then execute the program.

  In order to realize the system configuration as described above, a boot ROM with a small capacity such as a mask ROM or a NOR flash memory is provided, and a program stored in the NAND flash memory is transferred to the DRAM for execution. It is necessary to store software for performing preprocessing necessary for the boot ROM (see, for example, Patent Document 2).

In general, the cost of the boot ROM becomes lower as the memory capacity is smaller, so the software stored in the boot ROM is limited to the minimum necessary. In many cases, the boot ROM stores only an instruction code for initial setting of the external bus control unit and the memory control unit, and an instruction code for transferring a program stored in the NAND flash memory to the DRAM.
JP 2005-285161 A Japanese Patent Laid-Open No. 2005-10942

  An object of the present invention is to provide a semiconductor memory device in which two types of data areas for high-speed access and large-capacity storage are set in one chip.

A semiconductor memory device according to an aspect of the present invention is a semiconductor memory device configured by arranging NAND strings in which a plurality of electrically rewritable nonvolatile memory cells are connected in series,
A first data area;
And a second data area having a small capacity and capable of high-speed random access as compared with the first data area.

  According to the present invention, it is possible to provide a semiconductor memory device in which two types of data areas for high-speed access and large-capacity storage are set in one chip.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a schematic memory chip layout of a NAND flash memory according to an embodiment. This memory chip has a bank RNA-BNK that can be randomly accessed and a bank SQA-BNK that performs sequential access for storing large amounts of data.

  That is, the central portion of the chip is the peripheral circuit region 3, and the banks for high-speed random access RNA-BNK0 and RNA-BNK1 are arranged with this therebetween. Furthermore, sequential access banks SQA-BNK0 and SQA-BNK1, which are sequentially accessed using the center as an access unit, are arranged outside these.

  Each of the random access banks RNA-BNK0 and RNA-BNK1 is composed of two cell arrays 1c and 1d arranged with a sense unit (SU01, SU11) 2 interposed therebetween, and is used as an area for storing a program such as an OS. It is done.

  Each of the sequential access banks SQA-BNK0 and SQA-BNK1 is composed of two cell arrays 1a and 1b arranged with a sense unit (SU00, SU10) 2 interposed therebetween. For example, file data such as music and image data is stored. Used as a storage area.

  Each of the cell arrays 1a, 1b, 1c, and 1d includes a large number of information cell NAND strings and at least one reference cell NAND string. In the sequential access banks SQA-BNK0 and SQA-BNK1, when one information cell NAND string of the cell arrays 1a and 1b is selected, the other reference cell NAND string is selected, and the information cell and the reference cell Data sensing is performed by the sense unit on the basis of the cell current difference.

  Similarly, in the random access banks RNA-BNK0 and RNA-BNK1, when one information cell NAND string of the cell arrays 1c and 1d is selected, the other reference cell NAND string is selected and the information cell and the reference cell are selected. The data is sensed by the sense unit based on the cell current difference between

  In the random access banks RNA-BNK0 and RNA-BNK1, one cell array is 32 Mb, and a total of 128 Mb random access banks is configured by arranging four cell arrays. The sequential access banks SQA-BNK0 and SQA-BNK1 each have a single cell array of 256 Mb, and by arranging four cell arrays, a 1 Gb sequential access bank is configured.

  The row decoders 4 that selectively drive the word lines are distributed at both ends of the word lines of each cell array. That is, (RDEC00, RDEC01) and (RDEC02, RDEC03) are assigned to the cell arrays 1c and 1d of the random access bank RNA-BNK0 as row decoders 4 for the cell arrays 1a and 1b of one sequential access bank SQA-BNK0, respectively. Thus, (RDEC04, RDEC05) and (RDEC06, RDEC07) are arranged as the row decoder 4, respectively.

  Similarly, (RDEC10, RDEC11) and (RDEC12, RDEC13) are assigned to the cell arrays 1c and 1d of the random access bank RNA-BNK1 as row decoders 4 for the cell arrays 1a and 1b of the other sequential access bank SQA-BNK1, respectively. On the other hand, (RDEC14, RDEC15) and (RDEC16, RDEC17) are arranged as row decoders 4, respectively.

  A physical difference between the random access bank RNA-BNK and the sequential access bank SQA-BNK is a difference in word line length. RNA-BNK is composed of 2048 bit lines, whereas SQA-BNK is composed of 16384 bit lines. Therefore, RNA-BNK has a word line length as small as 1/8 compared to SQA-BNK, which enables high-speed random access. The bit line length of RNA-BNK and SQA-BNK is the same.

  One reason why NAND flash memory is generally not suitable for random access is that the memory cells are connected in series to form a NAND string, so that the cell current is small. The other is to increase the word line length and bit line length in order to reduce the number of drive circuits as much as possible, which increases parasitic capacitance and parasitic resistance, making it unsuitable for random access.

  In this embodiment, it is possible to increase the speed in the bit line direction (reducing the sensing time) by a current detection type sense amplifier described later. However, when the word line is long, the access time is almost equal to the selection time of the word line. Will be decided. Therefore, a word line length as short as possible is good for high-speed access.

  However, since NAND flash memory writes all or half of the memory cells connected to the selected word line at a time, the word line length is as long as possible to write many memory cells at once. Better. It is possible to arrange a large number of cell arrays with short word line lengths and select and write the word lines of a plurality of cell arrays at the same time. This is because there are many row decoders for selecting word lines in order to divide the word lines. It becomes necessary, thereby increasing the chip area.

  Therefore, in this embodiment, a memory bank with a short word line for high-speed random access is combined with a memory bank with a long word line capable of storing a large amount of data and capable of high-speed writing. Thereby, while suppressing an increase in the chip area, a certain data area can be randomly accessed, and another data area can be written in a large capacity and at a high speed.

  Note that the chip layout shown in FIG. 1 is an example, and other word line lengths, bit line lengths, and cell array arrangements are possible.

  FIG. 2 shows a block configuration of the cell arrays 1a and 1b constituting the sequential access bank SQA-BNK. The block configurations of the cell arrays 1c and 1d constituting the random access bank RNA-BNK are the same except that the word line length is different.

  As shown in the figure, the cell arrays 1a and 1b (or 1c and 1d) have 2n-1 information cell blocks I-cellBLKi (i = 0 to 0) in which “information cells” I-cell for storing data are arranged. 2n-1) are arranged. The cell arrays 1a and 1b also have at least one first reference cell block R-cellaBLK in which “reference cells” R-cella for generating a reference current for reading cell data of the information cell I-cell are arranged. Has been placed.

  Specifically, when one information cell block I-cellBLK on the cell array 1a side is selected, the reference cell block R-cellaBLK is selected from the other cell array 1b, and the simultaneously selected information cell and reference cell are bit lines. Connected to the pair BL, BLB. Similarly, when one information cell block I-cellBLK is selected from the cell array 1b side, the reference cell block R-cellaBLK is selected from the cell array 1a.

  In the example of FIG. 2, the reference cell block R-cellaBLK is arranged at approximately the center position of the information cell block array in the cell arrays 1a and 1b, respectively.

  In addition to the first reference cell block R-cellaBLK, the cell arrays 1a and 1b further generate a reference current necessary for the write verification at the reference level of the reference cell block R-cellaBLK and the erase verification of the information cell. At least one second reference cell block R-cellbBLK using the “reference cell” R-cellb is arranged.

  For the reference cell of the first reference cell block R-cellaBLK, a memory cell structure that can be written and erased similarly to the information cell block I-cellBLK is used, whereas in the second reference cell block R-cellbBLK, Although a similar memory cell structure is basically used, a passive reference current source that cannot be written and erased is configured.

  FIG. 3 shows a specific configuration common to the information cell block I-cellBLK and the first reference cell block R-cellaBLK, and a plurality of NAND cell units (that is, NAND strings) I-cellNAND and R-cellNAND are arranged in a matrix. Configured.

  Each NAND string includes a plurality (32 in the illustrated example) of electrically rewritable nonvolatile memory cells MC0 to MC31 connected in series. Each memory cell MC has a MOS transistor structure in which a floating gate and a control gate are stacked, and stores data in a nonvolatile manner depending on the charge accumulation state of the floating gate.

  One end of the NAND string is connected to the bit line BL (BLB) via the selection gate transistor S1, and the other end is connected to the common source line CELSRC via the selection gate transistor S2.

  Control gates of memory cells MC0 to MC31 are connected to different word lines WL0 to WL31, respectively. The gates of the selection gate transistors S1 and S2 are connected to selection gate lines SGD and SGS parallel to the word line WL, respectively. A set of a plurality of NAND strings sharing the word lines WL0 to WL31 constitutes a “block” serving as a basic unit of data erasure.

  As described in FIG. 2, at least one of the plurality of blocks arranged in the bit line direction in each of the cell arrays 1a and 1b is set as the first reference cell block R-cellaBLK. Which block of the plurality of NAND string blocks is used as the first reference cell block is arbitrary, but once it is set as the first reference cell block, it is subsequently used in a fixed manner and the rest is information. It becomes a cell block I-cellBLK.

  FIG. 4 shows a configuration of the second reference cell block R-cellbBLK. This also has the same basic memory cell structure as that of the information cell block I-cellBLK and the first reference cell block R-cellaBLK, but in the NAND string R-cellbNAND, the memory cells MC0 to MC31 have control gates and floating gates. All have gate wirings that are short-circuited, to which a reference voltage Vref is applied. That is, all the memory cells connected in series are operated as an integrated transistor in which the reference voltage Vref is applied to the floating gate to obtain the reference current.

  In principle, the reference current source circuit for detecting the cell current can be configured at the input terminal of each sense amplifier separately from the cell array. However, as in this embodiment, by configuring all reference current source circuits using a configuration basically similar to that of the memory cells in the cell array, a reference current that does not vary without using unnecessary transistor area. You can get a source.

  In order to enable large-capacity storage in the sequential access bank SQA-BNK, multi-value technology is indispensable. For example, in this embodiment, a four-value technique as shown in FIG. 5 is used.

  FIG. 5 shows the data threshold distribution of the information cell I-cell and the reference cell R-cella in the case of quaternary data storage. As shown in the figure, four data threshold states E, A, B, and C are set in the information cell I-cell in order from the lowest.

  For example, upper page data UP and lower page data LP are allocated to these data states E, A, B, and C as follows. That is, quaternary data is (UP, LP), data state E is (1, 1), data state A is (0, 1), data state B is (0, 0), and data state C is (1, 0).

  Data state E is a negative threshold erase state. In the data write, first, lower page write is performed, and the threshold voltage is selectively raised from the data state E to the data state B. In the upper page write, the threshold value is selectively raised from the data state E to A in the case of (0, 1) write, and the threshold value is selectively raised from the data state B to C in the case of (1, 0) write. . Therefore, it is necessary to read out the lower page data that has been written first, and to perform write control according to the read data.

  As in the case of binary data storage, the reference level R of the threshold voltage near 0V is written in the reference cell R-cella with the data state E as the erased state. At the time of write verification of the information cell I-cell, verify read is performed by detecting a cell current difference from the reference cell R-cella.

  The verify voltages at the time of writing data states A, B, and C are PA, PB, and PC, respectively, and the verify voltage applied to the reference cell Rcella is Pr. Using these verify voltages, data determination is performed by comparing the cell current Ic of the information cell I-cell with the cell current (reference current) Ir of the reference cell R-cell as in the case of binary storage. It is.

  As the cell read voltage applied to the word line during normal data read, RA, RB, RC set between the data states E, A, B, C are used, and the read voltage applied to the reference cell R-cella. A voltage Rr close to the reference level upper limit value is used. Even during the normal reading, data determination is performed by comparing the cell current Ic of the information cell I-cell with the cell current Ir of the reference cell R-cella.

  In the example of data bit allocation in FIG. 5, the lower page read is possible by one read using the read voltage RB, whereas the upper page data read is performed twice using the read voltages RA and RC. Action is required. In this case, the determination of the upper page data can be performed by the odd / even determination of the number of data “1”. That is, the upper page data can be determined to be “1” when the number of “1” is an even number, and “0” when the number is “odd”.

  As described above, the lower page write can be performed by the same operation as the case of binary data storage. However, the upper page write is based on the already written lower page data and the write data input from the outside. It will be necessary to determine which threshold level to raise. Also in the write verify operation, it is necessary to determine which memory cell is to be verified and read at which level.

  In 4-level storage, data sensing takes longer time than in 2-level storage. Therefore, in this embodiment, a binary storage system is preferably applied to the random access bank RNA-BNK requiring high speed performance. Specifically, binary storage using only the lower page (UP) data of the four-value storage system described in FIG. 5, that is, only data levels E and B is used.

  Thus, by using the memory cells of the random access bank RNA-BNK in binary, the current of the memory cells can be increased. This is because in multi-level memory cells, the intervals between the data levels (threshold levels) are narrow, and the word line voltage cannot be sufficiently increased with respect to the threshold. On the other hand, in the case of a binary memory cell, since there are only two threshold levels, the word line can be made sufficiently higher than the threshold. This makes it possible to sense at a higher speed than using memory cells stored in multiple values.

  Note that it is also effective to enable the sequential access bank SQA-BNK to be used in multiple values or binary values depending on the application.

  FIG. 6 shows a specific configuration of the sense unit 2 on the random access bank RNA-BNK side, that is, SU01 and SU11. Here, an example is shown in which one sense amplifier S / A is shared by 16 bit line pairs. That is, one sense amplifier S / A is arranged on the 16 bit lines BL (BL0 to BL15) on one cell array side and the 16 bit lines BLB (BLB0 to BLB15) on the other cell array side constituting the bank.

  The even-numbered bit line and the odd-numbered bit line are selectively connected to nodes GB0-GB7, GBB0-GBB7 by selection transistors Qe, Qo controlled by signals VTGE, VTGO, respectively. These nodes GB0-GB7, GBB0-GBB7 are connected to the input nodes IN, INB of the sense amplifier S / A via the transfer transistor Q21 selected by the signals PB0-PB7, PBB0-PBB7.

  The bit line selection transistors Qe and Qo are high voltage transistors, and the other sense unit transistors are low voltage transistors.

  In order to hold the write data, a number (eight) of data latches VL (VL0 to VL7) equal to the number of bit lines simultaneously selected are arranged on the bit line BL side. Similarly, on the bit line BLB side, A number of data latches VLB (VLB0-VLB7) equal to the number of bit lines selected at the same time are arranged.

  Eight data latches VL provided corresponding to the 16 bit lines on the bit line BL side share the data transfer node BIS, and similarly, eight data latches VL provided corresponding to the 16 bit lines on the bit line BLB side. The data latches VLB share the data transfer node BISB.

  Basically, the data latch VL is used for cell writing on the bit line BL side, and the data latch VLB is used for cell writing on the bit line BLB side. Such a latch circuit arrangement enables simultaneous writing on a large number of bit lines (all even-numbered bit lines or all odd-numbered bit lines).

  One data node VLDB of data latch VL is connected to node GB via transfer transistor Q23 that is simultaneously controlled by signal DT. At the time of data writing, bit line voltage control is performed according to the write data held in the data latch VL under the control of the transfer transistor Q23. The other data node VLDS is connected to one data transfer node BIS attached to the sense amplifier S / A via a transfer transistor Q22 controlled by different timing signals VLS (VLS0 to VLS7).

  Similarly, one data node VLDBB of each data latch VLB is connected to node GBB via transfer transistor Q23 controlled simultaneously by signal DTB, and the other data node VLDSB is connected to different timing signals VLSB (VLSB0− It is connected to the other data transfer node BISB via a transfer transistor Q22 controlled by VLSB7).

  Output nodes OUT and OUTB of the sense amplifier S / A are selectively connected to the data line IOn via the data transfer control circuit DL. The output nodes OUT and OUTB are selectively connected to the data transfer nodes BIS and BISB under the control of the transfer control circuit DL. That is, data transfer between one sense amplifier S / A and a plurality of data latches VL or VLB is performed via the common data transfer node BIS or BISB, respectively.

  The data latches VL and VLB are both loaded with write data at the time of writing, but one is rewritten according to the verify read result according to the cell array selection and is used for bit line voltage control, and the other is for verify control. The write data is held as it is until the end of the write cycle.

  That is, at the time of verify read in each write cycle, the bit line data is sequentially sensed by the sense amplifier S / A, and the sense output is transferred to the data latch VL or VLB via the data transfer node BIS or BISB, and the verify read result The write data is rewritten according to the above.

  Connected to the input nodes IN and INB of the sense amplifier S / A is a precharge circuit 21 using a transistor Q24 controlled by a signal NRRNA for precharging the bit line pair BL and BLB at the time of normal reading. Yes.

  Further, a verify control circuit (pull-up circuit) 22 for forcibly setting the level of the output nodes OUT and OUTB of a specific sense amplifier S / A at the time of verify read is provided at the input nodes IN and INB of the sense amplifier S / A. It is connected. Specifically, the pull-up circuit 22 is used to prevent the “1” write cell from being “0” written in the next cycle and perform “1” write again at the time of write verify read.

  These pull-up circuits 22 are constituted by a series circuit of a transistor Q26 controlled by timing signals REFR and REFL and a transistor Q25 controlled by nodes BIS and BISB to which data of the latch circuit VLB is transferred.

  FIG. 7 shows a configuration of the latch type transfer control circuit DL. The transfer control circuit DL has a latch circuit configured by combining clocked CMOS inverters 71 and 72. The data transfer nodes BIS and BISB are nodes shared by the data latches VL and VLB. The data transfer nodes BIS and BISB are connected to the input / output nodes of the latch circuit and are connected to the signals via the transistors Q71 and Q72 controlled by the selection signals Xi and Yj. It is selectively connected to internal data line IOn via transistors Q75 and Q76 controlled by LCLE and RCLE.

  The output nodes OUT and OUTB of the sense amplifier S / A and the data nodes BIS and BISB are connected by transistors Q73 and Q74 controlled by gate signals SAOC and SAOBC, respectively.

  The data transfer control circuit DL controls the connection between the data latches VL and VLB and the output nodes OUT and OUTB of the sense amplifier S / A, the connection between the output nodes OUT and OUTB and the data bus line IOn, and also performs data inversion processing. And so on.

  FIG. 8 shows the configuration of the sense unit 2, that is, SU00 and SU10 applied to the four-value data storage on the sequential access bank SQA-BNK side, in the case where one sense amplifier S / A is arranged on the 16-bit line. This is shown in correspondence with that on the random access bank RNA-BNK side (FIG. 6). Portions corresponding to those in FIG. 6 are denoted by the same reference numerals and detailed description thereof is omitted.

  Similar to the case of binary storage, the same number of data latches VL as the number of simultaneously selected bit lines are arranged on the bit line BL side, and similarly the same number of data latches VLB as the number of bit lines are arranged on the bit line BLB side. The The configuration of these data latches is the same as that in the case of binary storage shown in FIG.

  Unlike the case of binary storage, a precharge circuit 21a for normal reading and a precharge circuit 21b for verify reading are separately provided at the input nodes IN and INB of the sense amplifier S / A. This is because in the case of quaternary storage, it is necessary to perform bit line voltage control according to data to be written at the time of verify reading.

  The normal read precharge circuit 21a is a series circuit of a transistor Q24a controlled by a control signal NRSQA and a transistor Q27a to which Vdd is applied. The verify read precharge circuit 21b is a series circuit of a transistor Q24b controlled by a control signal VR and a transistor Q27b controlled by a node PV.

  A pull-up circuit (verify control circuit) 22 that controls the state of the sense amplifier S / A after the sensing operation for the verify control is also different from the case of binary storage. That is, it is constituted by a series circuit of an NMOS transistor Q25 controlled by a control signal REFR (or REFL) and PMOS transistors Q26a and Q26b provided side by side controlled by nodes PV and DH. Write data is transferred to the nodes PV and DH.

  The collective verify detection circuit 23 is configured to detect that the data latches VL and VLB are all “0”. Here, the data in the data latches VL and VLB are defined by the data nodes VLDS and VLDSB on the data transfer nodes BIB and BIBB side.

  That is, the verify read result after writing is sequentially stored in the data latch VL on the bit line BL side and in the data latch VLB on the bit line BLB side. The collective detection circuit 23 includes a node VSEN precharged by a precharging PMOS transistor P0 and an NMOS connected in series to the node VSEN and having a gate driven by the other data nodes VLDB and VLDBB of the data latches VL and VLB. A transistor N0.

  The verify read data is controlled so that “0” is stored in the data latches VL and VLB when writing is confirmed for each bit. When the data latches VL and VLB are all “0”, all the NMOS transistors N0 of the collective detection circuit 23 are turned on, the node VSEN is discharged, and this becomes a write completion signal.

  The data transfer control circuit DL connected to the output of the sense amplifier S / A needs to perform more complicated data processing than in the case of binary storage. As shown in FIG. 9, the data transfer control circuit DL in FIG. It is very different from the configuration. That is, the data transfer control circuit DL includes two latch circuits CL and TL using clocked CMOS inverters that are selectively connected to the data transfer nodes BIS and BISB in order to perform data inversion processing for verification. Prepare.

  Data nodes CLL and CLR of latch circuit CL are connected to data transfer nodes BIS and BISB via CMOS transfer gates T1 and T2, respectively. The data nodes CLL and CLR are selectively connected to the data line IOn via the transistors MN14 and MN15 controlled by the selection signals LYj and RYj and the transistor MN20 controlled by the selection signal Xi.

  The data transfer nodes BIS and BISB are selectively connected to the output nodes OUT and OUTB of the sense amplifier S / A via the transfer transistors MN3 and MN4. In order to transfer the data of the data transfer nodes BIS and BISB as they are or after inverting them if necessary and transferring them to the data nodes DH and PV, switching circuits SW1 and SW2 are formed between them.

  The NMOS transistors MN1 and MN2 whose gates are controlled by the data nodes CLR and CLL of the latch circuit CL, whose sources are connected to the data transfer nodes BIS and BISB, and whose drains are commonly connected are exclusive for performing data inversion processing. A logical OR (XOR) gate G0. The common drain is selectively connected to one of the data nodes TLL and TLR of the latch circuit TL by the transistors MN8 and MN9.

  That is, in the portions of the NMOS transistors MN1 and MN2, an XOR operation is performed between the data held in the latch circuit CL and the data sensed by the sense amplifier S / A and sent to the data transfer nodes BIS and BISB, for example. The data thus obtained is held in the latch circuit TL.

  Although the sense unit 2 in FIG. 6 on the random access bank side does not show the collective verify detection circuit, a collective verify detection circuit similar to that in FIG. 8 may be provided.

  FIG. 10 shows the configuration of the sense amplifier S / A used in the sense unit 2 described above. This sense amplifier S / A is a current detection type differential amplifier mainly composed of a latch composed of PMOS transistors M3 and M4 and NMOS transistors M1 and M2.

  The drains of the PMOS transistor M3 and NMOS transistor M1 connected in series with the gate GA connected in common serve as one output node OUT. Similarly, the drains of the PMOS transistor M4 and the NMOS transistor M2, which are connected in series with the common gate GB, become the other output node OUTB. The common gates GA and GB are cross-connected to the output nodes OUTB and OUT.

  The PMOS transistors M3 and M4 are connected to the power supply terminal Vdd via the PMOS transistors M5 and M6 and the current source PMOS transistor M0, respectively.

  The gates of the PMOS transistors M5 and M6 are connected to the common gates GA and GB, respectively. The gate of the current source PMOS transistor M0 is controlled by the activation signal ACCb.

  The sources of the NMOS transistors M1 and M2 are commonly connected to the ground terminal Vss. The common gates GA and GB are connected to the ground terminal Vss through NMOS transistors M7 and M8 whose gates are controlled by the sense signal SEb.

  The connection node NA of the PMOS transistors M5 and M3 is connected to one input node INB via the NMOS transistor M10 controlled by the activation signal ACC. Similarly, the connection node NB of the PMOS transistors M6 and M4 is connected to the activation signal ACC. Is connected to the other input node IN through the NMOS transistor M9 controlled by the above. These separate the standby state of the sense amplifier from the precharge of the bit line, shorten the operation time of the sense amplifier, and enable data sensing with low current consumption.

  Nodes NB and NA are connected to reset NMOS transistors M11 and M12 controlled by an activation signal ACCb, respectively. These are for setting the nodes NA and NB to Vss when the sense amplifier is inactive (ACCb = “H”).

  The operation of this sense amplifier S / A will be described. In a normal data read operation, the cell current difference between the information cell I-cell and the reference cell R-cell reflected in the differential input nodes IN and INB is detected. ACCb = “H”, SEb = “ In the inactive state of H ″, the NMOS transistors M3, M4, M7, and M8 are on, and the nodes GA, GB, NA, and NB and the output nodes OUT and OUTB are held at Vss.

  When a word line is selected one by one from two cell arrays and a pair of bit lines BL and BLB are connected to input nodes IN and INB, as shown in FIG. 11, ACCb = “L” (timing t0), After a little later, SEb = "L" (timing t1), and the sense amplifier S / A is activated. Assuming that the information cell I-cell and the reference cell R-cella are selected by the bit line pair BL and BLB, respectively, their cell currents are supplied to the nodes NB and NA, respectively.

  Immediately after the activation of the sense amplifier, the NMOS transistors M1 and M2 are both off, but the PMOS transistor P0 is on and the NMOS transistors M7 and M8 are on, so the output node OUT (= GB) that has been reset to Vss. , OUTB (= GA) are charged by the current from the power supply Vdd and the cell current overlapping therewith. When a potential difference occurs between the output nodes OUT and OUTB (and therefore between the gate nodes GA and GB) due to the cell current difference, a positive feedback operation is performed in the latch to amplify the differential voltage between the output nodes OUT and OUTB. The differential voltage expands rapidly.

  For example, if OUT (GB) is lower than OUTB (GA), the positive feedback operation from SEn turns on the NMOS transistor M1, turns off the NMOS transistor M2, turns off the PMOS transistor M3, turns on the PMOS transistor M4, and outputs. The nodes OUT and OUTB become Vss and Vdd, respectively.

  This sense amplifier S / A is basically sufficient in a NAND flash memory having a bit line capacity of several pF and a cell current of about several hundred nA. Enables high-speed sensing operation.

  It is preferable to use the same S / A control signal for the sequential access bank SQA-BNK and the random access bank RNA-BNK. The S / A control signal lines from the peripheral circuit region 3 to each sense unit 2 are arranged in the region of the sense unit 2 as shown in FIG.

  The control signal line 121 on the sense unit SU11 of the random access bank RNA-BNK near the peripheral circuit area 3 in the center of the chip and the control signal line 122 on the sense unit SU10 of the sequential access bank SQA-BNK farther from the peripheral circuit 3 Is physically separated by a transfer gate circuit 123 disposed between both sense units.

  FIG. 13 shows a configuration example of the transfer gate circuit 123, which includes a NAND gate G11 and a NOR gate G12 controlled by a selection signal SQBENB. These NAND gate G11 and NOR gate G12 are provided to fix the SQA-BNK control signal line to “L” and “H” during the RNA-BNK access.

  That is, when the signal SQBENB is “L”, both the NAND gate G11 and the NOR gate G12 are active, and the S / A control signal from the peripheral circuit region 3 is directly transmitted to the SQA-BNK sense unit. When SQBENB = “H”, both the NAND gate G11 and the NOR gate G12 are inactive, and the control signal from the peripheral circuit region 3 is supplied only to the sense unit of RNA-BNK through the control signal line 121, and SQA− The control signal line 122 on the BNK side is fixed at “H” or “L”.

  As described above, when SQBENB = “L”, the same S / A control signal is given to the sense units of RNA-BNK and SQA-BNK. However, in the sense unit configuration shown in FIGS. 6 to 9, the precharge signals NRRN and NRSQA to the bit line are made different signals, and ACCbRNA and ACCbSQA are made different signals as the sense amplifier activation signal ACCb. Thus, even if other control signals are common, it is possible to flow the sense amplifier current only in one of RNA-BNK and SQA-BNK and prevent the useless current from flowing in the other. Therefore, only the sense unit of SQA-BNK can be operated, and the sense unit on the RNA-BNK side can be inactivated.

  In this way, by arranging the S / A control signal transfer control gate circuit 123 between the sequential access bank SQA-BNK and the random access bank RNA-BNK, the control signal lines 121 and 122 are separated and their control signal lines 121 and 122 are separated. The load capacity can be reduced. This will be specifically described.

  Since many sense amplifiers S / A are arranged on the SQA-BNK side, the control signal line 122 becomes a large wiring load accordingly. On the other hand, if the transfer control gate circuit 123 is inserted and the potential of the control signal line 122 on the large-capacity SQA-BNK side is fixed when the RNA-BNK is accessed, the control signal line 122 is not directly loaded. In other words, the control signal load can be reduced to the gate capacity of the gate circuit 123.

  Thereby, the signal transmission to the random access bank RNA-BNK close to the peripheral circuit 3 for high-speed use can be performed at high speed. Since the sequential access bank SQA-BNK is sequential access, there is no problem even if there is a slight delay in the transmission of the control signal.

  Next, quaternary data write and read operations on the sequential access bank SQA-BNK side will be described. Prior to quaternary data writing, the selected block is erased at once so that all cells are in erased data state E. In addition, with respect to the reference cell block R-cellaBLK of both cell arrays, the reference data level R is written in all the cells. These detailed operations are basically the same as erasing and writing of binary storage, and detailed description thereof is omitted.

(Lower page write)
First, lower page (LP) writing that performs selective threshold shift from data state E to B will be described. Consider a case where data is simultaneously written to an even-numbered bit line BL0, BL2,... On the bit line BL side and an information cell group (one page) selected by one word line.

  FIG. 14 is a flow of lower page writing. Following the command input, write data is loaded together with the selected page address (step S11). In the case of writing on the bit line BL side, the write data is sequentially loaded into the data latch group VL and transferred to the data latch group VLB (step S12).

  Then, a write voltage application operation is performed on the selected word line (step S13). After the write voltage is applied, write verify is performed to confirm the write state (step S14).

  Next, a write completion determination which is a determination as to whether or not the data latch VL is all “0” (VLDS = “0”) is performed (step S15). If there is an insufficiently written cell in one page, the writing is repeated until the writing of all the cells is confirmed.

  To describe the write operation in detail, it is necessary to apply Vdd to the bit line in the case of “1” write and 0 V to the bit line in the case of “0” write. In FIG. 9, the initial state of each signal is as follows: BISPVE = BISDH = LMRE = RMRE = CLE = LXE = RXE = LTLE = RTLE = COLC = SAOC = SAOBC = DC1 = DC2 = Xi = RYj = LYj = “L”, LINVB = RINVB = CELEB = DC1B = DC2B = BISP = “H”.

  First, write data is loaded from the outside through the data line IOn. Xi = RYj = CLE = VLS0 = CLKB = DC1 = “H”, CLK = DC1B = CLEB = “L”, external data is inverted by data latch CL, and data latched via data transfer node BIS Transfer to VL and hold.

  That is, when the externally input data is “1”, the data in the data latch VL is VLDS = “1” and VLDB = “0”. When the external input data is “0”, VLDS = “0” and VLDB = “1”.

  By repeating such a data loading operation by sequentially switching the signals VLS0 to VLS7 within the range of one sense amplifier S / A, it is possible to input inverted data of the external input data to the data latch VL <7: 0>. it can. A similar data load operation is performed in the range of a plurality of sense amplifiers, and desired one page of write data is loaded.

  After inputting all the write data, the data in the data latch group VL is loaded into the data latch group VLB on the bit line BLB side. Specifically, the data transfer nodes BIS and BISB are short-circuited with COLC = “H”, and at the same time, the data of the data latch VL is transferred to the data latch VLB with VLS = VLSB = “H”.

  By repeating this operation by sequentially switching VLSB0-VLSB7 and VLS0-VLS7, the same data as the data latch VL <7: 0> can be input to the data latch VLB <7: 0>.

  In the case of writing information cells on the bit line BL side, the data in the data latch VL determines the bit line control voltage at the time of writing. That is, according to the write data “1” and “0”, VLDB = Vdd, Vss, which is given to the bit line via the transfer transistor Q23 and the selection transistor Qe or Qo. At this time, the write data in the data latch VLB is held as it is until the writing is completed, and is used for bit line precharge control at the time of verify reading.

  When writing to information cells of even-numbered bit lines, odd-numbered bit lines are not selected, and a voltage Vdd for prohibiting writing is applied to these non-selected bit lines.

  In the selected block, Vdd is written to the bit line side selection gate line SGD, Vss is written to the source line side selection gate line SGS, write voltage Vpgm (for example, 20 V) is written to the selected word line, and unselected word lines are written. A pass voltage Vpass (for example, 10 V) is applied.

  As a result, when the bit line is 0 V, the cell channel is 0 V, the selected word line is Vpgm, and writing (electron injection) is performed. When the bit line is Vdd, the cell channel rises due to capacitive coupling, and writing is not performed.

  When writing to the information cell on the bit line BLB side, externally written data is inverted by the latch circuit CL and loaded into the data latch VLB, and the same data is transferred to the data latch VL. Then, bit line voltage control is performed based on data in the data latch VLB. The rest is the same as the bit line BL side.

  Next, verify read of the information cell I-cell to which the write voltage is applied is performed. The verify read is based on a current comparison between the selected information cell I-cell on the bit line BL side and the reference cell R-cella on the bit line BLB side. At this time, the verify voltage applied to the selected word line on the selected information cell I-cell side is PB, and the verify voltage applied to the reference word line on the reference cell R-cella side is Pr. A read pass voltage is applied to unselected word lines.

  When the write reference level R of the reference cell block R-cellaBLK is close to 0V, the read pass voltage Vreadr on the reference cell block R-cellaBLK side is sufficiently lower than the read pass voltage Vread on the information cell block I-cellBLK side. Can be set.

  By comparing the cell current Ic of the information cell I-cell and the cell current Ir of the reference cell R-cell, if Ic <Ir, the data state B is written, and if Ic> Ir, the data state E remains. It can be determined that

  As an initial setting for verify reading, all of the input nodes IN and INB and the output nodes OUT and OUTB of the sense amplifier S / A are set to Vss by ACCb = SEb = “H” and ACC = “L”. A bit line is selected according to the selected address. For example, in the verify read of the cell of the bit line BL0, VTGE = VTGBE = “H” (for example, 5V), PB0 = PBB0 = Vdd, and the bit lines BL0 and BLB0 are precharged.

  In the normal read, the bit line precharge uses the precharge circuit 21a, and precharge is performed equally for all the bit lines. In the lower page write verify read, the precharge signal VR and the data node PV are used. The precharge circuit 21b controlled by the data is used.

  Specifically, the precharge operation by the precharge circuit 21b will be described as follows. First, prior to precharging, VLSB0 = VLS0 = BISVPE = Vdd + Vth is set, and data in the data latches VLB0 and VL0 are transferred to the data nodes PV and DH for verify control, respectively.

  That is, the data in the data latch VLB0 is transferred to the data node BISB, and further transferred to the node PV via the transistor MN18 of the switching circuit SW2. Data in the data latch VL0 is transferred to the data node BIS, and further transferred to the node DH via the transistor MN16 of the switching circuit SW1.

  Therefore, if the data in the data latch VLB is “1”, the precharge circuit 21b is turned on to perform bit line precharge. When the data in the data latch VLB is “0”, the precharge circuit 21b is turned off by the node PV = “0”, so that the bit line precharge is not performed.

  In this manner, the data latch VLB data is “0”, and the bit line of the information cell (write-inhibited cell) to which “1” is written does not need to be read, so the bit line is not precharged. Thereby, extra power consumption can be reduced.

  After the precharge is completed, the sense amplifier S / A and the bit line are connected by setting ACCb = “L” and ACC = “H”. After that, by setting SEb = “L”, the sense amplifier S / A is activated, and positive feedback amplification of the cell current difference between the input nodes IN and INB is performed. As described above, if the cell current Ic of the information cell I-cell is larger than the reference current Ir, OUT = “H”, and vice versa.

  That is, if the threshold value of the information cell to which “0” is written becomes the desired data state B, the output of the sense amplifier becomes OUT = “L” (= Vss). If the threshold value of the information cell to which “0” is written does not reach the desired data level B, OUT = “H” (= Vdd).

  On the other hand, when the data in the data latch VL is “0” and “0” is not written to the selected information cell (that is, “1” is written), the sense output OUT becomes “H”. This is a condition in which “0” is written in the next cycle when the sense data is transferred to the data latch VL as it is.

  In response to this, the pull-up circuit 22 on the bit line BL side works as follows. That is, the signal REFR = “H” is applied to the pull-up circuit 22 on the bit line BL side at the same time as the current starts to flow through the sense amplifier S / A. Then, when the data transferred to the node DH is “0” (that is, when “1” is written), the pull-up circuit 22 is turned on. As a result, the current at the input node IN of the sense amplifier S / A is supplied, and the sense output is forcibly set to OUT = “L”.

  The above sense output data is transferred to the data latch VL0 by setting VLS0 = SAOC = “H”. At this time, CLKB = “H” and CLK = “L” are set in the data latch VL0.

  In the information cell in which “0” writing is sufficiently performed by the above verify reading, “1” writing is thereafter performed, and in the information cell in which “0” writing is insufficient, “0” writing is performed again and “1” writing is performed. The write data of the data latch VL0 is controlled in accordance with the sense data so that “1” is written again in the information cell.

  The above verify read is sequentially performed on the selected even-numbered bit lines BL0, BL2,. Thus, writing and verify reading are repeated until all the information cells to be written are written.

  The verify determination is performed by the collective verify determination circuit 23. After the write verify, the data latch group VL has VLDS (7: 0> = Vss (= “0”) and VLDB <7: 0> = Vdd (= “1” if all the cells are written. Therefore, when the signal node VSEN is charged to Vdd by the PMOS transistor P0 in advance, if all the selected information cells have been written, the NMOS transistors N0 to N7 are all turned on and the signal line VSEN is set to 0V. When the signal line VSEN is not discharged, the next writing operation is performed.

  When performing verify read of the information cell on the bit line BLB side, the data in the data latch VL is transferred to the node PV, and the data in the data latch VLB is transferred to the node DH. Therefore, in the switching circuits SW1 and SW2, BISDH = Vdd + Vth Set to. Further, since the selection information cell and the reference cell are input to the sense amplifier S / A in reverse, REFL = “H” is set to operate the pull-up circuit 22 on the bit line BLB side. Then, the data at the output node OUTB of the sense amplifier S / A is transferred to the data latch VLB. The rest is the same as that on the bit line BL side.

(Upper page writing)
Next, upper page (UP) data writing will be described. FIG. 15 is a flow of upper page writing. Following the command input, write data is loaded together with the address (step S21). Next, since the lower page (LP) data already written needs to be referred to for the upper page write, this is read from the cell array (step S22).

  A data change process for changing the read lower page data to data suitable for the upper page data to be written is performed (step S23).

  Then, a write voltage is applied (step S24), and verify read for confirming writing of data levels A and C is sequentially performed (steps S25 and S26). After verify reading, it is determined whether or not all writing has been completed (step S27), and writing and write verification are repeated until writing completion is determined.

  FIG. 16 collectively shows the data state changes of the data latches VL and VLB in the upper page write to the information cell on the bit line BL side for each write data level E, A, B, and C.

  Unlike the case of lower page writing, externally written data is input to the data latch VLB without being inverted. Further, since the upper page write needs to refer to the lower page data, an internal data load (IDL) for reading the lower page data from the cell array and holding it in the data latch VL is performed. “IDL” in FIG. 16 indicates the data state of the data latches VL and VLB when the read data from the cell array is held in the data latch VL as it is.

  As in the case of the lower page write, the data in the data latch VL is used for voltage control of the selected bit line BL, but the data after the internal data load IDL in FIG. 16 is not so. Therefore, a necessary data level change is performed for “PRG” at the time of writing. Specifically, when the data in the data latch VLB is “1”, the data in the data latch VL is inverted. This actually performs data processing necessary when transferring read data to the data latch VL.

  More specifically, in the case of writing at the data level E, there is no threshold shift, so the bit line BL needs to be set to Vdd, and therefore the data latch VL needs to be set to data “0”. In writing data level C, in order to shift the threshold value from data level B, bit line BL needs to be set to 0 V, and therefore data latch VL needs to be set to data “1”.

  The data state of the PRG at the time of writing in FIG. 16 indicates that the data state of the data latch VL has been changed with respect to the data level E and C writing as described above. This data change process is performed by a logical operation of the XOR gate G0 by the NMOS transistors MN1 and MN2 in the data transfer control circuit DL. The method will be specifically described below.

  First, the internal data read is performed by a normal read operation regardless of the write data of the data latch VLB. The bit line precharge is performed by the precharge circuit 21a. The precharge circuit 21b and the pull-up circuit 22 during verification are kept off.

  A read voltage RB is applied to the selected word line on the selected information cell side, and a read voltage Rr is applied to the selected word line on the reference cell side. As a result, as in normal reading, the data states E and B of the selected information cell are sequentially determined by the sense amplifier S / A for each bit line BL.

  The data sense result of the bit line BL0 needs to be transferred to the data latch VL0 after performing necessary inversion processing according to the data of the data latch VLB0. Therefore, prior to the sensing operation, the data in the data latch VLB0 is transferred to the data latch CL in the transfer control circuit DL by VLSB0 = CLE = “H” and CLEB = “L”. Further, BISP = “L”, RTLE = “H”, the node TLR of the data latch TL is charged via the PMOS transistor MP2, and the states of TLR = “H” and TLL = “L” are set. .

  Thereafter, bit line precharge and data sensing are performed, and the sense data is transferred to the data nodes BIS and BISB by setting SAOC = SAOBC = “H”. That is, the sense outputs OUT and OUTB are connected to the data nodes BIS and BISB, respectively.

  As a result, the XOR logic operation between the data of the data latch VLB0 stored in the data latch CL and the sense output is performed by the transistors MN1 and MN2. That is, when VLB0 = "1", the sense output data is inverted and transferred to the data latch VL0.

  More specifically, the XOR logic operation will be described as follows. When the data in the data latch VLB0 is “1”, the NMOS transistor MN1 is turned on by the data in the data latch CL. At this time, if the read data is “0” (OUT = “L”, and therefore BIS = “L”), when RXE = “H” is given, the node TLR of the data latch TL passes through the NMOS transistor MN1. , “L” is discharged. If this is held in the data latch TL and further transferred to the data latch VL0, the data in the data latch VL0 becomes "1". Thereby, the data inversion of the data latch VL0 in the case of the cell data C in FIG. 15 is performed. In the case of cell data B, there is no data inversion.

  On the other hand, when the data in the data latch VLB0 is “0”, the NMOS transistor MN2 is turned on. At this time, if the read data is “1” (OUTB = “L”, therefore, BISB = “L”), when RXE = “H” is applied, the node TLR of the data latch TL turns on the NMOS transistor MN2. To “L”. If this is held in the data latch TL and further transferred to the data latch VL0, the data in the data latch VL0 becomes "1". That is, the data in the data latch VL0 is “1” in the case of data A in FIG. 15 and “0” in which the read data is inverted in the case of data E.

  By the above data inversion process, the data state of “PRG” at the time of writing in FIG. 15 is obtained. Thereafter, the connection between the sense outputs OUT and OUTB and the data nodes BIS and BISB is broken by setting SAOC = SAOBC = “L”.

  By sequentially repeating the above operation for the selected bit lines BL0, BL2,..., Write data can be initialized in the data latch VL for one page.

  Next, writing is performed according to the write data set in the data latch VL. That is, with DT = Vdd + Vth, Vdd or Vss is applied to the selected bit line according to the data of each data latch VL, the potential of the NAND cell channel is controlled, and the write voltage Vpgm is applied to the selected word line.

  In the case of writing to the information cell on the bit line BLB side, external data is loaded into the data latch VL, the operation processing result of the internal read data is transferred to the data latch VLB, and this is used for bit line control. At the time of calculation after reading internal data, LXE and LTXE are used instead of RXE and RTLE, but the other operations are the same as those on the bit line BL side.

  The upper page write verify requires an A level verify (AV) for confirming the writing of the data state A and a C level verify (CV) for confirming the writing of the data state C shown in FIG. At the time of verify reading of each selected information cell, cell voltages are compared using the verify voltages PA and PC shown in FIG. 5 and the verify voltage Pr on the reference cell side.

  The verify read requires a sense time of 100 ns and a word line level change of several μs, so that it is preferable to use a drive method capable of speeding up as much as possible. For example, with the same word line level, AV is performed for all bit lines, the word line level is switched, and CV is performed for all bit lines. In this method, the word line level is switched once, and the fastest verify read is possible.

  The upper page verify read basically uses the data in the data latches VL and VLB as in the lower page verify read, but here, the verify read is performed only when the data in the data latch VLB is “1”. It shall be determined.

  At the time when the upper page write is finished, the data latch VLB is in the state of PRG at the time of write in FIG. The data in the data latch VLB can be used as it is for the C level verification, but it is necessary to invert the data in the A level verification reading.

  The A level verify column in FIG. 15 shows a state in which the data in the data latch VLB is inverted. In order to perform C level verify read after A level verify read, it is necessary to invert the data in the data latch VLB again.

  The inversion operation of the data latch VLB is performed as follows using, for example, the data latch CL in the transfer control circuit DL. First, by setting BISP = “L” and RMRE = “H”, the PMOS transistor MP1 is turned on and the NMOS transistors MN12 and MN13 are turned on, thereby setting the node CLR of the data latch CL to the “L” level.

  Next, VLSB = “H” is set, the data in the data latch VLB is transferred to the node BISB, and RINVB is set to “H” at the same time. When the data in the data latch VLB is “1” (BISB = “H”), the PMOS transistor MP6 is kept off and the node CLR is kept at “0”. When the data in the data latch VLB is “0”, the PMOS transistors MP5 and MP6 are turned on, and the node CLR is charged to “1”.

  This state is held in the data latch CL, and then transferred to the data latch VLB via the transfer gate T2 and the data node BISB. Thereby, as shown in the column of A level verification (A-Level Verify) in FIG. 15, the data inversion of the data latch VLB at the time of writing is performed.

  The above data inversion operation is sequentially performed for eight data latches VLB0 to VLB7 per sense amplifier.

  Next, the A level verify read operation will be described. First, data in the data latch VL is transferred to the data latch CL. Thereafter, the data in the data latches VL and VLB are transferred to the nodes BIS and BISB, respectively, and further, BISPVE = “H”, and the transfer data is supplied to the nodes DH and PV for verification control, respectively.

  When PV = “1” (that is, when VLB = “1”), in FIG. 8, when the signal VR is set to “H”, the verification precharge circuit 21b is turned on and the bit line is precharged. When PV = “0”, the bit line is not precharged and verify reading is not performed.

  In the A level verify read, when VLB = “0” (that is, when data states E and C are written) and when VL = “0” (that is, when data states E and B are written), the A level verify read is forcibly performed. The output of the sense amplifier S / A is set to OUT = “L”. This is due to the pull-up circuit 22 on the bit line BL side when the bit line BL side is selected. That is, when PV = “0” or DH = “0”, when the signal REFR = “H” is given, the pull-up circuit 22 on the bit line BL side is turned on, and a current is supplied to the sense amplifier input node IN. Flows into OUT = “0”.

  Therefore, verify read is performed as usual only when PV = DH = “1” (that is, when data level A is written). When the threshold value of the selected information cell on the bit line BL side rises to a desired value and the cell current becomes smaller than the reference current, OUT = “L” is obtained. Otherwise, OUT = “H”. . In FIG. 15, “RD” shown in the data latch VL in the A level verify column indicates “0” or “1” depending on the result of the verify read.

  However, in order to correctly transfer the verify read data to the data latch VL, it is necessary to reset the data in the data latch VL held in the data latch CL during the verify read. This is done by giving LMRE = “H”. At this time, if BISB = “1”, the NMOS transistors MN10 and MN11 are turned on, and the node CLL is set to “L”. When BISB = "0" (that is, when verify reading is not performed), the data in the data latch CL is held as it is.

  When VLB = "0", the sense amplifier output becomes OUT = "L". Therefore, after that, even if the sense amplifier output OUT is transferred to the node BIS and RMRE = “H”, the data latch CL does not change. Thereby, the data transferred from the data latch VL to CL is held.

  When VLB = “1”, the node CLL of the data latch CL is forcibly set to “L” as described above. As a result of the verify read, if the sense amplifier output is OUT = “H”, this is transferred to the node BIS, and when RMRE = “H”, the data in the data latch CL is inverted. When OUT = “L”, there is no such data inversion. That is, when VLB = “1”, the data of the data latch CL is reset according to the sense output by the verify read.

  By returning the data in the data latch CL to the data latch VL, one verify read is completed. The above A level verify read is sequentially performed on all the selected bit lines.

  Next, C level verify read is performed. The order of A level verify read and C level verify read does not matter. When the A level verification is performed first, since the data inversion of the data latch VLB is performed as described above, an operation to invert the data again for the C level verification is required. When the C level verification is performed first, the data in the data latch VLB of the PRG at the time of writing can be used as it is.

  The basic operation of verify reading is the same as that at the A level. That is, the data in the data latch VL is transferred to the data latch CL in the transfer control circuit DL. As a result of the verify reading, it is determined whether the data in the data latch CL is held or set to the same value as the sense output according to the data in the data latch VLB.

  Further, at the time of C-level verification (C-Level Verify), as shown in FIG. 15, verify reading is performed on an E-level write cell with VLB = “1”. In response to this, the sense output is forcibly set to OUT = “L” by the verify control pull-up circuit 22. That is, for the E level write cell, VL = “0”. By transferring this data to the node DH via the node BIS, when REFR = “H” is given, the pull on the bit line BL side is pulled. The up circuit 22 is turned on and OUT = “L” is set.

  Also, when VLB = “0”, OUT = “L” is forcibly set.

  As described above, only when VLB = “1” and VL = “1” (that is, when writing at C level), verify read is performed as usual, and the data latch CL is set according to the sense result.

  The data in the data latch CL is transferred to the data latch VL. A similar verify read operation is repeated for all selected bit lines BL.

  After one cycle of writing, A level verification, and C level verification are completed, the batch verification determination circuit 23 performs verification determination. For information cells written in the E or B level, VL = “1” (that is, VLDB = Vdd) is set after the internal data read. Further, in a state where writing is completed in all information cells, VLDB <7: 0> = Vdd.

  Accordingly, the signal line VSEN that has been charged to Vdd in advance becomes VSEN = “L” when all writing is completed, and it can be determined that writing is completed. If VSEN = “L” cannot be obtained as a result of the batch verify determination, a further write cycle is performed.

  When the write verification of the information cell on the bit line BLB side is performed, the input relationship between the information cell and the reference cell to the sense amplifier is reversed from that in the information cell on the bit line BL side, and the data latches VL and VLB are used. The direction is also reversed. Therefore, when the data in the data latches VLB and VL are transferred to the nodes DH and PV, respectively, the switching circuits SW1 and SW2 are turned on by BISDH = “H” instead of BISPVE. Furthermore, LMRE, LINVB, LME, etc. are used instead of RMRE, RINVB, RXE, etc. In addition, the basic operation of verify reading is the same as that of the bit line BL side.

(Lower page read)
In the lower page read, the data states E and A are read as data “1” and the data states B and C are read as data “0” using the read voltages RB and Rr shown in FIG. In order to perform high-speed reading, the data latch VL or VLB is used as a cache.

  For example, when the even-numbered bit line on the bit line BL side is selected, the sense data of the bit lines BL0, BL2,..., BL14 are sequentially transferred to the data latches VL0, VL1,. Forward to. The read data transferred to the data latch VL is then serially transferred via the data transfer control circuit DL and the data line IOn and output.

(Read upper page)
In the upper page read, the data sense is performed twice using the read voltages RA and RC shown in FIG. 5, and the even / odd determination of the number of “1” data obtained by this is performed. The order of the two data senses does not matter. If the number of “1” data is an even number, the upper page data is UP = “1”, and if it is an odd number, UP = “0”.

  Even in upper page reading, it is preferable to minimize word line level transitions. Therefore, for example, when an even-numbered bit line and one word line on the bit line BL side are selected, first, data sense at the read voltage RA is sequentially performed for the bit lines BL0, BL2,. Transfer and hold to VL0, VL2,.

  Next, the word line level is switched to the read voltage RC, and similarly, data sense is sequentially performed on the bit lines BL0, BL2,..., And the data latch results VL0, VL2,. The lower page data is sequentially determined by calculation with the previous sense data.

  Specifically, a case where an information cell on the bit line BL side and a reference cell on the bit line BLB side are selected will be described. The word line levels on the information cell side and the reference cell side are set to read voltages RA and Rr, respectively. Then, the bit line BL0 is precharged by the precharge circuit 21a to sense data. After sensing, by setting SAOC = “H”, the data of the sense output OUT is transferred to the node BIS, and further transferred to the data latch VL0.

  Similarly, data sense is performed on the next bit line BL2, and the sense result is transferred to the data latch VL1. Thereafter, similar data sensing and sensing result transfer operations are repeated for all selected bit lines.

  Next, the selected word line level is changed to the read voltage RC to perform data sense. At this time, prior to the bit line precharge, the data in the data latch VL is transferred to the data latch CL in the transfer control circuit DL. To do. Further, after the data of the data latch VL is transferred to the data latch CL, BISP = “L”, RTLE = “H”, and the PMOS transistor MP2 and the NMOS transistor MN7 that are turned on set the node TLR of the data latch TL to “H”. Set. This is because an even / odd determination by XOR is performed in the transfer control circuit DL between the next sense result and the sense result held by the data latch VL.

  Subsequently, bit line precharge is performed, and data sensing is performed. When the sense result is set to SAOC = SAOBC = “H”, the data is transferred to the nodes BIS and BISB, and the XOR operation between this and the data of the data latch CL is performed using the NMOS transistors MN1 and MN2. That is, when RXE = “H” is given, the XOR operation result is latched in the data latch TL depending on whether or not the node TLR set to “H” of the data latch TL is discharged by the NMOS transistors MN1 and MN2. Is done.

  This will be specifically described. The previous sense data is transferred from the data latch VL to the data latch CL. For example, when the data is CLL = "H" (= "1") and the sense data transferred from OUT to BIS is BIS = "H" (= "1"), the NMOS transistor MN1 is on. However, the “H” level of the node TLR of the data latch TL is maintained. When the previous sense data is CLL = “L” and the subsequent sense data is BIS = “L”, the NMOS transistor MN2 is turned on, but the node TLR of the data latch TL is also maintained at “H”. The

  In contrast, when the previous sense data is CLL = “H” and the subsequent sense data is BIS = “L”, the previous sense data is CLL = “L”, and the subsequent sense data is In the case of “H”, the node TLR of the data latch TL is discharged by the NMOS transistor MN1 or MN2.

  As described above, the even / odd determination operation of the number of “1” data is performed, and the upper page read data is obtained. The operation result, that is, the data in the data latch TL is transferred to the data latch VL as upper page data.

  The operation of the data sense as described above and the previous sense data of the sense result is sequentially performed on the bit lines BL0, BL2,..., And the result is transferred to the data latches VL0, VL2,.

  Even when an information cell on the bit line BLB side is selected, a data latch VLB is used instead of the data latch VL, and data processing opposite to the data latches CL and TL is used for data processing in the transfer control circuit DL. This is the same as described above.

  When outputting the read data of the data latch VL to the outside, VLS = CLE = Xi = LYj = “H” and CLEB = “L”. Assuming that the data line IOn is set to Vdd as an initial state, the voltage does not change when the data in the data latch VL is Vdd. If the data is 0V, the data line IOn is discharged to read outside. Data can be transferred.

  When outputting data in the data latch VLB, RYj is set to “H” instead of LYj.

  The random access bank RNA-BNK side performs binary storage. For example, only the levels E and B of the quaternary data of the sequential access bank SQA-BNK, that is, only the lower page data may be used. In the case of writing on the bit line BL side, writing data is sequentially loaded into the data latch group VL, and then batch writing is performed as in the case of 4-level writing.

  In the write verify read or normal read operation, the bit line data is sequentially sensed, temporarily stored in the data latch VL, and transferred and output through the transfer control circuit. In addition, there is no need for complicated data processing such as inversion as in quaternary lower page writing, and basically the same operation as in the case of normal binary storage is performed.

  The random access bank RNA-BNK has a shorter word line length than the sequential access bank SQA-BNK, and therefore high-speed random access is possible.

  FIG. 17 shows a functional block configuration of a NAND flash memory chip according to this embodiment. The two types of memory cell arrays 1 constituting the sequential access bank SQA-BNK and the random access bank RNA-BNK are configured to be controlled by separate row decoders 4 and sense units 2, respectively. A column decoder 5 is prepared for each.

  Data, addresses and commands are supplied via the interface 10. The command is supplied to the flash controller 6 via the command register 8. The address is supplied to the row decoder 4 and the column decoder 5 via the address register 8 and the flash controller 6.

  Since the random access bank RNA-BNK is a randomly accessible bank, the interface 10 needs to be an interface such as an SRAM or NOR flash memory. That is, when accessing the random access bank RNA-BNK, the access is made by directly giving the row address and column address of the RNA-BNK. For that purpose, as many address pins as the address pins are accessible to the RNA-BNK.

  On the other hand, since SQA-BNK is a bank for storing large-capacity data, if the number of address pins that can access the memory is increased, the number of pins becomes very large. Therefore, here, as in a normal NAND flash memory, access is performed by inputting address data in a time-sharing manner. Specifically, an address other than RNA-BNK is input to the address pin as a register address. Next, SQA-BNK addresses are sequentially input from the data pins in a time division manner.

  As a result, even if the memory capacity of SQA-BNK increases, an increase in address pins can be prevented. Since RNA-BNK performs random access, if this memory capacity increases, it is necessary to increase the address pins.

  The NAND flash memory has a high defect occurrence rate due to an increase in capacity and miniaturization. Therefore, in order to detect and correct the error in the read data, an ECC circuit 9 is mounted inside. As a result, the data subjected to error correction can be output to the outside without error correction outside. Also, boot data that requires random access and programs such as an OS can be output with errors corrected. Thereby, boot data can be given to RNA-BNK, and it is not necessary to have a boot ROM or the like.

  FIG. 18 shows a memory system configuration using the flash memory chip 11 of this embodiment. Since the flash memory 11 has an ECC circuit therein, it is not necessary to have a separate memory controller. Further, since the random access bank RNA-BNK is provided, it is not necessary to have a separate boot ROM.

  Although the random access bank RNA-BNK is provided, since a higher-speed RAM is required for executing the program, the DRAM 12 is connected. That is, by using the NAND flash memory 11 described above, the system is booted from this memory, and the CPU 13 directly accesses the RNA-BNK in the memory 11 to execute the program. Alternatively, the SQA-BNK data in the memory 11 can be transferred to the DRAM 12 once and the program can be executed on the DRAM 12.

  The SQA-BNK of the NAND flash memory has an access unit called a sector (for example, 528 bytes). However, when error correction of data is performed in units of sectors, the time required for error detection and correction increases because the data unit is large.

  On the other hand, the randomly accessible RNA-BNK does not have a sector configuration, and the unit of data read at a time is, for example, 32 bits (or 64 bits, 128 bits). By calculating data in parallel in this access unit, the time required for error detection and correction becomes relatively short.

  In view of the above, preferably, in order to perform error detection and correction on the RNA-BNK and SQA-BNK data by the same ECC circuit, even the SQA-BNK data has a data length smaller than the sector of the access unit. For example, error detection and correction are calculated in units of 32 bits. This makes it possible to perform high-speed error detection and correction for the two data areas using a common ECC circuit.

1 is a diagram showing a chip layout of a NAND flash memory according to an embodiment. FIG. It is a figure which shows the block configuration of the cell array of the flash memory. It is a figure which shows the structure of the information cell block and 1st reference cell block of the flash memory. It is a figure which shows the structure of the 2nd reference cell block of the flash memory. It is a figure which shows the data threshold value distribution and bit allocation of 4-value storage of the flash memory. It is a figure which shows the sense unit structure used for the bank for random access RNA-BNK which performs binary storage of the flash memory. FIG. 7 is a diagram illustrating a configuration of a data transfer control circuit in FIG. 6. It is a figure which shows the sense unit structure used for the bank SQA-BNK for sequential access which performs 4 value storage of the flash memory. It is a figure which shows the structure of the data transfer control circuit of FIG. It is a figure which shows the structure of the sense amplifier used for the same sense unit. It is a figure which shows the operation | movement waveform of the same sense amplifier. It is a figure which shows the control signal line receipt out of the sense unit of two bank area | regions. It is a figure which shows the transfer gate circuit of the control signal arrange | positioned between the sense units of two bank area | regions. It is a figure which shows the upper page write sequence of 4 value data. It is a figure which shows the lower-order page write sequence of 4-value data. It is a figure for demonstrating the data transition of the data latch at the time of a lower page write. It is a figure which shows the functional block structure of the NAND type flash memory of embodiment. It is a figure which shows the memory system structure using the NAND type flash memory of embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1a-1d ... Cell array, 2 ... Sense unit, 3 ... Peripheral circuit, 4 ... Row decoder, SQA-BNK0, 1 ... Sequential access bank, RNA-BNK0, 1 ... Random access bank, I-cellBLK ... Information cell block , R-cellaBLK, R-cellbBLK ... reference cell block, S / A ... sense amplifier, VL, VLB ... data latch, DL ... data transfer control circuit.

Claims (7)

A semiconductor memory device configured by arranging NAND strings in which a plurality of electrically rewritable nonvolatile memory cells are connected in series,
A first data area;
A semiconductor memory device comprising: a second data area having a small capacity and capable of high-speed random access as compared with the first data area. The first data area is sequentially accessed with a sector of a predetermined bit as an access unit,
2. The semiconductor memory device according to claim 1, wherein the second data area has a word line length smaller than that of the first data area. The second data area has two random access banks arranged on both sides of the peripheral circuit area in the center of the chip,
2. The semiconductor memory device according to claim 1, wherein the first data area includes two sequential access banks arranged outside the random access bank. Each of the random access bank and the sequential access bank is
As information cells whose main part stores data, some have first and second cell arrays that are used as reference cells for passing a reference current for detecting the cell current of the information cells,
A sense unit for sensing data by detecting a cell current difference between an information cell NAND string selected from one and a reference cell NAND string selected from the other is provided between the first and second cell arrays. 4. The semiconductor memory device according to claim 3, wherein: The sense unit of the random access bank and the sense unit of the sequential access bank use the same control signal supplied from the peripheral circuit area, and between the two banks, the sequential access bank side 4. The semiconductor memory device according to claim 3, wherein a transfer gate circuit for selectively fixing the level of the arranged control signal line and inactivating it is inserted. The random access bank performs binary storage,
4. The semiconductor memory device according to claim 3, wherein the sequential access bank performs multi-value storage. A common ECC circuit that performs error detection and correction of read data is provided for the random access bank and the sequential access bank, and the ECC circuit is smaller than a sector that is an access unit of the sequential access bank. 4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is configured to perform error detection and correction in data units.

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