JP2000076880A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device, in which a malfunction due to the displacement of operation timing is not generated and a circuit layout not attended with increase of a chip area is adopted. SOLUTION: Word-line driver circuits 31a1, 31a2,... driving the word lines of an odd number of blocks B1, B3,... in a memory cell array 1 are arranged on the left side of the memory cell array 1, and word-line driver circuits 31b1, 31b2,... driving the word lines of an even number of blocks B2, B4,... are disposed on the right side of the memory cell array 1. Block-address selector circuits 32a1, 32b1, 32a2, 32b2,... transmitting selecting signals to each word-line driver circuit are arranged collectively on the left side of the memory cell array. The output signal conductors of block-address selector circuits 32b1, 32b2,... are disposed as through wirings 51 passed on the regions of the memory cell array 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which is useful when applied to a NAND type EEPROM or the like.

[0002]

2. Description of the Related Art Conventionally, as one of the semiconductor memory devices, an EEPOM capable of electrically rewriting has been known. Above all, NAN by connecting a plurality of memory cells in series
The NAND cell type EEPROM constituting the D cell is attracting attention as a device that can be highly integrated. NAND type EE
A PROM memory cell has an FETM in which a charge storage layer (floating gate) and a control gate are stacked on a semiconductor substrate.
An OS structure is used. This memory cell stores data “0” and “1” according to the amount of charge stored in the floating gate.

To write data in a NAND type EEPROM, a write voltage Vpgm boosted by about 20 V is applied to a selected control gate, an intermediate voltage Vpass is applied to a non-selected control gate, and data "0", The channel voltage of the selected memory cell is controlled according to “1”.
When writing “0” data, 0 V is transferred from the bit line to the channel of the selected memory cell. As a result, in the selected memory cell, electrons are injected into the floating gate by the tunnel current, and the threshold value becomes a positive state (data “0”). At the time of writing “1” data, the channel of the memory cell is made to float. As a result, the potential of the channel rises due to the capacitive coupling from the control gate, so that the threshold voltage does not change in the memory cell to which the write voltage is applied to the control gate, and the negative threshold state (erasing of data “1”) is obtained. State).

Data erasing in a NAND type EEPROM is performed, for example, by applying 0 V to the control gate for the entire memory cell array or in block units, applying an erasing voltage Verase of about 20 V to the substrate or well, and floating all memory cells. The charge of the gate is released to the substrate side. As a result, all the memory cells are erased to the state where the threshold value is negative data "1".

For data reading, 0 V is applied to a selected control gate, and an intermediate voltage Vread for turning on a memory cell regardless of data "0" or "1" is applied to the remaining control gates.
This is performed by detecting whether or not the NAND cell is conductive with a bit line. The control gates of the respective memory cells of the NAND type EEPROM are arranged continuously in the row direction to form word lines. Usually, a set of memory cells connected to one word line is called one page. Further, a range of a plurality of continuous word lines (8NAN) for selecting one NAND cell is selected.
D, the corresponding range of 8 word lines, 16N
In the case of AND, the range of 16 word lines) is called a NAND block (or simply a block). One page is composed of, for example, 256-byte memory cells, and writing and reading are simultaneously performed on the memory cells for one page.

In such a NAND type EEPROM, a high voltage is applied to a word line driver circuit connected to each word line of a row decoder circuit for selectively driving a word line. Long high voltage transistors are used. For this reason, it is difficult to arrange the high voltage transistors of the word line driver circuit at the pitch of the word line. To solve this problem, a method of distributing and arranging word line driver circuits on both sides of a memory cell array has already been proposed by the present applicant (see Japanese Patent Application No. 6-198840).

FIG. 11 shows one such method, in which one block B in which NAND cells of a memory cell array are arranged.
, A first word line driver circuit DRV1 is arranged on the left side, and a second word line driver circuit DRV2 is arranged on the right side. The first word line driver circuit DRV1 includes odd-numbered word lines WL1, WL3,.
The select gate line SG1 on the bit line side is driven. The second word line driver circuit RRV2 is an even-numbered word line W
L0, WL2,... And the source side select gate line SG2 are driven. These word line driver circuits DRV1, DRV
A row address selection circuit RDC that supplies a row address decode signal to V2 is arranged on one of the word line driver circuits RDV1.

FIG. 12 shows another method. In this method, a word line driver circuit DRV1 for driving all word lines in a block B1 of the memory cell array is arranged on the left side of the memory cell array, and a word line driver circuit DRV2 for driving all word lines in an adjacent block B2 is arranged on the right side. are doing. As described above, since the high voltage transistors of the word line driver circuit cannot be arranged at the word line pitch, the word line driver circuits DRV1, DRV
2, the word line driver circuits DRV1 and DRV2 can be arranged by alternately distributing the blocks B1 and B2 to both sides of the memory cell array as shown in the figure.

[0009]

In the layout system shown in FIG. 11, the word lines in block B are driven by left and right word line driver circuits RDV1 and RDV2. For this reason, when the word line is long and its RC time constant is large, the timing at which a predetermined voltage is applied to each memory cell in the NAND cell of interest is shifted, thereby causing a malfunction such as erroneous writing. There is. Specifically, for example, a write voltage Vpgm (= 18 V) is applied to the word line WL3 in the block B, and an intermediate voltage Vpass (= 10 V) is applied to the remaining word lines to write data into the memory cells along the word line WL3. Will be described as an example. At this time, focusing on the leftmost NAND cell in the block B, the word lines WL1, W
The control gate of the memory cell at the left end of L3, WL5, WL7 rises to a desired voltage in about 100 ns, whereas the word lines WL0, WL driven from the right.
The control gate at the end of WL2, WL4, WL6 requires, for example, 4 μs to rise to a desired voltage.

Therefore, during the period from the start of charging to 4 μs, in the leftmost NAND cell, the word lines WL0, WL2, WL4, and WL4, regardless of the control gate of the memory cell selected by word line WL3 being at Vpgm. The control gates of the unselected memory cells along WL6 are not charged to Vpass. The intermediate voltage Vpass is for raising the potential of the channel of the non-selected memory cell in the MAMD cell by capacitive coupling in the case of writing “1”, and therefore, the write voltage Vpgm is increased when the intermediate voltage Vpass is insufficient. When given, the channel potential of the non-selected memory cell does not rise, causing erroneous writing.

On the other hand, in the layout method shown in FIG. 12, since all the word lines in the block are driven from the same side, the above-mentioned timing shift of selection of each memory cell does not matter. However, in this layout method,
Another problem is that the row address selection circuit occupies a large area. This will be specifically described below.

FIGS. 13 and 14 show row decoders (including a word line driver circuit and a row address selection circuit) on a memory chip having two memory cell arrays when the layout schemes of FIGS. 11 and 12 are employed, respectively. 2 shows the layout. In the method of FIG.
Since the row address selection circuit RDC is provided only at one end of the memory cell array, the row address signal line entering the row address selection circuit exits from the row address generation circuit in the peripheral circuit area at the center of the chip as shown in FIG. It is arranged along only the peripheral circuit side of the memory cell array.
On the other hand, in the system of FIG. 12, the row address selection circuits RDC1 and RDC2 are arranged on both sides of the memory cell array, so that the row address signal lines are arranged as shown in FIG.

One block consists of 2 ^N word lines,
When 2 ^M blocks are arranged, the number of row address signal lines for performing word line selection is 2 (N + M). Specifically, when 512 blocks are arranged as 8 word lines per block, the number of row address signal lines is 24. Therefore, in the method of FIG. 14, the area occupied by the row address selection circuit is large. In the method of FIG. 14, the area of the wiring region for guiding the row address signal lines drawn from the row address generation circuit in the peripheral circuit region to the row decoder regions on both sides of the memory cell array is large.

The present invention has been made in consideration of the above circumstances, and provides a semiconductor memory device which does not cause a malfunction due to a shift in operation timing and employs a circuit layout which does not involve an increase in chip area. The purpose is.

[0015]

A semiconductor memory device according to the present invention includes a memory cell array in which memory cells for storing data are arranged, the memory cell array being divided into at least first and second blocks, and a memory cell array of the memory cell array. A first word line driver circuit disposed at one end of a word line for selectively driving a word line in the first block; and a first word line driver circuit for selectively driving a word line in a second block of the memory cell array. A second word line driver circuit disposed at the other end of the word line;
First and second address selection circuits arranged on one side of the first and second word line driver circuits for supplying a block selection signal to the first and second word line driver circuits, respectively; , Is characterized by having.

In the semiconductor memory device according to the present invention, memory cells for storing data in a nonvolatile manner are arranged, and are divided into at least first and second two blocks so as to include a plurality of continuous word lines. Memory cell array, a first word line driver circuit arranged at one end of a word line for selectively driving a word line in a first block of the memory cell array, and a second block of the memory cell array A second word line driver circuit arranged on the other end side of a word line for selectively driving a word line in the memory, and a block selection circuit for receiving an address signal to select the first and second word line driver circuits. First and second address selection circuits arranged on one side of the first and second word line driver circuits for supplying signals , Characterized by having a.

In the present invention, a plurality of the first word line driver circuits and a plurality of the second word line driver circuits are respectively arranged at both ends of a word line of the memory cell array, and a word of each block of the memory cell array is provided. The lines are alternately connected to the first and second word line driver circuits for each of a plurality of continuous blocks excluding the blocks at both ends, specifically, for example, for every two blocks.

In the present invention, one of the block selection signals supplied from the first and second address selection circuits to the first and second word line driver circuits, respectively, is connected to a region of the memory cell array. Arranged across the top.

In the present invention, when the number of blocks of the memory cell array is two or more, for example, a plurality of first word line driver circuits are arranged corresponding to a plurality of odd-numbered blocks of the memory cell array, respectively. Are arranged corresponding to the even-numbered blocks of the memory cell array, respectively. Alternatively, the first word line driver circuit and the second word line driver circuit may be configured such that the word lines of each block of the memory cell array are continuous except for the blocks at both ends.
A plurality of memory cells are arranged at both ends of a word line of the memory cell array so as to be alternately connected to the first and second word line driver circuits for each block.

In the present invention, for example, a memory cell is an electrically rewritable memory cell in which a floating gate and a control gate are stacked on a substrate via a gate insulating film. Further preferably, in the present invention, the memory cell is an electrically rewritable memory cell in which a floating gate and a control gate are stacked on a substrate via a gate insulating film, and adjacent memory cells share a source and a drain. Thus, a plurality of NAND cells are connected in series to form a NAND cell.

According to the present invention, the word line driver circuits are distributed to both ends of the word lines in block units of the memory cell array, and all the word lines in one block are charged from one of the word line driver circuits. Therefore,
There is no shift in the operation timing of the memory cell due to the influence of the RC time constant of the word line. Specifically, when the present invention is applied to a NAND type EEPROM, in a data write mode, a write voltage is applied to a selected word line in one block, and an intermediate voltage is applied to the remaining non-selected word lines. At this time, no matter which NAND cell is arranged along the word line, there is no deviation in the timing at which the control gates of a plurality of memory cells in the NAND cell reach a predetermined voltage. Erroneous writing in the data writing operation is prevented. This is the same as the conventional layout method shown in FIG.

On the other hand, in the present invention, unlike the layout system of FIG. 12, an address selection circuit for supplying a block selection signal to word line driver circuits arranged on both sides of a memory cell array is provided only at one end of a word line of the memory cell array. Be placed. Therefore, the address signal line entering the address selection circuit does not occupy a large area on the chip as in the example shown in FIG. 14, but can be arranged in a small area as in FIG. An increase in area can be suppressed.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block configuration of a NAND cell type EEPROM according to one embodiment of the present invention.
As described later, the memory cell array 1 is configured by arranging NAND cells in which nonvolatile memory cells are connected in series. A sense amplifier circuit (also serving as a data latch) 2 is provided to sense bit line data of the memory cell array 1 or hold write data. The sense amplifier circuit 2 also performs bit line potential control when verify reading after data writing and rewriting to a memory cell with insufficient writing are performed.
It is composed mainly of MOS flip-flops.

The sense amplifier circuit 2 is connected to the data input / output buffer 6. The connection between the sense amplifier circuit 2 and the data input / output buffer 6 is controlled by the output of the column decoder 43 receiving an address signal from the address buffer 5. A row decoder 3 is provided for selecting a memory cell in the memory cell array 1 and more specifically for controlling a control gate and a selection gate. The substrate potential control circuit 7 includes the memory cell array 1
Is provided to control the potential of the p-type substrate (or p-type well) on which is formed.

A write voltage (Vpgm) generating circuit 9a is provided to generate a write voltage Vpgm boosted from a power supply voltage when data is written to a selected memory cell of the memory cell array 1. Apart from the Vpgm generation circuit 9a, a write intermediate voltage (Vpass) generation circuit 9b for generating a write intermediate voltage Vpass applied to unselected memory cells at the time of data writing,
And a read intermediate voltage Vre applied to unselected memory cells during data read (including verify read).
A read intermediate voltage (Vread) generating circuit 9c for generating ad is provided.

The write intermediate voltage Vpass and the read intermediate voltage Vread are voltages lower than the write voltage Vpgm but higher than the power supply voltage VCC. These Vpgm
A control signal generation circuit 8 is provided to control the generation circuit 9a, the Vpass generation circuit 9b, and the Vread generation circuit 9c.

FIGS. 2A and 2B show the memory cell array 1.
FIGS. 3A and 3B are a plan view and an equivalent circuit diagram of one NAND cell portion of FIG.
It is B 'sectional drawing. The NAND cell is formed in a region surrounded by an element isolation insulating film 12 on a p-type silicon substrate 11. In each memory cell, a floating gate 14 (14 ₁ , 14 ₂ ,..., 14 ₈ ) is formed on a substrate 11 via a gate insulating film 13, and a control gate 16 (16 ₁ ) is provided thereon via an interlayer insulating film 15. , 16 ₂ ,..., 16 ₈ ) are formed. N-type diffusion layers 19 (19 ₀ , 19 ₁ ,..., 1) serving as source and drain diffusion layers of these memory cells.
9 ₁₀ ) are connected so as to be shared between adjacent ones, thereby forming a NAND cell.

The drain of the NAND cell, each of the source, a floating gate, selected simultaneously formed with the control gate gate 14 ₉ of the memory cells, 16 ₉ and 14 _10, 16 ₁₀
Is provided. The substrate on which the elements are formed is covered with a CVD oxide film 17, on which a bit line 18 is provided. The bit line 18 is in contact with the drain-side diffusion layer 19 at one end of the NAND cell. N lined up in the row direction
The control gates 14 of the AND cells are shared by a control gate line CG
1, CG2,..., CG8, which become the word lines WL1, WL2,. Select gate 1
4 _9, the 16 ₉ and 14 _10, 16 ₁₀ be disposed continuously in the row direction respectively select gate lines SG1, SG2.

FIG. 4 shows an equivalent circuit of a memory cell array 1 in which such NAND cells are arranged in a matrix. A NAND cell group in the range surrounded by a broken line that shares the same control gate line (word line) and select gate line is called a block, and the read and write operations are usually performed by selecting one of a plurality of blocks. Done.

FIG. 5 shows the layout of the memory cell array 1 and the row decoder 3 in this embodiment, and FIG. 6 shows a more specific part of FIG. The memory cell array 1 is divided into a plurality of blocks B1, B2,. In this embodiment, each block Bi includes (m + 1) NAND cells ai0 to aim as shown in FIG.

In this embodiment, the word line driver circuits 31 for driving the word lines of each block Bi of the memory cell array 1 in the row decoder 3 are arranged at both ends of the word lines of the memory cell array 1. That is, the first word line driver circuits 31a (31a1, 31a) for driving the odd-numbered blocks B1, B3,.
, Are arranged on the left side of the memory cell array 1, and the second word line driver circuits 31b (31b1, 31b2,...) For driving the even-numbered blocks B2, B4,. ing.

Block address selecting circuits 32a (32a1, 32a2,...) And 32b for decoding a block address of the row address and outputting a block selecting signal to word line driver circuits 31a and 31b, respectively.
(32b1, 32b2,...) Are both arranged on the left side of the memory cell array 1. In order to supply a block selection signal of the block address selection circuit 32b to the word line driver circuit 31b on the right side, a wiring 51 passing through the area of the memory cell array 1 is provided.

As the block selection signal line 51 passing through the area of the memory cell array 1, for example, the bit line (BL) 18 shown in FIG. 3 can be used as the second layer metal line, and the first layer metal line can be used. The wiring 51 is provided in parallel with the word line WL and the common source line 62 of the memory cell array 1. Therefore, the first-layer metal wiring is provided with a select gate line S for reducing the resistance of the select gate line SG in addition to the wiring 51.
The common source line 52 can be used as a backing wiring (bypass wiring) that contacts G at an appropriate position. Since the wiring 51 crosses the bit line BL,
The bit line BL may be formed of a first-layer metal line, and may be formed of a second layer.
The wiring 51 may be formed by a layer metal wiring. Furthermore,
Usually, in the case of a two-layer metal wiring structure, the wiring 51 can be added to the uppermost layer as a third-layer metal wiring.

The first and second block selecting circuits 32a, 32
2b may be arranged on the right side of the memory cell array 1. In this case, the block selection signal wiring of the first block selection circuit 32a is disposed across the area of the memory cell array 1.

FIG. 7 shows the word line driver circuit 31a1, the block address selection circuits 32a1, 3
3 specifically shows a configuration of a portion 2b1. When a predetermined block address RAi, RBi, RCi and an enable signal RDENBX are input, the block selection signal RDECL1 of the block address selection circuit 32a1 becomes "H", whereby the block B1 is selected. The block selection signal RDECI1 is transferred to the node N0 via D-type NMOS transistors Q701 and Q702 whose gates are respectively controlled by the control signal BSTON and the power supply VCC. These transistors Q70
1, Q702 is a high voltage transistor, and the threshold value is, for example, about -1V.

E type NM driven by this node N0
OS transistors Q611 to Q618, Q621, Q6
22 are word lines WL1 to WL1 of the selected block B1, respectively.
WL8 is a drive transistor that drives the select gate lines SG1 and SG2. These driving transistors are also high voltage transistors, and the threshold value is set to about 0.6V.

E type NMOS transistor Q704,
Q705, I-type NMOS transistor Q703, capacitors C71 and C72 and inverter 74
A switch circuit 70 using a charge pump function for transferring the voltage VRDEC obtained from the booster circuit to the node N0 is configured. The voltage VRDEC is, specifically,
According to the operation mode, the Vpgm generation circuit 9a shown in FIG.
Write voltage Vpg generated from Vread generation circuit 9c
m, the read voltage Vread or VCC. The threshold value of the I-type NMOS transistor Q703 is 0.2 V
It is about. This switch circuit 70 is also formed using high voltage transistors.

The capacitors C71 and C72 are D type N
This is a MOS capacitor using a MOS transistor.
When the block B1 is selected and “H” is transferred to the node N0, the voltage VRDEC is applied to the NMO supplied to the drain.
The S-transistor Q704 is turned on, and the voltage VRDEC is transferred to the node N0 via the NMOS transistor Q704 and the diode-connected NMOS transistor Q703.

The charge pump operation is performed by the NAND gate 7 receiving the block selection output RDECI1 and the AC signal CRD.
3 is controlled. That is, the block selection signal RDEC1
Is "H", an AC signal CRD appears at the output of the NAND gate 73. Capacitors C71, C72 and NMOS which are driven in opposite phases by this AC signal CRD
Charge pumping is performed in the portion of the transistor Q703. As a result, MOS transistors Q703, Q7
04 without a voltage drop corresponding to the threshold value of V.04.
The DEC will be transferred to the node N0. Node N
0 can increase to a voltage VRDEC + α higher than VRDEC, but the NMOS transistor Q705 suppresses the increase in the voltage of the node N0. That is, assuming that the threshold value of the NMOS transistor Q705 is Vth, the voltage of the node N0 is suppressed to VRDEC + Vth or less.

E type MOS transistors Q631 and Q632 controlled by signal RDECI1B obtained by inverting block selection signal RDECI1 by inverter 71.
Is provided to set the select gate lines SG1 and SG2 to the ground potential SGDS when the block B1 is not selected at the time of writing and reading.

The selection signal RDECI2 obtained from the block address selection circuit 32b1 is supplied to the word line driver circuit 3 arranged on the right side of the memory cell array 1 by the wiring 51 passing through the area of the memory cell array 1 as described above.
1b1. Next, data read, write, and erase operations of the EEPROM of this embodiment will be described with a focus on a row decoder.

At the time of data reading, if the word line WL1 of the block B1 is selected, the terminal CGN1 connected thereto is set to 0V. The terminals CGN2 to CGN8 connected to the remaining unselected word lines are connected to the Vread generation circuit 9
c, a voltage Vread for turning on the memory cell
(For example, 4.5 V). Select gate line SG
Vre also connected to terminals SGN1 and SGN2 connected to SG1 and SG2.
ad is given.

More specifically, when data is read, when the enable signal RDENBX goes to "H", the block address selection circuits 32a and 32b are activated. When the addresses RAi, RBi, and RCi all become “H”,
The output REDCI1 of the block address selection circuit 32a becomes "H", and its inverted signal REDCI1B becomes "L".

During data reading, the voltage VRDEC applied to the driver circuit 31 is set to a value slightly higher than Vread. Further, the control signal BSTON becomes “L”, and the node N0 and the input terminal of the NAND gate 73 are separated. Then, the oscillation output CRD passes through the NAND gate 73 to which RDECI1 = “H” is input, whereby the switch circuit 70 operates, and the voltage VRDEC (= about 8 V) is transferred to the node N0. As a result, the NMOS transistors Q611 to Q618, Q621, and Q622, which are the word line drive elements of the block B1, are turned on, and the terminals CGN1 to CGN8, SGN1, and SGN are turned on.
2 are applied to the word lines WL1 to WL8 and the selection gate line SG.
1, SG2.

As a result, the memory cell connected to the selected word line WL1 is turned on if the data is "1",
The bit line potential drops. If the data is "0", the memory cell is off and the potential of the bit line does not decrease. Data is read by detecting the potential change of the bit line by the sense amplifier circuit.

In an unselected block, a block selection signal R
Deci is "L" and its inverted signal RDECIB is "H"
become. As a result, the select gate lines SG1 and SG2 are grounded. In the unselected block, the oscillation output CRD is not transferred to the switch circuit 70, the control signal BSTON is "H", the node N0 is at 0 V, and all word lines are kept floating.

At the time of data writing, 0 V is applied to the bit line for writing “0” data, and VCC is applied to the bit line for writing “1” data. The writing voltage Vpgm (about 20 V) is applied to the selected word line. The intermediate voltage Vpass (about 10 V) is applied to the unselected word lines, VCC is applied to the selection gate line SG1 on the bit line side, and 0 V is applied to the selection gate line SG2 on the common source line side. Address selection circuit 3
2 and the operation of the switch circuit 70 in the driver circuit 31 are basically the same as those at the time of reading. However, at the time of data writing, the voltage VRDEC is set to a value slightly higher than the writing voltage Vpgm, and this is transferred to the node N0. Thereby, the NMOS transistors Q611 to Q6
18 is turned on, and the voltages of the terminals CGN1 to CGN8 are applied to the word lines WL1 to WL8. And "0"
In a selected memory cell along a bit line to which data is applied, electrons are injected into the floating gate, and the threshold value becomes positive. In the selected memory cell along the bit line to which "1" data is applied, the potential of the floating channel rises due to capacitive coupling with the control gate, and no electron injection occurs.

In data erasing, the bit line and the common source line are kept floating, and an erasing voltage Vera (about 20 V) is applied to the well in which the memory cell array is formed. Also, all word lines of the selected block are set to 0V.

In the word line driver circuit 31, when this data is erased, the oscillation output CRD is not supplied, the control signal BSTON is at "H", and the node N0 is set to VCC. Thereby, the NMOS transistors Q611 to Q6
18 is turned on, 0 V of the terminals CGN1 to CGN8 is applied to the word lines WL1 to WL8, and the data of all the memory cells are erased by emitting electrons from the floating gate.
In the unselected block, by keeping all word lines floating, the potential of the control gate rises due to capacitive coupling with the well, thereby preventing data erasure. When erasing data, SG
N1, SGN2, and SGDS are set to VCC. As a result, the select gates SG1 and SG2 become floating, and the potential rises due to capacitive coupling with the well. Therefore, no potential difference is generated between the gate electrode of the select gate and the channel, so that the oxide film of the select gate is not destroyed.

In this embodiment, as shown in FIG. 5, all the word lines in each block of the memory cell array 1 are driven from the same side. Therefore, the drive timing of the control gate in each NAND cell does not shift as in the conventional circuit system of FIG. 11, and erroneous writing and the like are prevented. Also, since the address selection circuits 32a and 32b for controlling the word line driver circuits 31a and 31b arranged on both sides of the memory cell array 1 are both arranged only on one side of the memory cell array 1, the row address signal lines are not shown. As in the case of the thirteenth example, it can be arranged only on one side of the memory cell array 1 without increasing the chip area.

FIG. 8 is based on the layout of FIG.
This is an embodiment in which the layout is slightly different from that in FIG. In the embodiment shown in FIG. 6, the word line driver circuits 31a and 31b are used for blocks sharing the bit line contact 61.
Are alternately arranged on both sides of the memory cell array 1. In this embodiment, the word line driver circuits 32a and 32b are alternately arranged for blocks sharing the common source line 62. Others are the same as the previous embodiment.

FIG. 9 shows an embodiment in which the layout of FIG. 5 is modified. In the embodiment shown in FIG. 5, the first word line driver circuits 31a1, 3 on the left side correspond to the plurality of odd-numbered blocks B1, B3,.
Are arranged, and even-numbered blocks B2, B4,
. Are arranged on the right side in correspondence with. On the other hand, in the embodiment of FIG. 9, the word line of the first block B1 is connected to the word line driver circuit 31a1 on the left side, and the word lines of the second and third blocks B2 and B3 are connected to the second line on the right side. The word lines of the fourth and fifth blocks B4 and B5 connected to the word line driver circuits 31b1 and 31b2 are connected to the left word line driver circuits 31a2 and 31b.
a3. Similarly, the word lines of each block of the memory cell array 1 are connected to first and second word line driver circuits 31a and 31b alternately arranged on the left and right every two consecutive blocks except for the blocks at both ends. Is done.

In the embodiments described so far, the first and second blocks are set every block of the memory cell array 1 or every two blocks.
Are distributed to both sides of the memory cell array 1, and the first and second word line driver circuits 31a and 31b have substantially the same number (the same number if the number of blocks is even). In the above-described embodiments, the high voltage MO is applied to the width of the block in the bit line direction.
The word line driver circuits are distributed on both sides of the memory cell array 1 on the assumption that the width of the word line driver circuit using S transistors is increased. in this case,
If the width of the word line driver circuit is smaller than twice the block width, the plurality of word line driver circuits respectively arranged on both sides of the memory cell array 1 are arranged substantially linearly by the method of the above embodiment. It is possible.

In consideration of the layout of the word line driver circuits, the word line driver circuits can be alternately arranged on both sides of the memory cell array 1 every three blocks or every four blocks.

In the embodiment shown in FIG. 9, adjacent blocks in which word line driver circuits are arranged on the same side, for example, blocks B2 and B3, or blocks B4 and B5, may share bit line contacts or may be common. Source lines may be shared. In addition, when adjacent blocks share a bit line contact, it is also effective to adopt a system in which select gate lines on the bit line contact side are collectively driven.

FIG. 10 specifically focuses on two adjacent blocks B4 and B5 in FIG.
A specific configuration when G1 is shared is shown in relation to the word line driver circuits 31a2 and 31a3. As shown, the select gate line SG1 on the bit line contact 61 side of the two blocks B4 and B5 is connected to one select gate line S.
These are grouped as G0 and are driven by the word line driver circuits 31a2 and 31a3. The specific configuration of the word line driver circuits 31a2 and 31a3 is the same as that of FIG.

The common selection gate line SG0 is connected to the output signals RDECI of the block address selection circuits 32a2 and 32a3.
2, RDECI1 inverted signal RDECI2B, RDEC
Two NMOs whose gates are controlled by I1B
Grounded via S transistors Q633 and Q634. That is, when the two blocks B4 and B5 are both unselected, RDECI1B = RDECI2B = "H", and the common selection gate line SG0 is grounded.

The present invention is not limited to the above embodiment. In the embodiment, the NAND type EEPROM has been described. However, the NOR type EEPROM, which is another electrically rewritable nonvolatile memory,
The present invention can be similarly applied to AND-type and DINOR-type EEPROMs. Further, the present invention is also applicable to an ultraviolet erasing type EPROM and a mask ROM which cannot be rewritten.

[0059]

As described above, according to the present invention, the word line driver circuits are distributed to both ends of the word line in units of the memory cell array block, and all the word lines in one block are connected to one word line. Since the charging is performed from the line driver circuit, the operation timing of the memory cell does not shift. Further, in the present invention, the address selection circuit for supplying the selection signal to the word line driver circuits arranged on both sides of the memory cell array is arranged only on one end of the word line of the memory cell array. Therefore, the address signal line entering the address selection circuit does not occupy a large area on the chip, and an increase in the chip area can be suppressed.

[Brief description of the drawings]

FIG. 1 shows a NAND type EEPROM according to an embodiment of the present invention.
It is an equivalent circuit diagram of OM.

FIG. 2 is a plan view and an equivalent circuit diagram of a NAND cell according to the same embodiment.

FIG. 3 is a sectional view taken along line AA ′ and line BB ′ of FIG. 2;

FIG. 4 is an equivalent circuit of the memory cell array of the embodiment.

FIG. 5 is a diagram showing a memory cell array and a row decoder layout of the same embodiment.

FIG. 6 is a diagram showing a part of FIG. 5 in a concrete form;

FIG. 7 is a diagram showing in detail a configuration of a main part of FIG. 6;

FIG. 8 is a diagram showing a memory cell array and a row decoder layout according to another embodiment corresponding to FIG. 6;

FIG. 9 is a diagram showing a memory cell array and a row decoder layout according to another embodiment, corresponding to FIG. 5;

FIG. 10 is a diagram showing a memory cell array and a row decoder layout according to another embodiment.

FIG. 11 shows a layout example of a memory cell array and a row decoder of a conventional NAND type EEPROM.

FIG. 12 shows another example of a memory cell array and a row decoder layout of a conventional NAND type EEPROM.

13 shows an on-chip layout of row address signal lines in the case of the circuit system of FIG. 11;

14 shows an on-chip layout of row address signal lines in the case of the circuit system of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Sense amplifier circuit and data latch, 3 ... Row decoder, 4 ... Column decoder, 5 ...
Address buffer, 6 data input / output buffer, 7 substrate potential control circuit, 8 control signal generation circuit, 9a, 9b,
9c: Vpgm, Vpass, Vread generation circuit, B: block, 31a: first word line driver circuit, 31b: second word line driver circuit, 32a, 32b: block address selection circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792 F term (Reference) 5B025 AA01 AB01 AC01 AD02 AD03 AE05 AE08 5F001 AA25 AB08 AB09 AC02 AD12 AD41 AD44 AD51 AD53 AE01 AE02 AE08 AE20 AE30 AE50 AG40 5F083 EP02 EP23 ER03 ER09 ER14 ER19 ER22 GA09 GA30 KA01 LA04 LA05 LA06 LA08 LA12 LA16 LA20 LA28 ZA01

Claims (8)

[Claims] 1. A memory cell array for storing data, wherein the memory cell array is divided into at least first and second two blocks, and a word line in the first block of the memory cell array is selectively driven. Of the first word line located at one end of the word line
A second word line driver circuit disposed on the other end of a word line for selectively driving a word line in a second block of the memory cell array.
Any one of the first and second word line driver circuits for receiving an address signal and supplying a block selection signal to the first and second word line driver circuits, respectively. And a first and a second address selection circuit disposed on the side of the semiconductor memory device. 2. A memory cell array in which memory cells for storing data in a nonvolatile manner are arranged and divided into at least first and second two blocks so as to include a plurality of continuous word lines, respectively. A first line arranged at one end of a word line for selectively driving a word line in a first block of the cell array.
A second word line driver circuit disposed on the other end of a word line for selectively driving a word line in a second block of the memory cell array.
Any one of the first and second word line driver circuits for receiving an address signal and supplying a block selection signal to the first and second word line driver circuits, respectively. And a first and a second address selection circuit disposed on the side of the semiconductor memory device. 3. The first word line driver circuit and a second word line driver circuit.
A plurality of word line driver circuits are arranged at both ends of the word lines of the memory cell array, and the word lines of each block of the memory cell array are alternately arranged every two blocks except for the blocks at both ends. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to first and second word line driver circuits. 4. One of the block selection signals supplied from the first and second address selection circuits to the first and second word line driver circuits, respectively, runs on the memory cell array area. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is arranged across the semiconductor memory device. 5. A plurality of the first word line driver circuits are respectively arranged corresponding to a plurality of odd-numbered blocks of the memory cell array, and the second word line driver circuit is an even number of the memory cell array. A plurality of blocks are arranged corresponding to the plurality of blocks, respectively.
3. The semiconductor memory device according to claim 1. 6. The first word line driver circuit and a second word line driver circuit.
A plurality of word line driver circuits are respectively arranged on both ends of the word line of the memory cell array, and the word lines of each block of the memory cell array are alternately arranged for a plurality of continuous blocks excluding the blocks at both ends. First
3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to a second word line driver circuit. 7. The memory cell according to claim 1, wherein the memory cell is an electrically rewritable memory cell in which a floating gate and a control gate are stacked on a substrate via a gate insulating film. Semiconductor storage device. 8. The memory cell is an electrically rewritable memory cell in which a floating gate and a control gate are stacked on a substrate via a gate insulating film, and adjacent memory cells share a source and a drain. 3. The semiconductor memory device according to claim 1, wherein a plurality of NAND cells are connected in series to form a NAND cell.