CN107622779A - A kind of storage array block and semiconductor memory - Google Patents
A kind of storage array block and semiconductor memory Download PDFInfo
- Publication number
- CN107622779A CN107622779A CN201711033349.5A CN201711033349A CN107622779A CN 107622779 A CN107622779 A CN 107622779A CN 201711033349 A CN201711033349 A CN 201711033349A CN 107622779 A CN107622779 A CN 107622779A
- Authority
- CN
- China
- Prior art keywords
- signal line
- row
- column signal
- column
- storage array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000003860 storage Methods 0.000 title claims abstract description 76
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000004458 analytical method Methods 0.000 claims abstract description 7
- 239000004744 fabric Substances 0.000 claims 2
- 238000005457 optimization Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 25
- 238000000034 method Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
Landscapes
- Static Random-Access Memory (AREA)
- Dram (AREA)
Abstract
The present invention proposes a kind of storage array block, including：Multiple storage array portions of array distribution, wherein the inside in each storage array portion is respectively equipped with the multiple array-supported of cross direction profiles；Multiple rows are connected with multiple storage array portions respectively to load；A plurality of column signal line, with multiple array-supported connections along straight line genesis analysis；Row signal line, connected respectively with the multiple row to load；First signal wire driver element, it is connected respectively with a plurality of column signal line and row signal line；Secondary signal line driver element, respectively with the connection of the row signal line and/or a plurality of column signal line.The present invention is driven simultaneously by both ends, can reduce the size of single driver element.Furthermore it is also possible to accelerate the response of length/heavy duty signal wire, to offset the Time Delay Impact of long line, so as to realize the quick control of length/heavy duty signal and timing optimization.
Description
Technical field
The present invention relates to technical field of semiconductor memory, more particularly to a kind of storage array block and semiconductor memory.
Background technology
In memory device, length/heavy duty signal wire is seen everywhere, and their drive circuit and driving method often turns into
One of design focal point of sequential and chip size.
When a signal wire is very long and drives many loads (loading), the output stage device of this root signal drive circuit
Size is often very big, and different sections (segment) time delay of this root signal wire also differs greatly, and this is generally to circuit
Timing Design and dimensionally-optimised bring many difficulties.
As shown in Figure 1-2, its be respectively in background technology dynamic RAM (DRAM) storage permutation signal wire
Schematic diagram and type of drive schematic diagram.The storage array block (bank) 100 of background technology, including：Multiple storages of array distribution
Array part (section) 110, multiple rows drive single to load 130, a plurality of column signal line 140, row signal line 150 and signal wire
Member 160.Wherein, the inside in each storage array portion 110 is respectively equipped with multiple loads 120 of cross direction profiles.It is the multiple
Row is connected with multiple storage array portions 110 respectively to load 130.The a plurality of column signal line 140, respectively with genesis analysis
Multiple connections of load 120.The row signal line 150, it is connected respectively with the multiple row to load 130.The signal wire driving
The connection with a plurality of column signal line 140 and the row signal line 150 respectively of unit 160, on row signal line 150
Row in load and column signal line 140 is driven to load.
It was found from above-mentioned background technology, the side of the signal wire of existing DRAM storage arrays is driven, and in order to drive
Multiple loads on the signal wire, then need signal line drive (Driver) size to set very big, be so then unfavorable for pair
The arrangement of device in circuit design.
Simultaneously as only being driven in the side of signal wire, cause the time delay difference of each node of signal wire very big.Such as
Shown in Fig. 3, waveform time delay schematic diagram when it drives for the signal wire of background technology.As can be known from Fig. 3, four on signal wire
, there is different degrees of time delay phenomenon respectively in different location point A, B, C, D, wherein further away from signal line drive, its
Time delay is bigger.Therefore, the size of simple increase driver can not effectively improve the signal quality of the signal wire.
Explanation above does not represent above content just for the sake of helping skilled in the art to understand the background of the present invention
It is known to those skilled in the art or know.
The content of the invention
The embodiment of the present invention provides a kind of storage array block and semiconductor memory, with least solve it is of the prior art with
Upper technical problem.
In a first aspect, the embodiments of the invention provide a kind of storage array block, including：
Multiple storage array portions of array distribution, wherein the inside in each storage array portion is respectively equipped with cross direction profiles
It is multiple array-supported；
Multiple rows are connected with multiple storage array portions respectively to load；
A plurality of column signal line, with multiple array-supported connections along straight line genesis analysis；
Row signal line, connected respectively with the multiple row to load；
First signal wire driver element, it is connected respectively with a plurality of column signal line and the row signal line, for institute
The array-supported row connected with the row signal line for stating column signal line connection is driven to load；And
Secondary signal line driver element, with forming group wherein by the row signal line and a plurality of column signal line
One or both connects, for the load to being connected from the column signal line and the row that the row signal line connects to loading institute structure
Into group one of them or both be driven.
With reference in a first aspect, the embodiment of the present invention in the first implementation of first aspect, first signal wire
Driver element is arranged on the side of the row signal line and a plurality of column signal line, and the secondary signal line driver element is set
In the row signal line and/or the opposite side of a plurality of column signal line.
With reference to the on one side, in second of implementation of the embodiment of the present invention, the first signal wire driver element
The side of the row signal line and a plurality of column signal line is arranged on, the secondary signal line driver element is arranged on the row
Interval region in signal wire and a plurality of column signal line.
With reference in a first aspect, of the invention in the third implementation of first aspect, the first signal wire driving is single
Member includes：Multiple column signal line drivers and a row signal line driver；The multiple column signal line driver passes through respectively
The a plurality of column signal line driving is described array-supported；The row signal line driver drives the row by the row signal line
To load；
The secondary signal line driver element includes multiple column signal drivers and a row signal line driver；It is described more
Individual column signal line driver is driven described array-supported by a plurality of column signal line respectively；The row signal line driver leads to
Cross the row signal line and drive the row to load.
With reference in a first aspect, of the invention in the 4th kind of implementation of first aspect, the first signal wire driving is single
Member includes：Multiple column signal line drivers and a row signal line driver；The multiple column signal line driver passes through respectively
The a plurality of column signal line driving is described array-supported；The row signal line driver drives the row by the row signal line
To load；
The secondary signal line driver element includes multiple column signal line drivers, the multiple column signal line driver point
Do not driven by a plurality of column signal line described array-supported.
With reference in a first aspect, of the invention in the 5th kind of implementation of first aspect, the first signal wire driving is single
Member includes：Multiple column signal line drivers and a row signal line driver；The multiple column signal line driver passes through respectively
The a plurality of column signal line driving is described array-supported；The row signal line driver drives the row by the row signal line
To load；
The secondary signal line driver element includes multiple column signal line drivers, and the row signal line driver passes through institute
State row signal line and drive the row to load.
With reference to the on one side, in the 6th kind of implementation of the embodiment of the present invention, the storage array block also includes：It is more
Individual sub- column signal driver, is electrically connected with each column signal line respectively, for driving the load that respectively column signal line is connected.
Second aspect, the embodiments of the invention provide a kind of storage array block, including：
Multiple storage array portions of array distribution, wherein the inside in each storage array portion is respectively equipped with cross direction profiles
It is multiple array-supported；
Multiple rows are connected with multiple storage array portions respectively to load；
A plurality of column signal line, with multiple array-supported connections along straight line genesis analysis；
Row signal line, connected respectively with the multiple row to load；
Signal wire driver element, the connection with the row signal line and a plurality of column signal line, for column signal line
The row that the load of connection connects with row signal line is driven to load；And
More sub- column signal drivers, are electrically connected respectively at the column signal line, for driving each column signal line
What is connected is array-supported.
In terms of second, in the first implementation of the embodiment of the present invention, the first signal wire driver element
Including：Multiple column signal line drivers and a row signal line driver；The multiple column signal line driver passes through institute respectively
It is described array-supported to state a plurality of column signal line driving；The row signal line driver by the row signal line drive the row to
Load.
3rd aspect, the embodiments of the invention provide the storage array of a kind of semiconductor memory, including first aspect
The storage array block of block or second aspect.
The present invention uses above-mentioned technical proposal, possesses following effect：
The present invention is driven simultaneously by both ends, is on the one hand driven by two driver elements and the small column signal of multiple auxiliary
Device substitutes a driver element of the prior art, can reduce the size of single driver element, so as to convenient in circuit
It can be set in layout compacter.In addition, by way of both ends driving plus process auxiliary drive, accelerate length/heavy duty signal wire
Response, to offset the Time Delay Impact of long line, so as to realize the quick control of length/heavy duty signal and timing optimization.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to is limited in any way.Except foregoing description
Schematical aspect, outside embodiment and feature, it is further by reference to accompanying drawing and the following detailed description, the present invention
Aspect, embodiment and feature would is that what is be readily apparent that.
Brief description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise represent same or analogous through multiple accompanying drawing identical references
Part or element.What these accompanying drawings were not necessarily to scale.It should be understood that these accompanying drawings depict only according to the present invention
Some disclosed embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is the signal wire schematic diagram of the storage permutation of the dynamic RAM (DRAM) of prior art.
Fig. 2 is the type of drive schematic diagram of the signal wire of the storage permutation of the dynamic RAM of prior art.
Waveform time delay schematic diagram when Fig. 3 is the signal wire driving of prior art.
Fig. 4 is the signal wire schematic diagram of the storage array of the present embodiment one.
Fig. 5 is the signal type of drive schematic diagram of the storage array of the present embodiment one.
Waveform time delay schematic diagram when Fig. 6 is the signal wire driving of the present embodiment one.
Fig. 7 is the signal wire schematic diagram of the storage array of the embodiment of the present invention two.
Fig. 8 is the signal wire schematic diagram of the storage array of the embodiment of the present invention three.
Fig. 9 is the signal wire schematic diagram of the storage array of the embodiment of the present invention four.
Figure 10 is that multipoint parallel drives schematic diagram on the column signal line of the embodiment of the present invention four.
Waveform time delay schematic diagram when Figure 11 is the signal wire driving of the embodiment of the present invention four.
Figure 12 is the signal wire schematic diagram of the storage array of the embodiment of the present invention five.
Figure 13 is that the multipoint parallel on column signal line of the embodiment of the present invention six drives schematic diagram.
Embodiment
Hereinafter, some exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be changed by various different modes.
Therefore, accompanying drawing and description are considered essentially illustrative rather than restrictive.
The embodiment of the present invention aims to solve the problem that is directed to length/multi-load signal wire when carrying out load driving in the prior art, meeting
The technical problem of larger time delay is produced, the technical scheme of the embodiment of the present invention is situated between especially by following embodiment
Continue.
Embodiment one
Fig. 4-5 are referred to, it is respectively signal wire schematic diagram and the type of drive signal of the storage array of the present embodiment one
Figure.The embodiment of the present invention one provides a kind of storage array block 200, including：It is multiple storage array portions 210 of array distribution, more
Individual row to load 230, a plurality of column signal line (YS) 240, the 250, first signal wire driver element of row signal line (RS) 260 and second
Signal wire driver element 270.
Wherein, the inside in each storage array portion 210 is respectively equipped with multiple array-supported the 220 of cross direction profiles.
The multiple row is connected with multiple storage array portions 210 respectively to load 230.
The a plurality of column signal line 240, it is connected with along multiple described array-supported the 220 of straight line genesis analysis.
The row signal line 250, it is connected respectively with the multiple row to load 230.
The first signal wire driver element 260 and secondary signal line driver element 270, respectively with the row signal line
250 and the connection of a plurality of column signal line 240, for simultaneously to the load on the row signal line 250 and the column signal
Row on line 240 is driven to load.
Further, the first signal wire driver element 260 is arranged on the row signal line 250 and a plurality of column signal
The side of line 240, the secondary signal line driver element 270 are arranged on the row signal line 250 and a plurality of column signal line
240 opposite side.
Specifically, the first signal wire driver element 260 includes：Multiple column signal line drivers 261 and a row letter
Number line drive 262.The multiple column signal line driver 261 drives the battle array by a plurality of column signal line 240 respectively
Row load 220；The row signal line driver 262 drives the row to load 230 by the row signal line 250.
The secondary signal line driver element 270 includes multiple column signal line drivers 271 and a row signal line driving
Device 272.The multiple column signal line driver 271 is driven described array-supported by a plurality of column signal line 240 respectively
220；The row signal line driver 272 drives the row to load 230 by the row signal line 250.
In the present embodiment one, by setting the first signal wire respectively at the both ends of column signal line 240 and row signal line 250
Driver element 260 and secondary signal line driver element 270, can be at both ends simultaneously to a plurality of column signal line 240 and row signal line
Load on 250 is driven.Driven simultaneously by both ends, on the one hand substitute of the prior art one by two driver elements
Individual driver element, the size of single driver element can be reduced, more stepped up so as to convenient can be set on circuit layout
Gather.In addition, by way of being driven both ends, the time delay between load can be effectively reduced.With reference to accompanying drawing 6, it is the present embodiment
Waveform time delay schematic diagram during one signal wire driving.It was found from from accompanying drawing 6, by being driven at the both ends of column signal line simultaneously,
A and D, B on the column signal line is identical with the time delay of C points, and because B and C is in the middle part of signal wire, so postponing a meeting or conference at that time
It is bigger than the A and D positioned at both ends.
Embodiment two
The embodiment of the present invention two is deformed on the basis of embodiment one, there is provided another implementation, i.e., only
Multiple column signal line drivers are only set on secondary signal line driver element, while the load on column signal line is driven
It is dynamic.Concrete scheme is described as follows：
Referring to Fig. 7, its signal wire schematic diagram for the storage array of the embodiment of the present invention two.The embodiment of the present invention two carries
A kind of storage array block 300 has been supplied, including：Multiple storage array portions 210 of array distribution, multiple rows are to load 230, a plurality of row
Signal wire 240, row signal line 250, the first signal wire driver element 260 and secondary signal line driver element 270.
The annexation of device inside the storage array block 300 of the present embodiment two is identical with embodiment one, refuses herein
Repeat.Illustrated below for the present embodiment two and the difference of embodiment one, it is specific as follows：
In the present embodiment two, the first signal wire driver element 260 is arranged on the row signal line 250 and described more
The side of bar column signal line 240, the secondary signal line driver element 270 are arranged on the another of a plurality of column signal line 240
Side.
Specifically, the first signal wire driver element 260 includes：Multiple column signal line drivers 261 and a row letter
Number line drive 262.The multiple column signal line driver 261 drives the array to bear by a plurality of column signal line 240
220 are carried, the row signal line driver 262 drives the row to load 230 by the row signal line 250.
The secondary signal line driver element 270 passes through a plurality of column signal including multiple column signal line drivers 271
The driving described array-supported 220 of line 240.
In the present embodiment two, by setting the He of the first signal wire driver element 260 respectively at the both ends of column signal line 240
Secondary signal line driver element 270, the load on a plurality of column signal line 240 can be driven simultaneously at both ends.Pass through two
End drives simultaneously, on the one hand substitutes a driver element of the prior art by two driver elements, can reduce single drive
The size of moving cell, it can be set on circuit layout so as to conveniently compacter.In addition, the side driven by both ends
Formula, the time delay between load can be effectively reduced.
Embodiment three
The embodiment of the present invention three is deformed on the basis of embodiment one, there is provided another implementation, i.e., only
Row signal line driver is set only on secondary signal line driver element, while the load on column signal line is driven.Tool
Body scheme is described as follows：
Referring to Fig. 8, it is the storage array signal wire schematic diagram of the embodiment of the present invention three.The embodiment of the present invention three provides
A kind of storage array block 400, including：Multiple storage array portions 210 of array distribution, multiple rows are believed to load 230, a plurality of row
Number line 240, row signal line 250, the first signal wire driver element 260 and secondary signal line driver element 270.
The annexation of device is identical with embodiment one in the storage array block 400 of above-mentioned the present embodiment three, herein no longer
Repeat.Illustrated below for the present embodiment three and the difference of embodiment one：
In the present embodiment three, the first signal wire driver element 260 is arranged on the row signal line 250 and described a plurality of
The side of column signal line 240, the secondary signal line driver element 270 are arranged on the opposite side of the row signal line 250.
Specifically, the first signal wire driver element 260 includes：Multiple column signal line drivers 261 and a row letter
Number line drive 262.The multiple column signal line driver 261 drives the array to bear by a plurality of column signal line 240
Carry 220.The row signal line driver 262 drives the row to load 230 by the row signal line 250.
The secondary signal line driver element 270 passes through the row signal line 250 including a row signal line driver 272
The row is driven to load 230.
In the present embodiment three, by setting the He of the first signal wire driver element 260 respectively at the both ends of row signal line 250
Secondary signal line driver element 270, the load on row signal line 250 can be driven simultaneously at both ends.It is same by both ends
When drive, on the one hand substitute a driver elements of the prior art by two driver elements, it is single that single driving can be reduced
The size of member, it can be set on circuit layout so as to conveniently compacter.In addition, by way of being driven both ends, can
To effectively reduce the time delay between load.
Example IV
The embodiment of the present invention four adds more sub- column signal drivers on the basis of embodiment one, for aiding in row
Load on signal wire is driven.Specific scheme is described as follows：
Please refer to Fig. 9-Figure 10, it is respectively the array storage signal wire schematic diagram and row letter of the embodiment of the present invention four
Multipoint parallel driving schematic diagram on number line.The embodiment of the present invention four provides a kind of storage array block 500, including：Array distribution
Multiple storage array portions 210, multiple rows to load 230, a plurality of column signal line 240, row signal line 250, the first signal wire drive
Moving cell 260, secondary signal line driver element 270 and more sub- column signal line drivers (sub-driver) 280.
In the present embodiment four, the annexation of the device of above-mentioned storage array block 500 is identical with embodiment one, therefore no longer
Repeat, the present embodiment four differs only in embodiment one：In the present embodiment four, it also add more sub- column signal lines and drive
Dynamic device 280.
The multiple sub- column signal driver 280, is electrically connected in the column signal line 240 respectively with respectively, each for driving
The load 220 that the column signal line is connected.
In the present embodiment four, by setting the first signal wire respectively at the both ends of column signal line 240 and row signal line 250
Driver element 260 and secondary signal line driver element 270, can be at both ends simultaneously to a plurality of column signal line 240 and row signal line
Load on 250 is driven.Meanwhile also by increasing more sub- column signal drivers 280 on column signal line 240, can be with
Auxiliary is driven to the load on column signal line.
Driven by both ends, on the one hand substituted by two driver elements and the small column signal driver of multiple auxiliary simultaneously
A driver element of the prior art, the size of single driver element can be reduced, so as to convenient on circuit layout
It can set compacter.In addition, both ends driving plus process auxiliary drive by way of, can effectively reduce load between when
Prolong.With reference to accompanying drawing 11, waveform time delay schematic diagram when it drives for the signal wire of the present embodiment four.It was found from from accompanying drawing 10, lead to
Cross at the both ends of column signal line while drive, the time delay of the A and D, B on the column signal line and C points is identical, and due to B and C at
In the middle part of signal wire, so it is bigger than the A and D positioned at both ends to postpone a meeting or conference at that time.And arranged compared to embodiment one, the present embodiment four
More sub- column signal drivers 280 are added on signal wire, can further reduce B and C time delay again.
In the present embodiment four, the secondary signal line driver element 270 can only include multiple column signal line drivers
271, or only include a row signal line driver 272.
Embodiment five
The present embodiment five is deformed on the basis of embodiment one, there is provided another implementation, i.e., by second
Signal driving unit is arranged on the middle part of column signal line and row signal line, and the load on column signal line and column signal line is entered successively
Row driving.Specific scheme is described as follows：
Figure 12 is referred to, it is the signal wire schematic diagram of the storage array of the embodiment of the present invention seven.The embodiment of the present invention five
A kind of storage array block 600 is provided, including：Multiple storage array portions 210 of array distribution, multiple rows are to load 230, a plurality of
Column signal line (YS) 240, the signal wire driver element 260 of row signal line (RS) 250, first and secondary signal line driver element 270.
The device annexation of the storage array block 600 of above-described embodiment five is identical with embodiment one, will not be described here.
Illustrated below for the present embodiment seven and the difference of embodiment one, it is specific as follows：
In the present embodiment five, the first signal wire driver element 260 is arranged on the row signal line 250 and described more
The side of bar column signal line 240, the secondary signal line driver element 270 are arranged on the row signal line 250 and described a plurality of
Interval region in column signal line 240.
Specifically, the first signal wire driver element 260 includes：Multiple column signal line drivers 261 and a row letter
Number line drive 262.Side of the multiple column signal line driver 261 respectively with a plurality of column signal line 240 is connected；Institute
The side that row signal line driver 262 is stated with the row signal line 250 is connected.
The secondary signal line driver element 270 includes multiple column signal line drivers 271 and a row signal line driving
Device 272.Middle part of the multiple column signal line driver 271 respectively with a plurality of column signal line 240 is connected；The row signal
Line drive 272 is connected with the middle part of the row signal line 250.
In the present embodiment five, by setting the first signal wire to drive in the side of column signal line 240 and row signal line 250
Unit 260, secondary signal line driver element 270 is set at the middle part of column signal line 240 and row signal line 250, so as to same
When the load on a plurality of column signal line and column signal line is driven.It is on the one hand single by two drivings by driving simultaneously
Member substitutes a driver element of the prior art, can reduce the size of single driver element, so as to convenient in circuit
It can be set in layout compacter.In addition, by way of diverse location drives simultaneously, can effectively reduce between loading
Time delay.
Embodiment six
Figure 13 is referred to, it is that the multipoint parallel on column signal line of the present embodiment six drives schematic diagram.The embodiment of the present invention
Six provide a kind of storage array block 700, including：Multiple storage array portions 210 of array distribution, multiple rows are to load 230, more
Bar column signal line (YS) 240, row signal line (RS) 250, signal wire driver element 260 and more sub- column signal drivers 280.
In the present embodiment six, the annexation of the device inside the storage array block 700 is identical with embodiment one,
This thus do not repeat, illustrated below only for the present embodiment six and the difference of embodiment one：
In the present embodiment six, secondary signal line driver element 270 is not used, and replaces with more sub- column signal drivers
280 carry out process auxiliary drive.
Specifically, the multiple sub- column signal driver 280, is electrically connected with the column signal line 240, for driving respectively
Load 220 on column signal line 240.
In the present embodiment six, by increasing more sub- column signal drivers 280 on column signal line 240, it can aid in
Load on column signal line is driven.
By process auxiliary drive mode, it on the one hand can reduce the size of single driver element, so as to convenient in circuit
It can be set in layout compacter.Furthermore it is also possible to effectively reduce the time delay between load.
Embodiment seven
The embodiment of the present invention seven provides a kind of semiconductor memory, including a kind of storage array block.The storage array
Block be specifically configured to embodiment one to embodiment six any one.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or the spy for combining the embodiment or example description
Point is contained at least one embodiment or example of the present invention.Moreover, specific features, structure, material or the feature of description
It can be combined in an appropriate manner in any one or more embodiments or example.In addition, in the case of not conflicting, this
The technical staff in field can be by the different embodiments or example described in this specification and the spy of different embodiments or example
Sign is combined and combined.
In addition, term " first ", " second " are only used for describing purpose, and it is not intended that instruction or hint relative importance
Or the implicit quantity for indicating indicated technical characteristic.Thus, " first " is defined, the feature of " second " can be expressed or hidden
Include at least one this feature containing ground.In the description of the invention, " multiple " are meant that two or more, unless otherwise
It is clearly specific to limit.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, its various change or replacement can be readily occurred in,
These should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
Shield scope is defined.
Claims (10)
- A kind of 1. storage array block (200), it is characterised in that including：Multiple storage array portions (210) of array distribution, wherein the inside in each storage array portion is respectively equipped with and laterally divided Multiple array-supported (220) of cloth；Multiple rows are connected with multiple storage array portions respectively to load (230)；A plurality of column signal line (240), with multiple array-supported connections along straight line genesis analysis；Row signal line (250), connected respectively with the multiple row to load；First signal wire driver element (260), is connected with a plurality of column signal line and the row signal line, for institute respectively The array-supported row connected with the row signal line for stating column signal line connection is driven to load；AndSecondary signal line driver element (270), with by the row signal line and a plurality of column signal line form group its Middle one or both connection, for the load to being connected from the column signal line and the row that the row signal line connects to loading institute One of them of group or both is formed to be driven.
- 2. storage array block according to claim 1, it is characterised in that the first signal wire driver element is arranged on institute The side of row signal line and a plurality of column signal line is stated, the secondary signal line driver element is arranged on the row signal line And/or the opposite side of a plurality of column signal line.
- 3. storage array block according to claim 1, it is characterised in that the first signal wire driver element is arranged on institute The side of row signal line and a plurality of column signal line is stated, the secondary signal line driver element is arranged on the row signal line And/or the interval region in a plurality of column signal line.
- 4. storage array block according to claim 1, it is characterised in that：The first signal wire driver element includes：It is more Individual column signal line driver (261) and a row signal line driver (262)；The multiple column signal line driver passes through respectively The a plurality of column signal line driving is described array-supported；The row signal line driver drives the row by the row signal line To load；The secondary signal line driver element includes multiple column signal drivers (271) and a row signal line driver (272)； The multiple column signal line driver is driven described array-supported by a plurality of column signal line respectively；The row signal line drives Dynamic device drives the row to load by the row signal line.
- 5. storage array block according to claim 1, it is characterised in that the first signal wire driver element includes：It is more Individual column signal line driver (261) and a row signal line driver (262)；The multiple column signal line driver passes through respectively The a plurality of column signal line driving is described array-supported；The row signal line driver drives the row by the row signal line To load；The secondary signal line driver element includes multiple column signal line drivers (271), the multiple column signal line driver Driven respectively by a plurality of column signal line described array-supported.
- 6. storage array block according to claim 1, it is characterised in that：The first signal wire driver element includes：It is more Individual column signal line driver (261) and a row signal line driver (262)；The multiple column signal line driver passes through respectively The a plurality of column signal line driving is described array-supported；The row signal line driver drives the row by the row signal line To load；The secondary signal line driver element includes a row signal line driver (272), and the row signal line driver passes through The row signal line drives the row to load.
- 7. storage array block according to claim 1, it is characterised in that the storage array block also includes：More height row Signal driver (280), electrically connected respectively with each column signal line, for driving the load that respectively column signal line is connected.
- A kind of 8. storage array block (700), it is characterised in that including：Multiple storage array portions (210) of array distribution, wherein the inside in each storage array portion is respectively equipped with and laterally divided Multiple array-supported (220) of cloth；Multiple rows are connected with multiple storage array portions respectively to load (230)；A plurality of column signal line (240), with multiple array-supported connections along straight line genesis analysis；Row signal line (250), connected respectively with the multiple row to load；Signal wire driver element (260), the connection with the row signal line and a plurality of column signal line, for column signal line The array-supported row connected with row signal line of connection is driven to load；AndMore sub- column signal drivers (280), electrically connect with the column signal line, for driving each column signal line respectively What is connected is array-supported.
- 9. storage array block according to claim 8, it is characterised in that the signal wire driver element includes：Multiple row Signal line drive and a row signal line driver；The multiple column signal line driver passes through a plurality of column signal respectively Line driving is described array-supported；The row signal line driver drives the row to load by the row signal line.
- 10. a kind of semiconductor memory, it is characterised in that including the storage array block as described in claim 1-9 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711033349.5A CN107622779B (en) | 2017-10-30 | 2017-10-30 | Memory array block and semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711033349.5A CN107622779B (en) | 2017-10-30 | 2017-10-30 | Memory array block and semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107622779A true CN107622779A (en) | 2018-01-23 |
| CN107622779B CN107622779B (en) | 2024-03-26 |
Family
ID=61093242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711033349.5A Active CN107622779B (en) | 2017-10-30 | 2017-10-30 | Memory array block and semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107622779B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108257641A (en) * | 2018-04-18 | 2018-07-06 | 睿力集成电路有限公司 | For the storage matrix and semiconductor memory of semiconductor memory |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1052966A (en) * | 1989-12-29 | 1991-07-10 | 三星电子株式会社 | Semiconductor memory apparatus |
| JP2000076880A (en) * | 1998-08-27 | 2000-03-14 | Toshiba Corp | Semiconductor storage device |
| US6160751A (en) * | 1998-07-21 | 2000-12-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device allowing efficient column selection |
| US6195301B1 (en) * | 1998-12-30 | 2001-02-27 | Texas Instruments Incorporated | Feedback driver for memory array bitline |
| CN104464804A (en) * | 2013-09-25 | 2015-03-25 | 北京兆易创新科技股份有限公司 | Method and circuit for driving storage array |
| CN207302638U (en) * | 2017-10-30 | 2018-05-01 | 睿力集成电路有限公司 | A kind of storage array block and semiconductor memory |
-
2017
- 2017-10-30 CN CN201711033349.5A patent/CN107622779B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1052966A (en) * | 1989-12-29 | 1991-07-10 | 三星电子株式会社 | Semiconductor memory apparatus |
| US6160751A (en) * | 1998-07-21 | 2000-12-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device allowing efficient column selection |
| JP2000076880A (en) * | 1998-08-27 | 2000-03-14 | Toshiba Corp | Semiconductor storage device |
| US6195301B1 (en) * | 1998-12-30 | 2001-02-27 | Texas Instruments Incorporated | Feedback driver for memory array bitline |
| CN104464804A (en) * | 2013-09-25 | 2015-03-25 | 北京兆易创新科技股份有限公司 | Method and circuit for driving storage array |
| CN207302638U (en) * | 2017-10-30 | 2018-05-01 | 睿力集成电路有限公司 | A kind of storage array block and semiconductor memory |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108257641A (en) * | 2018-04-18 | 2018-07-06 | 睿力集成电路有限公司 | For the storage matrix and semiconductor memory of semiconductor memory |
| CN108257641B (en) * | 2018-04-18 | 2023-08-11 | 长鑫存储技术有限公司 | Memory matrix for semiconductor memory and semiconductor memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107622779B (en) | 2024-03-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE3630835C2 (en) | Integrated semiconductor circuit arrangements and systems | |
| KR101839953B1 (en) | Driver, and display device using the same | |
| DE69630929T2 (en) | Plasma display panel, method for driving it to perform interlaced display, and plasma display device | |
| CN100337282C (en) | Buffer to multiple memory interface | |
| DE3906895C2 (en) | ||
| CN104700765A (en) | Gate driving method and display device | |
| DE102007019117B4 (en) | memory module | |
| DE202010018501U1 (en) | System that uses distributed bytewise buffers on a memory module | |
| CN102779101A (en) | Semiconductor device | |
| JP2002141477A5 (en) | ||
| JPH06119781A (en) | Semiconductor memory | |
| DE102008051035A1 (en) | Integrated circuit comprising memory module with a plurality of memory banks | |
| CN1181614C (en) | Semiconductor memory with single clock signal line | |
| CN103400559A (en) | Display device | |
| JP4989077B2 (en) | Semiconductor memory device having energy-saving word line enable signal line arrangement structure and word line enable signal line arrangement method | |
| KR910002962B1 (en) | Monolithic semiconductor memory decreasing resistance of data line | |
| CN207302638U (en) | A kind of storage array block and semiconductor memory | |
| CN107622779A (en) | A kind of storage array block and semiconductor memory | |
| KR0140213Y1 (en) | Semiconductor memory device | |
| CN110969983A (en) | Organic light emitting diode display | |
| CN1018401B (en) | Method of flash write for testing ram | |
| US6787859B2 (en) | Semiconductor memory device with shortened connection length among memory block, data buffer and data bus | |
| DE3333974A1 (en) | DYNAMIC MOS MEMORY WITH OPTIONAL ACCESS | |
| DE60118833T2 (en) | Semiconductor memory with a subdivided wordline structure | |
| DE10147201A1 (en) | Semiconductor memory has sub word selecting circuit which switches selection of sub word selection line of memory cell array arranged on corresponding substrate plates using drivers |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20181010 Address after: 230000 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Applicant after: CHANGXIN MEMORY TECHNOLOGIES, Inc. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Applicant before: INNOTRON MEMORY CO.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |