JPH1173790A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sharpen the scatter of threshold values and to stabilize the operation in low voltages by executing rewriting after a weak erase operation for a memory cell having a threshold value lower than the reading level and higher than the verify level. SOLUTION: The memory cell array 12 is stored with the threshold values corresponding to the data of four values, '11', '10', '01', '00'. For example, in the refresh operation for the data '01', a short pulse under 3.7 V of reading level for the data '01' is impressed as a weak erase pulse to shift the threshold of the memory cell to a higher side. Reading is carried out at the reading level of 3.7 V for the data '01'; the data held in a sense latch 13 is inverted and a verify operation is performed at the verify voltage of 3.5 V. As the result, the data held in the sense latch 13 conducts rewriting for the cell of '1'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique particularly effective when applied to a storage method of multi-valued information in a semiconductor memory device and a nonvolatile semiconductor memory device. For example, a plurality of stored information can be electrically erased collectively. The present invention relates to a technology effective for use in a nonvolatile memory device (hereinafter, simply referred to as a flash memory).

[0002]

2. Description of the Related Art A flash memory uses a nonvolatile memory element having a control gate and a floating gate for a memory cell, like a FAMOS.
A memory cell can be formed with the number of transistors. In such a flash memory, in a write operation, as shown in FIG. 12, the drain voltage of the nonvolatile memory element is set to about 5 V and the word line connected to the control gate is set to about -10 V, so that the floating gate is caused by the tunnel current. The charge is extracted from the gate to bring the threshold voltage to a low state (logic “0”). In the erase operation, as shown in FIG. 13, the P-type semiconductor region pwell
Is set to about -5 V, and the word line is set to about 10 V to generate a tunnel current to inject negative charges into the floating gate to bring the threshold value to a high state (logic "1").
Thus, one-bit data is stored in one memory cell.

By the way, in order to increase the storage capacity, 1
A concept of a so-called “multi-valued” memory that stores two or more bits of data in a memory cell has been proposed. An invention relating to this multi-valued memory is disclosed in Japanese Unexamined Patent Publication No.
No. 96 and the like.

[0004]

In a conventional flash memory, variations in threshold voltage increase due to weak writing and the like (disturb) and natural leak (retention) caused by writing, reading and erasing operations on adjacent bits. The half-value width of the variation distribution shape of the threshold value corresponding to the logic “0” and the logic “1” (the width at the position of ピ ー ク of the peak value of the mountain-shaped variation distribution as shown in FIG. 3) Is known to increase over time. As the power supply voltage of the LSI becomes lower in the future, the threshold voltage of the memory cell exceeds the voltage margin range for the read voltage due to the spread of the variation distribution shape with time, and there is a problem that a malfunction may occur. The inventor has discovered that.

In particular, in a multi-valued memory in which a plurality of bits of data are stored in one storage element due to a difference in threshold value, the difference in threshold voltage corresponding to each data is small. Become. Further, in the flash memory, there is a technical problem that the processing time and the circuit scale unique to the multi-valued memory should be suppressed to a minimum since there are erase and write verify operations unique to the nonvolatile memory device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-value storage type nonvolatile storage device capable of minimizing an increase in circuit scale and realizing highly accurate writing, reading and erasing operations in a short time. .

Another object of the present invention is to provide a method for steepening the distribution of the variation in threshold voltage and a nonvolatile memory device which can operate stably at a low voltage.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of typical inventions disclosed in the present application. That is, (1) In a nonvolatile memory device having a memory cell (memory element) configured to store information in accordance with a threshold value, at the time of writing data, a plurality of bits of data are converted by a data conversion logic circuit into data of the bit. The data is converted into data (multi-valued data) corresponding to the combination, the converted data is sequentially transferred to a latch circuit connected to the bit line of the memory array, and a write pulse is generated according to the data held in the latch circuit. By generating and applying it to the selected memory cell, the memory cell has a threshold value corresponding to the multi-valued data, and at the time of data reading, the read voltage is changed to an intermediate value between the respective threshold values so that the memory cell has a threshold voltage. The state is read out, transferred to a register for storing multi-valued data and held, and the reverse data is stored based on the multi-valued data stored in the register. The original data is restored by a data conversion logic circuit. (2) After performing a weak erase operation on a memory cell in the memory array, a memory cell having a threshold value lower than the read level and higher than the verify level is detected on the word line, and the memory cell is identified. By performing writing so that the threshold value is lower than the verify voltage, the spread of the variation distribution shape of the threshold voltage of the memory cell written corresponding to each input data is narrowed. It is.

According to the above-mentioned means (1), the peripheral circuit scale of the memory array can be kept relatively small, and in a write operation, the verify voltage value of the word line is reduced to the word line voltage for erasing. The value is sequentially changed by a predetermined value in a direction away from the near side (FIG. 3 (1) →
(4)), the total number of write pulses, that is, the write time can be reduced as compared with the multi-valued flash memory system in which the verify voltage is set at random, and the write operation can be performed in a short time.

Further, by means of the above (2), it is possible to return the variation distribution shape of the threshold voltage of the memory cell spread due to the disturbance, the retention or the like to a steep shape substantially equal to that immediately after the completion of writing.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to a flash memory will be described below with reference to the drawings. FIG. 1 shows a conversion method between externally input data to be stored and multi-value data stored in a memory cell, and FIG. 2 shows an inverse conversion method for restoring original data from the multi-value data. is there.

In FIG. 1, although not particularly limited, two bits, ie, “00” and “0” are stored in one memory cell (one storage element).
An example of a conversion method when any one of “1”, “10”, and “11” is stored is shown in FIG.
There are four types of combinations of the binary data "a" and the second binary data "b", and each combination has three types of logical operations (aNANDb),
By performing (NOTb) and (aNORb),
The number of “1” among the four bits is 0, 1, 2,
It is converted into four types of four-valued data of three.

Here, if a write operation, that is, a write pulse is applied to the storage elements by the number of "1" based on the above calculation result, the threshold value of each storage element is changed according to the number of times of writing, as shown in FIG. As shown in 3), there are four types, and 2-bit data can be written to one memory cell. For a plurality of storage elements in the memory array, "00",
FIG. 3 shows how the threshold distribution of each storage element changes when the same number of data “01”, “10”, and “11” are stored.

FIG. 2 shows the principle of data reading. By changing the read voltage of the word line in three stages (intermediate values of the respective threshold distributions in FIG. 3), three types of data, "c", "d", and "f" can be obtained from the same memory cell. They can be read sequentially. Therefore, by performing a logical operation (d * NAND f) NAND c * on the read data, one (a) of the 2-bit data written can be restored. Further, d in the read data matches the write data b as it is. Note that d * and c * represent inverted signals of d and c.

FIG. 4 shows an example of a specific circuit configuration of the conversion into the multi-value data and the inverse conversion shown in FIGS. At the time of data writing, 2n-bit data supplied to the multi-level flash memory from the outside is serially stored in two binary data registers REG1 and REG2 having a data width of n bits via a switch SW1. At this time, although not particularly limited, the switch SW1 is switched by the output of the flip-flop FF1 operated by the clock CLK1 supplied from the outside, and the clock CL is output from the frequency dividing circuit DVD.
A clock CLK1 'having a cycle twice as long as CLK1 obtained by dividing K1 is supplied via a switching circuit CHG, and the binary data registers REG1 and REG2 are shifted in synchronization with the clock CLK1', so that an input is made. The data is alternately stored one bit at a time in the binary data register RE.
G1 and REG2.

The data "a" stored in the first binary data register REG1 and the data "b" stored in the second binary data register REG2 are supplied from the internal clock generation circuit 30 via the switching circuit CHG. 1 (2) in synchronization with the clock CLK2
Is supplied to the data conversion logic circuit 11 for performing the above operation, and after a predetermined logical operation, the data is sequentially transferred to the n-bit length sense latch circuit 13 provided on one side of the memory array 12 via the switch SW2. Writing to the memory cells in the array 12 is performed. This write operation will be described later in detail.

The switching circuit CHG supplies the clock CLK1 'to the binary data registers REG1 and REG2 at the time of data input according to a control signal from the sequencer 18 which controls the inside of the memory, and transfers the data to and from the sense latch 13. The clock CLK2 from the clock generation circuit 30 to the binary data registers REG1, R
Switching control is performed so as to supply to EG2.

The data conversion logic circuit (arithmetic circuit for writing data) 11 includes the binary data register REG.
NAN which receives data a and b in REG2 and REG2 at input terminals and performs an operation of (aNANDb)
NO for performing operation of D gate G1 and (aNORb)
R gate G2 and the binary data register REG2
The switch SW2 selects one of the output signals of the logic gates G1, G2, G3 and sends the signal to the sense latch circuit 13. It is configured to supply.

On the other hand, at the time of data reading, the read data "c" appearing on the bit line in response to one word line in the memory array 12 being set to the read voltage level is amplified by the sense latch circuit 13. The binary data register REG1 via the switch SW3 in synchronization with the internal clock CLK2.
Is serially transferred to Next, the data "d" read out to the sense latch circuit 13 by changing the read voltage level is serially transferred to the binary data register REG2 via the switch SW3. Further, the data "f" read by the sense latch circuit 13 with the read voltage level changed is serially transferred to the inverse conversion logic circuit 14 via the switch SW3. At this time, the binary data registers REG1 and REG2 output the clock CLK.
2 and are shifted in synchronism. However, the cycle of the clock CLK2 at the time of data reading is the same as that of the clock C2 at the time of data writing.
The period may be shorter than the period of LK2. The cycle of the clock CLK2 can be determined and generated by the clock generation circuit 30 based on a control signal from the sequencer 18. The change of the word line read level is also performed according to the control signal from the sequencer 18.

The inverse conversion logic circuit (arithmetic circuit for data reading) 14 includes an inverter G11 that receives data output from the binary data register REG2,
The output from the inverter G11 and the sense latch circuit 1
, A delay circuit DLY that delays the data output from the binary data register REG1 and outputs the data at a predetermined timing, and a delay circuit DL2.
An inverter G13 that inverts the output of Y, and a NAND gate G14 that receives the output of the inverter G13 and the output of the NAND gate G12 as inputs, and the read data c and the read data c held in the binary data registers REG1 and REG2. The logical operation (d * NAND f) NAND c * shown in FIG. 2 is performed on d and the read data f directly transferred from the sense latch circuit 13. This calculation result is output to the data input / output terminal I / O via the switch SW1.

At the same time as outputting the 1-bit data, the binary data register REG2 shifts and holds one of the data "d" (= b) held.
Bit is output. At this time, the shift operation of the binary data registers REG1 and REG2 is performed by the clock CLK2.
It is performed in synchronization with. Next, the next bits of the data "c" and "d" are read again from the binary data registers REG1 and REG2, and the next bit of the read data "f" directly transferred from the sense latch circuit 13 is read. Logical operation (d * NAND f) NAND c *. Hereinafter, by repeating the same operation as described above, the data “a” and “b” which are inversely transformed and restored to the original 2 bits
Is output from the data input / output terminal I / O to the outside.

As described above, the inverse conversion logic circuit 14
Immediately converts the data "a" inversely converted by the input / output terminal I / O
Instead, the inversely converted data "a" is temporarily stored in the binary data register REG1, and after the inverse conversion is completed for all bits, the data in the binary data register REG2 is alternately input / output terminals I / O. It may be configured to output to In that case, it is desirable to provide a 1-bit latch circuit instead of the delay circuit DLY. Thus, an operation of reading out one bit of data “c” in the binary data register REG1, performing a logical operation on the data “d” and “f”, and writing the result to the original bit position in the binary data register REG1 Can be done easily. The data after the inverse conversion is temporarily stored in the binary data register R
The shift operation of the binary data registers REG1 and REG2 when stored in EG1 and REG2 and then output to the outside can be configured to be performed in synchronization with an external clock CLK1.

The flash memory of this embodiment includes, but is not limited to, a command register 16 for holding a command given from an external CPU or the like, a command decoder 17 for decoding a command stored in the command register 16, and a A sequencer 18 for sequentially forming and outputting a control signal to each circuit such as the switches SW2 and SW3 in order to execute a process corresponding to the command based on a decoding result of the command decoder 17;
When a command is given, it is configured to decode the command and automatically execute a corresponding process. The sequencer 18 is, for example, a ROM (read only memory) storing a series of microinstructions necessary for executing a command (instruction), similarly to a control section of a microprogram type CPU. Generates a start address of a microinstruction group corresponding to the command and supplies it to the sequencer 18 so that the microprogram is started.

The detailed writing procedure is described as follows in accordance with the writing flow of FIG.

First, prior to writing, all memory cells are erased collectively. As a result, all the memory cells are set to have the highest threshold value (about 5 V), and a state where "11" is stored as the write data (FIG. 3A). As shown in FIG. 13, the collective erasing is performed by raising the word line and setting 10 V to the control gate CG of the memory cell and 0 V to the drain through the bit line.
V, a voltage of −5 V is applied to the substrate (semiconductor region pwell) to inject electrons into the floating gate FG. The batch erasure is executed by writing an erasure command instructing erasure from the external CPU to the command register 16.

In FIG. 13 (FIGS. 12 and 14), psub is a p-type semiconductor substrate, pwell is a p-type semiconductor well region serving as a base of a memory cell, and niso is a substrate when data is erased (when a negative voltage is applied). The n + on the surface of the n-type semiconductor isolation region and p-type well region pwell for insulation from psub is the source / drain region of the memory cell, p + on the surface of the p-type well region pwell,
N + on the surface of the isolation region niso and the substrate p
p + on the surface of the sub is a contact region for reducing contact resistance with an electrode that applies a potential to each semiconductor region. Although not particularly limited, one p-type well region includes:
Memory cells connected to word lines such as 128 are formed, and all the memory cells formed on one such well can be collectively erased. Further, by setting the word line potential to selected (10 V) / non-selected (0 V) for a memory cell on one p-type well region, erasing can be performed in word line units.

When the batch erasure is completed, a write command is written from the external CPU into the command register 16 of FIG. 4 to put the flash memory into a write mode. In this write mode, write data is input at a predetermined timing. Then, the flash memory fetches the write data into the binary data registers REG1 and REG2, transfers them to the conversion logic circuit 11 two bits at a time, and converts them into four-value data (step S1). The conversion is performed in the order of aNANDb, NOTb (inversion of b), and aNORb. The converted data (the first time is aNANDb) is transferred to the sense latch circuit 13 (step S2).

In the next step S3, it is determined whether or not all the data in the binary data registers REG1, REG2 have been transferred.
A write pulse having a predetermined pulse width is written to a memory cell of a bit corresponding to "1" of the X (row) address supplied from the PU and the Y (column) address output from the built-in Y address counter 33 shown in FIG. Is applied, and writing is performed (step S4). Writing is performed as shown in FIG.
As shown in FIG.
This is performed by applying a voltage of −10 V to G, 5 V to the drain from the sense circuit via the bit line, and 0 V to the substrate. At this time, Vcc (for example, 3.3 V) is applied to the unselected word lines. As a result, the fluctuation of the threshold value due to the disturbance is suppressed.

Next, a verify voltage (approximately 3.5 V for the first time) corresponding to the write level is supplied to the selected word line at the time of writing, and reading of the memory cell to which the write pulse is applied is performed. . “0” is read as read data from a memory cell in which writing is sufficiently performed, while “1” is read as read data from a memory cell in which writing is insufficient. Therefore, it can be determined whether writing is completed or writing is insufficient according to the read data. Here, the data of the bit for which writing has been completed in the sense latch circuit 13 is inverted to "0" (step S6). Then, all the sense latch circuits 13
It is determined whether or not the latch data has become “0”. If all the latch data becomes “0”, the current writing is completed. Then, the process returns from step S7 to S4, and the write pulse is applied again to the insufficiently written memory cell corresponding to "1". By repeating the above steps S4 to S7, a write pulse is repeatedly applied so that the threshold values of all the memory cells fall below the write verify voltage. As a result, the written memory cell has an average threshold value of about 3.2 V.

When the writing of the desired data to all the memory cells is completed by the write verify operation, all the data of the sense latch circuit 13 becomes "0". Therefore, the flow shifts to step S8, and all the write levels are used. Write, that is, data “10”, “01”,
It is determined whether the writing for “00” has been completed. If not completed, the process returns to step S1, where the quaternary data based on the next operation result (NOTb) is written into the memory cell, and the verify voltage of the word line is changed (the second time is 2.5V) and verify is performed. The written and written memory cells have a threshold value of about 2.2 V on average. Then, the third calculation result (aNOR
b) Write and verify (verify voltage 1.5
V) is executed, the written memory cell has a threshold value of about 1.2 V on average, and the writing is completed.

FIG. 6 shows the control clock CLK2 and the sense latch circuit 13 at the time of the write and write verify operations.
5 shows waveforms of data to be written into a memory cell and a potential of a selected word line. In the first write, the first operation result (aNAN
After the transfer of Db) to the sense latch circuit 13, the write pulse is used to write to the selected memory cell whose latch value is "1". Next, a voltage of, for example, about 3.5 V is supplied to the word line as a write verify voltage, and it is determined whether or not the read data is “0”. If the threshold value is higher than 3.5 V, the read data becomes "1", indicating that the write operation is insufficient. Therefore, the write operation is repeated until the read data becomes "0". Next, the second operation result (NOTb) is transferred to the sense latch circuit 13, and a write operation is started in a desired memory cell by a write pulse. The write verify voltage is set to about 2.5 V, and it is determined whether or not writing is insufficient, and if it is insufficient, rewriting is performed. Finally, the third operation result (aNOR
b) is transferred to the sense latch circuit 13, and the same procedure as described above is performed. The write verify voltage in this case is about 1.5V.

As described above, in the above embodiment,
The word line voltage for the three-step write verification is set starting from the level (3.5 V) set closest to the erase level (about 5 volts), and thereafter the voltage value sequentially changes in a direction away from the erase level (3). .5V → 2.5V →
1.5V). In the above embodiment,
As shown in FIG. 7 (B), the highest threshold value (3.2 V) is set for the intermediate or the lowest threshold value (2.2 V, 1.2 V). Writing is performed at the same time as writing to a memory cell. This is one of the features of the present invention. As a result, an increase in multi-value data write processing time can be minimized.

In other words, in addition to the above-described method, as a method of setting the word line voltage for writing and verifying, the writing is performed by targeting the intermediate voltage (2.2 V) of the three threshold voltages at the first time. Then, a method of changing the setting so as to target a higher level (3.2 V) or a lower level (1.2 V) than the first voltage can be considered. Alternatively, as shown in FIG.
A method is considered in which writing is performed collectively on memory cells having the same target threshold value. However, in these methods, the writing process is complicated and time-consuming, and the time for charging / decharging for changing the word line voltage is also increased, so that the writing / verifying time is longer than that of the present embodiment. turn into.

Next, the read operation of the memory cell will be described with reference to FIGS. For reading data, as shown in FIG. 14, a word line is raised and a voltage of a selected level such as 3.7 V, 2.7 V or 1.7 V is applied to the control gate CG of the memory cell, and via a bit line. By applying a voltage of 1.5 V to the drain. The read operation is executed by writing a command instructing read to the command register 16.

When the read operation is started, first, the read level is set to the highest, 3.7 V, and the word line is activated (step S11). Then, in the selected memory cell, data appears on the bit line in accordance with the word line read voltage level, and the data is read by amplifying the bit line level by the sense latch circuit 13 (step S12). Next, the subsequent processing is divided depending on whether the read operation is the first time, the second time, or the third time (step S13). That is, when the read operation is performed for the first time, the sense latch circuit 13
The read data in the binary data register REG1
(Step S14).

When the transfer of all the read data in the sense latch circuit 13 is completed, the process returns from step S15 to S11, the read level is set to 2.7 V, the second data read is performed, and the binary data is read. Transfer to register REG2. When the second data read and transfer are completed, the read level becomes 1.7 V
And the third data read is performed, and the process proceeds from step S13 to S16 to directly transfer the read data to the inverse conversion logic circuit 14. Further, the data held in the binary data registers REG1 and REG2 are transferred one bit at a time to the inverse conversion logic circuit 14, where a logical operation for converting the quaternary data to two bits is performed (step S17). Then, the above procedure (S16 to S18) is repeated until the transfer and conversion of all data in the sense latch circuit 13 is completed, and the read operation is completed. The data conversion is obtained by executing the operation of FIG.

FIG. 9 shows the control clock CLK2 and the sense latch circuit 1 during the read operation according to the above procedure.
3 shows the timing of the data transferred from No. 3 and the read level of the word line. When a read command and an address are given from the outside, a read operation is started. First, a first read level (3.7 V) is set and a word line is activated, so that data appears on a bit line. The data "c" appearing at the first word line level of 3.7 V is read by the sense latch circuit 13, and has a first binary data register having the same data width as the data length of the sense latch, n bits. Data is transferred to REG1. Next, the data “d” obtained by lowering the word line voltage level by a predetermined value and setting the second read level to 2.7 V is transferred to the second binary data register REG2. The data "f" obtained by lowering the word line to the third read level 1.7V is transferred to the inverse conversion logic circuit 14, and the four-value data "c", "d", and "f" are converted into two bits. The data is restored and output to, for example, an external CPU.

FIG. 10 shows an example of the overall configuration of a multi-level flash memory MDFM provided with the above data conversion / inversion function circuit on the same semiconductor chip, and the relationship between the controller and the controller CONT connected thereto. I have. The controller CONT only needs to have an address generation function and a command generation function for the multilevel flash memory of this embodiment, so that a general-purpose microcomputer can be used.

In FIG. 10, circuit portions denoted by the same reference numerals as those in FIG. 4 are circuits having the same functions. That is, REG1 and REG2 are binary data registers for taking in 2-bit write data from the controller, 11 is a data conversion logic circuit for converting the taken-in 2-bit data into quaternary data, and 12 has a floating gate like FAMOS. A memory array in which nonvolatile memory elements are arranged in a matrix, 13 is a sense latch circuit that holds read data and write data, and 14 converts quaternary data read from the memory array into original 2-bit data. Inversion logic circuit, 16
Is a command register for holding a command given from the controller CONT, 17 is a command decoder for decoding a command code fetched in the command register 16, and 18 is a control signal for each circuit in the memory to execute processing corresponding to the command. Are sequentially formed and output.

Although not particularly limited, the multilevel flash memory of this embodiment is provided with two memory arrays, and a sense latch circuit 13 is provided corresponding to each of the two memory arrays. Each sense latch circuit 13 is configured to simultaneously amplify and hold data of one row of memory cells sharing a word line in each memory array, and hold the data in the two sense latch circuits 13, 13. The read data thus selected is selected by the common Y decoder circuit 15 and transferred to the output register 19 bit by bit or in units of bytes. The read data held in the output register 19 is output to an external CPU or the like via the buffer circuit 22. Since the sense latch circuit 13 of the embodiment of FIG. 4 performs a shift operation when transferring data, the same function as the shift register is required. However, the data is selected by the Y decoder circuit 15 as shown in FIG. And this Y
With the configuration in which the decoder circuit 15 shifts the selected bit by the clock, the sense latch circuit 1
3 may not require a shift function.

The multi-level flash memory of this embodiment includes:
In addition to the above circuits, the sense latch 1
3, a reset signal RES, a chip select signal CE, a write control signal WE, and an output control signal O, which are supplied from the controller CONT to determine whether the data read to No. 3 is all "0" or all "1".
E, a system clock SC, a buffer circuit 21 for receiving an external control signal such as a command enable signal CDE for indicating a command input or an address input, a buffer circuit 22 for receiving an address signal, a command signal, and a data signal, and the external control signal. , An internal signal generating circuit 23 for forming a control signal for an internal circuit, an address register 24 for storing an address fetched by a buffer circuit 22, a data register 25 for storing input data, and a memory for decoding a fetched address. X address decoders 26a and 26b for forming a signal for selecting a word line in the array 12, a word driver 27, and an internal power supply for generating a voltage required inside the chip such as a substrate potential, a write voltage, a read voltage, and a verify voltage. Circuit 28, operation of memory Supplied to the word driver 27 and the like by selecting a desired voltage from these voltages according to the state switching circuit 29, an internal clock (CLK2, etc.)
, A timer circuit 31 that counts clocks to give a time such as a write pulse width, a status register 32 indicating a memory control state by the sequencer 16, and a Y address counter 33 that automatically updates a Y address. A defective address register 34 for holding the position (address) of the defective bit, a redundant comparison circuit 35 for comparing the Y address with the defective address, and a relief destination address for switching a selected memory column when the address matches. A register 36 and the like are provided. Further, the multi-level flash memory of this embodiment is configured to output a ready / busy signal R / B * indicating the state of the memory as to whether or not it can be accessed from outside.

Further, the multi-level flash memory of this embodiment has a function (hereinafter, referred to as a refresh function) to sharpen the peak of the variation distribution of the threshold value (see FIG. 3) due to disturbance or retention. It has. This refresh function is made to work by receiving a command from the outside similarly to writing and erasing. When a refresh command is taken into the command register 16, the sequencer 18 of the microprogram control system is activated and refresh is performed. It is configured to do so. This refresh operation will be described later in detail. The signal indicating the determination result of the all determination circuit 20 is configured to be supplied to the sequencer 18, and the all determination circuit 2 is provided in the refresh mode.
When 0 determines all “0” of the read data and a signal indicating the determination result is supplied to the sequencer 18, the sequencer 18 stops the refresh operation. In addition, the sequencer 18 is configured to stop the erasing operation when the all determination circuit 20 determines all “1” of the read data at the time of data erasing.

In this embodiment, a decoder of the X address system adopts a pre-decoding method in which an address signal is decoded in two stages by a pre-decoder 26a and a main decoder 26b.
The upper three bits of the address are first decoded, and the word driver 27 is controlled by the predecode signal to select a desired word line. By adopting such a predecoding method, the main decoder 26b
Are arranged in accordance with the word line pitch of the memory array to increase the degree of integration and reduce the chip size.

The multi-level flash memory according to the above-described embodiment includes functional circuits 11 and 14 for executing conversion from 2-bit data to 4-level data and vice versa, as shown in FIGS. Although provided on the same silicon substrate, it is also possible to configure as a dedicated controller unit having these functions. In this case, since the multi-value specific function is not mounted on the flash memory chip, the chip area does not increase, and as shown in FIG. 11, a plurality of flash memories MDFM are connected to one controller unit. There is also an advantage that the control can be performed by connecting to the CONT by a bus BUS. This controller unit is configured to have an address generation function and a command generation function in addition to the data conversion / inverse conversion function.

FIG. 15 shows the word line voltage and the substrate potential Vsub.
FIG. 16 shows an example of the configuration of the word drive circuit 27. In FIG. Internal power supply generation circuit 28 receives an internal control signal corresponding to various operation modes generated from sequencer 18 and generates a necessary word line voltage.
The configuration of the internal power supply generating circuit 28 including the word line voltage and the configuration of the switching circuit (word line voltage switching circuit) 29 for receiving the generated voltage are the same as those of the conventional one, and the type of the voltage of the word line is multi-valued. Only increased.

That is, the word line voltage required in the conventional binary flash memory is the read voltage (2.7 V / 0
V), write voltage (-10 V, 0 V), write verify voltage (1.5 V), erase voltage (+10 V, 0 V), and erase verify voltage (4.3 V, 0 V). The word line voltage required in the example multi-level flash memory is a read voltage (3.7 V, 2.7
V, 1.7 V, 0 V), the write voltage (−10 V, 0 V)
V), write verify voltage (3.5V, 2.5V,
1.5V), erase and erase verify voltage (10V,
4.3V, 0V) and refresh voltage (-10V, 1
0V, 3.7V, 3.5V, 2.7V, 2.5V, 1.V
7V, 1.5V, 0V).

The switching circuit 29 receives internal control signals corresponding to various operation modes generated from the sequencer 18 and changes the voltage generated by the internal power supply generation circuit 28 according to the operation mode as shown in FIG. The power is supplied to the power supply terminals P1 and P2 of the configured word drive circuit 27.

The word driver WDRV shown in FIG. 16 employs a word line predecoding method. The inputs of eight voltage selection circuits VOLS1 to VOLS8 are commonly connected to the output node N1 of the logic selection circuit LOGS1, and The inputs of the eight voltage selection circuits VOLS9 to VOLS16 are commonly connected to the output node N2 of the logic selection circuit LOGS2,
Predecode signals Xp1, Xp1 * to Xp8, Xp8 *
Selects each voltage selection circuit. Signals XM, XN and predecode signals Xp1, X
p1 * to Xp8, Xp8 * are address decoders XDCR
(26b). At this time, the voltage selection circuit VO
LS1 to VOLS16 are not selected by the other logic selection circuits if the operation is not selected by the predecode signal, even if the corresponding logic selection circuit LOGS1 or 2 outputs the selection signal of the selection level. The same voltage must be selected and supplied to the word line.

For this purpose, the isolation MOSFETs Q56,
The switch of Q57 is controlled by a predecode signal. Further, the isolation MOSFETs Q56, Q57
Is set to the cut-off state, in order to output a non-selected voltage to the word line,
A pull-up MOSFET Q58 and a pull-down MO that are switch-controlled in a complementary manner to ETQ56 and Q57 so that a predetermined voltage can be supplied to each input of the output circuit INV2.
SFET Q59 is provided.

In FIG. 16, the signal XM is regarded as a 3-bit signal indicating which group of word lines is to be selected from a group of eight word lines including eight word lines. . Predecode signals Xp1, Xp1 * to Xp
8, Xp8 * is regarded as a complementary signal indicating which word line included in each word line group is to be selected. According to the present embodiment, the selection signal SEL is set to the high level as the selection level, and the predecode signals Xp1, Xp1 * to Xp8,
Each of Xp8 * has a high level and a low level as selection levels.

The voltage supplied to the terminal P1 of the word driver WDRV is 5V, 4.3V, 3.7V, 3.5V, used for erasing, writing, verifying, and reading.
A voltage Vpp such as 2.7V, 2.5V, 1.7V, 1.5V, 0V, and a voltage supplied to the terminal P2 is a voltage Vee such as -10V used for writing and refreshing, 0 V as ground potential or reference potential
Voltage Vss.

Each of the above logic selection circuits LOGS1, LOGS
2 includes an inverter INV1 for inverting the signal of the X decoder XDCR, a transfer gate TG1 for transmitting or blocking the output thereof, and a transfer gate TG2 for transmitting or blocking the signal of the X decoder XDCR.

The voltage selection circuits VOLS1 to VOLS1
6 have the same configuration, and like the voltage selection circuit VOLS1 whose details are typically shown, the terminals P3 and MO
An N-channel pull-up MOSFET Q58 switch-controlled by a predecode signal Xp1 * provided between the gate of the SFET Q52, a terminal P4 and a MOS
A P-channel type pull-up MOSFET Q59 switch-controlled by a predecode signal Xp1 provided between the gate of the FET Q53 and an M
The OSFET Q56 is switch-controlled by the predecode signal Xp1, and the other isolation MOSFET Q57 is switch-controlled by the predecode signal Xp1 *. A voltage Vcc is applied to the terminals P3 and P4.
Alternatively, Vss is supplied.

Next, the operation of the word driver WDRV shown in FIG. 16 will be described. Table 1 shows the terminal P in each operation mode.
Voltages of 1 to P4 and word line voltages are shown. A description of how to set each of the write mode, the erase mode, and the read mode is omitted.

[0056]

[Table 1] When the erase mode is instructed by the command, the voltage Vpp is applied to the terminal P1, the voltage Vss is applied to the terminal P2, and the voltage Vcc is applied to the terminals P3 and P4.
9 and the control signal DE is set to the low level. In addition, by setting the signal XM to the low level of all the bits, it becomes possible to select any one of the word lines W1 to W8. Thus, when the selection signal (SEL) of the selection level (high level) is supplied, the inverter I
The node N1 goes low through the NV1 and the transfer gate TG1, and this is supplied to the inputs of the respective voltage selection circuits VOLS1 to VOLS8. When the memory cell to be erased is a memory cell coupled to word line W1, predecode signals Xp1 and Xp1 *
Of Xp8 and Xp8 *, only Xp1 and Xp1 * are set to high level and low level. Therefore, for separation M
In the OSFETs Q56 and Q57, only the voltage selection circuit VOLS1 is turned on, and the signal of the node N1 is taken in only the voltage selection circuit VOLS1. At this time, the pull-up MOSFET Q58 and the pull-down MOSFET Q59 of the voltage selection circuit VOLS1 are both cut off.

As a result, the gates of the MOSFETs Q52 and Q53 of the voltage selection circuit VOLS1 are connected to the node N
1 signal is supplied. Thereby, the output circuit INV
The second MOSFET Q52 is turned on, and the word line W1 starts to be charged by the voltage Vpp of the terminal P1.
At this time, the low level supplied to the gate of the other MOSFET Q53 is initially set to a low level higher than the voltage Vss by the operation of the MOSFET Q57,
Although the FET Q53 is not completely cut off, the feedback MOSF is increased as the level of the word line W1 rises.
By increasing the conductance of the ETQ55, the gate of the MOSFET Q53 is forced to the voltage Vss, and the MOSFET Q53 is completely cut off. Therefore, in the erase mode, the word line W1 to which the selected memory cell is coupled is charged up to Vpp.

When the selection signal SEL is at the high level as described above and the memory cell Q1 of the word line W1 is a non-erased memory cell, the predecode signals Xp1 and Xp1 * are low and high, respectively. Be leveled. Therefore, the isolation MOSFETs Q56 and Q57 of the voltage selection circuit VOLS1 are both turned off, and the signal at the node N1 is not taken into the voltage selection circuit VOLS1. At this time, the pull-up MOSFET Q58 and the pull-down MOSFET Q5 of the voltage selection circuit VOLS1
9 are both turned on.

As a result, the terminals P3 and P3 are connected to the gates of the MOSFETs Q52 and Q53 of the voltage selection circuit VOLS1.
4 via the MOSFETs Q58 and Q59 to supply the Vcc voltage.
The FET Q53 is turned on, and the word line W1 starts discharging toward the voltage Vss via the terminal P2. At this time, since the high level supplied to the gate of the other MOSFET Q52 is lower than the voltage Vcc by the threshold voltage of the MOSFET Q58, the MOSFET Q52 is not completely cut off.
As the level of the word line W1 is lowered by the TQ53, the conductance of the feedback MOSFET Q54 is increased, and the gate of the MOSFET Q52 is forced to Vpp, so that the MOSFET Q52 is completely cut off. Therefore, in the erase mode, the unselected word line W1 is discharged to Vss.

The operation of the word driver circuit WDRV when a write mode is instructed or a read mode is instructed is similar to the operation in the write mode, and therefore detailed description is omitted. The word lines are driven such that the voltages shown in FIGS. 13 and 14 are respectively applied to the selected memory cells by the voltages supplied to P1 and P2.

Next, the refresh operation which is the second feature of the multi-level flash memory of the present invention will be described with reference to FIG. In the multi-valued flash memory in which data has been written once, as shown in FIG. 17A, the peaks of the variation distribution of the threshold values are clearly separated from each other. Is repeated, the variation of each threshold value increases as shown in FIG. The causes include, for example, a so-called disturbance in which a memory cell adjacent to a certain memory cell is weakly written when the memory cell is written, and retention due to a natural leak at the time of standby. Although this phenomenon can occur even in a normal flash memory storing only one bit, there is a possibility that a malfunction may occur in a multilevel flash memory in which the intervals between the thresholds are narrow as in the above embodiment. .

Accordingly, in the present embodiment, when the peak of the variation distribution of the threshold value (see FIG. 3) becomes dull, a refresh operation is performed to sharpen the peak. Hereinafter, the procedure of the refresh operation will be described.

FIG. 18 is a flowchart showing the procedure of the refresh operation. When a refresh command is input from an external CPU or the like, the sequencer 18 is started, and a refresh operation according to the flowchart of FIG. 18 is started. When the refresh operation is started, first, an erase pulse weaker than the word line is applied to all the memory cells connected to the selected word line (step S21). By applying the weak erase pulse, the threshold values of all the memory cells are changed as shown in FIG.
Shift a little higher. Although not particularly limited, the shift amount is about 0.2V. Here, the weak erase pulse means a pulse that is sufficiently short so that the threshold value of the memory cell at, for example, “10” does not exceed the immediately preceding read level of 3.7 V as a result of the addition. The pulse width is experimentally determined according to the amount to be shifted.

In the second stage, the word line voltage is set to the read level (3.7 V) corresponding to the storage data "10" and read is performed (step S22). Thereby, data is read according to the threshold value of each memory cell, and is amplified and held by the sense latch circuit 13 (step S23). At this time, the data of the sense latch corresponding to the memory cell having a threshold higher than the word line voltage becomes "1", and the data of the sense latch corresponding to the memory cell having the threshold lower than the word line voltage becomes "1". The data becomes "0". Next, the data of the sense latch is inverted (step S24). This data inversion can be easily performed by the sense latch circuit having the configuration shown in FIG. 20 (described later).

Next, a verify voltage (at first, 3.5 V) lower than the above-described read (step S22) is set to the word line, and the threshold value is determined (step S22).
25). As a result, the data of the sense latch corresponding to the memory cell having a threshold lower than the verify voltage (reference A in FIG. 17D) changes from “1” to “0”.
On the other hand, the data of the sense latch corresponding to the memory cell having the threshold higher than the verify voltage (reference B in FIG. 17 (4)) remains “1”. In the present embodiment, this is determined as a rewriting target. As a result, a memory cell that has been too close to the read level (3.7 V) when the threshold value has been shifted to a higher side due to the weak erasure in step S21 is specified. At this time, the data of the sense latch corresponding to the memory cell (reference numeral C in FIG. 17 (4)) corresponding to the storage data "11" having the highest threshold value is "0" set by the inversion operation. Will be left. Such an operation can be automatically performed by the sense latch circuit having the configuration shown in FIG. 20 (described later).

Therefore, next, a write voltage is set and the memory cell in which the data of the sense latch is "1" (FIG. 17).
(4) Rewrite the code B) (Step S2)
7). Thereafter, verify is performed by setting a verify voltage corresponding to the write level (steps S28 and S2).
9). When the threshold value becomes lower than the verify voltage, the latch data changes from “1” to “0”. Until all the latch data changes to "0", the writing and the verification are repeated, and the refresh processing of the memory cell of "10" data is completed (step S30). As a result, the variation distribution (half width) of the threshold value of the memory cell of “10” data is reduced as shown in FIG.
Thereafter, the same refresh processing is performed on the memory cells storing the data "01" and "00" (step S31). Further, in order to further narrow the width of the threshold distribution shape, steps S21 to S31 are repeated, and refreshing is completed when a predetermined number of times have been completed (step S32).

Table 2 shows that, when refreshing is performed according to the above-described procedure, the sense latches when reading out memory cells having threshold values indicated by reference numerals A, B, and C in FIG. Changes in the data held in the circuit are shown in order.

[0068]

[Table 2] FIG. 19 is a diagram showing timing for executing the refresh operation. As described above, the cause of the increase in the variation in the threshold value of the memory cell is that when a write / read operation is performed on an adjacent memory cell, a weak write / erase or read operation is performed on the adjacent memory cell. And retention due to natural leaks.

The execution timing of the refresh operation for the fluctuation of the threshold value due to the disturbance is as follows: (1) The flash memory is in the standby state (/ RES
Is at a high level), and after a certain number of write / erase and read operations are completed, a refresh operation is executed. (2) Refresh is executed immediately after the reset signal (/ RES) is activated at the time of reset. (3) The refresh is executed immediately after the reset state by setting / RES to low level from the standby state. (4) Immediately before turning off the power supply, / RES is set to a low level in advance, and this is sensed to execute refresh. (3) After the power is turned on and / RES is set to the high level, the refresh is executed. And so on.

On the other hand, as a countermeasure against the decrease in the threshold value due to the retention, it is conceivable to execute the refresh in the middle of a dummy cycle at power-on or at regular intervals in a standby state. All of these refresh timings may be executed, or one or some of them may be executed.

The refresh operation described above is not limited to the multilevel flash memory. If the power supply voltage of the flash memory shifts to a lower voltage in the future,
Even in a normal flash memory, the increase in the variation of the threshold value cannot be ignored, and this is an effective function for reducing the power supply voltage of the flash memory.

FIG. 20 shows a configuration example of the memory array 12 and the sense latch circuit 13. The memory array 12 includes a common drain line DL arranged in a direction orthogonal to the word lines and arranged in parallel with a bit line BL from which a read signal of a selected memory cell is output, and a common source line S
A plurality of memory cells MC (for example, 128 corresponding to 128 word lines that can be collectively erased) are connected in parallel between the memory cells MC and L. Common drain line DL
Can be connected to the corresponding bit line BL via a switch MOSFET Q1, and the common source line SL can be connected to a ground point via a switch MOSFET Q2. These switch MOSFETs Q1, Q2
Is formed based on the X address signal and the read / write control signal, and is set to a potential such as Vcc (3.3 V) at the time of data reading (including at the time of verifying), whereby the switch MOSFET is turned on. Q1 and Q2 are turned on, and the bit lines are discharged through the memory cells in the on state. On the other hand, at the time of data writing, the gate control signal of the switch MOSFET Q1 is set at 7 to transmit the write voltage (5 V) of the bit line to the drain of the memory cell.
A potential such as V is set, and Q1 is turned on. At this time, the switch MOSFET Q2 on the common source line SL side is turned off.

The sense latch circuit 13 is constituted by a CMOS differential sense amplifier SA provided corresponding to each memory column and amplifying the potential difference between the bit lines of the left and right memory arrays. Prior to reading, the bit line of the memory array on the selected side (the left side in the figure) is set to a precharge MOS (S
W21) is precharged to a potential such as 1 V,
The bit line in the memory array on the opposite side is
Precharged to a potential such as 0.5 V by S (SW22).

When the word line WL is set to the read level in the precharge state, the bit line maintains 1.0 V if the selected memory cell has a high threshold value. If the bit line has a low threshold value, a current flows and the charge of the bit line is extracted, so that the bit line has a potential of 0.2V. This 1.0 V or 0.
The sense amplifier SA detects and amplifies a potential difference between 2V and the potential 0.5V of the bit line on the opposite side, so that read data is held in the sense amplifier SA.

In the above embodiment, as described above,
"1" is set in a sense latch (sense amplifier) corresponding to a bit line to which a memory cell to be written is connected, a write pulse (-10 V) is applied to a word line, and then a verify operation according to the write level is performed. A voltage (approximately 3.5 V for the first time) is set to the word line, and the memory cell to which the write pulse has been applied is read.
Then, since "1" is read as read data to the bit line from the memory cell with insufficient writing, it is determined whether writing is completed or insufficient by looking at the read data. ) Is inverted to "0". That is, "1" is left as data in a sense latch (sense amplifier) corresponding to a memory cell with insufficient writing, and a write pulse is again applied to a memory cell with insufficient writing corresponding to a bit with "1". It is applied.

Also in the refresh operation, the data read into the sense latch is inverted, verify is performed, and a write pulse is applied to the memory cell corresponding to the bit where "1" is set. I have.

In the sense latch circuit of FIG. 20, it is easy to invert the latch data of the sense amplifier corresponding to the write-completed memory cell and to narrow down the memory cells to which the write pulse is to be applied at the time of writing as described above. For this purpose, four switches SW11, SW12, S are provided between the sense amplifier and the memory array.
A device such as an inversion control circuit 30 including W13 and SW14 is provided. Hereinafter, the operation of the sense latch circuit will be described. The switches SW21 and SW22 provided on each bit line BL are switches for precharging the bit lines.
It is composed of a MOSFET together with W11 to SW14.

At the time of data reading, first, the switch SW13 is turned off, and as shown in FIG.
With the L and the sense amplifier SA disconnected, the switches SW21 and SW22 are turned on to select the bit line BL on the selected side.
To a precharge level such as 1.0V. At this time, the unselected bit lines are charged to a level such as 0.5V. The sense amplifier SA is connected to the switch SW14.
Is turned on to bring it into a reset state, and a potential such as 0.5 V is applied in advance. Further, at this time, the switch MO
A voltage such as Vcc is applied to the gates of the SFETs Q1 and Q2 to turn on Q1 and Q2.

Then, any one of the word lines WL in the memory array 12 is set to a selection level such as 3.7V. Then, memory cells (for example, cells A and B in FIG. 17) whose threshold value is lower than the word line selection level are turned on, and the bit line BL to which the cell is connected is
When a current flows toward the common source line SL through the memory cells in the ON state, the current is discharged to a level such as 0.2 V. On the other hand, a memory cell whose threshold value is higher than the word line selection level (for example, cell C in FIG. 17) is turned off, and the bit line BL to which the cell is connected maintains the precharge level of 1.0 V. .

Next, the switch SW14 is turned off to release and activate the reset state of the sense amplifier SA, and the switch SW13 on the bit line BL is turned on to connect the bit line BL to the sense amplifier SA. The power supply voltage Vcc is applied to the P-MOS side of the sense amplifier SA.
And the ground potential (0 V) is supplied to the N-MOS side.
Then, after the sense amplifier SA sufficiently amplifies the potential difference between the bit lines BL and BL *, the switch SW on the bit line BL
13 is turned off. As a result, the sense amplifier SA amplifies the level difference between the bit lines on the selected side and the non-selected side, and enters a state where the data is held.

When inverting the latch data of the sense amplifier SA, the switch SW13 is turned off, and FIG.
As shown in FIG. 7, in a state where the bit line BL and the sense amplifier SA are disconnected, the switches SW21 and SW22 are turned on to set the selected and unselected bit lines BL to Vcc-V.
The precharge is performed to a level such as tn (for example, 3.3 V-0.6 V = 2.7 V). Then, the switch S
W21 and SW22 are turned off and switch SW11 is turned on. Then, according to the data held in the sense amplifier SA, if the data is “1”, the switch SW12 is turned on, and the bit line BL is discharged to the bit line inversion level (0 V). On the other hand, if the data held in the sense amplifier SA is “0”, the switch SW
12 is turned off, the bit line BL is connected to Vcc
Maintain levels. That is, the inverted level of the data held by the sense amplifier SA appears on the corresponding bit line BL.

Here, after once turning on the switch SW14 to reset the sense amplifier SA, the switch SW14 is turned on.
14 is turned off and the switch SW13 on the bit line BL is turned on to connect the bit line BL and the sense amplifier SA. During this time, the P-MOS side of the sense amplifier SA and N
-The power supply voltage on the MOS side is set to 0.5V. Then, the power supply voltage Vc is applied to the P-MOS side of the sense amplifier SA.
and supply the ground potential (0 V) to the N-MOS side, and turn off the switch SW13 on the bit line BL. As a result, as shown in FIG. 22, the sense amplifier SA is in a state of holding data corresponding to the level of the bit line in the inverted data holding state. That is, FIG.
The sense amplifiers corresponding to the cells A and B hold the high level “1”, and the sense amplifiers corresponding to the cell C hold the low level “0”. This is the same operation as the so-called write verify. Therefore, the bit line precharge must be performed only when the sense latch is at "H". Then, by turning on the switch SW11 and setting the bit line precharge voltage (1) to 1 V, only the bit lines BL0 and BL1 become 1 V (BL
2 is reset to 0 V in advance).

Next, the switch SW13 on the bit line BL
While the switches are turned off, the switches SW21 and SW22 are turned on to charge the selected bit line BL to a precharge level such as 1.0 V and the non-selected bit line BL to a level such as 0.5 V. After that, a verify voltage such as 3.5 V slightly lower than the previous read level (3.7 V) is applied to the selected word line. Then, a memory cell whose threshold value is lower than the word line selection level (for example, FIG. 17)
Cell A) is turned on, and the bit line BL to which the cell is connected is discharged to a level such as 0.2V. On the other hand, a memory cell whose threshold value is higher than the word line selection level (for example, cell B in FIG. 17) is turned off, and the bit line BL to which the cell is connected maintains the precharge level 1V. At this time, the bit line to which the memory cell (cell C in FIG. 17) corresponding to the data "11" having the highest threshold value is originally held at the low level, that is, "0",
When the word line is turned to the selected level, it is at the low level even in the off state (FIG. 23).

Therefore, when the switch SW13 on the bit line BL is turned on after resetting the sense latch in this state, the memory cell corresponding to data "11" (FIG. 17)
Of the memory cell (cell A of FIG. 17) corresponding to the bit line to which the cell C) is connected and the memory cell (cell A of FIG. 17) having a threshold lower than the word line selection level. 0 "and a memory cell having a threshold higher than the word line selection level (FIG. 17).
The sense amplifier corresponding to the bit line to which the cell B) is connected holds the high level “1”. In this embodiment, using the data held by the sense amplifier, the operation shifts to the write operation and the write pulse (−1) is applied to the selected word line.
By applying 0 V), the threshold value of the memory cell corresponding to data "1" held by the sense amplifier is lowered.

After the writing pulse is applied, when the word line is again set to the selected level and reading is performed, the level of the bit line of the memory cell whose threshold value is lower than the word line verify level becomes low level, ie, "0". In other words, the bit line to which the insufficiently written memory cell is connected maintains the high level “1”. Therefore, by latching this with a sense amplifier and writing again, the threshold value of only the memory cell whose data held in the sense latch corresponds to "1" can be lowered, and the distribution shape of the threshold value can be sharpened. . The data held by the sense amplifier SA is supplied to the above-described all determination circuit 20 through a so-called column switch that is turned on and off by an output signal of the Y decoder 15 and a common I / O line, and whether the data is all “0” is determined. Is determined. Then, when all become "0", the refresh for the memory cell of data "10" is ended, and the refresh for the memory cells of data "01" and "00" is performed.

Note that the rewrite operation for the insufficiently written memory cell in the above-described write mode is the same as the above-described write operation by the sense latch circuit 13 during the refresh operation.

As described above, in the above embodiment, at the time of data writing, a plurality of bits of data are converted by the data conversion logic circuit into data (multi-valued data) corresponding to the combination of the bits, and the converted data is written. Is sequentially transferred to the latch circuit connected to the bit line of the memory array, and a write pulse is generated in accordance with the data held in the latch circuit and applied to the selected storage element, thereby supporting multi-value data. At the time of data reading, the read voltage is changed to a value between the respective thresholds, the state of the storage element is read, and transferred to a register for storing multi-valued data to be held. The original data is restored by the inverse data conversion logic circuit based on the multi-valued data stored in the register. The size of the peripheral circuit of the ray can be kept relatively small, and in the write operation, the verify voltage value of the word line is sequentially changed by a predetermined value in a direction away from the side closer to the word line voltage for erasing. As a result, the total number of write pulses, that is, the write time, can be reduced as compared with the multi-level flash memory system in which the verify voltage is set at random,
There is an effect that a writing operation in a short time can be realized.

After performing a weak erase operation on the storage elements in the memory array, a storage element having a threshold value lower than the read level and higher than the verify level on the word line is detected and the storage element is detected. Is performed so that the threshold voltage of the storage element becomes lower than the verify voltage so as to reduce the spread of the variation distribution shape of the threshold voltage of the storage element written corresponding to each input data. Therefore, there is an effect that the variation distribution shape of the threshold voltage of the storage element, which has been spread due to the disturbance, the retention, or the like, can be returned to a steep shape almost equal to that immediately after the completion of the writing.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say. For example, in the above embodiment, the threshold value of one memory cell is set to four levels to store four-level data.
The threshold value can be set in three steps or five or more steps.

Further, in the embodiment, the inversion of the read data at the time of refresh, the narrowing down of the memory cells to be written, and the like can be performed using only the sense latch circuit. However, the register holding the read data and the contents thereof are used. A logic circuit may be provided for performing a logical operation such as inverting the above and narrowing down the memory cells to be written.

Further, in the embodiment, a method of converting 2-bit data into quaternary data and its inverse conversion are shown in FIG.
Although three types of operations are performed as shown in (2), the logical operation is not limited to that shown in FIG. 1, and as a result, data having different numbers of bits having "1" is obtained. I just need. Further, the operation for the inverse data conversion is not limited to that shown in FIG. 2, and any operation may be used as long as it can restore the original 2-bit data. It may be above.

The writing method for each memory cell is not limited to the method of once erasing and raising the threshold value and then lowering the threshold value by the writing pulse as in the embodiment, but the method of increasing the threshold value by the writing pulse is used. Or the like. In the embodiment, the threshold value is changed by writing to the memory cell corresponding to the sense latch holding the data “1”, but the memory cell corresponding to the sense latch holding the data “0” is changed to the threshold value. The threshold value may be changed by performing writing.

In the above description, the case where the invention made by the present inventor is mainly applied to a batch erasing type flash memory, which is the field of application, has been described. However, the present invention is not limited to this. FAMO
The present invention can be widely used in general non-volatile storage devices using S as a storage element, and also in semiconductor storage devices including memory cells having a plurality of threshold values.

[0094]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to realize a multi-value storage type nonvolatile storage device capable of minimizing an increase in circuit scale and performing a high-accuracy write, read, and erase operation in a short time, and a memory element. It is possible to realize a non-volatile memory device capable of performing a stable operation at a low voltage by sharpening a threshold variation distribution shape.

[Brief description of the drawings]

FIG. 1 is written to one memory cell according to the present invention /
FIG. 9 is an explanatory diagram showing an embodiment of an operation for converting 2-bit data to be read into 4-level data which is a level physically written / read to / from each memory cell.

FIG. 2 is an explanatory diagram showing an embodiment of an operation for inversely converting quaternary data converted by a data conversion logic circuit into original 2-bit data.

FIG. 3 is an explanatory diagram showing a relationship between the quaternary data and a threshold value of a memory cell.

FIG. 4 is a block diagram schematically showing an embodiment of a multi-level flash memory according to the present invention.

FIG. 5 is a flowchart illustrating a writing procedure of the multi-level flash memory according to the embodiment;

FIG. 6 is a timing chart showing a write operation waveform of the multilevel flash memory of the example.

FIG. 7 is an explanatory diagram showing the difference between the writing method of the multilevel flash memory of the embodiment and another writing method, and shows operation waveforms.

FIG. 8 is a flowchart showing a reading procedure of the multilevel flash memory according to the embodiment.

FIG. 9 is a timing chart showing a read operation waveform of the multilevel flash memory of the example.

FIG. 10 is a block diagram illustrating a configuration example of the entire multi-level flash memory according to the embodiment;

FIG. 11 is a block diagram illustrating a configuration example of a system in an embodiment in which a controller has a function of converting between 2-bit data and quaternary data unique to a multi-level memory.

FIG. 12 is a schematic diagram showing a structure of a memory cell used in a flash memory of an example and a voltage state at the time of writing.

FIG. 13 is a schematic diagram showing a voltage state at the time of erasing a memory cell used in the flash memory of the example.

FIG. 14 is a schematic diagram showing a voltage state at the time of reading of a memory cell used in the flash memory of the example.

FIG. 15 is an explanatory diagram showing an internal power supply generating circuit and a switching circuit for selecting a generated voltage and supplying the selected voltage to a word drive circuit and the like.

FIG. 16 is a circuit diagram showing a configuration example of a word drive circuit.

FIG. 17 is an explanatory diagram showing a refresh method of the multi-level flash memory according to the embodiment.

FIG. 18 is a flowchart illustrating a refresh procedure of the multi-level flash memory according to the embodiment.

FIG. 19 is a timing chart showing operation waveforms at the time of refresh execution.

FIG. 20 is a circuit diagram illustrating a configuration example of a sense latch circuit according to an embodiment;

FIG. 21 is a circuit state diagram showing the operation of the sense latch circuit at the start of data inversion.

FIG. 22 is a circuit state diagram showing the operation of the sense latch circuit at the end of data inversion.

FIG. 23 is a circuit state diagram at the time of verification showing the operation of the sense latch circuit.

[Explanation of symbols]

Reference Signs List 11 data conversion logic circuit 12 memory array 13 sense latch circuit 14 reverse conversion logic circuit REG1, REG2 register XDCR X address decoder WDRY word drive circuit LOGS logic selection circuit VOLS voltage selection circuit SA sense amplifier BL bit line WL word line MC memory cell A Memory cell for "11" data (threshold about 5 V) B Memory cell for "10" data (threshold about 3.6
V) C "10" data memory cell (threshold value about 3.2
V)

Claims (20)

[Claims] 1. A method for setting a threshold value of a memory cell to three or more levels and changing a word line level to two or more levels to perform reading of a memory cell, so that one memory cell has two or more bits of data. A non-volatile storage device configured to store the input write data, a predetermined operation is performed on a plurality of bits of the input data, and a combination thereof is performed. A non-volatile storage device comprising: a data conversion logic circuit for converting the multi-valued data according to the data; and an inverse conversion logic circuit for converting the multi-valued data read from the memory cell to the original binary data. . 2. The nonvolatile memory device according to claim 1, further comprising a control circuit for sequentially writing the multi-value data to a selected memory cell in a memory array while changing a write voltage. . 3. The method according to claim 1, wherein the word line voltage in the write verify and read operations is sequentially changed in a direction away from a set voltage closest to the word line voltage for erasing. Nonvolatile storage device. 4. A method of setting a threshold value of a memory cell to three or more levels and changing a word line level to two or more levels to perform reading of a memory cell, so that two bits or more of data can be stored in one memory cell. A binary data register for holding write data, a predetermined operation being performed on a plurality of bits of input data, and a set of the binary data register and the binary data register. A data conversion logic circuit for converting the multi-valued data according to the combination, and an inverse conversion logic circuit for converting the multi-valued data read from the nonvolatile storage device to the original binary data. A control device for a nonvolatile storage device. 5. A method of setting a threshold value of a memory cell in two or more stages and changing a word line level in two or more stages to perform reading of a memory cell, so that two or more bits of data can be stored in one memory cell. A first binary data register that holds input write data, and performs a predetermined operation on a plurality of bits of the input data to execute a predetermined operation. A data conversion logic circuit for converting to multi-valued data according to the combination; and a second binary data register for holding data read out from the memory cell, and based on the multi-valued data read from the memory cell. And a reverse conversion logic circuit that converts the binary data into binary data. 6. The nonvolatile memory device according to claim 5, further comprising a control circuit for sequentially writing the multi-value data to a selected memory cell in a memory array while changing a write voltage. . 7. The method according to claim 5, wherein the word line voltage in the write verify and read operations is sequentially changed in a direction away from a set voltage closest to the word line voltage for erasing. Nonvolatile storage device. 8. A method of setting a threshold value of a memory cell in two or more steps and changing a word line level in two or more steps to perform reading of a memory cell, so that two bits or more of data can be stored in one memory cell. A first binary data register for holding write data, and a predetermined operation for a plurality of bits of input data. A data conversion logic circuit for converting the data into multi-valued data according to a combination thereof; and a second binary data register for holding data read from the nonvolatile storage device. And a reverse-conversion logic circuit for converting the outputted multi-valued data into original binary data. Device. 9. A memory array having a plurality of memory cells capable of electrically writing and erasing and capable of holding three storage states “0”, “1”, and “2”; A write circuit for performing a write operation on the memory cell to change a storage state, wherein the write circuit sets the storage state to “1” when the memory cell holds the storage state “2” And a write operation for changing the storage state from "1" to the storage state "2". 10. Electrically erasable writing and erasing,
Three storage states “0”, “1”,
A memory array having a plurality of memory cells capable of holding “2”; and a write circuit for performing a write operation on the memory cells to change the storage state of the plurality of memory cells, and corresponding to “1”. The threshold to be performed exists between the threshold corresponding to “0” and the threshold corresponding to “2”, and the write circuit holds the memory state “2” in the memory cell. In this case, after performing a write operation for changing the storage state to "1", a write operation for changing the storage state from "1" to the storage state "2" is further performed. apparatus. 11. The memory according to claim 1, wherein said write circuit is adapted to store information in a plurality of memory cells in a state of "0".
After changing only a part of the plurality of memory cells in the state "1" to the state "1", and then changing only a part of the plurality of memory cells in the state "1" to the state "2". 11. The semiconductor memory device according to claim 10, wherein a write operation is performed. 12. Electrically erasable writing and erasing,
Three storage states “0”, “1”,
A memory array having a plurality of memory cells capable of holding “2”; and a write circuit for performing a write operation on the memory cells to change the storage state of the plurality of memory cells, and corresponding to “1”. The threshold value to be set exists between the threshold value corresponding to the above “0” and the threshold value corresponding to the above “2”, and the write circuit includes a plurality of memory cells in the “0” state. When information is stored in the memory cell, only a part of the plurality of memory cells in the “0” state is changed to the “1” state, and then one of the plurality of memory cells in the “0” state is changed. A semiconductor memory device performing a write operation for changing only a portion to a state of "2". 13. Electrically erasable and erasable,
Three storage states “0”, “1”,
A memory array having a plurality of memory cells capable of holding “2”; and a write circuit for performing a write operation on the memory cells to change the storage state of the plurality of memory cells, and corresponding to “1”. The threshold value to be set exists between the threshold value corresponding to the above “0” and the threshold value corresponding to the above “2”, and the write circuit includes a plurality of memory cells in the “0” state. A semiconductor memory device, wherein at least two write operations are performed when information is recorded in a state where "0", "1", and "2" are mixed. 14. The semiconductor memory device according to claim 13, wherein at least one verify operation is performed between said at least two write operations. 15. Electrically erasable writing and erasing,
Three storage states “0”, “1”,
A memory array having a plurality of memory cells capable of holding “2”; and a write circuit for performing a write operation on the memory cells to change the storage state of the plurality of memory cells, and corresponding to “1”. The threshold value to be set exists between the threshold value corresponding to the above “0” and the threshold value corresponding to the above “2”, and the write circuit includes a plurality of memory cells in the “0” state. In the case where information is recorded in the memory cell and "0", "1", and "2" are mixed, the memory cell in the state of "0" is changed to the state of "1". A semiconductor memory device, comprising: performing a write operation and a write operation of changing a memory cell in a “1” state to a “2” state in this order. 16. A first verify operation is performed between the first write operation and the second write operation, and the second verify operation is performed.
16. The semiconductor memory device according to claim 15, wherein a second verify operation is performed after said write operation. 17. The semiconductor memory device according to claim 16, wherein said first verify operation and said second verify operation have different threshold values for detecting a threshold value of a memory cell. 18. A memory array having a plurality of memory cells holding three different storage states by at least three threshold voltages, and data holding for holding data corresponding to the storage states of the plurality of memory cells. And a write circuit for performing a write operation on the memory cell in accordance with the contents of the data holding circuit. A semiconductor memory device, wherein a verify operation is performed with a verify voltage, and a verify operation is performed with a plurality of verify voltages when setting the second threshold voltage. 19. The method according to claim 19, wherein writing and erasing are enabled electrically.
Three storage states “0”, “1”,
A memory array having a plurality of memory cells capable of holding “2”; and a write circuit for performing a write operation on the memory cells to change the storage state of the plurality of memory cells, and corresponding to “1”. The threshold value to be set exists between the threshold value corresponding to the above “0” and the threshold value corresponding to the above “2”, and the write circuit includes a plurality of memory cells in the “0” state. When the information is recorded in the memory cell and "0", "1" and "2" are mixed, a first verify operation for confirming whether or not the memory cell is in the "1" state is performed. A second verify operation for checking whether or not the memory cell is in the state of "2" in this order. 20. A method of electrically writing and erasing data, comprising:
Three storage states “0”, “1”,
A memory array having a plurality of memory cells capable of holding “2”; and a write circuit for performing a write operation on the memory cells to change the storage state of the plurality of memory cells, and corresponding to “1”. The threshold value exists between the threshold value corresponding to “0” and the threshold value corresponding to “2”, and information is recorded in a plurality of memory cells in the “0” state. Then, when the state where "0", "1", and "2" are mixed is present, a first verify operation for confirming whether the memory cell is in the state of "1" and the memory cell Performs a second verify operation to confirm whether or not is in the state of “2”. When reading the storage state from the memory array in which “0”, “1” and “2” are mixed, First reading for reading the state of “1” of the memory cell Performing a read operation and a second read operation for reading the state of “2” of the memory cell. A first voltage is used for the first read operation, and a second voltage is used for the first verify operation. And the third voltage is used in the second read operation, the fourth voltage is used in the second verify operation, and the first to fourth voltages are set in descending order or in increasing order. An access method for a semiconductor memory device, characterized in that: