JP2003196990A - Semiconductor nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-level storing type nonvolatile memory in which increment of circuit scale is suppressed to the minimum, and highly accurate write, read, and erasure operation can be realized in a short time. <P>SOLUTION: A nonvolatile semiconductor constituted so that data of two bits or more are stored in one memory cell by setting a threshold value of a memory cell to three stages or more, while by varying a level of a word line by two stages or more, and performing read of the memory cell, is provided with a first external terminal to which binary data to be stored are supplied in serial, a plurality of memory cells of which threshold voltage can be varied electrically and which holds data as a value of threshold voltage, and a means coupled to the external terminal and the plurality of memory cells, converting a plurality of binary data supplied in serial to multi-level data, and writing them to the memory cell. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique which is particularly effective when applied to a storage system for multi-valued information in a semiconductor memory device, and further in a non-volatile semiconductor memory device. For example, a plurality of stored information can be electrically erased at once. The present invention relates to a technique effectively used for a semiconductor non-volatile memory (hereinafter, simply referred to as a flash memory).

[0002]

2. Description of the Related Art A flash memory uses a non-volatile memory element having a control gate and a floating gate as a memory cell, like a FAMOS.
A memory cell can be configured with individual transistors. In such a flash memory, in the write operation, by setting the drain voltage of the nonvolatile memory element to about 5 V and the word line connected to the control gate to about −10 V as shown in FIG. The electric charge is extracted from the device, and the threshold voltage is low (logic “0”). In the erase operation, as shown in FIG. 13, the P-type semiconductor region pwell
Is set to about −5 V, the word line is set to about 10 V to generate a tunnel current, and negative charges are injected into the floating gate to set the threshold value to a high state (logic “1”).
As a result, one memory cell stores 1-bit data.

By the way, in order to increase the storage capacity, 1
The concept of a so-called "multi-valued" memory has been proposed in which two or more bits of data are stored in a memory cell. An invention relating to this multi-valued memory is disclosed in JP-A-59-1216
No. 96, etc.

[0004]

In the conventional flash memory, the variation of the threshold value is increased due to the weak write (disturb) and the natural leak (retention) which are caused by the write / read / erase operation to the adjacent bits. Half-value width of the variation distribution shape of the threshold values corresponding to the logic "0" and the logic "1" (width at the position of 1/2 of the peak value of the mountain-shaped variation distribution as shown in FIG. 3) Is known to grow over time. With the decrease in the power supply voltage of the LSI in the future, the threshold voltage of the memory cell exceeds the voltage margin range for the read voltage due to the spread of the variation distribution shape over time, which may cause a malfunction. The inventor has discovered that.

Particularly, in a multi-valued memory in which a plurality of bits of data are stored in one storage element due to a difference in threshold value, the difference in threshold voltage corresponding to each data is small, so that the above-mentioned problems are remarkable. Become. Further, since the flash memory has erase and write verify operations unique to the non-volatile memory device, there is a technical problem that the processing time and circuit scale unique to the multi-valued memory should be minimized.

An object of the present invention is to provide a multi-value memory type semiconductor non-volatile memory which can minimize the increase of the circuit scale and can realize highly accurate writing, reading and erasing operations in a short time. .

Another object of the present invention is to provide a semiconductor nonvolatile memory having a small number of external terminals.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the binary data to be stored can change its threshold voltage electrically with the first external terminal supplied serially, and the data can be stored as the threshold voltage value. A plurality of memory cells to be held as, and a unit that is coupled to the external terminal and the plurality of memory cells and that converts a plurality of serially supplied binary data into multi-valued data and writes the multi-valued data into the memory cells. I did it.

According to the above-mentioned means, since the binary data is converted into multi-valued data and stored in the memory cell, the circuit size of the memory array can be kept relatively small and stored. Since the first external terminal to which binary data to be supplied is serially supplied is provided, the number of external terminals can be reduced as compared with the case where binary data is supplied in parallel.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to a flash memory will be described below with reference to the drawings. FIG. 1 shows a conversion method of data to be stored inputted from the outside and multi-valued data stored in a memory cell,
Further, FIG. 2 shows an inverse conversion method for restoring original data from multi-valued data.

Although not particularly limited to FIG. 1, one memory cell (one storage element) has two bits, that is, "00" and "0".
An example of the conversion method in the case of storing any one of "1", "10", and "11" is shown.
There are four types of combinations of the binary data “a” and the second binary data “b”, and each combination includes three types of logical operations (aNANDb) shown in FIG.
By performing (NOTb) and (aNORb),
Of the four bits, the number of "1" s is 0, 1, 2,
It is converted into four kinds of four-valued data of three pieces.

If a write operation, that is, a write pulse is applied to the memory elements by the number "1" obtained by the above calculation result, the threshold value of each memory element is changed according to the number of times of writing, as shown in FIG. As shown in 3), there are four types, and 2-bit data can be written in one memory cell. “00” for multiple storage elements in the memory array,
FIG. 3 shows how the threshold distribution of each storage element changes when the same number of data of "01", "10", and "11" are stored.

FIG. 2 shows the principle of data reading. By changing the read voltage of the word line in three steps (intermediate value of each threshold value distribution of FIG. 3), three kinds of data, “c”, “d”, and “f” are read from the same memory cell. It can be read sequentially. Therefore, one (a) of the written 2-bit data can be restored by performing a logical operation (d * NAND f) NAND c * on the read data. In addition, d of the read data matches the write data b as it is. Note that d * and c * represent inverted signals of d and c.

FIG. 4 shows an example of a concrete circuit configuration for conversion into multi-valued data and inverse conversion shown in FIGS. At the time of data writing, data of 2n-bit length supplied from the outside to the multi-level flash memory is serially stored in two binary data registers REG1 and REG2 having a data width of n bits via the switch SW1. At this time, although not particularly limited, the switch SW1 is switched by the output of the flip-flop FF1 operated by the clock CLK1 supplied from the outside, and the clock CL in the frequency dividing circuit DVD is switched.
A clock CLK1 ′ having a cycle twice that of CLK1 obtained by dividing K1 is supplied through the switching circuit CHG, and the binary data registers REG1 and REG2 are shifted in synchronization with the clock CLK1 ′, thereby inputting. Data is alternated bit by bit binary data register RE
It is stored in G1 and REG2.

The data "a" stored in the first binary data register REG1 and the data "b" stored in the second binary data register REG2 are supplied from the internal clock generation circuit 30 via the switching circuit CHG. 1 (2), which is shifted in synchronization with the clock CLK2
Is supplied to the data conversion logic circuit 11 for performing the above operation one bit at a time, and after a predetermined logic operation, is sequentially transferred to the n-bit length sense latch circuit 13 provided on one side of the memory array 12 via the switch SW2, Writing to the memory cells in array 12 is performed. This write operation will be described later in detail.

The switching circuit CHG supplies a clock CLK1 'to the binary data registers REG1 and REG2 at the time of data input by a control signal from the sequencer 18 which controls the internal memory, and when transferring data to and from the sense latch 13. The clock CLK2 from the clock generation circuit 30 to the binary data registers REG1, R
The switching is controlled so as to supply to EG2.

The data conversion logic circuit (data write operation circuit) 11 has the binary data register REG.
1, NAN adapted to receive the data a and b in REG2 at their input terminals and perform the operation (aNANDb)
NO for calculating D gate G1 and (aNORb)
R gate G2 and the binary data register REG2
Of the logic gates G1, G2 and G3 are selected by the switch SW2 to the sense latch circuit 13. Is configured to supply.

On the other hand, when data is read, the read data "c" appearing on the bit line in response to one word line in the memory array 12 being set to the read voltage level is amplified by the sense latch circuit 13. Are latched by the binary data register REG1 through the switch SW3 in synchronization with the internal clock CLK2.
Serially transferred to. Next, the data “d” read by the sense latch circuit 13 with the read voltage level changed is serially transferred to the binary data register REG2 via the switch SW3. Further, the data “f” read by the sense latch circuit 13 with the read voltage level changed is serially transferred to the inverse conversion logic circuit 14 via the switch SW3. At this time, the binary data registers REG1 and REG2 are
It is shifted in synchronization with 2. However, the cycle of the clock CLK2 for reading data is the clock C for writing data.
It may be shorter than the cycle of LK2. The cycle of the clock CLK2 can be generated by the clock generation circuit 30 determined by the control signal from the sequencer 18. The word line read level is also changed according to the control signal from the sequencer 18.

The inverse conversion logic circuit (data read operation circuit) 14 has an inverter G11 to which the data output from the binary data register REG2 is input,
Output of the inverter G11 and the sense latch circuit 1
3, a NAND gate G12 whose input terminal receives the transfer data directly, a delay circuit DLY which delays the data output from the binary data register REG1 and outputs the delayed data at a predetermined timing, and the delay circuit DL.
The read data c, which is composed of an inverter G13 that inverts the output of Y and a NAND gate G14 that receives the output of the inverter G13 and the output of the NAND gate G12 as input, and is held in the binary data registers REG1 and REG2. The logical operation (d * NAND f) NAND c * shown in FIG. 2 is performed on the read data f directly transferred from d and the sense latch circuit 13. The calculation result is output to the data input / output terminal I / O via the switch SW1.

In this way, at the same time when 1-bit data is output, the binary data register REG2 is shifted to hold 1 of data "d" (= b).
The bits are output. At this time, the shift operation of the binary data registers REG1 and REG2 is performed by the clock CLK2.
It is done in synchronization with. Next, the next bit of the data “c” and “d” is read again from the binary data registers REG1 and REG2, and the next bit of the read data “f” directly transferred from the sense latch circuit 13 is read. Logical operation (d * NAND f) NAND c *. Thereafter, by repeating the same operation as the above, the data “a” and “b” which are inversely converted and restored to the original 2 bits are obtained.
Is output to the outside from the data input / output terminal I / O.

As described above, the inverse conversion logic circuit 14
The data "a" inversely converted by the I / O terminal I / O
Instead of outputting it to, the inversely converted data “a” is temporarily stored in the binary data register REG1, and after the inverse conversion is completed for all the bits, the data in the binary data register REG2 is alternately input / output terminal I / O. It may be configured to output to. In that case, it is desirable to provide a 1-bit latch circuit instead of the delay circuit DLY. As a result, one bit of the data "c" in the binary data register REG1 is read, a logical operation is performed with the data "d" and "f", and the result is written in the original bit position in the binary data register REG1. Can be done easily. The data after the inverse conversion is once stored in the binary data register R
The shift operation of the binary data registers REG1 and REG2 when the data is stored in the EG1 and REG2 and then output to the outside can be configured to be performed in synchronization with the clock CLK1 from the outside.

The flash memory of this embodiment is not particularly limited, but a command register 16 for holding a command given from an external CPU, a command decoder 17 for decoding a command stored in the command register 16, and a command decoder 17 for decoding the command. And a sequencer 18 for sequentially forming and outputting control signals for the circuits such as the switches SW2 and SW3 in order to execute processing corresponding to the command based on the decoding result of the command decoder 17.
When a command is given, the command is decrypted and the corresponding process is automatically executed. The sequencer 18 is, for example, a ROM (read only memory) storing a series of microinstruction groups necessary to execute a command (instruction), like the control unit of a microprogram type CPU, and the command decoder 17 Generates the start address of the microinstruction group corresponding to the command and gives it to the sequencer 18, so that the microprogram is activated.

The detailed writing procedure will be described as follows according to the writing flow of FIG.

First, prior to writing, all memory cells are collectively erased. As a result, all the memory cells are made to have the highest threshold value (about 5 V), and "11" is stored as the write data (FIG. 3 (1)). For collective erasing, as shown in FIG. 13, the word line is raised to 10 V to the control gate CG of the memory cell and 0 to the drain via the bit line.
V, a voltage of -5 V is applied to the substrate (semiconductor region pwell) to inject electrons into the floating gate FG. The batch erase is executed by writing an erase command instructing the erase from the external CPU into the command register 16.

In FIG. 13 (FIGS. 12 and 14), psub is a p-type semiconductor substrate, pwell is a p-type semiconductor well region which is a base of a memory cell, and niso is a substrate when erasing data (when a negative voltage is applied). n + on the surface of the n-type semiconductor isolation region and p-type well region pwell for insulation from the psub is p + on the surface of the source / drain region and p-type well region pwell of the memory cell,
Isolation region niso surface n + and substrate p
p + on the surface of the sub is a contact region for reducing the contact resistance with an electrode that applies a potential to each semiconductor region. Although not particularly limited, in one p-type well region,
Memory cells such as 128 connected to word lines are formed, and it is possible to collectively erase all the memory cells formed on one well. Further, erasing in word line units is possible by selecting (10 V) / non-selecting (0 V) the word line potential for the memory cells on one p-type well region.

When the batch erasing is completed, a write command is written in the command register 16 of FIG. 4 from the external CPU, so that the flash memory enters the write mode. In this write mode, write data is input at a predetermined timing. Then, the flash memory fetches the write data into the binary data registers REG1 and REG2, transfers the write data to the conversion logic circuit 11 bit by bit, and converts the data into four-value data (step S1). The conversion is performed in the order of aNANDb, NOTb (inversion of b), and aNORb. The converted data (aNANDb for the first time) is transferred to the sense latch circuit 13 (step S2).

At the next step S3, it is judged whether or not all the data in the binary data registers REG1, REG2 have been transferred, and if it is judged that the transfer is completed, the external C
A write pulse having a predetermined pulse width to the memory cell of the bit corresponding to "1" of the X (row) system address supplied from PU and the Y (column) system address output from the built-in Y address counter 33 shown in FIG. Is applied and writing is executed (step S4). Writing is shown in Figure 12.
As shown in FIG.
It is performed by applying a voltage of -10 V to G, a voltage of 5 V to the drain and a voltage of 0 V to the substrate from the sense circuit via the bit line. At this time, Vcc (for example, 3.3V) is applied to the unselected word lines. As a result, the fluctuation of the threshold value due to the disturbance is suppressed.

Next, a verify voltage (about 3.5 V for the first time) according to the write level is supplied to the word line which is in the selected state at the time of writing, and the memory cell to which the write pulse is applied is read. . "0" is read as read data from a memory cell that has been sufficiently written, but "1" is read as read data from a memory cell that has not been sufficiently written. Therefore, it can be determined whether the writing is completed or the writing is insufficient depending on the read data. Here, the data of the sense latch circuit 13 of the bit for which writing has been completed is inverted to "0" (step S6). And all the sense latch circuits 13
It is determined whether the latch data of "0" has become "0", and if all "0" have been reached, the write is completed, but if there is even one memory cell with insufficient write that has "1" as the latch data. Then, the process returns from step S7 to S4, and the write pulse is applied again to the insufficiently written memory cell corresponding to "1". By repeating steps S4 to S7, the write pulse is repeatedly applied so that the threshold values of all the memory cells fall below the write verify voltage. As a result, the programmed memory cell has a threshold value of about 3.2 V on average.

When the writing of desired data into all the memory cells is completed by the above-described write verify operation, all the data in the sense latch circuit 13 becomes "0", so that the process proceeds to step S8 and all the write levels are changed. Write, that is, data “10”, “01”,
It is determined whether the writing to "00" is completed. If not completed, the process returns to step S1, four-value data based on the next operation result (NOTb) is written in the memory cell, and the verify voltage of the word line is changed (2.5V for the second time) to verify. The memory cells that have been written and written have an average threshold value of about 2.2V. After that, the third calculation result (aNOR
b) Write and verify (verify voltage 1.5
V) is executed, the programmed memory cells are made to have a threshold value of about 1.2 V on average, and the programming is completed.

FIG. 6 shows the control clock CLK2 and the sense latch circuit 13 during the write and write verify operations.
2 shows waveforms of write data to and write word line potential. In the first writing, the first operation result (aNAN
After Db) is transferred to the sense latch circuit 13, a write pulse writes data in the selected memory cell whose latch value is "1". Next, a voltage of, for example, about 3.5 V is supplied to the word line as the write verify voltage, and it is determined whether the read data is "0". When the threshold value is higher than 3.5V, the read data becomes "1" and it is understood that the write is insufficient, and therefore the write operation is repeated until the read data becomes "0". Next, the second operation result (NOTb) is transferred to the sense latch circuit 13, and the write pulse starts the write operation to the desired memory cell. The write verify voltage is set to about 2.5 V, and it is determined whether or not there is insufficient writing, and if insufficient, rewriting is performed. Finally, the third calculation result (aNOR
b) is transferred to the sense latch circuit 13, and the same procedure as above is performed. The write verify voltage in this case is about 1.5V.

As described above, in the above embodiment,
The setting of the word line voltage for the three-step write verification starts from the level (3.5 V) set closest to the erase level (about 5 volts), and thereafter the voltage value sequentially changes in the direction away from the erase level (3 .5V → 2.5V →
It is controlled to be 1.5 V). Further, in the above embodiment,
As shown in FIG. 7B, the highest threshold value (3.2V) is set as the target even if the target threshold value is intermediate or lowest (2.2V, 1.2V). When writing to the memory cell, writing is performed at the same time. This is one of the features of the present invention. As a result, the increase in the write processing time for multi-valued data can be minimized.

That is, as a method of setting the word line voltage for writing and writing verification other than the above-mentioned method, writing is performed at the first time with the middle (2.2 V) of the three types of threshold voltages as the target. Then, there may be a method of changing the setting so as to target a higher level (3.2V) or a lower level (1.2V) than the voltage of the first time. Alternatively, as shown in FIG.
A method of collectively writing to memory cells having the same target threshold value is conceivable. However, these methods require a longer write / verify time than that of the present embodiment because the write process is complicated and time-consuming and the time for charge / decharge for changing the word line voltage is also increased. turn into.

Next, the read operation of the memory cell will be described with reference to FIGS. To read data, as shown in FIG. 14, a word line is raised to apply a voltage of a selection level such as 3.7V, 2.7V or 1.7V to the control gate CG of the memory cell, and via the bit line. By applying a voltage of 1.5 V to the drain. The read operation is executed by writing a command instructing read to the command register 16.

When the read operation is started, first, the read level is set to the highest 3.7V and the word line is activated (step S11). Then, in the selected memory cell, data appears on the bit line according to the word line read voltage level, so that the data is read by amplifying the bit line level by the sense latch circuit 13 (step S12). Next, the subsequent processing is divided depending on whether the read operation is the first read, the second read, or the third read (step S13). That is, when the read operation is the first time, the sense latch circuit 13 is
Read data in the binary data register REG1
(Step S14).

When the transfer of all the read data in the sense latch circuit 13 is completed, the process returns from step S15 to S11, the read level is set to 2.7 V, the second data read is performed, and the read data is set to the binary data. Transfer to register REG2. When the second data read and transfer are completed, the read level is set to 1.7V.
Is set to read the data for the third time, the process proceeds from step S13 to S16, and the read data is directly transferred to the inverse conversion logic circuit 14. Further, the data held in the binary data registers REG1, REG2 are transferred bit by bit to the inverse conversion logic circuit 14, and the logical operation for converting the 4-value data into 2 bits is performed here (step S17). Then, the above procedure (S16 to S18) is repeated until the transfer and conversion of all the data in the sense latch circuit 13 is completed, and the read operation is completed. The above data conversion is obtained by performing the operation of FIG.

FIG. 9 shows the control clock CLK2 and the sense latch circuit 1 during the read operation according to the above procedure.
3 shows the timing of the data transferred from No. 3 and the read level of the word line. When a read command and an address are given from the outside, the read operation is started, first the first read level (3.7V) is set, and the word line is raised, so that the data appears on the bit line. The data "c" appearing at the first word line level of 3.7 V is read by the sense latch circuit 13 and has a first binary data register having the same data width as the sense latch data length of n bits. Data is transferred to REG1. Next, the data "d" obtained by lowering the word line voltage level by a predetermined value and setting it to the second read level 2.7V is transferred to the second binary data register REG2. The data "f" obtained by lowering the word line to the third read level 1.7V is transferred to the inverse conversion logic circuit 14, and the four-value data of "c", "d" and "f" is 2 bits. The data is restored and output to an external CPU, for example.

FIG. 10 shows an example of the overall configuration of a multi-valued flash memory MDFM having the above-mentioned data conversion / inverse conversion function circuit on the same semiconductor chip, and the relationship between the controller CONT connected thereto. There is. The controller CONT need only have an address generation function and a command generation function for the multilevel flash memory of this embodiment, so a general-purpose microcomputer can be used.

In FIG. 10, the circuit parts designated by the same reference numerals as those in FIG. 4 are circuits having the same function. That is, REG1 and REG2 are binary data registers that capture the 2-bit write data from the controller, 11 is a data conversion logic circuit that converts the captured 2-bit data into 4-value data, and 12 has a floating gate such as FAMOS. A memory array in which non-volatile memory elements are arranged in a matrix, 13 is a sense latch circuit for holding read data and write data, and 14 is 4-value data read from the memory array into original 2-bit data. Inverse conversion logic circuit, 16
Is a command register for holding a command given from the controller CONT, 17 is a command decoder for decoding the command code fetched in the command register 16, and 18 is a control signal for each circuit in the memory to execute a process corresponding to the command. Is a sequencer for sequentially forming and outputting.

Although not particularly limited, the multilevel flash memory of this embodiment is provided with two memory arrays, and the sense latch circuit 13 is provided corresponding to each memory array. Each of the sense latch circuits 13 is configured to simultaneously amplify and hold the data of one row of memory cells having a common word line in each memory array and hold the data in the two sense latch circuits 13 and 13. The read data thus selected is selected by the common Y decoder circuit 15 and transferred to the output register 19 bit by bit or in units of bytes or the like. The read data held in the output register 19 is output to an external CPU or the like via the buffer circuit 22. Since the sense latch circuit 13 of the embodiment shown in FIG. 4 performs a shift operation when transferring data, it needs a function similar to that of a shift register, but the Y decoder circuit 15 selects data as shown in FIG. The method and this Y
By configuring the decoder circuit 15 to shift the selected bit by the clock, the sense latch circuit 1
The shift function may be unnecessary for the No. 3.

The multi-valued flash memory of this embodiment includes:
In addition to the above circuits, the memory array 12 to the sense latch 1
3, an all determination circuit 20 for determining whether all the data read to 3 is “0” or all “1”, a reset signal RES supplied from the controller CONT, a chip selection signal CE, a write control signal WE, an output control signal O
E, a system clock SC, a buffer circuit 21 for fetching an external control signal such as a command enable signal CDE for indicating a command input or an address input, a buffer circuit 22 for fetching an address signal, a command signal, and a data signal, and the above external control signal. An internal signal generation circuit 23 for forming a control signal for an internal circuit based on the above, an address register 24 for holding an address taken in by the buffer circuit 22, a data register 25 for holding input data, a memory for decoding the taken address. X address decoders 26a and 26b forming a signal for selecting a word line in the array 12 and a word driver 27, generation of an internal power supply for generating a voltage required inside the chip such as a substrate potential, a write voltage, a read voltage and a verify voltage. Circuit 28, memory operation Supplied to the word driver 27 and the like by selecting a desired voltage from these voltages according to the state switching circuit 29, an internal clock (CLK2, etc.)
, A timer circuit 31 that counts clocks and gives a time such as a write pulse width, a status register 32 that indicates the memory control state by the sequencer 16, and a Y address counter 33 that automatically updates the Y address. A defective address register 34 that holds the position (address) of a defective bit, a redundancy comparison circuit 35 that compares the Y address with the defective address, and a rescue destination address that stores a rescue destination address that switches the selected memory column when the addresses match. The register 36 and the like are provided. Further, the multilevel flash memory of this embodiment is configured to output a ready / busy signal R / B * indicating whether the memory is accessible from the outside or not.

Further, the multi-valued flash memory of this embodiment has a function of sharpening the peaks (see FIG. 3) of the threshold voltage variation distribution due to disturb or retention (hereinafter referred to as refresh function). Is equipped with. This refresh function is designed to be actuated by an external command as in the case of writing or erasing. When the refresh command is fetched into the command register 16, the microprogram control type sequencer 18 is activated to refresh. It is configured to do. This refresh operation will be described later in detail. The signal indicating the determination result of the all determination circuit 20 is configured to be supplied to the sequencer 18, and the all determination circuit 2 is provided in the refresh mode.
When 0 determines that all the read data is “0” and a signal indicating the determination result is supplied to the sequencer 18, the sequencer 18 stops the refresh operation. When erasing data, the sequencer 18 is configured to stop the erasing operation if the all deciding circuit 20 decides all "1" s in the read data.

In this embodiment, the X-address system decoder adopts a pre-decoding system in which the address signal is decoded in two stages by the pre-decoder 26a and the main decoder 26b.
The upper 3 bits of the address are first decoded, and the predecode signal controls the word driver 27 to select a desired word line. By adopting such a pre-decoding system, the main decoder 26b
It is possible to increase the degree of integration and reduce the chip size by arranging the unit decoders that compose the above in accordance with the word line pitch of the memory array.

The multi-level flash memory of the above-described embodiment is provided with the functional circuits 11 and 14 for converting 2-bit data into 4-level data and vice versa as shown in FIGS. 4 and 10. Although provided on the same silicon substrate, it can be configured as a dedicated controller unit having these functions. In this case, since the multi-valued unique function is not mounted on the flash memory chip, the chip area does not increase, and as shown in FIG. 11, a plurality of flash memories MDFM are combined into one controller unit. It also has an advantage that it can be configured to be connected to CONT via a bus BUS and controlled. This controller unit is configured to have an address generation function and a command generation function in addition to the data conversion / inverse conversion function.

FIG. 15 shows the word line voltage and the substrate potential Vsub.
FIG. 16 shows an internal power supply generation circuit 28 for generating the power supply and a switching circuit 29 for selecting them and supplying them to the word drive circuit 27 and the like, and FIG. 16 shows a configuration example of the word drive circuit 27. Internal power supply generation circuit 28 receives an internal control signal corresponding to various operation modes generated from sequencer 18, and generates a necessary word line voltage.
The configuration of the internal power supply generation circuit 28 including the word line voltage and the configuration of the switching circuit (word line voltage switching circuit) 29 that receives the generated voltage are the same as the conventional ones, and the type of the voltage value of the word line is multi-valued. It just increased to.

That is, the word line voltage required in the conventional binary flash memory is the read voltage (2.7 V / 0).
V), write voltage (-10V, 0V), write verify voltage (1.5V), erase voltage (+ 10V, 0V), and erase verify voltage (4.3V, 0V) The word line voltage required in the example multi-level flash memory is the read voltage (3.7V, 2.7V).
V, 1.7V, 0V), write voltage (-10V, 0)
V), write verify voltage (3.5V, 2.5V,
1.5V), erase and erase verify voltage (10V,
4.3V, 0V and refresh voltage (-10V, 1V)
0V, 3.7V, 3.5V, 2.7V, 2.5V, 1.
7V, 1.5V, 0V).

The switching circuit 29 receives an internal control signal corresponding to various operation modes generated from the sequencer 18, and outputs the voltage generated by the internal power supply generation circuit 28 according to the operation mode as shown in FIG. The power is supplied to the power supply terminals P1 and P2 of the constructed word drive circuit 27.

The word driver WDRV shown in FIG. 16 adopts the word line pre-decoding method. The inputs of eight voltage selection circuits VOLS1 to VOLS8 are commonly connected to the output node N1 of the logic selection circuit LOGS1. The inputs of the eight voltage selection circuits VOLS9 to VOLS16 are commonly connected to the output node N2 of the logic selection circuit LOGS2.
Predecode signals Xp1, Xp1 * to Xp8, Xp8 *
The individual voltage selection circuits are selected by. Signals XM and XN and predecode signals Xp1 and X
p1 * to Xp8, Xp8 * are address decoders XDCR
It is supplied from (26b). At this time, the voltage selection circuit VO
LS1 to VOLS16 are deselected by other logic selection circuits if the operation is not selected by the predecode signal even if the corresponding logic selection circuit LOGS1 or 2 outputs a selection level selection signal. The same voltage must be selected and applied to the word line.

Therefore, the separation MOSFET Q56,
Q57 is switch-controlled by a predecode signal. Further, the separation MOSFETs Q56 and Q57.
Is cut off, in order to output the voltage in the non-selected state to the word line, the isolation MOSF
A pull-up MOSFET Q58 and a pull-down MO that are switch-controlled in a complementary manner to the ETQ56 and Q57 and can supply a predetermined voltage to each input of the output circuit INV2.
SFET Q59 is provided.

In FIG. 16, the signal XM is regarded as a 3-bit signal for instructing which group of word lines is selected from the group of eight word lines, each group consisting of eight word lines. . Predecode signals Xp1, Xp1 * to Xp
8, Xp8 * is regarded as a complementary signal for instructing which word line included in each word line group is selected. According to the present embodiment, the high level of the selection signal SEL is set to the selection level, and the predecode signals Xp1, Xp1 * to Xp8,
Each of Xp8 * has a high level and a low level as a selection level.

The voltage supplied to the terminal P1 of the word driver WDRV is 5V, 4.3V, 3.7V, 3.5V, which is used for erasing, writing, verifying and reading.
The voltage Vpp is such as 2.7V, 2.5V, 1.7V, 1.5V, 0V, and the voltage supplied to the terminal P2 is the voltage Vee such as -10V used for writing and refreshing, and the voltage of the circuit. 0V as ground potential or reference potential
The voltage is Vss.

Each of the above logic selection circuits LOGS1, LOGS
Reference numeral 2 includes an inverter INV1 that inverts the signal of the X decoder XDCR, a transfer gate TG1 that transmits or blocks the output of the inverter INV1, and a transfer gate TG2 that transmits or blocks the signal of the X decoder XDCR.

The voltage selection circuits VOLS1 to VOLS1
6 have the same configuration, and like the voltage selection circuit VOLS1 whose details are representatively shown, the terminals P3 and MO are connected.
An N-channel pull-up MOSFET Q58 which is switch-controlled by a predecode signal Xp1 * provided between the gate of the SFET Q52, a terminal P4 and a MOS.
A P channel pull-up MOSFET Q59 which is switch-controlled by the predecode signal Xp1 provided between the gate of the FET Q53 and the isolation M
The OSFET Q56 is switch-controlled by the predecode signal Xp1, and the other isolation MOSFET Q57 is switch-controlled by the predecode signal Xp1 *. A voltage Vcc is applied to the terminals P3 and P4.
Alternatively, Vss is supplied.

Next, the operation of the word driver WDRV shown in FIG. 16 will be described. Table 1 shows the terminal P in each operation mode.
The voltages of 1 to P4 and the word line voltage are shown. A description of how to set each of the write mode, erase mode, and read mode is omitted.

[0056]

[Table 1]

When the erase mode is instructed by the command, the voltage Vpp is applied to the terminal P1 and Vs is applied to the terminal P2.
The voltage Vcc is supplied from the switching circuit 29 to s and the terminals P3 and P4, and the control signal D
E is set to low level. Further, by setting the signal XM to the low level for all bits, it becomes possible to select one of the word lines W1 to W8. As a result, when the selection signal SEL of the selection level (high level) is supplied, the inverter INV1 and the transfer gate TG
The node N1 goes low via 1 and is applied to the inputs of the respective voltage selection circuits VOLS1 to VOLS8. When the memory cell to be erased is the memory cell coupled to the word line W1, the predecode signals Xp1, Xp1 * to Xp8, Xp8 * are Xp among them.
Only 1, Xp1 * is set to high level and low level.
Therefore, in the separation MOSFETs Q56 and Q57, only the voltage selection circuit VOLS1 is turned on, and the signal of the node N1 is taken in only by the voltage selection circuit VOLS1. At this time, the pull-up MOSFET of the voltage selection circuit VOLS1
Both the TQ58 and the pull-down MOSFET Q59 are cut off.

As a result, the node N is connected to the gates of the MOSFETs Q52 and Q53 of the voltage selection circuit VOLS1.
1 signal is provided. As a result, the output circuit INV
The second MOSFET Q52 is turned on, and the word line W1 starts to be charged by the voltage Vpp at the terminal P1.
At this time, the low level supplied to the gate of the other MOSFET Q53 is set to a low level higher than the initial voltage Vss by the action of the MOSFET Q57, and the
Although the FET Q53 is not completely cut off, the feedback MOSF increases as the level of the word line W1 rises.
By increasing the conductance of the ETQ55, the gate of the MOSFET Q53 is forced to the voltage Vss, and the MOSFET Q53 is completely cut off. Therefore, in the erase mode, the word line W1 to which the selected memory cell is coupled is charged to Vpp.

When the select signal SEL is set to the high level as described above and the memory cell Q1 of the word line W1 is the non-erased memory cell, the predecode signals Xp1 and Xp1 * are low level and high, respectively. Be leveled. Therefore, the separation MOSFETs Q56 and Q57 of the voltage selection circuit VOLS1 are both turned off, and the signal of the node N1 is not taken into the voltage selection circuit VOLS1. At this time, the pull-up MOSFET Q58 and the pull-down MOSFET Q5 of the voltage selection circuit VOLS1.
Both 9 are turned on.

As a result, the gates of the MOSFETs Q52 and Q53 of the voltage selection circuit VOLS1 have terminals P3 and P3.
4 is supplied with the Vcc voltage through MOSFETs Q58 and Q59, and the MOS of the output circuit INV2 is thereby supplied.
The FET Q53 is turned on, and the word line W1 starts to be discharged toward the voltage Vss via the terminal P2. At this time, since the high level supplied to the gate of the other MOSFET Q52 is lower than the voltage Vcc by the threshold voltage of the MOSFET Q58, the MOSFET Q52 is not completely cut off, but the MOSFET in the ON state is turned off.
As TQ53 lowers the level of the word line W1, the conductance of the feedback MOSFET Q54 increases, the gate of the MOSFET Q52 is forced to Vpp, and the MOSFET Q52 is completely cut off. Therefore, in the erase mode, the non-selected word line W1 is discharged to Vss.

The operation of the word driver circuit WDRV when the write mode is instructed or when the read mode is instructed is similar to the operation in the write mode, so a detailed description thereof will be omitted. The word line is driven so that the voltages supplied to P1 and P2 are applied to the selected memory cell as shown in FIGS. 13 and 14, respectively.

Next, the refresh operation, which is the second feature of the multilevel flash memory of the present invention, will be described with reference to FIG. In the multi-level flash memory in which data is once written, as shown in FIG. 17 (1), the peaks of the threshold voltage distribution distribution are clearly separated, but subsequent writing, reading, standby, etc. When the above operation is repeatedly executed, the variation in each threshold increases as shown in FIG. 17 (2). The cause thereof is, for example, a so-called disturb in which a memory cell adjacent to a certain memory cell is weakly written when the memory cell is written, and a retention due to a natural leak during standby. This phenomenon can occur even in a normal flash memory that stores only one bit, but in the multilevel flash memory in which the intervals between the threshold values are narrow as in the above-described embodiment, it may cause a malfunction. .

Therefore, in this embodiment, when the peaks of the threshold distribution (see FIG. 3) are distorted, a refresh operation is performed to make the peaks steep. The procedure of the refresh operation will be described below.

FIG. 18 is a flowchart showing the procedure of the refresh operation. When a refresh command is input from an external CPU or the like, the sequencer 18 is activated and the refresh operation according to the flowchart of FIG. 18 is started. When the refresh operation is started, first, an erase pulse weaker than the word line is applied to all the memory cells connected to the selected word line (step S21). By applying this weak erase pulse, the threshold values of all the memory cells are as shown in FIG.
Shift a little to the higher side. Although not particularly limited, the shift amount is about 0.2V. Here, the weak erase pulse means a pulse that is sufficiently short so that the threshold value of the memory cell at "10", for example, does not exceed the read level 3.7V immediately above as a result of the addition. The pulse width is experimentally determined according to the amount to be shifted.

In the second stage, the word line voltage is set to the read level (3.7 V) corresponding to the storage data "10" and read is performed (step S22). As a result, data is read according to the threshold value of each memory cell, and is amplified and held by the sense latch circuit 13 (step S23). At this time, the data of the sense latch corresponding to the memory cell having the threshold value higher than the word line voltage becomes “1”, and the data of the sense latch corresponding to the memory cell having the threshold value lower than the word line voltage becomes. The data becomes "0". Next, the data in the sense latch is inverted (step S24). This data inversion can be easily performed by the sense latch circuit having the structure shown in FIG. 20 (described later).

Next, a verify voltage (3.5 V initially) lower than that in the above-mentioned reading (step S22) is set to the word line, and the threshold value judgment is executed (step S).
25). As a result, the data in the sense latch corresponding to the memory cell having a threshold value lower than the verify voltage (reference A in FIG. 17 (4)) changes from "1" to "0".
On the other hand, the data of the sense latch corresponding to the memory cell (reference numeral B in FIG. 17 (4)) having a threshold value higher than the verify voltage remains "1". In this embodiment, this is determined as the rewriting target. As a result, the memory cells that have come too close to the read level (3.7 V) when the threshold value is shifted to the higher side by the weak erase in step S21 are specified. At this time, the data of the sense latch corresponding to the memory cell (reference numeral C in FIG. 17 (4)) corresponding to the stored data "11" having the highest threshold value is "0" set by the inversion operation. Left alone. Such an operation can be automatically performed by the sense latch circuit having the configuration shown in FIG. 20 (described later).

Therefore, next, the write voltage is set and the memory cell in which the data of the sense latch is "1" (see FIG. 17).
(4) Rewrite the code B) (step S2)
7). Then, the verify voltage corresponding to the write level is set to perform the verify (steps S28, S2).
9). When the threshold voltage becomes lower than the verify voltage, the latch data changes from "1" to "0". Writing and verification are repeated until all the latch data are changed to "0", and the refresh process of the memory cell of "10" data is completed (step S30). As a result, the variation distribution (half-value width) of the threshold value of the memory cell of “10” data is reduced as shown in FIG. 17 (5).
After that, the same refresh process is performed on the memory cells storing the data of "01" and "00" (step S31). Further, in order to further narrow the width of the threshold distribution shape, steps S21 to S31 are repeated, and the refresh is completed when a predetermined number of times are completed (step S32).

Table 2 shows the sense latches when the memory cells having the threshold values shown by the symbols A, B and C in FIG. 17 (4) are read when the refresh is performed according to the above procedure. Changes in the data held by the circuit are shown in order.

[0069]

[Table 2]

FIG. 19 is a diagram showing the timing for executing the refresh operation. As described above, the reason why the variation in the threshold value of the memory cell is widened is that when the write / read operation is performed on the adjacent memory cell, the weak write / erase / read operation is performed on the adjacent memory cell. There is a disturbance caused by a leak and a retention caused by a natural leak.

As the execution timing of the refresh operation with respect to the fluctuation of the threshold value due to the disturb, (1) the flash memory is in the standby state (/ RES
Is at a high level), and the refresh operation is executed after the write / erase / read operation is completed a certain number of times. (2) Refresh is executed immediately after the reset signal (/ RES) is activated at reset. (3) Refreshing is executed immediately after entering the reset state by setting / RES to low level from the standby state. (4) / RES is set to a low level in advance immediately before the power is turned off, and this is sensed to execute refresh. (3) After turning on the power and setting / RES to high level, refresh is executed. And so on.

On the other hand, as a measure against the decrease in the threshold value due to the retention, it is conceivable to execute the refresh in the middle of the dummy cycle when the power is turned on or in the standby state at regular intervals. All of these refresh timings may be executed, or any one or some of them may be executed.

The refresh operation described above is not limited to the multi-value flash memory, and if the power supply voltage of the flash memory shifts to a lower voltage in the future,
Even in a normal flash memory, the increase in threshold variation cannot be ignored, and this is an effective function for reducing the power supply voltage of the flash memory.

FIG. 20 shows a configuration example of the memory array 12 and the sense latch circuit 13. The memory array 12 has a common drain line DL and a common source line S, which are arranged in a direction orthogonal to the word lines and arranged in parallel with the bit lines BL from which the read signal of the selected memory cell is output.
A plurality of (for example, 128 memory cells MC corresponding to 128 word lines that can be collectively erased) memory cells MC are connected in parallel with L and are of an AND type. Common drain line DL
Can be connected to the corresponding bit line BL via the switch MOSFET Q1, and the common source line SL can be connected to the ground point via the switch MOSFET Q2. These switch MOSFETs Q1, Q2
Is formed based on the X address signal and the read / write control signal, and is set to a potential such as Vcc (3.3 V) at the time of data read (including verify), thereby the switch MOSFET Q1 and Q2 are turned on, and the bit line is discharged through the memory cell in the on state. On the other hand, at the time of data writing, since the write voltage (5V) of the bit line is transmitted to the drain of the memory cell, the gate control signal of the switch MOSFET Q1 is 7
The potential is set to V and Q1 is turned on. At this time, the switch MOSFET Q2 on the common source line SL side is turned off.

The sense latch circuit 13 is formed of a CMOS differential sense amplifier SA which is provided corresponding to each memory column and amplifies the potential difference between the bit lines of the left and right memory arrays. Prior to reading, the bit lines of the memory array on the selected side (left side in the figure) are precharge MOS (S
W21) precharges to a potential like 1V,
The bit lines in the memory array on the opposite side are precharged MO
It is precharged to a potential such as 0.5V by S (SW22).

When the word line WL is set to the read level in such a precharge state, if the selected memory cell has a high threshold value, the bit line maintains 1.0 V, but the selected memory cell is If it has a low threshold value, a current flows, the charge of the bit line is extracted, and the potential of the bit line becomes 0.2V. This 1.0V or 0.
The sense amplifier SA detects and amplifies the potential difference between 2 V and the potential of the bit line on the opposite side, 0.5 V, and the read data is held in the sense amplifier SA.

In the above embodiment, as described above,
"1" is set in the sense latch (sense amplifier) corresponding to the bit line to which the memory cell to be written is connected, a write pulse (-10 V) is applied to the word line, and then the verify operation according to the write level is performed. The voltage (about 3.5 V for the first time) is set to the word line to read the memory cell to which the write pulse is applied.
Then, since "1" is read as read data from the memory cell in which writing is insufficient to the bit line, it is determined whether writing is completed or insufficient by seeing the read data, and the sense latch (sense The data of the amplifier) is inverted to "0". In other words, “1” is left as data in the sense latch (sense amplifier) corresponding to the memory cell in which the write is insufficient, and the write pulse is again applied to the memory cell in which the write is insufficient corresponding to the bit in which “1” is set. I am trying to apply.

Also in the refresh operation, the data read to the sense latch is inverted and verified to apply the write pulse to the memory cell corresponding to the bit in which "1" is set. There is.

In the sense latch circuit of FIG. 20, it is possible to easily invert the latch data of the sense amplifier corresponding to the memory cell for which the writing is completed and to narrow down the memory cells to which the write pulse is applied in the above-described writing. In order to do so, four switches SW11, SW12, S are provided between the sense amplifier and the memory array.
The device is devised such that an inversion control circuit 30 including W13 and SW14 is provided. The operation of this sense latch circuit will be described below. The switches SW21 and SW22 provided on each bit line BL are switches for precharging the bit line.
It is composed of a MOSFET together with W11 to SW14.

At the time of data reading, first, the switch SW13 is turned off to set the bit line B as shown in FIG.
With the L and the sense amplifier SA separated, the switches SW21 and SW22 are turned on to select the bit line BL on the selected side.
To a precharge level such as 1.0V. At this time, the bit line on the non-selected side is charged to a level such as 0.5V. The sense amplifier SA is a switch SW14.
Is turned on to enter the reset state, and a potential such as 0.5 V is applied. Furthermore, at this time, switch MO
A voltage such as Vcc is applied to the gates of the SFETs Q1 and Q2 to turn on Q1 and Q2.

Then, one of the word lines WL in the memory array 12 is set to a selection level such as 3.7V. Then, the memory cell whose threshold value is lower than the word line selection level (for example, cells A and B in FIG. 17) is turned on, and the bit line BL to which the cell is connected is
A current flows toward the common source line SL through the memory cells in the ON state, and is discharged to a level such as 0.2V. On the other hand, a memory cell whose threshold value is higher than the word line selection level (for example, cell C in FIG. 17) is turned off, and the bit line BL to which the cell is connected maintains the precharge level of 1.0V. .

Next, the switch SW14 is turned off to release and activate the reset state of the sense amplifier SA, and the switch SW13 on the bit line BL is turned on to connect the bit line BL and the sense amplifier SA. The power supply voltage Vcc is applied to the P-MOS side of the sense amplifier SA.
And a ground potential (0V) to the N-MOS side.
Then, after the sense amplifier SA sufficiently amplifies the potential difference between the bit lines BL and BL *, the switch SW on the bit line BL
Turn off 13. As a result, the sense amplifier SA is in a state of holding the data by amplifying the level difference between the bit lines on the selected side and the non-selected side.

When inverting the latch data of the sense amplifier SA, the switch SW13 is turned off, and the switch SW13 shown in FIG.
As shown in, the switches SW21 and SW22 are turned on in the state where the bit line BL and the sense amplifier SA are separated from each other, and the bit lines BL on the selected side and the non-selected side are set to Vcc-V.
Precharge to a level such as tn (for example, 3.3V-0.6V = 2.7V). Then, the switch S
W21 and SW22 are turned off and the switch SW11 is turned on. Then, depending on the data held in the sense amplifier SA, if the data is "1", the switch SW12 is turned on, and the bit line BL is discharged to the bit line inversion level (0V). On the other hand, if the data held in the sense amplifier SA is “0”, the switch SW
Since 12 is turned off, the bit line BL is Vcc.
Maintain the level. That is, the inversion level of the data held in the sense amplifier SA appears on the corresponding bit line BL.

Here, after the switch SW14 is once turned on to reset the sense amplifier SA, the switch SW14 is turned on.
14 is turned off and the switch SW13 on the bit line BL is turned on to connect the bit line BL and the sense amplifier SA. During this period, the P-MOS side of the sense amplifier SA and N
The power supply voltage on the -MOS side is set to 0.5V. Then, the power supply voltage Vc is applied to the P-MOS side of the sense amplifier SA.
c and the ground potential (0 V) are supplied to the N-MOS side, and the switch SW13 on the bit line BL is turned off. As a result, the sense amplifier SA is in a state of holding data according to the level of the bit line in the inverted data holding state, as shown in FIG. That is, in FIG.
The sense amplifiers corresponding to the cells A and B are in the state of holding the high level "1", and the sense amplifiers corresponding to the cell C are in the state of holding the low level "0". The operation is the same as so-called write verify. Therefore, the bit line precharge must be performed only when the sense latch is "H". Therefore, by turning on the switch SW11 and setting the bit line precharge voltage (1) to 1V, only the bit lines BL0 and BL1 are set to 1V (BL
2 is reset to 0V in advance).

Next, the switch SW13 on the bit line BL
While the switch is off, the switches SW21 and SW22 are turned on to charge the bit line BL on the selected side to a precharge level such as 1.0V and the bit line on the non-selected side to a level such as 0.5V. After that, a verify voltage such as 3.5 V, which is slightly lower than the previous read level (3.7 V), is applied to the selected word line. Then, a memory cell whose threshold value is lower than the word line selection level (for example, in FIG.
Cell A) is turned on, and the bit line BL to which the cell is connected is discharged to a level such as 0.2V. On the other hand, a memory cell whose threshold value is higher than the word line selection level (for example, cell B in FIG. 17) is turned off, and the bit line BL to which the cell is connected maintains the precharge level 1V. Further, at this time, since the bit line to which the memory cell (cell C in FIG. 17) corresponding to the data “11” having the highest threshold value is originally held in the low level, that is, “0”,
When the word line is set to the selection level, it is at the low level even in the off state (FIG. 23).

Therefore, when the switch SW13 on the bit line BL is turned on after resetting the sense latch in this state, the memory cell corresponding to the data "11" (see FIG. 17).
Cell C) is connected to the bit line connected to the bit line and the sense amplifier corresponding to the bit line connected to the bit line connected to the memory cell (cell A in FIG. 17) having a threshold value lower than the word line selection level. 0 "is held and a memory cell having a threshold value higher than the word line selection level (see FIG.
Cell B) is connected to the bit line corresponding to the bit line and holds the high level "1". In the present embodiment, the data held in the sense amplifier is used to shift to the write operation and write pulse (-1
By applying 0 V), the threshold value of the memory cell corresponding to the data held in the sense amplifier corresponding to "1" is lowered.

After the application of the write pulse, when the word line is set to the selection level again and reading is performed, the bit line level of the memory cell whose threshold value becomes lower than the word line verify level becomes low level, that is, "0". In contrast, the bit line connected to the memory cell which is insufficiently written maintains the high level "1". Therefore, by latching this with a sense amplifier and writing again, only the memory cell corresponding to the data held in the sense latch is "1", the threshold value can be lowered and the distribution shape of the threshold value can be made steep. . The data held in the sense amplifier SA is supplied to the all determination circuit 20 described above through a so-called column switch and common I / O lines that are turned on and off by the output signal of the Y decoder 15, and whether all the data becomes "0". To be judged. Then, when all become "0", the refresh of the memory cell of the data "10" is completed, and the refresh of the memory cells of the data "01" and "00" is performed.

The rewriting operation for the insufficiently written memory cells in the above-mentioned writing mode is the same as the above writing operation by the sense latch circuit 13 in the refresh operation.

As described above, in the above embodiment, the data conversion logic circuit converts the data of a plurality of bits into the data (multivalued data) corresponding to the combination of the bits at the time of writing the data, and the converted data. Is sequentially transferred to the latch circuit connected to the bit line of the memory array, a write pulse is generated according to the data held in the latch circuit, and the write pulse is applied to the memory element in the selected state, thereby supporting multi-valued data. In addition, the read voltage is changed to an intermediate value between the respective threshold values when reading data, the state of the storage element is read, transferred to a register for storing multi-valued data, and held. The original data is restored by the inverse data conversion logic circuit based on the multi-valued data stored in the register. The size of the peripheral circuit of the ray can be kept relatively small, and in the write operation, the verify voltage value of the word line is sequentially changed by a predetermined value in the direction away from the side close to the word line voltage for erasing. This makes it possible to reduce the total number of write pulses, that is, the write time, as compared with the multi-value flash memory method in which the verify voltage is set randomly,
There is an effect that the write operation can be realized in a short time.

In addition, after performing a weak erase operation on a storage element in the memory array, a storage element having a threshold value of the word line lower than the read level and higher than the verify level is detected to detect the storage element. Writing is performed so that the threshold value of is lower than the verify voltage to narrow the spread of the variation distribution shape of the threshold voltage of the memory element written corresponding to each input data. Therefore, there is an effect that it is possible to return the variation distribution shape of the threshold voltage of the storage element, which is spread due to the disturbance or the retention, to the steep shape almost equal to that immediately after the completion of writing.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above embodiment, the threshold value of one memory cell is set in four steps to store four-valued data.
The threshold value can be set in three steps or five steps or more.

In the embodiment, the read data is inverted at the time of refreshing, the memory cells to be written are narrowed down, etc. by using only the sense latch circuit. It is also possible to provide a logic circuit that narrows down the memory cells to be written by performing a logical operation such as inverting.

Further, in the embodiment, as a method of converting 2-bit data into 4-value data and its inverse conversion, FIG.
Although three types of operations as shown in (2) are performed, the logical operation is not limited to that shown in FIG. 1, and as a result, data having different numbers of bits with "1" s can be obtained. I wish I had it. Further, the operation for the data inverse conversion is not limited to that shown in FIG. 2, and any operation may be used as long as it can restore the original 2-bit data, and the number of operations is not one but two. It may be more.

The method of writing to each memory cell is not limited to the method of erasing once to raise the threshold value and then lowering the threshold value by the write pulse as in the embodiment, but the threshold value is raised by the write pulse. It is also possible to adopt a method of doing so. Further, in the embodiment, the threshold voltage is changed by writing to the memory cell corresponding to the sense latch holding the data “1”, but the memory cell corresponding to the sense latch holding the data “0” is changed. The threshold value may be changed by writing.

In the above description, the case where the invention made by the present inventor is mainly applied to the batch erasing type flash memory which is the field of application which is the background has been described, but the present invention is not limited to this. FAMO
The present invention can be widely used for general nonvolatile memory devices having S as a memory element and further for semiconductor memory devices including memory cells having a plurality of threshold values.

[0096]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, since the binary data is converted into multi-valued data and stored in the memory cell, the circuit size of the memory array can be kept relatively small, and the memory array can be stored. Since the first external terminal for serially supplying the binary data to be processed is provided, the number of external terminals can be reduced as compared with the case of supplying the binary data in parallel.

[Brief description of drawings]

FIG. 1 is written in one memory cell according to the present invention /
FIG. 6 is an explanatory diagram showing an example of an operation for converting 2-bit data to be read into 4-value data which is a level to be physically written / read in each memory cell.

FIG. 2 is an explanatory diagram showing an example of an operation for inversely converting 4-value data converted by a data conversion logic circuit into original 2-bit data.

FIG. 3 is an explanatory diagram showing a relationship between the 4-level data and a threshold value of a memory cell.

FIG. 4 is a block diagram showing an outline of an embodiment of a multilevel flash memory according to the present invention.

FIG. 5 is a flowchart showing a writing procedure of the multilevel flash memory according to the embodiment.

FIG. 6 is a timing chart showing a write operation waveform of the multilevel flash memory according to the embodiment.

FIG. 7 is an explanatory diagram showing the difference between the writing method of the multilevel flash memory of the embodiment and another writing method.

FIG. 8 is a flowchart showing a read procedure of the multilevel flash memory according to the embodiment.

FIG. 9 is a timing chart showing a read operation waveform of the multilevel flash memory according to the embodiment.

FIG. 10 is a block diagram showing a configuration example of an entire multilevel flash memory according to an embodiment.

FIG. 11 is a block diagram showing a configuration example of a system in an embodiment in which a controller is provided with a conversion function of 2-bit data and 4-value data unique to a multi-valued memory.

FIG. 12 is a schematic diagram showing a structure of a memory cell used in the flash memory of the embodiment and a voltage state during writing.

FIG. 13 is a schematic diagram showing a voltage state at the time of erasing a memory cell used in the flash memory of the example.

FIG. 14 is a schematic diagram showing a voltage state at the time of reading of a memory cell used in the flash memory of the example.

FIG. 15 is an explanatory diagram showing an internal power supply generation circuit and a switching circuit that selects a generated voltage and supplies it to a word drive circuit or the like.

FIG. 16 is a circuit diagram showing a configuration example of a word drive circuit.

FIG. 17 is an explanatory diagram showing a refresh method of the multilevel flash memory according to the embodiment.

FIG. 18 is a flowchart showing a refresh procedure of the multilevel flash memory according to the embodiment.

FIG. 19 is a timing chart showing operation waveforms when refresh is executed.

FIG. 20 is a circuit diagram showing a configuration example of a sense latch circuit of the embodiment.

FIG. 21 is a circuit state diagram at the start of data inversion showing the operation of the sense latch circuit.

FIG. 22 is a circuit state diagram at the end of data inversion showing the operation of the sense latch circuit.

FIG. 23 is a circuit state diagram at the time of verification showing an operation of the sense latch circuit.

[Explanation of symbols]

11 data conversion logic circuit 12 memory array 13 sense latch circuit 14 inverse conversion logic circuit REG1, REG2 register XDCR X address decoder WDRY word drive circuit LOGS logic selection circuit VOLS voltage selection circuit SA sense amplifier BL bit line WL word line MC memory cell A "11" data memory cell (threshold value about 5V) B "10" data memory cell (threshold value about 3.6V)
V) C "10" data memory cell (threshold value about 3.2)
V)

[Procedure amendment]

[Submission date] November 29, 2002 (2002.11.
29)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

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Claims (16)

[Claims] 1. The binary data to be stored is capable of electrically changing its threshold voltage with a first external terminal supplied serially, the data being the value of the threshold voltage. A plurality of memory cells that are held as, and a means that is coupled to the external terminals and the plurality of memory cells and that converts a plurality of serially supplied binary data into multi-valued data and writes the multi-valued data to the memory cells. A semiconductor non-volatile memory comprising: 2. The semiconductor non-volatile memory according to claim 1, wherein the plurality of memory cells and the writing means are formed in one semiconductor. 3. The writing means comprises a buffer means for holding the plurality of binary data, and a conversion means for converting the binary data held in the buffer means into multi-valued data. Item 1. A semiconductor nonvolatile memory according to item 1 or 2. 4. A conversion means for converting multi-valued data read from a memory cell into a plurality of binary data, and a second external terminal to which the plurality of binary data converted by the conversion means are serially supplied. The semiconductor non-volatile memory according to claim 1 or 2, further comprising: 5. The semiconductor nonvolatile memory according to claim 4, wherein the first external terminal is the second external terminal. 6. A plurality of binary data to be stored can change its threshold voltage electrically with a first external terminal supplied serially, and the data can be changed to a threshold voltage. A plurality of memory cells to be held as values of a plurality of data lines, a plurality of data lines to which a predetermined memory cell in the plurality of memory cells is respectively connected, and a plurality of latches connected to each of the plurality of data lines. A circuit, and a conversion unit that is coupled to the first external terminal and that converts a plurality of serially supplied binary data into multi-valued data, when reading the stored data from the predetermined memory cell. Is latched with data from the predetermined memory cell in the plurality of latch circuits, and when writing data to the predetermined memory cell, the data is output according to the output from the conversion means. A semiconductor nonvolatile memory in which a plurality of latch circuits are set. 7. The semiconductor nonvolatile memory according to claim 6, wherein the data set in the plurality of latch circuits from the predetermined memory cell is serially output via the second external terminal. 8. The semiconductor nonvolatile memory according to claim 6, wherein the first external terminal is the second external terminal. 9. The semiconductor nonvolatile memory according to claim 6, wherein each of the plurality of memory cells has a floating gate and a control gate. 10. A first plurality of non-volatile memories connected to a first word line, a second word line, and the first word line for holding data as a threshold voltage value. A cell, a second plurality of non-volatile memory cells connected to the second word line and holding data as a threshold voltage value, the first word line and the second word line A selection means for selecting a word line from and a plurality of binary data to be written are serially supplied to the input external terminal. A semiconductor non-volatile memory in which data is written in the non-volatile memory cell, and the number of non-volatile memory cells connected to the word line is
A semiconductor non-volatile memory characterized by being less than the number of binary data to be written. 11. The semiconductor nonvolatile memory according to claim 10, wherein the first word line and the second word line are connected to one decoder. 12. The semiconductor nonvolatile memory according to claim 10, wherein each of the plurality of nonvolatile memories has a floating gate and a control gate. 13. The semiconductor nonvolatile memory according to claim 12, further comprising an output external terminal that serially outputs data written in a plurality of nonvolatile memories connected to the selected word line. 14. The semiconductor nonvolatile memory according to claim 13, wherein the input external terminal and the output external terminal are the same external terminal. 15. A latch circuit having the same number as the number of non-volatile memory cells connected to a selected word line, and when writing data to the non-volatile memory cell, the latch circuit is according to the data to be written. Is set and the latch circuit is set according to the data written in the non-volatile memory cell when outputting the data written in the non-volatile memory cell.
3. Semiconductor non-volatile memory. 16. Each of the plurality of memory cells comprises:
The semiconductor nonvolatile memory according to claim 2, further comprising a floating gate and a control gate.