JP2009252290A - Semiconductor integrated circuit and operation method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce chip area when verify-read-out and normal data read-out are performed, incorporating a nonvolatile memory writing complementary data in two memory cells. <P>SOLUTION: A semiconductor integrated circuit is provided with a nonvolatile memory DFL, including first and second nonvolatile memory arrays 21, 22, first and second selectors 24, 25, and a sense amplifier 26. Complementary data are written electrically in two nonvolatile memory cells MC1, MC2. In normal data read-out operation NR_RD, one side of selectors 24 supplies data which are complementary to two memory cells MC1, MC2 to first and second input terminal In1, In2 of the sense amplifier 26. In verify-read-out operation VR_RD, one side of the selectors 24 supplies first verify-read-out data from one memory cell MC1 to one side of the input terminal of the sense amplifier 26, on the other hand, and supplies a verify-reference signal to the other side of the input terminal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a method of operating the same, and more particularly to a semiconductor non-volatile memory that writes complementary data in two memory cells and performing verify read and normal data read from the semiconductor non-volatile memory. The present invention relates to a technique effective for reducing the chip area of a semiconductor integrated circuit.

  In the following Patent Document 1, two currents of transistors of two memory cells of a non-volatile memory are supplied to a differential detector through switching means, and the magnitude relationship between the two currents is determined by the differential detector. Thus, it is described that two states corresponding to the determination result are output. Also, the current of the transistor of one memory cell of the two memory cells is supplied to one input terminal of the sense amplifier via the switching means, and the reference current from the reference current generator is supplied to the other input terminal of the sense amplifier. The read information is discriminated by the sense amplifier.

  In Patent Document 2 below, complementary data is written to two memory cells of a semiconductor nonvolatile memory at the time of data writing, and the potential difference between the bit line pairs read from the two memory cells at the time of data reading is differentially amplified. -It is described that the read data is determined by amplification with an amplifier. In this semiconductor nonvolatile memory, verification immediately after writing is performed by using a differential amplification type sense amplifier used at the time of data reading. During verification by the differential amplification type sense amplifier, the pull-up transistor connected to the sense line of the differential amplification type sense amplifier to which the memory cell in the write state (“0” state) is connected receives the write data. The held write latch circuit turns it off. Accordingly, the memory cell in the non-write state is reduced so that the potential difference between the sense line pair of the differential amplification type sense amplifier is reduced by the difference in conductance gm between the transistor in the memory cell in the write state and the transistor in the non-write state. The potential of the connected sense line is pulled up. As a result, the criterion for verify comparison by the differential amplification type sense amplifier becomes strict, and rewriting to a memory cell with insufficient writing amount is performed.

JP 2007-87441 A JP-A-1-263997

  Prior to the present invention, the inventors store various software programs installed in the microcomputer for the central processing unit (CPU) of the microcomputer, while storing various data of program execution results by the CPU. Engaged in the development of non-volatile memory for storage. The number of data rewrites in the data flash, which is a non-volatile memory that stores program execution result data, is much greater than the number of data rewrites in the program flash, which is a non-volatile memory that stores programs.

  Therefore, in the development of this nonvolatile memory, it is necessary to reduce the deterioration of the data retention characteristic in the data flash due to the deterioration of the data retention characteristic of the cell due to the exhaustion of the nonvolatile flash memory cell of the data flash having a large number of rewrites. It became. As described in Patent Document 2, the present inventors write complementary data in two nonvolatile memory cells during data writing, while differentially amplifying the complementary data written in the two nonvolatile memory cells during data reading. We arrived at the idea of building a data flash using a method that uses a sense amplifier.

  In general, due to exhaustion of the nonvolatile flash memory cell, the threshold voltage of the transistor of the memory cell, which is data written in the memory cell, gradually varies with time. If the fluctuation of the threshold voltage of the memory cell transistor over time exceeds the read reference value for reading data, the read data at the time of data reading becomes erroneous data.

  However, according to the above-described method, even if the nonvolatile memory cell is exhausted, the difference between the threshold voltages of the transistors of the two memory cells (twin cells) which are complementary data written in the two nonvolatile memory cells at the time of data writing. Can be maintained. Therefore, even if the difference between the threshold voltages of the two memory cells (twin cells) is slightly reduced due to exhaustion, the differential amplification type sense amplifier can accurately amplify the slightly reduced threshold voltage difference. it can. As a result, even when the number of rewrites increases and the memory cells of the data flash are somewhat exhausted, accurate read data can be output when reading data.

  On the other hand, it is necessary to perform a write verify operation for confirming whether or not the complementary data written in the two nonvolatile memory cells (twin cells) is correctly written when writing data to the data flash. For example, when complementary data “1” is written in two nonvolatile memory cells (twin cells), for example, a low threshold voltage is applied to one memory cell (positive cell) and the other memory cell (negative cell) of the twin cell. And write data corresponding to a high threshold voltage are written respectively. In order to verify the complementary data “1”, it is necessary to verify whether a high threshold voltage corresponding to the data “1” is written in the other memory cell (negative cell). Similarly, in order to verify writing of complementary data “0”, it is necessary to verify whether a high threshold voltage corresponding to the writing data of data “0” is written in one memory cell (positive cell). For verifying both, a write verify reference voltage having a voltage level corresponding to a high threshold voltage is used. In the data flash of the non-volatile memory developed prior to the present invention, the present inventors, as described in Patent Document 1, described above, verify current from one memory cell or the other memory cell as a verify sense amplifier. The idea of supplying the write verify reference current to the other input terminal of the verify sense amplifier has been reached.

  In this data flash, an initializing erase operation (blank erase) for writing, for example, erased data (erased data) corresponding to a low threshold voltage to both of the two nonvolatile memory cells (twin cells) prior to data writing. Operation) is also required. This initialization erase operation also requires an erase verify operation for confirming whether erase data with a low threshold voltage has been correctly written in both of the two nonvolatile memory cells (twin cells). For this erase verify, an erase verify reference voltage having a voltage level corresponding to a low threshold voltage is used. A current from one memory cell or the other memory cell is supplied to one input terminal of the verify sense amplifier, and an erase verify reference current is supplied to the other input terminal of the verify sense amplifier.

  However, this type of data flash requires a verify sense amplifier for writing and erasing and a differential amplification type sense amplifier for normal data reading, and the chip area of the semiconductor integrated circuit constituting the microcomputer is small. The problem of being large was clarified by the study of the present inventors. Also, in this type of data flash, it is necessary to guarantee the operation correlation between the verify sense amplifier and the differential amplification type sense amplifier, and it is difficult to design the operation margin of the semiconductor integrated circuit constituting the microcomputer. This problem has also been clarified by the study of the present inventors.

  The present invention has been made as a result of the study of the present inventors prior to the present invention as described above.

  Accordingly, an object of the present invention is to incorporate a semiconductor nonvolatile memory that writes complementary data into two memory cells, and to perform a verify read and a normal data read of the semiconductor nonvolatile memory. It is to reduce the area.

  Still another object of the present invention is to facilitate operation margin design for verify read and normal data read in the semiconductor integrated circuit as described above.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

  That is, a representative semiconductor integrated circuit according to the present invention includes at least a first nonvolatile memory array (21), a second nonvolatile memory array (22), a first selector (24), and a second selector. A first nonvolatile memory (DFL) including a selector (25) and a first sense amplifier (26) is provided (see FIG. 2).

  In the first and second nonvolatile memory arrays of the first nonvolatile memory (DFL), complementary data is electrically written into two nonvolatile memory cells (MC1, MC2).

  One memory array (21) performs a normal data read operation (NR_RD), and one selector (24) receives complementary data from two nonvolatile memory cells (MC1, MC2) of one memory array (21). Supplying to the first and second input terminals of the first sense amplifier. In the one memory array (21), a nonvolatile storage operation of either writing or erasing is executed, and a verify read operation (VR_RD) related to the nonvolatile storage operation is executed. In the verify read operation, the one selector supplies the first verify read data from the one nonvolatile memory cell to one of the first and second input terminals of the first sense amplifier. A first verify reference signal is supplied to the other of the first and second input terminals of the first sense amplifier (see FIG. 2).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, a semiconductor non-volatile memory for writing complementary data in two memory cells is built in, and the chip area of the semiconductor integrated circuit can be reduced when performing verify read and normal data read from the semiconductor non-volatile memory.

<Typical embodiment>
First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor integrated circuit according to a typical embodiment of the present invention includes at least a first nonvolatile memory array (21), a second nonvolatile memory array (22), and a first selector (24). And a first nonvolatile memory (DFL) including a second selector (25) and a first sense amplifier (26) (see FIG. 2).

  In each of the first nonvolatile memory array and the second nonvolatile memory array, complementary data can be electrically written into two nonvolatile memory cells (MC1, MC2).

  The plurality of signal input lines of the first selector are connected to the plurality of bit lines (SBL) of the first nonvolatile memory array, and the plurality of signal input lines of the second selector are connected to the second nonvolatile memory. It is connected to a plurality of bit lines (SBL) of the memory array.

  The plurality of signal output lines of the first selector are connected to a first input terminal (In1) and a second input terminal (In2) of the first sense amplifier, and a plurality of signals of the second selector The output line is connected to the first input terminal and the second input terminal of the first sense amplifier.

  In one memory array (21) of the first and second nonvolatile memory arrays, a first normal data read operation (NR_RD) is performed. In the first normal data read operation, one selector (24) of the first and second selectors receives complementary data from two nonvolatile memory cells (MC1, MC2) of the one memory array. 1 is supplied to the first and second input terminals of one sense amplifier.

  In the one memory array, a first nonvolatile memory operation of writing or erasing one nonvolatile memory cell (MC1) of the two nonvolatile memory cells is executed, and the first nonvolatile memory operation is performed. A related first verify read operation (VR_RD) is performed.

  In the first verify read operation, the one selector sends the first verify read data from the one nonvolatile memory cell to one of the first and second input terminals of the first sense amplifier. Meanwhile, a first verify reference signal is supplied to the other of the first and second input terminals of the first sense amplifier (see FIG. 2).

  According to the embodiment, complementary data at the time of normal data reading is read by the first sense amplifier, and verify read data at the time of verify reading is also read by the first sense amplifier. The chip area of the circuit can be reduced. Furthermore, it is possible to easily design an operation margin for verify reading and normal data reading.

  A semiconductor integrated circuit according to a preferred embodiment includes at least a third nonvolatile memory array (31), a fourth nonvolatile memory array (32), a third selector (34), and a fourth selector ( And a second non-volatile memory (PFL) including a second sense amplifier (36) (see FIG. 3).

  In each of the third nonvolatile memory array and the fourth nonvolatile memory array, data can be electrically written to one nonvolatile memory cell (MC0).

  The signal input line of the third selector is connected to the bit line (SBL) of the third nonvolatile memory array, and the signal input line of the fourth selector is a bit line (of the fourth nonvolatile memory array). SBL).

  The signal output line of the third selector is connected to the first input terminal (In1) and the second input terminal (In2) of the second sense amplifier, and the signal output line of the fourth selector is The second sense amplifier is connected to the first input terminal and the second input terminal (see FIG. 10).

  In one of the third and fourth nonvolatile memory arrays (31), the second normal data read operation (NR_RD) is executed. In the second normal data read operation, one selector (34) of the third and fourth selectors is one nonvolatile memory cell of the one memory array of the third and fourth nonvolatile memory arrays. Data from (MC0) is supplied to one input terminal (In1) of the first and second input terminals of the second sense amplifier. In the second normal data read operation, a normal read reference signal is supplied to the other input terminal (In2) of the first and second input terminals of the second sense amplifier.

  In the one memory array of the third and fourth nonvolatile memory arrays, a second nonvolatile storage operation of either writing or erasing of the one nonvolatile memory cell is performed, and the second nonvolatile memory is performed. A second verify read operation (VR_RD) related to the operation is executed.

  In the second verify read operation, the one of the third and fourth selectors outputs the second verify read data from the one nonvolatile memory cell to the first sense amplifier. And one of the second input terminals. On the other hand, a second verify reference signal is supplied to the other of the first and second input terminals of the second sense amplifier (see FIG. 3).

  The semiconductor integrated circuit according to a more preferred embodiment further comprises a central processing unit (2).

  A program for the central processing unit can be stored in the second non-volatile memory (PFL).

  The first nonvolatile memory (DFL) can store data of the execution result of the program stored in the second nonvolatile memory by the central processing unit.

  In a semiconductor integrated circuit according to a more preferred embodiment, the first nonvolatile memory (DFL) and the second nonvolatile memory (PFL) form a built-in nonvolatile memory (6).

  The semiconductor integrated circuit includes a built-in random access memory (5), a high-speed bus (HBUS), a peripheral bus (PBUS), and a sequencer connected to a low-speed access port (LACSP) of the built-in nonvolatile memory (6). 7).

  The central processing unit is connected to the built-in random access memory and the high-speed access port (HACSP) of the built-in nonvolatile memory via the high-speed bus.

  The central processing unit stores data stored in the first nonvolatile memory and a program stored in the second nonvolatile memory via the high-speed bus and the high-speed access port of the built-in nonvolatile memory. It is possible to read.

  In response to an instruction from the central processing unit, the sequencer stores data stored in the first nonvolatile memory and the second nonvolatile memory via the low-speed bus and the low-speed access port. A program is stored in the built-in nonvolatile memory.

  In one specific embodiment, the two nonvolatile memory cells (MC1, MC2) of the first nonvolatile memory (DFL) and the one nonvolatile memory of the second nonvolatile memory (PFL). Each cell with the memory cell (MC0) performs a nonvolatile storage operation by injection of electrons into the charge storage layer (SiN) and emission of electrons from the charge storage layer.

  In another specific embodiment, in one of the first and second nonvolatile memory arrays of the first nonvolatile memory (DFL), the one of the two nonvolatile memory cells is the one of the two nonvolatile memory cells. The first nonvolatile memory operation and the first verify read operation of one nonvolatile memory cell are repeated. In the one of the third and fourth nonvolatile memory arrays of the second nonvolatile memory (PFL), the second nonvolatile memory operation and the second verify of the one nonvolatile memory cell are performed. The read operation is repeated.

  In still another specific embodiment, the first and second input terminals of the first sense amplifier in the first verify read operation of the first nonvolatile memory (DFL). Is supplied with the first verify reference signal generated from the first reference cell (Ref_Cell) (see FIG. 7). In the second verify read operation of the second nonvolatile memory (PFL), a second reference cell (Ref_Cell) is provided on the other of the first and second input terminals of the second sense amplifier. The second verify reference signal generated from the above is supplied (see FIG. 8).

  In still another specific embodiment, in the second normal data read operation of the second non-volatile memory (PFL), the first and second of the second sense amplifier are used. A normal read reference signal generated from the second reference cell (Ref_Cell) is supplied to the other input terminal.

  In a more specific embodiment, the one nonvolatile memory cell of the one of the third and fourth nonvolatile memory arrays of the second nonvolatile memory (PFL) has 2 It is possible to electrically write multi-value data of bits or more.

  In a most specific embodiment, the arrangement of the first nonvolatile memory (DFL) and the arrangement of the second nonvolatile memory (PFL) in the built-in nonvolatile memory (6) are: It can be set according to initialization control code data (INT_Data) used for system initialization of the semiconductor integrated circuit (see FIG. 12).

  [2] A typical embodiment of another aspect of the present invention includes at least a first nonvolatile memory array (21), a second nonvolatile memory array (22), and a first selector (24). And a method of operating a semiconductor integrated circuit (see FIG. 2) including a first nonvolatile memory (DFL) including a second selector (25) and a first sense amplifier (26).

  In each of the first nonvolatile memory array and the second nonvolatile memory array, complementary data is electrically written into two nonvolatile memory cells (MC1, MC2).

  The plurality of signal input lines of the first selector are connected to the plurality of bit lines (SBL) of the first nonvolatile memory array, and the plurality of signal input lines of the second selector are connected to the second nonvolatile memory. It is connected to a plurality of bit lines (SBL) of the memory array.

  The plurality of signal output lines of the first selector are connected to a first input terminal (In1) and a second input terminal (In2) of the first sense amplifier, and a plurality of signals of the second selector The output line is connected to the first input terminal and the second input terminal of the first sense amplifier.

  In one memory array (21) of the first and second nonvolatile memory arrays, a first normal data read operation (NR_RD) is performed. In the first normal data read operation, one selector (24) of the first and second selectors receives complementary data from two nonvolatile memory cells (MC1, MC2) of the one memory array. One sense amplifier is supplied to the first and second input terminals.

  In the one memory array, a first nonvolatile memory operation of writing or erasing one nonvolatile memory cell (MC1) of the two nonvolatile memory cells is executed, and the first nonvolatile memory operation is performed. The related first verify read operation (VR_RD) is executed.

  In the first verify read operation, the one selector sends the first verify read data from the one nonvolatile memory cell to one of the first and second input terminals of the first sense amplifier. On the other hand, a first verify reference signal is supplied to the other of the first and second input terminals of the first sense amplifier (see FIG. 2).

  According to the embodiment, complementary data at the time of normal data reading is read by the first sense amplifier, and verify read data at the time of verify reading is also read by the first sense amplifier. The chip area of the circuit can be reduced. Furthermore, it is possible to easily design an operation margin for verify reading and normal data reading.

  A preferred embodiment comprises at least a third nonvolatile memory array (31), a fourth nonvolatile memory array (32), a third selector (34), a fourth selector (35), This is a method of operating a semiconductor integrated circuit further comprising a second nonvolatile memory (PFL) including a second sense amplifier (36) (see FIG. 3).

  In each of the third nonvolatile memory array and the fourth nonvolatile memory array, data is electrically written into one nonvolatile memory cell (MC0).

  The signal input line of the third selector is connected to the bit line (SBL) of the third nonvolatile memory array, and the signal input line of the fourth selector is a bit line (of the fourth nonvolatile memory array). SBL).

  The signal output line of the third selector is connected to the first input terminal (In1) and the second input terminal (In2) of the second sense amplifier, and the signal output line of the fourth selector is The second sense amplifier is connected to the first input terminal and the second input terminal (see FIG. 10).

  In one of the third and fourth nonvolatile memory arrays (31), the second normal data read operation (NR_RD) is executed. In the second normal data read operation, one selector (34) of the third and fourth selectors is one nonvolatile memory cell of the one memory array of the third and fourth nonvolatile memory arrays. Data from (MC0) is supplied to one input terminal (In1) of the first and second input terminals of the second sense amplifier. In the second normal data read operation, a normal read reference signal is supplied to the other input terminal (In2) of the first and second input terminals of the second sense amplifier.

  In the one memory array of the third and fourth nonvolatile memory arrays, a second nonvolatile storage operation of either writing or erasing of the one nonvolatile memory cell is performed, and the second nonvolatile memory is performed. A second verify read operation (VR_RD) related to the operation is executed.

  In the second verify read operation, the one of the third and fourth selectors outputs the second verify read data from the one nonvolatile memory cell to the first sense amplifier. And one of the second input terminals. On the other hand, a second verify reference signal is supplied to the other of the first and second input terminals of the second sense amplifier (see FIG. 3).

<< Description of Embodiment >>
Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

<Microcomputer>
FIG. 1 is a diagram showing a configuration of a microcomputer (MCU) 1 according to an embodiment of the present invention. The microcomputer 1 shown in FIG. 1 is formed on a single semiconductor chip made of single crystal silicon by a miniaturized CMOS semiconductor manufacturing process.

  The microcomputer 1 has a two-level bus configuration of a high-speed bus HBUS and a peripheral bus PBUS. The high-speed bus HBUS and the peripheral bus PBUS each have a data bus, an address bus, and a control bus. By separating the bus into a two-level bus configuration, the bus load is reduced compared to the case where all circuits are commonly connected to the common bus, and high-speed access operation is possible.

  The high-speed bus HBUS includes a central processing unit (CPU) 2, a direct memory access controller (DMAC) 3, and a bus interface control between the high-speed bus HBUS and the peripheral bus PBUS. A bus interface circuit (BIF) 4 that performs bus bridge control is connected. Further, a random access memory (RAM) 5 used for a work area of the central processing unit 2 and a flash memory module (FMDL) 6 as a nonvolatile memory module for storing data and programs are connected to the high-speed bus HBUS. Is done. The flash memory module (FMDL) 6 includes a data flash DFL shown in FIG. 2 and a program flash PFL shown in FIG. Various software programs for the central processing unit (CPU) 2 are stored in the program flash PFL, and various data of program execution results by the central processing unit (CPU) 2 are stored in the data flash DFL.

  The peripheral bus PBUS includes a flash sequencer (FSQC) 7 for controlling command access related to the flash memory module (FMDL) 6, external input / output ports (PRT) 8 and 9, a timer (TMR) 10, and an internal microcomputer. A clock pulse generator (CPG) 11 for generating a clock signal is connected. An oscillator is connected to the clock terminals XTAL / EXTAL or an external clock signal is supplied, a standby state instruction signal is supplied to the external hardware standby terminal STBY, and a reset instruction signal is supplied to the external reset terminal RES. Supplied. An operating power supply voltage is supplied between the external power supply terminal Vcc and the external ground terminal Vss.

  Here, since the flash sequencer 7 is designed by logic synthesis as a logic circuit, and the flash memory module 6 having a memory array configuration is designed by using a CAD tool, it is shown as a separate circuit block for convenience. Is configured as one flash memory integrated with each other. The flash memory module 6 is connected to the high-speed bus HBUS via a read-only high-speed access port (HACSP). Therefore, the CPU 2 and the DMAC 3 can read-access the flash memory module 6 via the high-speed bus HBUS and the high-speed access port (HACSP). When the CPU 2 or the DMAC 3 executes a write / erase access to the flash memory module 6, it issues a command to the flash sequencer 7 via the bus interface 4 and the peripheral bus PBUS. As a result, the flash sequencer 7 controls the erase and write operations of the flash memory module via the peripheral bus PBUS and the low-speed access port (LACSP).

<Flash memory module>
FIG. 2 is a diagram showing the configuration of the data flash DFL included in the flash memory module (FMDL) 6 built in the microcomputer (MCU) 1 shown in FIG.

  The data flash DFL of the flash memory module 6 shown in FIG. 2 stores various data of program execution results by the central processing unit (CPU) 2 of the microcomputer (MCU) 1 of FIG. In order to enable accurate data reading even by exhaustion due to the large number of data rewrites of the data flash DFL of FIG. 2, the data flash DFL of FIG. 2 has complementary data stored in the twin cell composed of two nonvolatile memory cells MC1 and MC2. A 2-cell / 1-bit writing method of writing 1 bit is employed.

  FIG. 3 is a diagram showing a configuration of the program flash PFL included in the flash memory module (FMDL) 6 built in the microcomputer (MCU) 1 shown in FIG.

  The program flash PFL of the flash memory module 6 shown in FIG. 3 stores various software programs for the central processing unit (CPU) 2 of the microcomputer (MCU) 1 of FIG. In order to enable high-density storage of the program flash PFL with a small number of data rewrites in FIG. 3, in the program flash PFL in FIG. 3, one cell / 1 that says that one bit of single data is written in one nonvolatile memory cell MC0. Bit writing method is adopted.

<< Nonvolatile memory cell >>
4 includes two nonvolatile memory cells MC1 and MC2 in which one bit of complementary data is written and included in the data flash DFL of FIG. 2, and one bit of single data is written in the program flash PFL in FIG. It is a figure which shows the structure and operation | movement of non-volatile memory cell MC0.

  As shown in FIG. 4A, each of these nonvolatile memory cells MC1, MC2, and MC0 is formed of a split gate type flash memory element. This memory element has a control gate (CG) and a memory gate (MG) formed on a channel region between the source and drain via a gate insulating film, and the memory gate (MG) and the gate insulating film. A charge trapping region (SiN) such as silicon nitride is formed between them. The source or drain region on the control gate (CG) side is connected to the bit line (BL), and the source or drain region on the memory gate (MG) side is connected to the source line (SL).

  Various modes of operation of the nonvolatile memory cell shown in FIG. 4A are shown in FIG.

  First, in order to lower the threshold voltage (Vth) of the memory cell, BL = Hi−Z (high impedance state), CG = 1.5V, MG = −10V, SL = 6V, and WELL = 0V. Thus, electrons are extracted from the charge trap region (SiN) to the well region (WELL) by a high electric field between the well region (WELL) and the memory gate MG. This processing unit is a plurality of memory cells sharing a memory gate.

  Next, to raise the threshold voltage (Vth) of the memory cell, BL = 0V, CG = 1.5V, MG = 10V, SL = 6V, WELL = 0V, and writing from the source line SL to the bit line Apply current. As a result, hot electrons generated at the boundary between the control gate and the memory gate are injected into the charge trap region (SiN). Since the electron injection is determined by whether or not the bit line current is passed, this process is controlled in units of bits.

  Further, the read operation is executed with BL = 1.5V, CG = 1.5V, MG = 0V, SL = 0V, and WELL = 0V. If the threshold voltage of the memory cell is low, the memory cell is turned on. If the threshold voltage is high, the memory cell is turned off. Each of the nonvolatile memory cells MC1, MC2, and MC0 is not limited to the split gate type flash memory element shown in FIG. 4A, but may be a stacked gate type flash memory element. This stacked gate flash memory device is configured by stacking a floating gate (FG) and a control gate (WL) on a channel formation region between a source / drain region via a gate insulating film. . The threshold voltage can be raised by a hot carrier writing method or an FN tunnel writing method, and the threshold voltage can be lowered by emitting electrons to the well region (WELL) or emitting electrons to the bit line (BL).

<< Two nonvolatile memory cells included in data flash >>
FIG. 5 is a diagram for explaining three states of one twin cell comprised of two nonvolatile memory cells MC1 and MC2 that are included in the data flash DFL of FIG. 2 and in which one bit of complementary data is written.

  The information storage state by one twin cell composed of two nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) in which 1 bit of complementary data is written is the initialized erase state (blank erase state) of FIG. There are three types of data “1” write states in FIG. 5B and data “0” write states in FIG.

  The initialization erase state in FIG. 5A of one twin cell composed of two nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) of the data flash DFL shares the memory gate (MG) described in FIG. This can be realized by the operation of lowering the threshold voltage (Vth) of the memory cell using a plurality of memory cells as processing units.

  The write state of the data “1” in FIG. 5B of one twin cell composed of two nonvolatile memory cells MC1 and MC2 of the data flash DFL will be described with reference to FIG. 4 from the initialized erase state in FIG. 5A. The increase of the threshold voltage (Vth) of the memory cell by the control in bit units can be realized by executing the nonvolatile memory cell MC2 (negative cell).

  The write state of the data “0” in FIG. 5C of one twin cell composed of two nonvolatile memory cells MC1 and MC2 of the data flash DFL will be described with reference to FIG. 4 from the initialized erase state in FIG. 5A. The increase of the threshold voltage (Vth) of the memory cell by the bit unit control can be realized by executing the nonvolatile memory cell MC1 (positive cell).

<< Nonvolatile memory cell included in program flash PFL >>
FIG. 6 is a diagram illustrating two states of the nonvolatile memory cell MC0 that is included in the program flash PFL of FIG. 3 and in which one bit of single data is written.

  There are two types of information storage states of the nonvolatile memory cell MC0 to which one bit of single data is written, an erase state of data “1” in FIG. 6A and a write state of data “0” in FIG. It becomes.

  The erased state of the data “1” in FIG. 6A is a decrease in the threshold voltage (Vth) of the memory cell having a plurality of memory cells sharing the memory gate (MG) described in FIG. It can be realized by operation.

  The write state of the data “0” in FIG. 6B is the threshold voltage (Vth) of the memory cell by the bit unit control described in FIG. 4 from the erase state of the data “1” in FIG. The increase can be realized by executing the nonvolatile memory cell MC0.

<Data Flash Architecture>
2 includes various twin cells composed of two nonvolatile memory cells MC1 and MC2 into which 1 bit of complementary data is written as described in FIG. 5, and shows various results of program execution by the CPU 2 of the MCU 1 in FIG. 1 shows an architecture of a data flash DFL for storing data.

  2 includes a first nonvolatile memory array (MARY_J) 21, a second nonvolatile memory array (MARY_K) 22, a column decoder (YDEC) 23, a first column selector (YSEL_J) 24, and a second column selector. (YSEL_K) 25 and sense amplifier (SA) 26 are included. The data flash DFL further includes a write data input buffer 27, a data write / verify circuit 28, and a data output latch driver 29.

  Each of the first non-volatile memory array (MARY_J) 21 and the second non-volatile memory array (MARY_K) 22 includes a large number of twin cells composed of two non-volatile memory cells MC1 (positive cell) and MC2 (negative cell). Various data of the program execution result by the CPU 2 can be stored. The control gate (CG), memory gate (MG) and source of the two nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) in the row direction are the word line (WL), memory gate line (MGL) and source line. (SL) is connected to each.

  The first non-volatile memory array (MARY_J) 21 and the second non-volatile memory array (MARY_K) 22 employ a hierarchical bit line architecture in order to increase the speed of data writing and data reading and to reduce power consumption. Yes. That is, one write main bit line WMBL and one read main bit line RMBL are connected to the first and second nonvolatile memory arrays (MARY_J, K) 21 and 22.

  The plurality of sub bit lines SBL to which the plurality of nonvolatile memory cells MC1 and MC2 are connected are connected to one write main bit line WMBL via the source / drain path of the switch MOS transistor Q3 of the bit line switch BL_SW. When data is written to the nonvolatile memory cell MC1 (positive cell), the bit line switch BL_SW between the sub bit line SBL connected to the nonvolatile memory cell MC1 (positive cell) and one write main bit line WMBL. The switch MOS transistor Q3 is controlled to be turned on by the control signal line ZL. At the time of data writing to the data flash DFL of FIG. 2, write data Qin is supplied to one write main bit line WMBL via the write data input buffer 27, the selector V_SEL of the data write / verify circuit 28, and the write latch Write Latch. Is done. Write data supplied to one write main bit line WMBL is stored in the nonvolatile memory cell MC1 (positive cell) of the data flash DFL via the bit line switch BL_SW in the first and second nonvolatile memory arrays 21 and 22. The data is written into the nonvolatile memory cell MC2 (negative cell). The write data Qin supplied to the write data input buffer 27 is sent from the flash memory module 6 via the peripheral bus PBUS and the low-speed access port (LACSP) by the flash sequencer 7 in response to the write request from the CPU 2 in the MCU 1 of FIG. Is supplied along with a write command to the data flash DFL.

  The plurality of sub bit lines SBL to which the plurality of nonvolatile memory cells MC1 and MC2 of the first and second nonvolatile memory arrays (MARY_J, K) 21 and 22 are connected are connected to the first and second column selectors ( YSEL_J, K) 24 and 25 and a sense amplifier (SA) 26 are connected to one read main bit line RMBL. Each sub bit line SBL is connected to a discharge switch Dis_Sw controlled by a discharge control signal Dch in order to discharge the potential of the sub bit line SBL at the end of the read operation and at the end of the write operation.

<Reading normal data with data flash>
In response to a read request from the CPU 2 in the MCU 1 in FIG. 1, the read operation of the data flash DFL in FIG. Be started.

  That is, two nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) constituting one twin cell of one of the first and second nonvolatile memory arrays 21 and 22 of the data flash DFL of FIG. ) Starts reading normal data. The data read by the normal data reading is data in a writing state of data “1” in FIG. 5B or data in a writing state of data “0” in FIG. That is, data read by normal data reading is complementary data from two nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) constituting one twin cell.

  As shown in the normal data read signal path NR_RD of FIG. 2, complementary data from the two nonvolatile memory cells MC1 and MC2 of the first nonvolatile memory array 21 are composed of two sub-bit lines SBL and a first selector. 24 is supplied in parallel to the first input terminal In1 and the second input terminal In2 of the sense amplifier 26. Even if the difference between the threshold voltages of the transistors of the two nonvolatile memory cells MC1 and MC2 is slightly reduced due to exhaustion due to the large number of data rewrites of the data flash DFL of FIG. 2, the sense amplifier is a differential amplification type sense amplifier. The amplifier 26 can accurately amplify the slightly reduced threshold voltage difference. As a result, even if the number of rewrites of the data flash DFL in FIG. 2 is increased and the memory cells of the data flash DFL are somewhat exhausted, accurate read data is read from the sense amplifier 26 and the data output latch driver 29 at the time of data read. Can be output. The data read by the sense amplifier 26 and the data output latch driver 29 from the nonvolatile memory arrays 21 and 22 of the data flash DFL in FIG. 2 by normal data reading is read-only high-speed access port in the MCU 1 in FIG. (HACSP) and a high-speed bus (HBUS) can be supplied to the CPU 2.

  As described above, in the normal data reading of the data flash DFL, the column selectors 24 and 25 receive the complementary data from the positive cells and negative cells constituting one twin cell of the nonvolatile memory arrays 21 and 22 in the first of the sense amplifier 26. And the second input terminals In1 and In2 can be supplied in parallel.

<Verify read with data flash>
In the MCU 1 of FIG. 1, regarding the write request from the CPU 2, the data flash DFL of FIG. The write operation is started. In the write operation of the nonvolatile memory of the data flash DFL, a write verify read for verifying whether correct data is written in the nonvolatile memory must be performed.

  Therefore, the two nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) constituting one twin cell of either the first or second nonvolatile memory array 21, 22 of the data flash DFL of FIG. At the time of writing complementary data, write verify read is performed. As described above, the complementary data is written to the nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) as shown in FIGS. 5B and 5C from the initialized erase state of FIG. 5A. This can be realized by increasing the threshold voltage (Vth) of one of the positive cell and the negative cell.

  As shown in the verify read signal path VR_RD in FIG. 2, the write verify read data from the memory cell whose threshold voltage (Vth) is increased during the writing of the complementary data is connected to one sub-bit line SBL. The signal is supplied to the first input terminal In 1 of the sense amplifier 26 via the first selector 24. In parallel with this, the write verify reference level is supplied to the second input terminal In2 of the sense amplifier 26.

  Voltages BL = 0V, CG = 1.5V, MG = 10V, SL = 6V, WELL = 0V in order to increase the threshold voltage (Vth) of one of the positive and negative memory cells when writing complementary data A conditional write pulse is applied. If the threshold voltage (Vth) of one memory cell is determined to be lower than the write verify reference level by verify reading through the signal path VR_RD after the application of the write pulse, writing is insufficient. In this case, another write pulse with the above voltage condition is applied again to one memory cell. If it is determined that the threshold voltage (Vth) of one memory cell is higher than the write verify reference level by the write verify read through the signal path VR_RD after another application of the write pulse, the write is sufficient. Become.

  When the writing is insufficient, a low level “0” is generated from the output of the exclusive NOR circuit EXNOR of the data write / verify circuit 28. If the write unit is an 8-bit twin cell, when a low level “0” is output from the output of at least one exclusive-OR circuit EXNOR of the eight exclusive-NOR circuits EXNOR, an AND circuit A low level “0” is output from the AND output, and the next write pulse is applied again to the twin cell in the 8-bit write unit. When writing is sufficient, a high level “1” is generated from the output of the exclusive NOR circuit EXNOR of the data write / verify circuit 28. If the write unit is an 8-bit twin cell, a high level “1” is output from the outputs of the eight exclusive-OR circuits EXNOR, a high level “1” is output from the output of the AND circuit AND, and an 8-bit Writing to the twin cell of the writing unit is completed.

  In this manner, in the write verify read of the data flash DFL, the column selectors 24 and 25 perform the write verify read data and the write verify reference level from one cell in which writing is performed in one twin cell of the nonvolatile memory arrays 21 and 22. Can be supplied to the first and second input terminals of the sense amplifier 26 in parallel.

  In the MCU 1 of FIG. 1, regarding the erase request from the CPU 2, according to the erase command to the data flash DFL of the flash memory module 6 via the peripheral bus PBUS and the low speed access port (LACSP) by the flash sequencer 7. The erase operation is started. In the erase operation of the nonvolatile memory of the data flash DFL, erase verify read for verifying whether the nonvolatile memory has been erased must be performed.

  Further, in the data flash DFL of FIG. 2, the two nonvolatile memory cells have a low threshold prior to the writing of complementary data to the two nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) constituting one twin cell. An initializing erase operation for writing erase data of data “1” corresponding to the value voltage is required. This initialization erasing operation also requires an erasure verifying operation as to whether erasure data of low threshold voltage data “1” has been correctly written in the two nonvolatile memory cells. In the initialize erase operation, a plurality of twin cell nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) sharing the control gate (CG) and the memory gate (MG) are used as a processing unit of the erase operation. In order to lower the threshold voltage (Vth) of a plurality of twin-cell non-volatile memory cells MC1 (positive cell) and MC2 (negative cell) in the processing unit of the erase operation, BL = Hi-Z (high impedance state), CG = An erase pulse having a voltage condition of 1.5 V, MG = −10 V, SL = 6 V, and WELL = 0 V is applied. If the threshold voltage (Vth) of the memory cell is higher than the erase verify reference level by the erase verify read by the signal path VR_RD after the application of the erase pulse, the erase is insufficient. In this case, the erase pulse having the voltage condition described above is applied to the memory cell. If it is determined that the threshold voltage (Vth) of the memory cell is lower than the verify reference level by erase verify read by the erase signal path VR_RD after application of another erase pulse, the erase is sufficient.

  When the erasure is insufficient, a low level “0” is generated from the output of the exclusive NOR circuit EXNOR of the data write / verify circuit 28. If the erase unit is an 8-bit twin cell, when a low level “0” is output from the output of at least one exclusive NOR circuit EXNOR of the eight exclusive NOR circuits EXNOR, an AND circuit A low level “0” is output from the AND output, and the next erase pulse is applied again to the twin cell of the 8-bit erase unit. When erasing is sufficient, a high level “1” is generated from the output of the exclusive NOR circuit EXNOR of the data write / verify circuit 28. If the erasing unit is an 8-bit twin cell, a high level “1” is output from the outputs of the eight exclusive NOR circuits EXNOR, and a high level “1” is output from the output of the AND circuit AND. Erase of the erase unit twin cell is completed.

  As described above, in the erase verify read of the data flash DFL, the column selectors 24 and 25 determine the erase verify read data and the erase verify reference level from the cells to be erased by the twin cells in the erase unit of the nonvolatile memory arrays 21 and 22, respectively. It is possible to supply the first and second input terminals of the sense amplifier 26 in parallel.

《Program Flash Architecture》
FIG. 3 shows a program flash PFL that stores various software programs for the CPU 2 of the MCU 1 of FIG. 1 including a large number of nonvolatile memory cells MC 0 to which one bit of single data is written as described in FIG. It shows the architecture.

  The structure of the program flash PFL in FIG. 3 is very similar to that of the data flash PFL in FIG. That is, the program flash PFL of FIG. 3 includes a third nonvolatile memory array (MARY_J) 31, a fourth nonvolatile memory array (MARY_K) 32, a column decoder (YDEC) 33, a third column selector (YSEL_J) 34, a fourth A column selector (YSEL_K) 35 and a sense amplifier (SA) 36 are included. The program flash PFL further includes a write data input buffer 37, a data write / verify circuit 38, and a data output latch driver 39.

  Each of the third non-volatile memory array (MARY_J) 31 and the fourth non-volatile memory array (MARY_K) 32 includes a large number of non-volatile memory cells MC0 to store various software programs for the CPU 2. Can do. The control gate (CG), memory gate (MG) and source of a large number of nonvolatile memory cells MC0 in the row direction are respectively connected to the word line (WL), memory gate line (MGL) and source line (SL). ing.

  In the third non-volatile memory array (MARY_J) 31 and the fourth non-volatile memory array (MARY_K) 32, a hierarchical bit line architecture is adopted for high-speed data writing and data reading and low power consumption. Yes. That is, one write main bit line WMBL and one read main bit line RMBL are connected to the third and fourth nonvolatile memory arrays (MARY_J, K) 31 and 32.

  The plurality of sub bit lines SBL to which the plurality of nonvolatile memory cells MC0 are connected are connected to one write main bit line WMBL via the source / drain path of the switch MOS transistor Q3 of the bit line switch BL_SW. When data is written to the nonvolatile memory cell MC0, the switch MOS transistor Q3 of the bit line switch BL_SW between the sub bit line SBL connected to the nonvolatile memory cell MC0 and one write main bit line WMBL is The on state is controlled by the control signal line ZL. At the time of writing data to the program flash PFL in FIG. 3, the write data Qin is supplied to one write main bit line WMBL via the write data input buffer 37, the selector V_SEL of the data write / verify circuit 38, and the write latch Write Latch. Is done. Write data supplied to one write main bit line WMBL is written into the nonvolatile memory cell MC0 of the program flash PFL via the bit line switch BL_SW in the third and fourth nonvolatile memory arrays 31 and 32. The write data Qin supplied to the write data input buffer 37 is stored in the flash memory module 6 via the peripheral bus PBUS and the low-speed access port (LACSP) by the flash sequencer 7 in response to the write request of the CPU 2 in the MCU 1 of FIG. Is supplied along with a write command to the program flash PFL.

  The plurality of sub bit lines SBL to which the plurality of nonvolatile memory cells MC0 of the third and fourth nonvolatile memory arrays (MARY_J, K) 31, 32 are connected are connected to the third and fourth column selectors (YSEL_J, K) are connected to one read main bit line RMBL via 34 and 35 and a sense amplifier (SA) 36. Each sub bit line SBL is connected to a discharge switch Dis_Sw controlled by a discharge control signal Dch in order to discharge the potential of the sub bit line SBL at the end of the read operation and at the end of the write operation.

<Reading normal data with program flash>
The MCU 1 in FIG. 1 reads the program flash PFL in FIG. 3 according to the read command to the program flash PFL in the flash memory module 6 via the high-speed bus HBUS and the high-speed access port (HACSP) in relation to the read request from the CPU 2. Operation starts.

  That is, an operation of reading 1-bit normal data of single data from one nonvolatile memory cell MC0 of one of the first and second nonvolatile memory arrays 31 and 32 of the program flash PFL in FIG. Is started. The data read by the normal data reading is data in a write state of data “0” in FIG. 6B or data in an erase state of data “1” in FIG.

  As shown in the normal data read signal path NR_RD in FIG. 3, single data from one nonvolatile memory cell MC0 of the first nonvolatile memory array 31 is composed of one sub-bit line SBL and the first selector 34. To the first input terminal In1 of the sense amplifier 36. At the same time, a normal data read reference level generated from a reference cell (not shown) is supplied to the second input terminal In2 of the sense amplifier 36. The normal data read reference level is approximately halfway between the low threshold voltage of the data “1” erased state in FIG. 6A and the high threshold voltage of the data “0” written state in FIG. This corresponds to a threshold voltage of a certain level. The program flash PFL with a relatively small number of rewrites in FIG. 3 employs a 1-cell / 1-bit write method in which 1 bit of single data is written in one nonvolatile memory cell MC0. High density storage of PFL is possible. Program data read by the sense amplifier 36 and the data output latch driver 39 from the nonvolatile memory arrays 31 and 32 of the program flash PFL in FIG. 3 by normal data reading is read-only high-speed access in the MCU 1 in FIG. It can be supplied to the CPU 2 via a port (HACSP) and a high-speed bus (HBUS).

  As described above, in the normal data read of the program flash PFL, the column selectors 34 and 35 receive the single data from one nonvolatile memory cell MC0 of the nonvolatile memory arrays 31 and 32 as the first and the first of the sense amplifier 36. The voltage is supplied to one input terminal of the second input terminals In1 and In2. On the other hand, in this normal data read, the column selectors 34 and 35 can supply the normal data read reference level to the other input terminal of the first and second input terminals In1 and In2 of the sense amplifier 36.

<Verify read with program flash>
In the MCU 1 in FIG. 1, a program write request is issued from the CPU 2 or the DMAC 3 to the flash memory module 6 although the frequency is relatively low. The program of the program flash PFL of FIG. 3 according to the program write command to the program flash PFL of the flash memory module 6 via the peripheral bus PBUS and the low speed access port (LACSP) by the flash sequencer 7 in relation to the program write request The write operation is started. In the program write operation of the nonvolatile memory of the program flash PFL, a write verify read for verifying whether the program data is correctly written in the nonvolatile memory has to be performed.

  Therefore, the write verify read is performed when writing one bit of single data to one of the first and second nonvolatile memory arrays 31 and 32 of the program flash PFL of FIG. Is called. As described above, the single data write to the nonvolatile memory cell MC0 is performed by changing the threshold voltage (Vth) of the nonvolatile memory cell MC0 from the erased state of FIG. 6A as shown in FIG. 6B. It can be realized by rising.

  As shown in the verify read signal path VR_RD in FIG. 3, single data from one nonvolatile memory cell MC0 of the first nonvolatile memory array 31 is 1 in the same manner as the normal data read signal path NR_RD. The signal is supplied to the first input terminal In 1 of the sense amplifier 36 through the sub bit line SBL and the first selector 34. At the same time, the write verify reference level generated from the reference cell (not shown) is supplied to the second input terminal In2 of the sense amplifier 36. This write verify reference level is approximately halfway between the low threshold voltage in the erased state of data “1” in FIG. 6A and the high threshold voltage in the written state of data “0” in FIG. This corresponds to the threshold voltage of the level. Preferably, the write verify reference level is closer to the threshold voltage of the write state of data “0” in FIG. 6B than the intermediate level threshold voltage.

  Voltages of BL = 0V, CG = 1.5V, MG = 10V, SL = 6V, WELL = 0V in order to increase the threshold voltage (Vth) of one nonvolatile memory cell MC0 when writing single data A conditional write pulse is applied. If the threshold voltage (Vth) of one nonvolatile memory cell MC0 is lower than the write verify reference level by verify read by the signal path VR_RD after the application of the write pulse, the writing is insufficient. In this case, another write pulse with the above voltage condition is applied again to one nonvolatile memory cell MC0. If it is determined that the threshold voltage (Vth) of one nonvolatile memory cell MC0 is higher than the write verify reference level by the write verify read by the signal path VR_RD after the application of another write pulse, the write is performed. It will be enough.

  When the writing is insufficient, a low level “0” is generated from the output of the exclusive NOR circuit EXNOR of the data write / verify circuit 38. If the write unit is a non-volatile memory cell MC0 of 8 bits, a low level “0” is output from the output of at least one exclusive NOR circuit EXNOR of the eight exclusive NOR circuits EXNOR. Then, a low level “0” is output from the output of the AND circuit AND, and the next write pulse is applied again to the nonvolatile memory cell MC0 in the 8-bit write unit. When writing is sufficient, a high level “1” is generated from the output of the exclusive NOR circuit EXNOR of the data write / verify circuit 38. If the write unit is a non-volatile memory cell MC0 of 8 bits, the high level “1” is output from the outputs of the eight exclusive NOR circuits EXNOR, and the high level “1” is output from the output of the AND circuit AND. , Writing to the nonvolatile memory cell MC0 in 8-bit writing units is completed.

  Thus, in the write verify read of the program flash PFL, single data from one nonvolatile memory cell MC0 of the first nonvolatile memory array 31 is subjected to the verify read exactly the same as the signal path NR_RD for normal data read. The signal path VR_RD is used and supplied to the first input terminal In1 of the sense amplifier 36 through one sub-bit line SBL and the first selector 34. At the same time, the write verify reference level generated from the reference cell (not shown) is supplied to the second input terminal In2 of the sense amplifier 36.

  Although the frequency is relatively low, in relation to the erasure request from the CPU 2 in the MCU 1 in FIG. 1, the flash sequencer 7 sends the flash memory module 6 to the program flash PFL via the peripheral bus PBUS and the low-speed access port (LACSP). According to the erase command, the erase operation of the program flash PFL in FIG. 3 is started. In the erase operation of the nonvolatile memory of the program flash PFL, erase verify read for verifying whether the nonvolatile memory has been erased must be performed.

  Further, in the program flash PFL of FIG. 3, all the nonvolatile memory cells MC0 included in the first and second nonvolatile memory arrays 31 and 32 prior to the writing of single data to one nonvolatile memory cell MC0. It is necessary to perform the erase operation. By this erasing operation, all the non-volatile memory cells MC0 included in the first and second non-volatile memory arrays 31, 32 have a low threshold voltage in the erased state of the data “1” in FIG. State. This erase operation also requires an erase verify operation as to whether erase data of low threshold voltage data “1” has been correctly written in the nonvolatile memory cell MC0. In the erase operation, a plurality of nonvolatile memory cells MC0 sharing the control gate (CG) and the memory gate (MG) are used as a processing unit of the erase operation. In order to lower the threshold voltage (Vth) of the plurality of nonvolatile memory cells MC0 in the processing unit of the erase operation, BL = Hi−Z (high impedance state), CG = 1.5V, MG = −10V, SL An erase pulse having a voltage condition of 6V and WELL = 0V is applied. If the threshold voltage (Vth) of the memory cell is determined to be higher than the verify reference level by the erase verify read through the signal path VR_RD after the application of the erase pulse, the erase is insufficient. In this case, the erase pulse having the above voltage condition is applied again to the plurality of nonvolatile memory cells MC0 in the processing unit of the erase operation. If it is determined that the threshold voltage (Vth) of the memory cell is higher than the verify reference level by the erase verify read by the erase signal path VR_RD after application of another erase pulse, the erase is sufficient.

  When erasing is insufficient, a low level “0” is generated from the output of the exclusive NOR circuit EXNOR of the data write / verify circuit 38. If the erase unit is an 8-bit nonvolatile memory cell MC0, a low level “0” is output from the output of at least one of the exclusive NOR circuits EXNOR of the eight exclusive NOR circuits EXNOR. Then, a low level “0” is output from the output of the AND circuit AND, and the next erase pulse is applied again to the nonvolatile memory cell MC0 in the 8-bit erase unit. When erasing is sufficient, a high level “1” is generated from the output of the exclusive NOR circuit EXNOR of the data write / verify circuit 38. If the erasing unit is an 8-bit nonvolatile memory cell MC0, a high level “1” is output from the outputs of the eight exclusive NOR circuits EXNOR, and a high level “1” is output from the output of the AND circuit AND. , Erasure of the nonvolatile memory cell MC0 of the 8-bit erase unit is completed.

  As shown in the verify read signal path VR_RD in FIG. 3, single data from one nonvolatile memory cell MC0 of the first nonvolatile memory array 31 is 1 in the same manner as the normal data read signal path NR_RD. The signal is supplied to the first input terminal In 1 of the sense amplifier 36 through the sub bit line SBL and the first selector 34. At the same time, the erase verify reference level generated from the reference cell (not shown) is supplied to the second input terminal In2 of the sense amplifier 36. This erase verify reference level is approximately halfway between the low threshold voltage in the erased state of data “1” in FIG. 6A and the high threshold voltage in the written state of data “0” in FIG. This corresponds to the threshold voltage of the level. Preferably, the erase verify reference level is closer to the threshold voltage of the erased state of data “1” in FIG. 6A than the intermediate level threshold voltage.

  As described above, in the erase verify read of the program flash PFL, single data from one nonvolatile memory cell MC0 of the first nonvolatile memory array 31 is subjected to the verify read exactly the same as the signal path NR_RD for normal data read. The signal path VR_RD is used and supplied to the first input terminal In1 of the sense amplifier 36 through one sub-bit line SBL and the first selector 34. At the same time, the erase verify reference level generated from the reference cell (not shown) is supplied to the second input terminal In2 of the sense amplifier 36.

<Verify operation with data flash>
FIG. 7 shows a write verify operation of two nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) that constitute one twin cell by the first and second nonvolatile memory arrays 21 and 22 of the data flash DFL of FIG. 2 is a diagram showing a configuration of a data flash DFL for specifically performing an erase verify operation. FIG.

  In FIG. 7, the parasitic capacitance C1 of the first input terminal In1 and the parasitic capacitance C2 of the second input terminal In2 of the sense amplifier 26 are precharged to the precharge voltage Vpc by the precharge circuit PC during the precharge period. Can do. The precharge circuit PC includes a transistor Q5, a transistor Q6, and a transistor Qs. The transistor Q5 supplies the precharge voltage Vpc to the first input terminal In1 of the sense amplifier 26, and the transistor Q6 supplies the precharge voltage Vpc to the second input terminal In2 of the sense amplifier 26. The transistor Qs equalizes the voltage at the first input terminal In1 and the voltage at the second input terminal In2 of the sense amplifier 26. The transistors Q5, Q6, and Qs of the precharge circuit PC are P channel MOS transistors to which a precharge control signal PC_Cnt is supplied.

  The voltage of the first input terminal In1 and the second input terminal In2 of the sense amplifier 26 are connected to the reference cell Ref_Cell for the verify operation via the switch Ref_DC_SW. The switch Ref_DC_SW includes P-channel MOS transistors Q7 and Q8 to which control signals Ref_DC_J and Re_DC_K are supplied, respectively, and the reference cell Ref_Cell for the verify operation is configured by an N-channel MOS transistor Q9 to which a verify setting voltage Vgs_Ref_Cell is supplied. . The voltage level of the verify setting voltage Vgs_Ref_Cell supplied to the gate of the N-channel MOS transistor Q9 of the reference cell Ref_Cell is set by the reference cell control circuit Ref_Cell_Cnt.

  The reference cell control circuit Ref_Cell_Cnt includes a reference control register Cnt_Reg and an N-channel MOS transistor Q12 to which a reference voltage setting trimming voltage Vtrim is supplied. A current mirror circuit constituted by P channel MOS transistors Q10, Q11, Q13, Q14, Q15, Q16, Q17, Q18 is connected between the drain of the N channel MOS transistor Q12 and the power supply voltage Vcc. . The drain current of the N-channel MOS transistor Q12 to which the reference voltage setting trimming voltage Vtrim is supplied flows to the input transistors Q10 and Q11 of the current mirror circuit. A current mirror output current proportional to the current mirror input current flowing through the input transistors Q10 and Q11 of the current mirror circuit can flow through the output transistors Q13, Q14, Q15, Q16, Q17 and Q18 of the current mirror circuit.

  By supplying the current mirror output current of the current mirror circuit to the N-channel MOS transistor Q19 as a load, a verify setting voltage Vgs_Ref_Cell is generated between both ends of the load MOS transistor Q19. When the output data D0 and D1 of the reference control register Cnt_Reg change sequentially as “11”, “10”, “01”, and “00”, the voltage level of the verify setting voltage Vgs_Ref_Cell increases sequentially. In response to this, the current level of the verify reference current flowing in the drain / source path of the N-channel MOS transistor Q9 of the reference cell Ref_Cell can also increase sequentially.

  Two nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) constituting one twin cell in one of the first and second nonvolatile memory arrays 21 and 22 of the data flash DFL. ) Of the memory cell MC1 (positive cell) is performed. When writing in one memory cell MC1 (positive cell) is insufficient, the threshold voltage (Vth) of one memory cell MC1 (positive cell) is relatively low. Therefore, the cell current of one memory cell MC1 (positive cell) in one first nonvolatile memory array 21 is larger than the verify reference current of the N-channel MOS transistor Q9 of the reference cell Ref_Cell. At this time, in the switch Ref_DC_SW, the control signal Ref_DC_J is set to the high level “1”, the control signal Re_DC_K is set to the low level “0”, the P channel MOS transistor Q7 is turned off, and the P channel MOS transistor Q8 is turned on. Therefore, the parasitic capacitance C1 of the first input terminal In1 of the sense amplifier 26 is discharged by the large cell current of the memory cell MC1 (positive cell) from the precharge voltage level, and the parasitic capacitance C2 of the second input terminal In2 of the sense amplifier 26. Are discharged from the precharge voltage level by a small verify reference current of the reference cell Ref_Cell. Then, the potential of the first input terminal In1 of the sense amplifier 26 is lower than the potential of the second input terminal In2, and an unverified output signal corresponding to the input potential difference is generated from the output of the sense amplifier 26.

  Then, the next write pulse is applied again to one memory cell MC1 (positive cell), and the threshold voltage (Vth) of one memory cell MC1 (positive cell) rises. When writing in one memory cell MC1 (positive cell) reaches a sufficient level, the threshold voltage (Vth) of one memory cell MC1 (positive cell) is sufficiently high. Accordingly, the parasitic capacitance C1 of the first input terminal In1 of the sense amplifier 26 is discharged by the small cell current of the memory cell MC1 (positive cell) from the precharge voltage level, and the parasitic capacitance C2 of the second input terminal In2 of the sense amplifier 26 is detected. Are discharged from the precharge voltage level by a large verify reference current of the reference cell Ref_Cell. Then, the potential of the second input terminal In2 of the sense amplifier 26 is lower than the potential of the first input terminal In1, and a verify completion output signal corresponding to the input potential difference is generated from the output of the sense amplifier 26.

<Verify operation with program flash>
FIG. 8 specifically shows the normal read operation, write verify operation and erase verify operation of one of the first and second nonvolatile memory arrays 31 and 32 of the program flash PFL of FIG. It is a figure which shows the structure of the program flash PFL for performing.

  In FIG. 8, the parasitic capacitance C1 of the first input terminal In1 and the parasitic capacitance C2 of the second input terminal In2 of the sense amplifier 36 are precharged to the precharge voltage Vpc by the precharge circuit PC during the precharge period. Can do. The precharge circuit PC includes a transistor Q5, a transistor Q6, and a transistor Qs. The transistor Q5 supplies the precharge voltage Vpc to the first input terminal In1 of the sense amplifier 36, and the transistor Q6 supplies the precharge voltage Vpc to the second input terminal In2 of the sense amplifier 36. The transistor Qs equalizes the voltage at the first input terminal In1 and the voltage at the second input terminal In2 of the sense amplifier 36. The transistors Q5, Q6, and Qs of the precharge circuit PC are P channel MOS transistors to which a precharge control signal PC_Cnt is supplied.

  The voltage of the first input terminal In1 and the second input terminal In2 of the sense amplifier 36 are connected to a reference cell Ref_Cell for normal read operation and write / write verify operation via a switch Ref_DC_SW. The switch Ref_DC_SW includes P-channel MOS transistors Q7 and Q8 supplied with control signals Ref_DC_J and Re_DC_K, respectively, and the reference cell Ref_Cell is formed of an N-channel MOS transistor Q9 supplied with a verify setting voltage Vgs_Ref_Cell. The voltage level of the set voltage Vgs_Ref_Cell supplied to the gate of the N-channel MOS transistor Q9 of the reference cell Ref_Cell is set by the reference cell control circuit Ref_Cell_Cnt.

  The reference cell control circuit Ref_Cell_Cnt includes a reference control register Cnt_Reg and an N-channel MOS transistor Q12 to which a reference voltage setting trimming voltage Vtrim is supplied. A current mirror circuit constituted by P channel MOS transistors Q10, Q11, Q13, Q14, Q15, Q16, Q17, Q18 is connected between the drain of the N channel MOS transistor Q12 and the power supply voltage Vcc. . The drain current of the N-channel MOS transistor Q12 to which the reference voltage setting trimming voltage Vtrim is supplied flows to the input transistors Q10 and Q11 of the current mirror circuit. A current mirror output current proportional to the current mirror input current flowing through the input transistors Q10 and Q11 of the current mirror circuit can flow through the output transistors Q13, Q14, Q15, Q16, Q17 and Q18 of the current mirror circuit.

  By supplying the current mirror output current of the current mirror circuit to the N-channel MOS transistor Q19 as a load, a set voltage Vgs_Ref_Cell is generated between both ends of the load MOS transistor Q19. When the output data D0, D1 of the reference control register Cnt_Reg sequentially change to “11”, “10”, “01”, “00”, the voltage level of the set voltage Vgs_Ref_Cell increases sequentially. In response to this, the current level of the reference current flowing in the drain / source path of the N-channel MOS transistor Q9 of the reference cell Ref_Cell can also increase sequentially.

  A normal read operation of the nonvolatile memory cell MC0 is performed in one of the first and second nonvolatile memory arrays 31 and 32 of the program flash PFL. The storage state of the nonvolatile memory cell MC0 is either the erase state of data “1” in FIG. 6A or the write state of data “0” in FIG. Therefore, the level of the normal read reference current of the N channel MOS transistor Q9 of the reference cell Ref_Cell in this normal read operation is the low threshold voltage corresponding to the erased state of the data “1” in FIG. This corresponds to a threshold voltage substantially in the middle of the high threshold voltage corresponding to the writing state of data “0” of 6 (B).

  If the storage state of the nonvolatile memory cell MC0 in the first nonvolatile memory array 31 is the erased state of the data “1” in FIG. 6A, the cell current of the nonvolatile memory cell MC0 is equal to that of the reference cell Ref_Cell. It is larger than the read reference current of the N-channel MOS transistor Q9. At this time, in the switch Ref_DC_SW, the control signal Ref_DC_J is set to the high level “1”, the control signal Re_DC_K is set to the low level “0”, the P channel MOS transistor Q7 is turned off, and the P channel MOS transistor Q8 is turned on. Therefore, the parasitic capacitance C1 of the first input terminal In1 of the sense amplifier 36 is discharged by the large cell current of the nonvolatile memory cell MC0 from the precharge voltage level, and the parasitic capacitance C2 of the second input terminal In2 of the sense amplifier 36 is It is discharged from the precharge voltage level by an intermediate reference current of the reference cell Ref_Cell. Then, the potential of the first input terminal In1 of the sense amplifier 36 is lower than the potential of the second input terminal In2, and corresponds to the erase state of the data “1” in FIG. 6A from the output of the sense amplifier 36. An output signal is generated.

  If the storage state of the nonvolatile memory cell MC0 in the first nonvolatile memory array 31 is the data “0” write state of FIG. 6B, the cell current of the nonvolatile memory cell MC0 is the current of the reference cell Ref_Cell. It is smaller than the read reference current of the N channel MOS transistor Q9. At this time, in the switch Ref_DC_SW, the control signal Ref_DC_J is set to the high level “1”, the control signal Re_DC_K is set to the low level “0”, the P channel MOS transistor Q7 is turned off, and the P channel MOS transistor Q8 is turned on. Therefore, the parasitic capacitance C1 of the first input terminal In1 of the sense amplifier 36 is discharged by the small cell current of the nonvolatile memory cell MC0 from the precharge voltage level, and the parasitic capacitance C2 of the second input terminal In2 of the sense amplifier 36 is It is discharged from the precharge voltage level by an intermediate reference current of the reference cell Ref_Cell. Then, the potential of the second input terminal In2 of the sense amplifier 36 is lower than the potential of the first input terminal In1, and corresponds to the write state of the data “0” in FIG. 6B from the output of the sense amplifier 36. An output signal is generated.

  The write verify operation of the nonvolatile memory cell MC0 is performed in one first nonvolatile memory array 31 of the first and second nonvolatile memory arrays 31 and 32 of the program flash PFL. When writing in the nonvolatile memory cell MC0 is insufficient, the threshold voltage (Vth) of the nonvolatile memory cell MC0 is relatively low. Therefore, the cell current of the nonvolatile memory cell MC0 in one of the first nonvolatile memory arrays 31 is larger than the verify reference current of the N-channel MOS transistor Q9 of the reference cell Ref_Cell. At this time, in the switch Ref_DC_SW, the control signal Ref_DC_J is set to the high level “1”, the control signal Re_DC_K is set to the low level “0”, the P channel MOS transistor Q7 is turned off, and the P channel MOS transistor Q8 is turned on. Therefore, the parasitic capacitance C1 of the first input terminal In1 of the sense amplifier 36 is discharged by the large cell current of the nonvolatile memory cell MC0 from the precharge voltage level, and the parasitic capacitance C2 of the second input terminal In2 of the sense amplifier 36 is It is discharged from the precharge voltage level by a small verify reference current of the reference cell Ref_Cell. Then, the potential of the first input terminal In1 of the sense amplifier 36 is lower than the potential of the second input terminal In2, and an unverified output signal corresponding to the input potential difference is generated from the output of the sense amplifier 36.

  Then, the next write pulse is applied again to the nonvolatile memory cell MC0, and the threshold voltage (Vth) of the nonvolatile memory cell MC0 increases. When writing in the nonvolatile memory cell MC0 becomes a sufficient level, the threshold voltage (Vth) of the nonvolatile memory cell MC0 is sufficiently high. Accordingly, the parasitic capacitance C1 of the first input terminal In1 of the sense amplifier 36 is discharged by the small cell current of the nonvolatile memory cell MC0 from the precharge voltage level, and the parasitic capacitance C2 of the second input terminal In2 of the sense amplifier 36 is obtained. Are discharged from the precharge voltage level by a large verify reference current of the reference cell Ref_Cell. Then, the potential of the second input terminal In2 of the sense amplifier 36 is lower than the potential of the first input terminal In1, and a verify completion output signal corresponding to the input potential difference is generated from the output of the sense amplifier 36.

<Details of normal data reading with data flash>
FIG. 9 shows normal complementary data from two nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) that constitute one twin cell by the first and second nonvolatile memory arrays 21 and 22 of the data flash DFL of FIG. It is a figure which shows the read-out operation | movement in detail.

  In FIG. 9, a third column selector 241 is connected to the first column selector 24 connected to the first nonvolatile memory array 21, and a second column connected to the second nonvolatile memory array 22. A fourth column selector 251 is connected to the selector 25. The third column selector 241 is connected between the plurality of output terminals of the first column selector 24 and the first input terminal In1 and the second input terminal In2 of the sense amplifier 26, and the fourth column selector 251 is the first column selector 251. The second column selector 25 is connected between the plurality of output terminals and the first input terminal In1 and the second input terminal In2 of the sense amplifier 26.

  The precharge circuit PC and the switch Ref_DC_SW shown in FIG. 7 and FIG. 8 are arranged between the third column selector 241 and the fourth column selector 251, and the precharge circuit PC and the switch Ref_DC_SW are sensed. The amplifier 26 is connected to the first input terminal In1 and the second input terminal In2. The switch Ref_DC_SW is connected to the N-channel MOS transistor Q9 of the reference cell Ref_Cell.

  The first column selector 24 is supplied with 8-bit first column address signals YRA_J <0> to <7>, and the second column selector 25 is supplied with an 8-bit second column address signal YRA_K <0>. ~ <7> are supplied. The third column selector 241 is supplied with 4-bit third column address signals YRB_J <0> to <3>, and the fourth column selector 251 is supplied with a 4-bit fourth column address signal YRB_K <0>. ~ <3> are supplied.

  For example, in the normal data read of the data flash shown in FIG. 9, the read data from the nonvolatile memory cell MC1 (positive cell) of the first nonvolatile memory array 21 is transmitted from the sub bit line SBLJ <0> and the first column selector 24. The voltage is supplied to the first input terminal In1 of the sense amplifier 26 via the transistor Q20 of the third column selector 241. In parallel with this, the read data from the nonvolatile memory cell MC2 (negative cell) of the first nonvolatile memory array 21 is the transistor of the sub bit line SBLJ <8>, the first column selector 24, and the third column selector 241. This is supplied to the second input terminal In2 of the sense amplifier 26 via Q21.

  In this way, the normal complementary read data from the two nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) of the first nonvolatile memory array 21 is sense amplifier 26 which is a differential amplification type sense amplifier. Can be read. The data read by the sense amplifier 26 from the data flash DFL in FIG. 9 in normal data read is supplied to the CPU 2 via the read-only high-speed access port (HACSP) and high-speed bus (HBUS) in the MCU 1 in FIG. Can be done. The first column address signals YRA_J <0> to <7> and the third column that enable complementary reading from the two nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) by the sense amplifier 26. Address signals YRB_J <0> to <3> are generated from the column decoder (YDEC) 23 shown in FIG. Such an address signal from the column decoder (YDEC) 23 is generated according to a read command to the data flash DFL of the flash memory module 6 in response to a read request from the CPU 2 of the MCU 1 in FIG.

<< Details of verify read in data flash >>
FIG. 10 shows a verification from one of two nonvolatile memory cells MC1 (positive cell) and MC2 (negative cell) that constitute one twin cell by the first and second nonvolatile memory arrays 21 and 22 of the data flash DFL of FIG. It is a figure which shows the operation | movement which performs reading in detail.

  In the MCU 1 of FIG. 1, a write operation for a verify operation related to a write operation or an erase operation of the data flash DFL of the data flash DFL of the flash memory module 6 by the flash sequencer 7 in relation to a write request or an erase request from the CPU 2. An erase verify read must be performed.

  In this verify read, for example, in FIG. 10, the verify read data from the nonvolatile memory cell MC1 (positive cell) of the first nonvolatile memory array 21 is the sub bit line SBLJ <0>, the first column selector 24, and the third column selector 24. The signal is supplied to the first input terminal In1 of the sense amplifier 26 via the transistor Q20 of the column selector 241. In parallel with this, the verify reference level from the N-channel MOS transistor Q9 of the reference cell Ref_Cell is supplied to the second input terminal In2 of the sense amplifier 26 via the transistor Q8 of the switch Ref_DC_SW.

  In this way, the verify read data from the nonvolatile memory cell MC1 (positive cell) of the first nonvolatile memory array 21 and the verify reference level from the reference cell Ref_Cell are sense amplifiers that are differential amplification type sense amplifiers. It can be compared by the amplifier 26. When it is determined that the writing or erasing is insufficient by the comparison verification by the sense amplifier 26, the next writing pulse or erasing pulse is applied again to the nonvolatile memory cell MC1 (positive cell) of the first nonvolatile memory array 21. Thereafter, a verify operation similar to the above is performed. The application of the write pulse and the erase pulse and the verify operation are repeated until it is determined that the write or erase is sufficient by the comparison verification by the sense amplifier 26.

<< Details of reading normal data with program flash >>
FIG. 11 is a diagram showing in more detail the operation of reading normal data from one nonvolatile memory cell MC0 by the first and second nonvolatile memory arrays 31 and 32 of the program flash PFL of FIG.

  The program flash PFL shown in FIG. 11 is very similar to the configuration of the data flash DFL shown in FIG. That is, in FIG. 11, the third column selector 341 is connected to the first column selector 34 connected to the first nonvolatile memory array 31, and the second column selector 341 connected to the second nonvolatile memory array 32 is connected. A fourth column selector 351 is connected to the column selector 35. The third column selector 341 is connected between the plurality of output terminals of the first column selector 34 and the first input terminal In1 and the second input terminal In2 of the sense amplifier 36, and the fourth column selector 351 is the first column selector 351. The plurality of output terminals of the second column selector 35 are connected between the first input terminal In1 and the second input terminal In2 of the sense amplifier 36.

  The precharge circuit PC and the switch Ref_DC_SW shown in FIGS. 7 and 8 are arranged between the third column selector 341 and the fourth column selector 351, and the precharge circuit PC and the switch Ref_DC_SW are sense The amplifier 36 is connected to the first input terminal In1 and the second input terminal In2. The switch Ref_DC_SW is connected to the N-channel MOS transistor Q9 of the reference cell Ref_Cell.

  The first column selector 34 is supplied with 8-bit first column address signals YRA_J <0> to <7>, and the second column selector 35 is supplied with an 8-bit second column address signal YRA_K <0>. ~ <7> are supplied. The third column selector 341 is supplied with 4-bit third column address signals YRB_J <0> to <3>, and the fourth column selector 351 is provided with a 4-bit fourth column address signal YRB_K <0>. ~ <3> are supplied.

  For example, in the normal data read of the program flash shown in FIG. 11, the read data from the nonvolatile memory cell MC0 of the first nonvolatile memory array 31 is the sub bit line SBLJ <0>, the first column selector 34, and the third column selector 34. The signal is supplied to the first input terminal In1 of the sense amplifier 36 via the transistor Q20 of the column selector 341. In parallel with this, the normal data read reference level from the N-channel MOS transistor Q9 of the reference cell Ref_Cell is supplied to the second input terminal In2 of the sense amplifier 36 via the transistor Q8 of the switch Ref_DC_SW.

  In this way, the normal read data from the nonvolatile memory cell MC0 of the first nonvolatile memory array 31 is sensed as a differential amplification type sense amplifier with reference to the normal data read reference level from the reference cell Ref_Cell. It can be read by the amplifier 36. The program data read by the sense amplifier 36 from the program flash PFL in FIG. 11 in the normal data read is sent to the CPU 2 via the read-only high-speed access port (HACSP) and the high-speed bus (HBUS) in the MCU 1 in FIG. Can be supplied. Note that the first column address signals YRA_J <0> to <7> and the third column address signals YRB_J <0> to <3> that enable complementary reading from the nonvolatile memory cell MC0 by the sense amplifier 36. Are generated from the column decoder (YDEC) 23 shown in FIG. Such an address signal from the column decoder (YDEC) 23 is generated according to a read command to the program flash PFL of the flash memory module 6 in relation to a read request from the CPU 2 of the MCU 1 in FIG.

  The verify read for writing and erasing in the program flash PFL can be performed in substantially the same manner as the normal data reading operation from the nonvolatile memory cell MC0 described above. That is, during the write / erase verify read operation, the write / erase verify read data from the nonvolatile memory cell MC0 of the first nonvolatile memory array 31 is the sub-bit line SBLJ <0> and the first column. The signal is supplied to the first input terminal In1 of the sense amplifier 36 through the selector 34 and the transistor Q20 of the third column selector 341. In parallel with this, the verify reference level for writing and erasing from the N-channel MOS transistor Q9 of the reference cell Ref_Cell is supplied to the second input terminal In2 of the sense amplifier 36 via the transistor Q8 of the switch Ref_DC_SW. If it is determined by the comparison verifying by the sense amplifier 36 that the writing or erasing is insufficient, the next writing pulse or erasing pulse is applied again to the nonvolatile memory cell MC0 of the first nonvolatile memory array 31, and A similar verify operation is performed. The application of the write pulse and the erase pulse and the verify operation are repeated until it is determined that the write or erase is sufficient by the comparison verification by the sense amplifier 36.

<< Data Flash and Program Flash partition >>
As described above, the program flash PFL shown in FIG. 11 is very similar to the configuration of the data flash DFL shown in FIG. Therefore, in one preferred embodiment of the present invention, the arrangement of the data flash DFLs of FIGS. 2, 7, 9, and 10 inside the flash memory module 6 of the MCU 1 of FIG. It can be arbitrarily set to the arrangement of the program flash PFL in FIG.

  FIG. 12 is a diagram for explaining how to arbitrarily set the arrangement of the data flash DFL and the arrangement of the program flash PFL inside the flash memory module (FMDL) 6 of the MCU 1 of FIG. A control management area Cnt_Area is included at the bottom of the flash memory module (FMDL) 6 shown in FIG. The control management area Cnt_Area can contain various control codes of MCU1, and initialization control code data INT_Data of MCU1 is included at the head thereof.

  In the system initialization at the time of system reset such as power-on of the MCU 1 in FIG. 1, the CPU 2 includes the control management area Cnt_Area at the bottom of the flash memory module (FMDL) 6 shown in FIG. 12 in response to the external reset signal RES. Read initialization control code data INT_Data.

  The read initialization control code data INT_Data is supplied to peripheral modules such as the external input / output ports 8 and 9, the timer 10, and the clock pulse generator 11, and the operation mode of the peripheral modules can be initialized. At this time, the initialization control code data INT_Data read by the CPU 2 includes the final address EA of the data flash DFL arranged in the flash memory module (FMDL) 6 of FIG.

  When the system is initialized at the time of system reset such as power-on of the MCU 1 in FIG. 1, the CPU 2 uses the read final address EA to arrange the data flash DFL and the program flash PFL inside the flash memory module (FMDL) 6. Is arbitrarily set. In FIG. 12, the portion from the non-volatile memory array MARY_00 designated by the initial address at the upper left of the flash memory module 6 to the non-volatile memory array MARY_3M designated by the final address EA in order is the initial operation mode as the data flash DFL. Is set. Therefore, this portion of the nonvolatile memory array is a data flash DFL that employs a 2-cell / 1-bit high-reliability write method in which 1 bit of complementary data is written to a twin cell composed of two nonvolatile memory cells. Will work.

  Next, the CPU 2 initializes the operation mode as a program flash PFL from the non-volatile memory array MARY_40 next to the non-volatile memory array MARY_3M specified by the final address EA to the last non-volatile memory array MARY_NM. Therefore, this portion of the nonvolatile memory array functions as a program flash PFL that employs a high density writing method of 1 cell / 1 bit, in which 1 bit of single data is written in one nonvolatile memory cell. .

  As described above, the partition of the data flash DFL and the program flash PFL inside the flash memory module (FMDL) 6 can be completed when the system is initialized at power-on. When changing the partition between the data flash DFL and the program flash PFL, the final address included in the initialization control code data INT_Data in the control management area Cnt_Area at the bottom of the flash memory module (FMDL) 6 shown in FIG. The EA is rewritten by the CPU 2.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, a program flash for storing various software programs is not limited to one cell / one bit, but one cell / one for writing two bits or more of quaternary data or the like in one nonvolatile memory cell. A multi-bit multi-value high-density writing method can be adopted.

  Further, ECC (error correction code) can be added to complementary data by twin cells by data flash, while ECC can be added to multi-value data of program flash.

  Furthermore, the present invention can be widely applied to a semiconductor integrated circuit having a single nonvolatile memory device, as well as a semiconductor integrated circuit used for various purposes by incorporating a nonvolatile memory, in addition to a microcomputer incorporating a flash memory. Can do.

FIG. 1 is a diagram showing a configuration of a microcomputer according to an embodiment of the present invention. FIG. 2 is a diagram showing a configuration of a data flash included in a flash memory module built in the microcomputer shown in FIG. FIG. 3 is a diagram showing the configuration of the program flash included in the flash memory module built in the microcomputer shown in FIG. 4 shows two nonvolatile memory cells included in the data flash of FIG. 2 to which 1 bit of complementary data is written, and nonvolatile memory cells included in the program flash of FIG. 3 to which 1 bit of single data is written. It is a figure which shows the structure and operation | movement of. FIG. 5 is a diagram for explaining three states of one twin cell comprised of two nonvolatile memory cells that are included in the data flash of FIG. 2 and in which one bit of complementary data is written. FIG. 6 is a diagram for explaining two states of the nonvolatile memory cell included in the program flash of FIG. 3 in which one bit of single data is written. FIG. 7 shows a data flash for concretely performing a write verify operation and an erase verify operation of two nonvolatile memory cells constituting one twin cell by the first and second nonvolatile memory arrays of the data flash of FIG. FIG. FIG. 8 shows a program flash for concretely performing a normal read operation, a write verify operation, and an erase verify operation of any one of the first and second nonvolatile memory arrays of the program flash of FIG. FIG. FIG. 9 is a diagram showing in more detail the operation of reading normal complementary data from two nonvolatile memory cells constituting one twin cell by the first and second nonvolatile memory arrays of the data flash of FIG. FIG. 10 is a diagram showing in more detail the operation of performing verify read from one of two nonvolatile memory cells constituting one twin cell by the first and second nonvolatile memory arrays of the data flash of FIG. FIG. 11 is a diagram showing in more detail the operation of reading normal data from one nonvolatile memory cell in the first and second nonvolatile memory arrays of the program flash of FIG. FIG. 12 is a diagram for explaining how the data flash placement and program flash placement are arbitrarily set within the MCU flash memory module of FIG.

Explanation of symbols

1 Microcomputer 2 Central processing unit 3 DMAC
4 Bus interface circuit 5 RAM
6 Flash Memory Module 7 Flash Sequencer HACSP High Speed Access Port LACSP Low Speed Access Port DFL Data Flash PFL Program Flash MC0 1 Cell / 1 Bit Write Nonvolatile Memory Cell MC1, MC2 2 Cell / 1 Bit Write Nonvolatile Memory Cell MARY_J , MARY_K nonvolatile memory array YDEC column decoder YSEL_J, YSEL_K column selector SA sense amplifier

Claims (20)

A first nonvolatile memory including at least a first nonvolatile memory array, a second nonvolatile memory array, a first selector, a second selector, and a first sense amplifier. And
In each of the first nonvolatile memory array and the second nonvolatile memory array, complementary data can be electrically written to two nonvolatile memory cells,
The plurality of signal input lines of the first selector are connected to the plurality of bit lines of the first nonvolatile memory array, and the plurality of signal input lines of the second selector are connected to the second nonvolatile memory array. Connected to multiple bit lines,
The plurality of signal output lines of the first selector are connected to a first input terminal and a second input terminal of the first sense amplifier, and the plurality of signal output lines of the second selector are the first input terminal. Connected to the first input terminal and the second input terminal of the sense amplifier,
In one of the first and second nonvolatile memory arrays, a first normal data read operation is executed,
In the first normal data read operation, one of the first and second selectors receives complementary data from two nonvolatile memory cells of the one memory array in the first sense amplifier. To the first and second input terminals,
In the one memory array, a first nonvolatile memory operation of writing or erasing one of the two nonvolatile memory cells is executed, and a first nonvolatile memory operation related to the first nonvolatile memory operation is performed. 1 verify read operation is executed,
In the first verify read operation, the one selector sends the first verify read data from the one nonvolatile memory cell to one of the first and second input terminals of the first sense amplifier. A semiconductor integrated circuit in which a first verify reference signal is supplied to the other of the first and second input terminals of the first sense amplifier while being supplied. And a second nonvolatile memory including at least a third nonvolatile memory array, a fourth nonvolatile memory array, a third selector, a fourth selector, and a second sense amplifier. Is,
In each of the third nonvolatile memory array and the fourth nonvolatile memory array, data can be electrically written to one nonvolatile memory cell,
The signal input line of the third selector is connected to the bit line of the third nonvolatile memory array, and the signal input line of the fourth selector is connected to the bit line of the fourth nonvolatile memory array. And
The signal output line of the third selector is connected to the first input terminal and the second input terminal of the second sense amplifier, and the signal output line of the fourth selector is the second sense amplifier. Connected to the first input terminal and the second input terminal,
In one of the third and fourth nonvolatile memory arrays, a second normal data read operation is executed,
In the second normal data read operation, one of the third and fourth selectors selects data from one nonvolatile memory cell of the one memory array of the third and fourth nonvolatile memory arrays. To one input terminal of the first and second input terminals of the second sense amplifier,
In the second normal data read operation, a normal read reference signal is supplied to the other input terminal of the first and second input terminals of the second sense amplifier,
In the one memory array of the third and fourth nonvolatile memory arrays, a second nonvolatile storage operation of either writing or erasing of the one nonvolatile memory cell is performed, and the second nonvolatile memory is performed. A second verify read operation related to the operation is performed;
In the second verify read operation, the one of the third and fourth selectors outputs the second verify read data from the one nonvolatile memory cell to the first sense amplifier. The second verify reference signal is supplied to the other of the first and second input terminals of the second sense amplifier, while being supplied to one of the first and second input terminals. Semiconductor integrated circuit. Further comprising a central processing unit,
The second nonvolatile memory can store a program for the central processing unit,
3. The semiconductor integrated circuit according to claim 2, wherein the first nonvolatile memory can store data of a result of executing a program stored in the second nonvolatile memory by the central processing unit. A built-in nonvolatile memory is formed by the first nonvolatile memory and the second nonvolatile memory,
Further comprising a built-in random access memory, a high-speed bus, a peripheral bus, and a sequencer connected to the low-speed access port of the built-in nonvolatile memory;
The central processing unit is connected to the built-in random access memory and the high-speed access port of the built-in nonvolatile memory via the high-speed bus,
The central processing unit stores data stored in the first nonvolatile memory and a program stored in the second nonvolatile memory via the high-speed bus and the high-speed access port of the built-in nonvolatile memory. Can be read,
In response to an instruction from the central processing unit, the sequencer stores data stored in the first nonvolatile memory and the second nonvolatile memory via the low-speed bus and the low-speed access port. 4. The semiconductor integrated circuit according to claim 3, wherein the program is stored in the built-in nonvolatile memory.   Each cell of the two nonvolatile memory cells of the first nonvolatile memory and the one nonvolatile memory cell of the second nonvolatile memory includes injection of electrons into the charge storage layer and the charge storage layer. 4. The semiconductor integrated circuit according to claim 3, wherein a nonvolatile memory operation is executed by releasing electrons from the semiconductor device. In the one memory array of the first and second nonvolatile memory arrays of the first nonvolatile memory, the first nonvolatile memory operation of the one nonvolatile memory cell of the two nonvolatile memory cells And the first verify read operation are repeated,
In the one memory array of the third and fourth nonvolatile memory arrays of the second nonvolatile memory, the second nonvolatile memory operation and the second verify read operation of the one nonvolatile memory cell. The semiconductor integrated circuit according to claim 5, wherein In the first verify read operation of the first nonvolatile memory, the other one of the first and second input terminals of the first sense amplifier is generated from the first reference cell. 1 verify reference signal is supplied,
In the second verify read operation of the second nonvolatile memory, the other one of the first and second input terminals of the second sense amplifier is generated from a second reference cell. 7. The semiconductor integrated circuit according to claim 6, wherein two verify reference signals are supplied.   In the second normal data read operation of the second nonvolatile memory, the other one of the first and second input terminals of the second sense amplifier is generated from the second reference cell. The semiconductor integrated circuit according to claim 6, wherein a normal read reference signal is supplied.   The one non-volatile memory cell of the one of the third and fourth non-volatile memory arrays of the second non-volatile memory is electrically supplied with multi-value data of 2 bits or more. The semiconductor integrated circuit according to claim 6, wherein writing is possible.   The arrangement of the first nonvolatile memory and the arrangement of the second nonvolatile memory inside the built-in nonvolatile memory can be set according to initialization control code data used for system initialization of the semiconductor integrated circuit. The semiconductor integrated circuit according to claim 4. A semiconductor comprising a first nonvolatile memory including at least a first nonvolatile memory array, a second nonvolatile memory array, a first selector, a second selector, and a first sense amplifier. A method of operating an integrated circuit, comprising:
In each of the first nonvolatile memory array and the second nonvolatile memory array, complementary data is electrically written into two nonvolatile memory cells,
The plurality of signal input lines of the first selector are connected to the plurality of bit lines of the first nonvolatile memory array, and the plurality of signal input lines of the second selector are connected to the second nonvolatile memory array. Connected to multiple bit lines,
The plurality of signal output lines of the first selector are connected to the first input terminal and the second input terminal of the first sense amplifier, and the plurality of signal output lines of the second selector are the first input terminal. Connected to the first input terminal and the second input terminal of the sense amplifier,
In one of the first and second nonvolatile memory arrays, a first normal data read operation is executed,
In the first normal data read operation, one of the first and second selectors receives complementary data from two nonvolatile memory cells of the one memory array in the first sense amplifier. 1 and the second input terminal,
In the one memory array, a first nonvolatile memory operation of writing or erasing one of the two nonvolatile memory cells is performed, and a first nonvolatile memory operation related to the first nonvolatile memory operation is performed. 1 verify read operation is executed.
In the first verify read operation, the one selector sends the first verify read data from the one nonvolatile memory cell to one of the first and second input terminals of the first sense amplifier. A method of operating a semiconductor integrated circuit, wherein the first verify reference signal is supplied to the other of the first and second input terminals of the first sense amplifier while the first verify amplifier is supplied. The semiconductor integrated circuit includes a second nonvolatile memory including at least a third nonvolatile memory array, a fourth nonvolatile memory array, a third selector, a fourth selector, and a second sense amplifier. Further comprising a memory,
In each of the third nonvolatile memory array and the fourth nonvolatile memory array, data is electrically written into one nonvolatile memory cell,
The signal input line of the third selector is connected to the bit line of the third nonvolatile memory array, and the signal input line of the fourth selector is connected to the bit line of the fourth nonvolatile memory array. And
The signal output line of the third selector is connected to the first input terminal and the second input terminal of the second sense amplifier, and the signal output line of the fourth selector is the second sense amplifier. Connected to the first input terminal and the second input terminal,
In one of the third and fourth nonvolatile memory arrays, a second normal data read operation is executed,
In the second normal data read operation, one of the third and fourth selectors selects data from one nonvolatile memory cell of the one memory array of the third and fourth nonvolatile memory arrays. Is supplied to one input terminal of the first and second input terminals of the second sense amplifier,
In the second normal data read operation, a normal read reference signal is supplied to the other input terminal of the first and second input terminals of the second sense amplifier.
In the one memory array of the third and fourth nonvolatile memory arrays, a second nonvolatile storage operation of either writing or erasing of the one nonvolatile memory cell is performed, and the second nonvolatile memory is performed. A second verify read operation related to the operation is performed,
In the second verify read operation, the one of the third and fourth selectors outputs the second verify read data from the one nonvolatile memory cell to the first sense amplifier. And a second input terminal, and a second verify reference signal is supplied to the other of the first and second input terminals of the second sense amplifier. The operation method of the semiconductor integrated circuit according to claim 11. The semiconductor integrated circuit further comprises a central processing unit,
The second nonvolatile memory stores a program for the central processing unit,
The operation method of the semiconductor integrated circuit according to claim 12, wherein the first nonvolatile memory stores data of a result of executing a program stored in the second nonvolatile memory by the central processing unit. In the semiconductor integrated circuit, a built-in nonvolatile memory is formed by the first nonvolatile memory and the second nonvolatile memory,
The semiconductor integrated circuit further includes a built-in random access memory, a high-speed bus, a peripheral bus, and a sequencer connected to a low-speed access port of the built-in nonvolatile memory,
The central processing unit is connected to the built-in random access memory and the high-speed access port of the built-in nonvolatile memory via the high-speed bus,
The central processing unit stores data stored in the first nonvolatile memory and a program stored in the second nonvolatile memory via the high-speed bus and the high-speed access port of the built-in nonvolatile memory. Read out,
In response to an instruction from the central processing unit, the sequencer stores data stored in the first nonvolatile memory and the second nonvolatile memory via the low-speed bus and the low-speed access port. 14. The method of operating a semiconductor integrated circuit according to claim 13, wherein the program is stored in the built-in nonvolatile memory.   Each cell of the two nonvolatile memory cells of the first nonvolatile memory and the one nonvolatile memory cell of the second nonvolatile memory includes injection of electrons into the charge storage layer and the charge storage layer. 14. The method of operating a semiconductor integrated circuit according to claim 13, wherein a nonvolatile storage operation is performed by releasing electrons from the semiconductor device. In the one memory array of the first and second nonvolatile memory arrays of the first nonvolatile memory, the first nonvolatile memory operation of the one nonvolatile memory cell of the two nonvolatile memory cells And the first verify read operation are repeated,
In the one memory array of the third and fourth nonvolatile memory arrays of the second nonvolatile memory, the second nonvolatile memory operation and the second verify read operation of the one nonvolatile memory cell. The method of operating a semiconductor integrated circuit according to claim 15, wherein: In the first verify read operation of the first nonvolatile memory, the other one of the first and second input terminals of the first sense amplifier is generated from the first reference cell. 1 verify reference signal is supplied,
In the second verify read operation of the second nonvolatile memory, the other one of the first and second input terminals of the second sense amplifier is generated from a second reference cell. 16. The method of operating a semiconductor integrated circuit according to claim 15, wherein two verify reference signals are supplied.   In the second normal data read operation of the second nonvolatile memory, the other one of the first and second input terminals of the second sense amplifier is generated from the second reference cell. The method of operating a semiconductor integrated circuit according to claim 16, wherein a normal read reference signal is supplied.   The one non-volatile memory cell of the one of the third and fourth non-volatile memory arrays of the second non-volatile memory is electrically supplied with multi-value data of 2 bits or more. The method for operating a semiconductor integrated circuit according to claim 16, wherein writing is possible.   The arrangement of the first nonvolatile memory and the arrangement of the second nonvolatile memory inside the built-in nonvolatile memory can be set according to initialization control code data used for system initialization of the semiconductor integrated circuit. The method of operating a semiconductor integrated circuit according to claim 13.

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