JPH11242891A - Non-volatile semiconductor storage device and its data write-in method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device, which can improve disturbance characteristic at write-in level and which can detect at high speed a cell insufficient in writing in all write-in steps, and a data write-in method for the device. SOLUTION: The data '10' level is weakest against disturbance; hence, this device 10 is structured such that, against the memory cell with the write-in data of '01' and '00', after writing in the '01' level, the memory cell with the write-in data of '000' is written and that, finally, the cell of the write-in data '10' is written to complete the writing of quarternary level. As a result, the disturbance characteristic of the write-in level can be improved, permitting high speed detection of an insufficiently written cell in all write-in steps.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-valued nonvolatile semiconductor memory device capable of recording data of at least three values in a memory cell and a data writing method thereof.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory device such as a flash memory, a binary memory cell structure in which data having two values "0" and "1" are recorded in one memory cell transistor is usually used. It is. Further, in response to recent demands for increasing the capacity of a semiconductor memory device, data of at least three values or more is recorded in one memory cell transistor.
A so-called multi-level nonvolatile semiconductor memory device has been proposed (for example, "A Multi-Level 32M").
b Flash Memory "'95 ISSCC
p. 132-).

FIG. 6 is a diagram showing a relationship between a threshold voltage Vth level and data contents when two-bit quaternary data is recorded in one memory transistor in a NAND flash memory. .

In FIG. 6, the vertical axis represents the threshold voltage Vth of the memory transistor, and the horizontal axis represents the distribution frequency of the memory transistor. The contents of 2-bit data constituting data to be recorded in one memory transistor are represented by [IO _{n + 1} , IO _n ] and [I _n
O _n + 1, IO _n] = [1,1], [1,0], [0,
1] and [0, 0]. That is, data “0”, data “1”, data “2”, data “3”
There are four states:

A NAND flash memory in which multi-level data is written in page units (word line units) has been proposed (for example, reference: 1996 IEEE Intern).
ational Solid-State Circuits Conference, ISSCC96 /
SESSION 2 / FLASH MEMORY / PAPER TP 2.1: A 3.3V 128Mb M
ulti-Level NAND Flash Memory For Mass Storage Appl
ication.pp32-33).

FIG. 7 is a circuit diagram showing a configuration of a main part of a NAND flash memory which performs writing in page units disclosed in the above document. In FIG. 7, 1 is a memory cell array, 2 is a write / read control circuit, and BL2 and BL1 are bit lines, respectively.

The memory cell array 1 is composed of memory strings A0 and A1 whose memory cells are connected to common word lines WL0 to WL15. The memory string A0 is connected to the bit line BL1, and the memory string A1 is connected to the bit line BL2. The memory string A0 has a NAND string in which memory cell transistors MT0A to MT15A each composed of a nonvolatile semiconductor memory device having a floating gate are connected in series, and the drain of the memory cell transistor MT0A in this NAND string has a selection gate SG1A.
Is connected to the bit line BL1, and the source of the memory cell transistor MT15A is connected to the reference potential line VGL via the selection gate SG2A. The memory string A1 includes memory cell transistors MT0B to MT0B, each of which is a nonvolatile semiconductor memory device having a floating gate.
MT15B has a NAND string connected in series, and the memory cell transistor MT0B of this NAND string
Of the bit line BL via the select gate SG1B.
2 and the source of the memory cell transistor MT15B is connected to the reference potential line VGL via the selection gate SG2B.

Then, the gates of the selection gates SG1A and SG1B are commonly connected to the selection signal supply line SSL, and the gates of the selection gates SG2A and SG2B are connected to the selection signal supply line G.
It is commonly connected to SL.

The write / read control circuit 2 has an n-channel MO
S (NMOS) transistors NT1 to NT17, p-channel MOS (PMOS) transistor PT1, and latch circuit Q1,
Q2.

The NMOS transistor NT1 has a power supply voltage V
_The gate is connected between the supply line of _CC and the bit line BL1, and the gate is connected to the supply line of the inhibit signal IHB1. The NMOS transistor NT2 is connected between the supply line of the power supply voltage V _CC and the bit line BL2, and has a gate connected to the supply line of the inhibit signal IHB2. A depletion type NMOS transistor N is connected between a connection point between the bit line BL1 and the NMOS transistor NT1 and a connection point between the memory string A0 and the bit line BL1.
T18 is connected, and a depletion type NMOS transistor NT19 is connected between a connection point between the bit line BL2 and the NMOS transistor NT2 and a connection point between the memory string A1 and the bit line BL2. The gates of the NMOS transistors NT18 and NT19 are connected to a decouple signal supply line DCPL.

An NMOS is provided between a connection point between bit line BL1 and NMOS transistor NT1 and bus line IOi.
Transistors NT3, NT5 and NT16 are connected in series, and bit line BL2 and NMOS transistor NT2
The NMOS transistors NT4, NT7, and NT17 are connected in series between the connection point (1) and the bus line IOi + 1. The connection point between the NMOS transistors NT3 and NT5 and the connection point between the NMOS transistors NT4 and NT7 are grounded via the NMOS transistor NT6, and the drain of the PMOS transistor PT1 and N
It is connected to the gates of MOS transistors NT8 and NT13. Then, the gate of the NMOS transistor NT6 is connected to the supply line of the reset signal RST,
The source of the OS transistor PT1 is connected to the supply line of the power supply voltage V _CC, the gate of the PMOS transistor PT1 is connected to the supply line of the signal Vref.

First storage node N1a of latch circuit Q1
Is connected to a connection point between the NMOS transistors NT5 and NT16, and the second storage node N1b is grounded via NMOS transistors NT8 to NT10 connected in series. The first storage node N2a of the latch circuit Q2 is connected to a connection point between the NMOS transistors NT7 and NT17, and the second storage node N2b is connected in series.
It is grounded via MOS transistors NT13 to NT15. Also, the NMOS transistors NT8 and NT9
NMOS transistor NT whose connection point is connected in series
11, grounded via NT12. The gate of the NMOS transistor NT9 is connected to the first storage node N2a of the latch circuit Q2.
0 is connected to the supply line of the signal φLAT2,
The gate of the NMOS transistor NT11 is connected to the second storage node N2b, and the NMOS transistor NT12
Is connected to the supply line of the signal φLAT1,
The gates of the MOS transistors NT14 and NT15 are connected to a supply line for the signal φLAT3. The gate of the NMOS transistor NT16 as a column gate is connected to the supply line of the signal Yi, and the gate of the NMOS transistor NT17 is connected to the supply line of the signal Yi + 1.

FIG. 8A shows a timing chart at the time of reading, and FIG. 8B shows a timing chart at the time of writing (program). FIG. 8B
As can be understood from the above, the quaternary writing is performed in three steps, and the process proceeds to the next step when it is determined that all the cells to be written in page units in each step are sufficiently written.

The read operation will be described. First, the reset signal RST and the signals PGM1 and PGM2 are set to a high level. As a result, the first storage nodes N1a and N2a of the latch circuits Q1 and Q2 are pulled to the ground level. As a result, the latch circuits Q1 and Q2 are cleared.
Next, reading is performed with the word line voltage set to 2.4V. If the threshold voltage Vth is higher than the word line voltage (2.4 V), the cell current does not flow, so that the bit line voltage holds the precharge voltage and high is sensed. On the other hand, if the threshold voltage Vth is lower than the word line voltage (2.4 V), the cell current flows to lower the bit line voltage and sense low. Next, the word line voltages 1.
Reading is performed at 2 V, and finally reading is performed at a word line voltage of 0 V.

Specifically, when the cell data is "00",
Since no current flows in all word lines, the bus IOi + 1,
(1, 1) is output to IOi. First, when reading with the word line voltage set to 2.4 V, the signal φLAT1 is set to a high level. At this time, since the cell current does not flow, the bit line is kept at a high level, so that the NMOS transistor NT8 is kept conductive, and the latch circuit Q2
Is kept high, the second storage node N2b of the latch circuit Q2 is kept at a high level.
Transistor NT11 is kept conductive. Therefore, the NMOS transistors NT8, NT11, NT12
Is held in a conductive state, the second storage node N1b of latch circuit Q1 is pulled to the ground level, and latch circuit Q1
Transitions to the high level. Next, when reading is performed by setting the word line voltage to 1.2 V, the signal φLA
Set T3 to high level. At this time, since the cell line does not flow, the bit line is kept at a high level,
MOS transistor NT13 is kept conductive, second storage node N2b of latch circuit Q2 is pulled to the ground level, and first storage node N2a of latch circuit Q2 transitions to the high level. Finally, when reading with the word line voltage set to 0 V, the signal φLAT1 is set to a high level.
At this time, since the cell current does not flow, the bit line is kept at a high level and the NMOS transistor NT8 is kept conductive, but the second storage node N2b of the latch circuit Q2 is at a low level and the NMOS transistor NT8
11 is turned off, and the first storage node N1a of the latch circuit Q1 holds the high level.

When the cell data is "01", a current flows only when the word line voltage is VWL00, and buses IOi + 1,
(0, 1) is output to IOi. First, when reading with the word line voltage set to 2.4 V, the signal φLAT1 is set to a high level. At this time, the bit line goes low due to the flow of the cell current, so that the NMOS transistor NT8 is kept in a non-conductive state, and the first storage node N1a of the latch circuit Q1 holds the low level. Next, when reading is performed with the word line voltage set to 1.2 V, the signal φLAT3
Is set to high level. At this time, since the cell line does not flow, the bit line is kept at a high level.
S transistor NT13 is kept conductive, second storage node N2b of latch circuit Q2 is pulled to the ground level, and first storage node N2a of latch circuit Q2 transitions to the high level. Finally, when reading with the word line voltage set to 0 V, the signal φLAT1 is set to a high level. At this time, since the cell current does not flow, the bit line is kept at a high level and the NMOS transistor NT8 is kept in a conductive state. However, the second storage node N of the latch circuit Q2 is kept
NMOS transistor NT11 because 2b is at low level
Is turned off, and the first storage node N1a of the latch circuit Q1 holds the low level. Cell data is "1"
Similarly, in the case of “0” and “11”, IOi + 1 and I
(0, 1) and (0, 0) are read out to Oi.

Next, the write operation will be described. In the circuit of FIG. 7, first, writing is performed by the data stored in the latch circuit Q1, then writing is performed by the latch circuit Q2, and finally by the data of the latch circuit Q1 again. Write data is (Q2, Q1) =
In the case of (1, 0), the latch circuit Q1 inverts from “0” to “1” when writing is sufficient, but (Q2, Q1) =
In the case of (0, 0), the latch circuit Q1 must be used also as write data in the third step, so that even if the write becomes sufficient in the first step, it is not (inverted) from "0" to "1".

In each step, the end of the write is determined when all the latched data becomes "1". Write data (Q
In the cell of (2, Q1) = (0, 0), the inversion of the latch circuit Q1 in the first step does not occur, so that the end determination by the wired OR is not performed.

[0019]

By the way, in multi-value writing, writing in a state away from the erasing level is performed sequentially from writing in a state near the erasing level. For this reason, the lower the level of the write disturb, the more the disturbance was received. For example, in the case of a quaternary value of a NAND flash, as shown in FIG. 9, writing of "01" and "00" is performed after writing of a memory cell whose writing data is "10". The write disturb has the weakest level of “10”, but the memory cell having the write data of “10” is disturbed at the time of writing “01” or “00” after the writing, and the writing of the level “00” is completed. At this point, the threshold voltage Vth may be shifted due to the disturbance. 8 levels of multi-level, 1
As the value becomes six, the number of steps increases, and the disturbance near the erasing level becomes more severe.

FIG. 10 shows a conventional write procedure for an 8-level NAND flash memory. As shown in FIG.
Conventionally, writing is performed sequentially from a level near the erased state to a level far from the erased state. Then, when the write level is reached, the bit line voltage is converted to a write inhibit voltage. For example, when the write data is "110", writing is performed in step 1 of FIG. 10, and the bit line voltage is converted to a write inhibit voltage when it is determined that the write is sufficient. Then, in the write cycle of steps 2 to 7, a disturbance is received. Regarding the disturbance resistance, UV (UV erasing level: data “1” in FIG. 10)
(Equivalent to around "10" or "101").
Or the area around “101” is the weakest. On the other hand, the writing time of each step becomes longer as the value of n in step n increases. Thus, the memory cell with the write data of “110” has the weakest disturb resistance and the longest disturb time. Therefore, there is a possibility that the threshold voltage Vth has shifted to the next write level due to the disturb at the stage where the write in Step 7 is completed.

In multi-level writing, it is necessary to judge the end of writing in each step, and to proceed to the next step when all the writing is sufficient. is there. That is, in the conventional method, insufficiently-written memory cells could not be detected. In the verify read, when the latch data of the latch circuit Q2 of the memory cell with sufficient writing is inverted to “1”, the writing data “01” becomes “11” and the writing data “00” becomes “ 10 ". On the other hand, the cell whose original write data is “10” has no change and thus has “1”.
In the next step, when writing a cell whose write data is "00", it is determined that the write target is "10" and that the write data is "10". Although it is an inverted memory cell, the original write data cannot be distinguished from the memory cell whose original write data is “10.” Therefore, in the conventional write, the latch of the latch circuit Q2 of the cell which is determined to be sufficient in the verify operation is determined. The data could not be inverted to "1", that is, high-speed insufficiently-written cells could not be detected by the inverted signal of the latch circuit Q2.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to improve the disturb characteristic of a write level, and to provide a nonvolatile nonvolatile memory capable of quickly detecting an insufficiently written cell in all write steps. An object of the present invention is to provide a semiconductor memory device and a data writing method thereof.

[0023]

In order to achieve the above object, according to the present invention, the amount of charge stored in a charge storage section changes in accordance with the voltage applied to a word line and a bit line. A nonvolatile semiconductor memory device in which a threshold voltage is changed and which has a memory cell that stores data having a value corresponding to the threshold voltage, and writes multi-bit data to a memory cell in page units. There is write control means for first writing data to the memory cell of the data to which the most significant bit is to be written, and then writing the data of the memory cell to which the most significant bit is not to be written.

In the present invention, the write control circuit stores the transferred data in the latch circuit and performs writing. In the present invention, the write control circuit includes the latch circuit for one bit corresponding to each bit line.

Further, in the present invention, at the time of the write operation, verify read is performed for each write bit to determine whether the write is sufficient, and the latch data of the latch circuit corresponding to the memory cell determined to be sufficiently write is written. There is provided a means for inverting to non-write data, and thereafter performing readout as necessary to restore write data to be the next write data.

Further, according to the present invention, the amount of charge stored in the charge storage portion changes according to the voltage applied to the word line and the bit line, and the threshold voltage changes according to the change. A data writing method for a nonvolatile semiconductor memory device having a memory cell for storing data of a value corresponding to a voltage and writing multi-bit data to the memory cell in page units, wherein the most significant bit performs writing at the time of writing The memory cell of data is written first, and then the memory cell of the data whose most significant bit is not written is written.

According to the present invention, the transferred data is stored in a latch circuit to perform writing, and at the time of the writing operation, a verify reading is performed for each write bit to determine whether or not writing is sufficient. Invert the latch data of the latch circuit corresponding to the memory cell determined to be sufficiently written to non-write data, and then read as necessary to restore the write data,
The next write data is assumed.

According to the present invention, at the time of writing, verify reading is performed for each writing step. In writing, the memory cell of the data whose highest bit is to be written is written first. Then, after that, writing of data in which the most significant bit is not written into the memory cell is performed. In the verify read in each write step, the latch data of the latch circuit corresponding to the memory cell determined to be sufficiently written is inverted to the non-write data. After that, reading is performed as necessary, and the write data is restored to be the next write data.

[0029]

FIG. 1 is a circuit diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention, and FIG.
FIG. 6 is a diagram illustrating a threshold voltage distribution of values.

This nonvolatile semiconductor memory device 10 includes a memory array 11 and a write / read control circuit 12, and has a data "10" in the distribution shown in FIG.
Since the write data “00” is written to the memory cell “01” and “00”, the write data “00” is applied to the memory cell “01” and “00”. The memory cell of "" is written, and finally, the cell of write data "10" is written, and the quaternary writing is completed.

The memory array 11, as shown in FIG.
Each memory cell has a common word line WL0-WL15
Are connected to memory strings A0 and A1. The memory string A0 is connected to the bit line B
L1 and the memory string A1 is connected to the bit line BL.
2 are connected. The memory string A0 is a NAND string in which memory cell transistors MT0A to MT15A each composed of a nonvolatile semiconductor memory device having a floating gate are connected in series.
The drain of the memory cell transistor MT0A of the D string is connected to the bit line BL1 via the selection gate SG1A, and the source of the memory cell transistor MT15A is connected to the reference potential line VGL via the selection gate SG2A. The memory string A1 is composed of a NAND string in which memory cell transistors MT0B to MT15B each composed of a nonvolatile semiconductor memory device having a floating gate are connected in series, and the drain of the memory cell transistor MT0B of this NAND string is connected via a selection gate SG1B. The memory cell transistor MT15B is connected to the bit line BL2, and the source of the memory cell transistor MT15B is connected to the reference potential line VGL via the selection gate SG2B.

Then, the gates of the selection gates SG1A and SG1B are commonly connected to the selection signal supply line SSL, and the gates of the selection gates SG2A and SG2B are connected to the selection signal supply line G.
It is commonly connected to SL.

The write / read control circuit 12 includes NMOS transistors NT21 to NT39 and a PMOS transistor P
T21, an inverter INV21, and latch circuits Q21 and Q22 formed by coupling inputs and outputs of the inverter.

The NMOS transistor NT21 is connected between the supply line of the power supply voltage V _CC and the bit line BL1,
The gate is connected to the supply line of the inhibit signal IHB1. The NMOS transistor NT22 is connected between a supply line of the power supply voltage V _CC and the bit line BL2, and has a gate connected to a supply line of the inhibit signal IHB2. NM
A depletion-type NMOS transistor NT38 is connected between the source of the OS transistor NT21 and a connection point between the memory string A0 and the bit line BL1, and a connection point between the source of the NMOS transistor NT22 and the memory string A1 and the bit line BL2. A depletion-type NMOS transistor NT39 is connected between them. Then, the NMOS transistor NT3
Gates 8 and 39 are connected to a decouple signal supply line DCPL.

NMOS transistors NT38 and NM
Connection point of OS transistor NT21 and bus line IOi
Between the NMOS transistors NT23, NT25, N
T34 is connected in series, and the NMOS transistor NT3
9 and a connection point between the NMOS transistor NT2 and the bus line IOi + 1.
4, NT26 and NT35 are connected in series. A connection point between the NMOS transistors NT23 and NT25 and a connection point between the NMOS transistors NT24 and NT26 (these connection points are referred to as a node SA21) are NMOS transistors.
Grounded via a transistor NT27 and P
Drain of MOS transistor PT21 and NMO
It is connected to the gates of S transistors NT29 and NT32. The connected gate of the NMOS transistor NT27 is the supply line of the signal RST, the source of the PMOS transistor PT21 is connected to the supply line of the power supply voltage V _CC, is connected to the gate of the PMOS transistor PT21 is the supply line of the signal Vref .

First storage node N2 of latch circuit Q21
1a is connected to a connection point between the NMOS transistors NT25 and NT34, and the second storage node N21b is grounded via NMOS transistors NT28 and NT29 connected in series. The first storage node N22a of the latch circuit Q22 is connected to the NMOS transistors NT26 and NT3.
5 and grounded via NMOS transistors NT30-NT32.
Then, the NMOS transistors NT31 and NT32
Between the connection point of the second storage node N22b and the second storage node N22b
The transistor NT33 is connected.

The address decode signal Ai is supplied to the gate electrode of the NMOS transistor NT23, and the inverted signal / Ai of the address decode signal Ai is supplied to the gate electrode of the NMOS transistor NT24. Also, NMOS
The signal PGM1 is supplied to the gate electrode of the transistor NT25, and the signal PGM2 is supplied to the gate electrode of the NMOS transistor NT26. NMOS transistor NT
30 gate electrodes are connected to the second storage node N21b of the latch circuit Q21. Further, the signal φLAT2 is supplied to the gate electrode of the NMOS transistor NT28, the signal φLAT1 is supplied to the gate electrode of the NMOS transistor NT31, and the NMOS transistor NT33
Is supplied with a signal φLAT0. And
The gate of the NMOS transistor NT34 as a column gate is connected to the supply line of the signal Yi, and the gate of the NMOS transistor NT35 is connected to the supply line of the signal Yi + 1.

Further, the inverters INV21 and INV2
2 is grounded, the output terminal of the inverter INV21 is connected to the determination circuit 20, and the inverter INV22
Are connected to the determination circuit 21. Further, N is connected between the output terminal of the inverter INV21 and the ground line.
MOS transistor NT36 is connected, and inverter I
The NMOS transistor NT37 is connected between the output terminal of the NV22 and the ground line. And NMOS
The gate electrode of the transistor NT36 is connected to the second storage node N21b of the first latch circuit Q21,
The gate electrode of the S transistor NT37 is connected to the second storage node N22b of the second latch circuit Q22.

At the time of the write operation, the determination circuits 20 and 21 determine whether or not the writing has been completed for all the memory cell transistors, based on the potentials of the output lines of the inverters INV21 and INV22. Specifically, when writing is completed, each latch circuit Q21,
Q22 of the first storage node N21a, 22a becomes the power supply voltage V _CC level, the second memory node N21b, 22b
At the ground level. As a result, NMOS transistors NT36, NT37 becomes potential supply voltage V _CC level of the output lines of being held in the nonconductive state inverters INV21, INV22, determines that thereby that the writing has been completed. On the other hand, if there is a cell for which writing is not sufficient, one or all of the first storage nodes N21a and N22a of each of the latch circuits Q21 and Q22 are set to the ground level, and the second storage nodes N21b and N22b are set.
Becomes the power supply voltage V _CC level. As a result, the NMOS transistor NT36 or NT37, or both transistors are kept conductive, and the inverters INV21, INV21
The potential of the output line of the NV 22 becomes the ground level, and it is determined that there is a cell in which writing is insufficient.

Next, write, verify read, and read operations according to the above configuration will be described in order with reference to the drawings.

First, the write operation will be described with reference to the timing charts of FIGS. FIG. 4 shows a timing chart at the time of reading. First,
After the write data is captured by the latch circuits Q22 and Q21, the word line is set to the write voltage “VPGM”, the signal PGM2 is set to the high level, the signal PGM1 is set to the low level, and the data latched by the latch circuit Q22. Is written.

At this time, the write data is "00",
In the case of “01”, the latch data of the latch circuit Q22 is at the low level (the level of the first storage node N22a), and the ground level voltage is applied to the bit line and the channel of the write cell, so that writing is performed. On the other hand, when the write data is “10” or “11”, the latch data of the latch circuit Q22 is at the high level (the power supply voltage V _CC).
Level), and this level is the NMOS transistor N
At T26, the voltage drops by the threshold voltage Vth,
V _CC -Vth is applied to the bit line, and a write inhibit voltage is applied to the channel of the memory cell by self-boost to prevent writing.

Then, in the verify read after the write, the latch data of the latch circuit Q22 of the memory cell enough to be written is inverted to "1". This is inverter I
The determination is made by a wired-OR circuit including the NV21 and the INV22. If there is an insufficiently written cell, the writing of “01” is repeated. If no insufficiently written cell is detected, the next write step “0” is performed.
The operation shifts to writing 0 ”.

In the conventional circuit, high-speed insufficiently-written cells cannot be detected by the inversion signal by the latch circuit Q22 because data cannot be distinguished. However, in the present embodiment, reading is performed (Copy).
Back), the data of the latch circuit Q22 is restored to enable distinction.

That is, after the writing of the data "01" is completed, all the latch data of the latch circuit Q22 is "1". Here, when the word line voltage is set to VRD1 and the reading is performed in the same manner as the normal reading, the threshold voltage Vth of the cell whose original write data is “01” or “00” becomes higher than VVF1. Therefore, no cell current flows when the word line voltage is VRD1. Therefore, the node SA21 is connected to the PMOS transistor PT2
1 to the power supply voltage V _CC . Here, when the write data is “00”, the second
Is high, the signal φ is high.
When LAT1 is set to the high level, the NMOS transistors NT30 to NT32 are kept conductive, the first storage node N22a of the latch circuit Q22 is pulled to the ground level, and the latch data switches from the high level to the low level. .

In the memory cell where the write data is "01", since the latch data of the latch circuit Q21 is at the high level, the second storage node N2 of the latch circuit Q21
1b is a low level. Therefore, since the NMOS transistor NT30 is kept off, even if the signal φLAT1 is set to the high level, the first storage node N22a of the latch circuit Q22 is at the high level, that is, the latch data of the latch circuit 22 is “ It remains at 1 ".

On the other hand, the original write data is "1".
Since the memory cells of "0" and "11" have the threshold voltage Vth at the level of "11" which is the erase level, when the word line voltage is set to VRD1 and read is performed,
Since the voltage of the node SA21 is maintained at a low level by the cell current, the NMOS transistor NT32 is maintained in a non-conductive state. Therefore, even if the signal φLAT1 is set to a high level, the first storage node N22a of the latch circuit Q22 is maintained. Is high level, that is, the latch data of the latch circuit 22 remains "1".

As described above, when reading (copy back) is performed at the word line voltage VRD1, the latch data of the latch circuit Q22 is inverted to "0" only in the memory cell of the write data "00", and the other write data In the case of, the data “1” is held in the latch circuit Q22.

Data "00" is written by the signal PGM
2 is set to the high level, and the NMOS transistor N
T26 is held in a conductive state, and writing is performed with the data of the latch circuit Q22. Thus, writing can be performed only on the memory cell whose write data is “00”. Then, in the verify reading, the data of the latch circuit Q22 is inverted to "1" from the cell in which the writing is sufficient, and the inverted data of the latch circuit Q22 is determined by the wired-OR circuit every verify. As described above, the writing of “00” and the high-speed termination determination are realized.

Even when it is determined that all the writings of “00” are sufficiently written, the relationship between the original write data and the latch data is “00” → “10”, “01” → “1”.
1 ”,“ 10 ”→“ 10 ”,“ 11 ”→“ 11 ”.

Finally, this time, based on the latch data of the latch circuit Q21, the writing of the cell whose write data is "10" is performed. In this case, as for the memory cell which is the write data ("0") of the latch circuit Q21, the cell of "00" is also "0" in addition to the cell of which the write data is "10". Here, before writing the data “10”, reading is performed with the word line voltage VRD0. At this time, since no cell current flows through the memory cell where the write data is “00”, the node SA21
The power supply voltage V _CC is charged by the charging current from the OS transistor PT21. Thus, the NMOS transistors NT32 and NT29 are kept conductive. When the signal φLAT2 is set to a high level, NM
The OS transistor NT28 is kept conductive, the second storage node N21b of the latch circuit Q21 is pulled to the ground level, and the latch data of the latch circuit Q21 switches from a low level to a high level.

On the other hand, when the write data is "10", the cell current flows because the threshold voltage Vth is at the level of "11", the node SA21 is kept at the low level, and the NMOS transistors NT32 and NT29 are turned off. Held in state. Therefore, even if signal φLAT2 is set to the high level, the latch data of latch circuit Q21 is held at “0”. As a result, the data of the latch circuit Q21 becomes "0" only in the memory cell whose write data is "10". Thereafter, the signal PGM1 is set to the high level, the NMOS transistor NT25 is kept in the conductive state, and writing is performed, and the write data "1" is written.
The cell of "0" is written, and the inverted data of the latch circuit Q21 is determined by the wired-OR circuit.
As described above, insufficiently written cells can be detected at high speed.

In the manner described above, writing at a weak level for disturb is performed at the end of writing, so that the disturb time can be shortened and the copy back (Copy B
By performing the process of (ack), it becomes possible to detect the insufficiently written cells at high speed by the wired-OR circuit in each writing step.

As described above, according to the present embodiment, in the distribution shown in FIG. 2, the level of data "10" is weakest against disturbance,
Then, after the write data is written to the memory cells of “01” and “00” to the “01” level,
Since the memory cell of the write data “00” is written and the write of the memory cell of the write data “10” is performed at the end to finish the quaternary write, the disturb characteristic of the write level can be improved. There are advantages. In addition, it is possible to detect insufficiently written cells at high speed in all write steps.

In the above-described embodiment, the case of four values has been described as an example. However, it goes without saying that the present invention can be applied to the case of other multi-value levels. Hereinafter, the writing method in the case of octal data will be described with reference to FIG.

First, when the write data is “011”, “0”
Write is performed to the memory cells of “10”, “001”, and “000” up to the level of “011.” At this time, the write data is “111”, “110”, “101”,
The memory cell “100” is at the erase level “111”. Thereafter, the write data is “010”, “00”
1 and "000" in the memory cell in step 2, write data in the memory cell in "001" and "000" in step 3 and write data in the memory cell in "000" To write in step 4.

Thereafter, the write data is "110",
The write in step 5 is performed on the memory cells “101” and “100”, and the write data is “101” and “10”
The write of step 6 is performed on the memory cell of "0", and the write of step 7 is finally performed on the memory cell of which the write data is "100".

According to this write method, the disturb time of the memory cells having the write data "110", "101", and "100" is shortened, and the shift of the threshold voltage Vth due to the disturbance is reduced.

In the method shown in FIG. 5B, the write order of cells having write data "110", "101", and "100" is changed from that in the case of FIG. The disturb time of the memory cell whose write data is “110” is set to be the shortest.

[0060]

As described above, according to the nonvolatile semiconductor memory device of the present invention, there is an advantage that the disturbance characteristic of the write level can be improved. In addition, it is possible to detect insufficiently written cells at high speed in all write steps.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a diagram showing a correspondence relationship between a threshold voltage Vth distribution and write data.

FIG. 3 is a timing chart for explaining a write operation of the circuit of FIG. 1;

FIG. 4 is a timing chart for explaining a read operation of the circuit of FIG. 1;

FIG. 5 is a diagram for explaining a writing method according to the present invention in the case of eight values.

FIG. 6 is a diagram showing a relationship between a threshold voltage Vth level and data contents when data of two bits and having four values is recorded in one memory transistor in a NAND flash memory.

FIG. 7 is a circuit diagram showing a configuration of a main part of a conventional NAND flash memory.

FIG. 8 is a timing chart for explaining the operation of the circuit of FIG. 7;

FIG. 9 is a diagram for explaining a conventional quaternary writing method.

FIG. 10 is a diagram for explaining a conventional 8-level writing method.

[Explanation of symbols]

10: nonvolatile semiconductor memory device, 11: memory array,
A0, A1 memory string, WL0 to WL15 word line, BL0, BL1 bit line, 12 write / read control circuit, NT21 to NT39 NMOS transistor, PT21 PMOS transistor, INV21 inverter, Q21, Q22 Latch circuit.

Claims (8)

[Claims] An amount of charge stored in a charge storage unit changes according to a voltage applied to a word line and a bit line, and a threshold voltage changes according to the change. A non-volatile semiconductor memory device having a memory cell for storing value data and writing multi-bit data to the memory cell in page units, wherein at the time of writing, the memory cell of the data whose most significant bit is to be written is written first. , And thereafter, a write control means for writing the memory cell with data whose most significant bit is not written. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said write control circuit stores the transferred data in a latch circuit and performs writing. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said write control circuit includes one bit of said latch circuit corresponding to each bit line. 4. The nonvolatile semiconductor memory device according to claim 2, wherein said write control circuit is provided with one bit of said latch circuit corresponding to each bit line. 5. A verify read for judging whether or not write is sufficient for each write bit at the time of the write operation, and latch data of a latch circuit corresponding to a memory cell determined to be sufficiently written is converted to non-write data. 3. The non-volatile semiconductor memory device according to claim 2, further comprising means for inverting the data, reading the data as needed, and restoring the write data to obtain the next write data. 6. A verify read for judging whether or not writing is sufficient for each write bit at the time of the writing operation, and latch data of a latch circuit corresponding to the memory cell determined to be sufficiently written is converted to non-writing data. 4. The non-volatile semiconductor memory device according to claim 3, further comprising means for inverting the data, reading the data as needed, and restoring the write data to make the next write data. 7. The amount of charge stored in the charge storage unit changes according to the voltage applied to the word line and the bit line, and the threshold voltage changes according to the change. What is claimed is: 1. A data writing method for a nonvolatile semiconductor memory device, comprising a memory cell for storing value data, and writing multi-bit data to a memory cell in page units, wherein at the time of writing, the most significant bit is written to the memory cell for data. A method of writing data in a nonvolatile semiconductor memory device, in which data is written first, and then data of the most significant bit is not written in a memory cell. 8. A write operation is performed by storing the transferred data in a latch circuit and performing a verify read to determine whether or not write is sufficient for each write bit at the time of the write operation. 8. The non-volatile semiconductor device according to claim 7, wherein the latch data of the latch circuit corresponding to the selected memory cell is inverted to non-write data, and then read as necessary to restore the write data to obtain the next write data. A data writing method for a storage device.