JP3143161B2 - Non-volatile semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory, and more particularly, to a nonvolatile semiconductor memory capable of simultaneously executing an erasing operation and a reading operation on a memory array divided into a plurality of blocks in block units.

[0002]

2. Description of the Related Art FIG. 7 is a schematic block diagram of a conventional flash EEPROM. Flash E shown in FIG.
EPROM is IEEE Journal of Sol
id-State Circuits, Vol. 23,
No. 5, October 1988. 1157 to 1
This is shown on page 163. Referring to FIG.
Around the memory cell array, a Y gate 2, a source line switch 3, an X decoder 4, and a Y decoder 5 are provided. An address register 6 is connected to the X-decoder 4 and the Y-decoder 5, and receives an externally input address signal. The write circuit 7 and the sense amplifier 8 are connected to the memory cell array 1 via the Y gate 2. The write circuit 7 and the sense amplifier 8 are connected to an input / output buffer 9.

A program voltage generating circuit 10 and a verify voltage generating circuit 11 are provided to generate a voltage different from power supplies Vcc and Vpp supplied from outside, and this voltage is applied to Y gate 2 and X decoder 4 and the like. Can be A command register 12 and a command decoder 13 for setting an operation mode in accordance with externally input data are provided. Further, control signals / WE, / CE, and / OE are externally applied to a control circuit 14.

FIG. 8 is a sectional view of the memory cell shown in FIG. Referring to FIG. 8, a memory cell includes a floating gate 16, a control gate 17, a source diffusion region 18, and a drain diffusion region 19 formed on a semiconductor substrate 15.
And The oxide film thickness between the floating gate 16 and the substrate 15 is as thin as, for example, about 100 °, so that the electrons of the floating gate 16 can be moved by utilizing a tunnel phenomenon. The operation of the memory cell 1 is as follows. That is, at the time of programming, the drain 19 is set to 6.
A program voltage of about 5 V is applied, Vpp (12 V) is applied to the control gate 17, and a source 18
Is grounded. Therefore, the memory cell 1 is turned on and a current flows. At this time, avalanche breakdown occurs near the drain 19, and electron and hole pairs are generated. The holes flow through the substrate 15 to the ground potential, and the electrons flow in the channel direction and flow into the drain 19. Some of the electrons are accelerated by an electric field between the floating gate 16 and the drain 19 and injected into the floating gate 16. Thus, the threshold voltage of the memory cell 1 is increased.
This is defined as recording of information "0".

On the other hand, for erasing, the drain 19 is opened, the control gate 17 is grounded, and
pp is applied. Due to the potential difference between the source 18 and the floating gate 16, a tunnel phenomenon occurs, and electrons in the floating gate 16 are extracted. In this way, the threshold value of memory cell 1 decreases. This is defined as storage of information “1”.

FIG. 9 is a diagram showing a configuration of the memory cell array shown in FIG. Referring to FIG. 9, the memory cell array has a drain connected to a bit line 24 and a control gate connected to a word line 25. Word line 2
5 is connected to the X decoder 4, and the bit line 24 is connected to the I / O line 27 via the Y gate transistor 26 to which the output of the Y decoder 5 is input to its gate. The sense amplifier 8 and the write circuit 7 are connected to the I / O line 27, and the source line 28 is connected to the source line switch 3.

Next, the operation of the conventional flash EEPROM will be described with reference to FIGS. First,
An operation when data is written to the memory cell 1 surrounded by a dotted line shown in FIG. 9 will be described. The write circuit 7 is activated in accordance with externally input data, and a program voltage is supplied to the I / O line 27. At the same time, the Y signal is applied via the Y decoder 5 and the X decoder 4 by the address signal.
The gate 26 and the word line 25 are selected, and Vpp is applied to the memory cell 1. The source line 28 is grounded by the source line switch 3 during programming. Thus, a current flows through only one cell in FIG. 9, hot electrons are generated, and the threshold voltage increases.

On the other hand, erasing is performed as follows. First, X decoder 4 and Y decoder 5 are deactivated, and all memory cells 1 are deselected. That is, the word line 25 of each memory cell is grounded, and the drain is opened. On the other hand, a high voltage is applied to the source line 28 by the source line switch 3. Thus, the threshold value of the memory cell array 1 shifts to a lower value due to the tunnel phenomenon. Since the source line 28 is common, erasing is performed on all memory cell arrays at once.

Next, the read operation will be described. In the same manner as the write operation, reading of a memory cell surrounded by a dotted line in FIG. 9 will be described. First, if the address signal is Y
The Y gate 26 and the word line 25 selected and decoded by the decoder 5 and the X decoder 4 become “H”.
At this time, the source line 28 is grounded by the source line switch 3. In this way, if data is written to the memory cell and the threshold value is high, the memory cell is not turned on even if an "H" level signal is supplied from word line 25 to the control gate of the memory cell, and the bit is not turned on. No current flows from line 24 to source line 28.

On the other hand, when the memory cell is erased, the memory cell is turned on, so that a current flows from the bit line 24 to the source line 28. Whether or not a current flows through the memory cell is detected by the sense amplifier 8, and read data "1" and "0" are obtained. Thus, writing and reading of data in the flash EEPROM are performed.

As another example of the ROM, there is an EPROM which erases data by irradiating ultraviolet rays. In such an EPROM, when the floating gate becomes electrically neutral, no further electrons are extracted from the floating gate, and the threshold value of the memory transistor does not fall below about 1V. On the other hand, in the extraction of electrons using the tunnel phenomenon, electrons are excessively extracted from the floating gate, and the floating gate is positively charged. This phenomenon is called over-erasing or over-erasing.

If the threshold value of the memory transistor becomes negative, it interferes with subsequent reading and writing.
That is, the word line level is "L" when read is not selected.
Level, and even if the level of the signal applied to the control gate line of the memory transistor is at the "L" level, a current flows from the bit line 24 through the memory transistor. The memory cell to be read reads "1" even if the threshold value is high in the written state. Also, at the time of writing, since a leak current flows through the over-erased memory cell, the writing characteristics are deteriorated, and furthermore, writing becomes impossible.

For this reason, reading is performed after erasing to check whether erasing has been performed correctly (hereinafter referred to as "erase verify"), and when there is a bit that is not erased, erasing is performed again. A method of preventing an extra erase pulse from being applied to a memory cell is adopted.

FIGS. 10 and 11 show flowcharts of erasing and programming including the above-described verify operation, and FIGS. 12 and 13 show them in a timing chart.

Next, the write and erase operations will be described with reference to FIGS. 7, 10, 11, 12, and 13. FIG. In the conventional flash EEPROM, writing and erasing modes are set by a combination of input data. That is, the mode is set by the rising data of write enable signal / WE. First, FIG.
2 will be described with reference to FIG. at first,
Vcc and Vpp are steps (abbreviated as S in the drawing) S
At step S1, the write enable signal / WE falls at step S2. Then, the input data 40 _H is latched in the command register 12 on the rising edge of of the write enable signal / WE. Thereafter, the input data is decoded by the command decoder 13, and the operation mode is set to the program mode.

Next, in step S3, the write enable signal / WE falls again, an external input address is latched in the address register 6, and data is latched in the write circuit 7 when the write enable signal WE rises. . Next, a program pulse is generated from the program voltage generation circuit 10 and applied to the X decoder 4 and the Y decoder 5. Thus, the program is performed as described above.

Next, the write enable signal / WE falls, input data (CO _H ) is input and latched in the command register 12. Subsequently, with the rise of the write enable signal / WE, the operation mode becomes the program verify mode (S6). At this time, a program verify voltage (up to 6.5 V) is generated inside the chip by the verify voltage generating circuit 11 and applied to the X decoder 4 and the Y decoder 5. For this reason, the voltage applied to the control gate of the memory cell array 1 becomes higher than that during normal reading (up to 5 V), and those showing an inadequate threshold value shift are easily turned on, and a write failure can be found.

Next, reading is performed in step S7.
Check the write data. If it is determined in step S8 that there is a write failure, the processes in steps S2 to S7 are further performed to perform writing. If the writing has been performed, the mode is set to the reading mode in step S9, and the program ends.

Next, referring to FIG. 13, the erase operation will be described.
explain. First, in step S10, Vcc, V
pp is started, and then follows the above described write flow processing.
In step S11, "0" is written to all bits.
Now. If you erase the erased memory cell further,
This is because the recell array 1 is over-erased. Next, write
Input the erase command with the enable signal / WE falling
I do. That is, in step S12, (20_H)
Enter Subsequently, in step S13, the erasure confirmation
Command is input and the write enable signal /
An erase pulse is generated internally with the rise of WE
You. That is, the memory cell is connected via the switch 3 of the source line.
Vpp is applied to the source of the array 1. Then calligraphy
Source signal 28 until the fall of the enable signal / WE
Is applied to Vpp. At the same time,
The address is also latched in the address register 6. Step S1
5 at the rise of write enable signal / WE
Delete verify command (AO _H) Is entered and the erase verify
Set to phi mode.

In the erase verify mode, an erase verify voltage (up to 3.2) is applied by a verify voltage generating circuit 11.
V) is applied to the X decoder 4 and the Y gate 2. Therefore, the voltage applied to the control gate of the memory cell array 1 becomes lower than that during normal reading (5 V), and a memory cell with insufficient erasing becomes difficult to turn on. In this way, erasure confirmation can be performed more reliably.

Next, reading is performed in step S16, and erasure is actually confirmed. Step S17
In step S18, if it is determined that the erasure is insufficient, the erasure is further repeated.
The address is incremented, and the erase data at the next address is verified. Step S19
If it is determined that the verified address is the last address, the operation mode is set to the read mode in step S20, and a series of operations is completed.

FIG. 14 is a block diagram of a conventional flash EEPROM which can be erased in sector units. This block diagram shows the 1990 Symposium on VLSI
It is shown in a paper at Circuits (pages 103-104). Referring to FIG. 14, this flash EE
The PROM comprises an address buffer 30 and an X decoder 31 having 32 output word lines XW0 to XW31.
And a memory cell array 32 divided into 64 segments, a Y decoder 33, a sense amplifier 34, a bit line latch circuit 29, and an input / output buffer 9. This flash EEPROM has a memory capacity of 4 megabits. Each segment in the memory cell array 32 has 32 word lines, and each word line has X
Connected to output word lines XW0 to XW31 of decoder 31.

Therefore, one output word line of the X decoder 31 has 256 bytes (=
2 kilobits = (4 megabits / 64) / 32) data is handled. As a result, the entire chip handles 16 kilobytes (= 256 bytes × 64 segments) of data.
A unit of data or memory cell that can be handled by one output word line of the X decoder 31 (= 16 kilobytes)
Are referred to as “sectors” in the following description. Flash EE
A PROM can normally only erase all data stored in a chip at once, but can erase data in sectors by applying a potential to each word line as described later.

The bit line latch circuit 29 is provided to temporarily hold data in page writing, and allows a maximum of 256 bytes of data to be written in one cycle. The sense amplifier 34 reads stored data by detecting whether or not a current flows through a memory cell selected in a read operation. The input / output buffer 9 is connected to the memory cell array 32 via the sense amplifier 34, and is connected to input / output data terminals D0 to D7.

FIG. 15 is a circuit diagram in one segment of the memory cell array 32 shown in FIG. Referring to FIG. 15, each memory cell (that is, memory transistor) is provided between a local bit line LB and a local source line LS formed by an n ⁺ diffusion buried layer. Each NMOS transistor 35 connects a local bit line LB of the selected segment to a global bit line (not shown) of a metal wiring in response to a segment select signal SS output from a segment select decoder (not shown). I do. In addition, each NMOS transistor 3
6 connects the local source line LS to the common source line CS in response to the common source select signal CSS.

In FIG. 15, the potential of each signal applied when the erasing operation is performed in sector units is shown in parentheses. In the case where a sector including a memory cell surrounded by a dotted line in FIG. 15 is erased, a potential Vee of -11 volts is applied to word line XW1, and power supply potential Vcc is applied to other word lines XW0 and XW2 to XW31. Can be The power supply potential Vc is connected to the common source line CS.
c is given. Since the potential Vcc is also applied to the common source select signal CSS, the transistor 36 is turned on, and the source potential Vcc is applied to the sources of all the memory transistors.
cc is given. On the other hand, since the potential Vss is applied to the gate of the transistor 35, the transistor 35 is turned off, so that the drains of all the memory transistors are brought into a floating state. As a result, a potential difference of 16 volts is generated between the control gate and the source of the memory transistor in the selected sector, and electrons are extracted from the floating gate.
That is, data is erased.

On the other hand, when the sector erase is being performed,
In the memory transistors connected to the unselected word lines XW0 and XW2 to XW31, the potential difference between the control gate and the source is 0 V, and no injection or extraction of electrons occurs.

The definition of block erasure and sector erasure has not been clarified conventionally, and generally,
When the memory cell is divided and erased, a unit having a large unit is called a block erase, and a small unit is read as a sector erase.

[0029]

In the conventional flash EEPROM described above, when a block erase or a sector erase is performed, no access is made to a block or a sector which is not to be erased. Performing the erase operation generally requires a relatively long time (for example, 10 ms for an internal erase signal). Therefore, with the recent increase in the speed of microprocessors, it has been an issue that the time required for erasing data in the flash EEPROM is long. Therefore, if another access, for example, reading, is possible for the remaining portion during the partial erasing operation, the problem of a long erasing time can be alleviated as much as possible.

The present invention has been made to solve the above-described problem. In a nonvolatile semiconductor memory in which a memory array block can be erased in block units, a read operation is performed in a memory array block which is not to be erased. The purpose is to do.

[0031]

A nonvolatile semiconductor memory according to the present invention includes a plurality of memory array blocks each having a plurality of memory transistors arranged in rows and columns, and is provided corresponding to each memory array block. selects a source line connected to the source of each memory transistor of the corresponding memory array block, the source line corresponding to the memory array blocks corresponding to the vanishing <br/> removed by address supplied from the outside, the source line giving the erase voltage to the pair
A selective block erase means for collectively erasing data in the memory array block which respond, and reading the read means the data in the memory array block corresponding to the read address supplied from the outside, and reading of erasing the data in the data To
In the erase / read mode performed in parallel, the erase address and
Compares the read address with the memo corresponding to the erase address.
Memory array according to the rearray block and read address
If the block matches the
While maintaining the erase operation of the stage, readout of the readout means
Control means for inhibiting the operation . Also,
Other nonvolatile semiconductor memories according to the present invention
Has multiple memory transistors arranged in a matrix
Memory array blocks and each memory array block
Block corresponding to the memory array block
Connected to the source of each memory transistor
Line and memory according to externally applied erase address
Select the source line corresponding to the array block and
Erasing voltage to the corresponding memory array block.
Block erasing means for erasing data in blocks
And a memory corresponding to an externally applied read address
Reading means for reading data in the array block;
/ Readout for erasing data and reading data in parallel
Compare erase address and read address in read mode
And read from the memory array block according to the erase address.
Address does not match the memory array block
The erase operation of the selective block erase
And activates the reading means to read the address.
Data in the memory array block according to the
Control means. Preferably, further,
Externally giving erase address to selective block erase means
And externally giving a read address to the read means.
Address input means for obtaining
The erase address is received from the input means, and the other end is
The erase address bus connected to the stage and one end
At least one of the read addresses from the
Block address for specifying memory array block
And a read address having one end connected to the control means.
A resbass is provided.

[0032]

[Action] In the nonvolatile semiconductor memory according to the present invention, in accordance with the erase address source line for each memory array block is given from the provided Rutotomoni, external Memoria
Apply erase voltage to the source line corresponding to the
Selective block for batch erasing data in memory array block
Lock erasing means and externally provided read address
Read data in memory array block according to
Means and an erase address and a read address in the erase / read mode.
Memory address according to the erase address
Memory array according to array block and read address
If the block matches, select block erasing means
To maintain the erasing operation of the
Control means for inhibiting the operation. Therefore,
Since a source line is provided for each memory array block, 1
Erasure and readout of data can be performed in parallel in one memory chip. Also, the memory corresponding to the erase address
Memory array according to array block and read address
If the block matches, the read operation is prohibited.
The erase operation can be prioritized over the read operation.
To perform stable erase operation and accurate read operation
Can be. In addition, another nonvolatile semiconductor memory according to the present invention.
Memory, a source line is provided for each memory array block.
At the same time as the erase address given from the outside.
Erase power is applied to the source line corresponding to the same memory array block.
Data in memory array block by applying pressure
Selective block erasing means that performs
Data in the memory array block according to the output address
Read means for reading the data, and erase in the erase / read mode.
Compare the address with the read address, and
Memory array block and read address
If the memory array block does not match, select block
While maintaining the erasing operation of the lock erasing means,
And control means for activating the control means. But
Therefore, a source line is provided for each memory array block.
Data erase and read in one memory chip
Can be done on a queue. Also, according to the erase address
Memory according to memory array block and read address
Activates reading means when array block does not match
Since to reduction, main data erasure is performed Moria
Prevent reading means from accessing the ray block
be able to. Preferably, further, an external selective
Give the erase address to the lock erase means and externally
To give read address to read means from
Input means and one end of which is erased from the address input means.
Erase receiving dress and other end connected to control means
Address bus and one end read from address input means
At least the memory array block of the output address
Receives the block address for specifying
Is provided with a read address bus connected to the control means.
It is. In this case, the erase address bus and the read address
Since the bus and the bus are provided separately, the erase address and the read address
Control means for at least the block address of the address
Can be given in parallel to each other.
Read operation can be performed at high speed.

[0033]

FIG. 2 is a block diagram of a flash EEPROM showing an embodiment of the present invention. Referring to FIG.
The improved memory cell array 1 'has four blocks B
It is divided into L1 to BL4. Four blocks B
Source line switches SS1 corresponding to L1 to BL4
Through SS4, and the source line switch SS
Erase voltage V externally applied through 1 to SS4
pp is applied to blocks BL1 to BL4, respectively. An erase / read control circuit 50 is newly provided, and the source line switches SS1 to SS4 are connected to a block selection signal BS generated from the erase / read control circuit 50.
1 to BS4.

FIG. 1 is a schematic circuit diagram showing the relationship between the memory array block shown in FIG. 2 and each of the decoders 5, 41 to 44. Referring to FIG. 1, four X decoders 41 to 44 are provided corresponding to four blocks BL1 to BL4 of the memory cell array, respectively.
X decoders 41 to 44 correspond to X decoder 4 'shown in FIG. In each of the blocks BL1 to BL4,
To simplify the drawing, six memory transistors (or cells) are shown. Each of the X decoders 41 to 4
4 is connected to the memory transistors in the corresponding blocks BL1 to BL4 via word lines. Source lines SL1 to SL4 are provided for each of the blocks BL1 to BL4, and the source lines SL1 to SL4 are provided.
4 is connected to the corresponding source line switches SS1 to SS4. In each of the blocks BL1 to BL4, the sources of all the memory transistors are connected to the corresponding source lines SL1 to SL4.

Output lines Y101, Y10 of Y decoder 5
, 402 are connected to the gates of the corresponding Y gate transistors 101, 102, 201,. Data is transmitted between the blocks BL1 to BL4 and the I / O line 27 via these Y gate transistors.

FIG. 3 is a circuit block diagram of the erase / read control circuit 50 shown in FIG. Referring to FIG. 3, erase / read control circuit 50 responds to a signal applied from command decoder 13 'shown in FIG. 2 to select block select signals BS1 to BS B for selecting a block to be erased.
In response to a source line switch selection circuit 51 that outputs S4, an address mismatch detection circuit 52 that detects a mismatch between an erase address and a read address, and a mismatch detection signal NC given from the address mismatch detection circuit 52, FIG. And a sense amplifier activating circuit 53 for activating the sense amplifier 8 shown in FIG.

In operation, data relating to a block to be erased is included in an externally applied block select command, and the command decoder 13 'decodes the applied command to obtain an erase address. The erase address is stored in the source line switch selection circuit 51.
And the address mismatch detection circuit 52. Source line switch selection circuit 51 outputs a block selection signal in response to the applied erase address. For example, when the block BL1 is externally selected as a block to be erased, the source line switch selection circuit 51 outputs a high-level block selection signal BS1.

The address mismatch detection circuit 52 receives a read address for a read operation to be performed simultaneously (or in parallel) with the above-described erase operation from the outside via the address register 6. Address mismatch detection circuit 52
Detects a mismatch between the erase address and the read address, and outputs a mismatch detection signal NC only when the mismatch is detected. The sense amplifier activation circuit 53 activates the sense amplifier 8 in response to the mismatch detection signal NC. Therefore, a read operation based on a read address given externally is performed on blocks BL2, BL3 and BL4 in the above-described example in which the erase operation is not performed, and the read data signal is activated. It is amplified by the sense amplifier 8. If the erase address matches the read address, sense amplifier 8 is not activated by sense amplifier activation circuit 53.

FIG. 4 shows the flash EEPROM shown in FIG.
5 is a timing chart for explaining the operation of the OM. Referring to FIG. 1 and FIG.
The operation of the PROM will be described. In steps S20 and S21, an erase command ERC (20 _H ) is input. Next, in step S22, a block selection command BSC is input. Both the erase command ERC and the block selection command BSC are applied to the command decoder 13 'shown in FIG. 2, where they are decoded. In step S23, the erase operation is started in the selected block.

In the example described above, the erase operation is performed in block BL1. That is, since only the source line switch SS1 shown in FIG. 1 is turned on, the erase voltage Vpp (= 12 volts) is applied to the source line SL1. Transistors 101 and 102 are turned off, and all bit lines in block BL1 are brought into a floating state. In addition to this, the X decoder causes the block BL1
0 volt potential is applied to all word lines WL11 to WL13. Therefore, an erasing operation is performed in block BL1.

In step 23, while the erase operation of block BL1 is performed, the remaining blocks BL2, B
At L3 and BL4, a read operation is performed.
In the blocks BL2, BL3 and BL4, the source line S
L2, SL3 and SL4 are grounded, and in response to an externally applied read address signal ADR, Y decoder 5 and X decoders 42, 43 and 44 operate to perform a read operation. As a result, in step S23, the read data DR is output.

FIG. 5 is a block diagram of a flash EEPROM showing another embodiment of the present invention. This embodiment is characterized in that the erase address ADE is not supplied from the command decoder 13 but to the erase / read control circuit 50 'via the address register 6 and the Y decoder 5. The erase / read control circuit 50 'performs an erase operation on a block to be erased in response to the erase address ADE, and on the other hand, the read address AD.
In response to R, a read operation is performed on another block.

FIG. 6 is a timing chart in the case where the erasing operation is performed on block BL1 and the reading operation is performed on other blocks BL2, BL3 and BL4. Referring to FIG. 6, erase commands ERC are provided in steps S24 and S25. In step S25, an erase address ADE is further provided. In step S26, the block BL1 is erased based on the erase address ADE, and at the same time (or in parallel), a read operation is performed on the other blocks BL2, BL3 and BL4 based on the read address ADR.

As described above, in the flash EEPROM shown in FIGS. 2 and 5, while the erase operation is performed in the selected block of memory cell array 1 ', the erase operation is performed simultaneously (or in parallel) with the selected block. A read operation can be performed on a block that is not performed.
Therefore, it takes approximately the same time to erase data as before, but data can be read out during that period, and the processing speed can be improved while the microprocessor speeds up. Can contribute to.

[0045]

As described above, the nonvolatile memory according to the present invention
The semiconductor memory, Rutotomoni source lines are provided for each memory array block, the data in the memory array blocks by applying an erase voltage to the source line corresponding to the memory array blocks corresponding to the erasure address supplied from the outside
Selective block erasing means for batch erasing and externally applied
In the memory array block corresponding to the read address
Read means for reading out the data in the erase / read mode
The erase address and the read address,
Memory array block and read address according to dress
If the memory array block corresponding to
In addition to maintaining the erase operation of the selective block erase means,
Control means for inhibiting the read operation of the read means.
Be killed. Therefore, each memory array block has its software
Since the source line is provided , erasing and reading of data can be performed in parallel in one memory chip, and the operating speed can be increased. Also, according to the erase address
Memory according to memory array block and read address
Disables read operation when array block matches
Therefore, the erase operation can be given priority over the read operation.
To perform stable erase operation and accurate read operation.
Can be. Another nonvolatile semiconductor according to the present invention
In a memory, a source line is provided for each memory block.
According to the erase address given from the outside.
Apply the erase voltage to the source line corresponding to the memory array block.
To erase data in the memory array block at once
Selective block erase means and externally applied read
Reads data in the memory array block corresponding to the address.
Readout means for outputting data and an erase address in the erase / readout mode.
Address and read address, and according to the erase address
Memo corresponding to the memory array block and read address
If the rear array block does not match, select block
In addition to maintaining the erase operation of the
Control means for activating the stage. Accordingly
Therefore, a source line is provided for each memory array block.
Data erase and read in one memory chip
Can be performed in a row, and the operating speed can be increased.
it can. Also, the memory array block corresponding to the erase address
Memory array blocks and corresponding to click and read address
If the values do not match, the reading means is activated.
Data to the memory array block from which data has been erased.
Access to the delivery means can be prevented. Good
More preferably, externally, a means for selectively erasing blocks is provided.
Give the erase address and externally
Address input means for providing a read address;
Receives an erase address from the address input means,
Erase address bus with the other end connected to the control means
And one end thereof is the address read from the address input means.
At least one of the memory array blocks
The other end to control means
A connected read address bus is provided. This place
Separate the erase address bus and read address bus
In the erase address and the read address.
The block address can be given to the control means in parallel.
Speed of read operation in erase / read mode
Can be achieved.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram showing a relationship between a memory array block shown in FIG. 2 and each decoder.

FIG. 2 is a flash EEPROM showing an embodiment of the present invention;
It is a block diagram of OM.

FIG. 3 is a circuit block diagram of an erase / read control circuit shown in FIG. 2;

FIG. 4 is a timing chart for explaining the operation of the flash EEPROM shown in FIG. 2;

FIG. 5 shows a flash EEP showing another embodiment of the present invention.
It is a block diagram of ROM.

FIG. 6 is a timing chart for explaining an operation of the flash EEPROM shown in FIG. 5;

FIG. 7 is a block diagram of a conventional flash EEPROM.

FIG. 8 is a sectional structural view of a memory cell applied to a flash EEPROM.

FIG. 9 is a circuit diagram around the memory cell array shown in FIG. 7;

FIG. 10 is a flowchart for explaining an erasing operation of a conventional flash EEPROM.

FIG. 11 is a flowchart illustrating a program operation of a conventional flash EEPROM.

FIG. 12 is a timing chart for explaining a write operation of a conventional flash EEPROM.

FIG. 13 is a timing chart for explaining an erasing operation of a conventional flash EEPROM.

FIG. 14 shows a conventional flash E which can be erased in sector units.
It is a block diagram of EPROM.

15 is a circuit diagram in one segment of the memory cell array shown in FIG.

[Explanation of symbols]

 1 'Memory cell array divided into four blocks 3' Source line switch provided for each block 4 'X decoder provided for each block 5 Y decoder 8 Sense amplifier 50 Erase / read control circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 16/00-16/34

Claims (3)

(57) [Claims] 1. A plurality of memory array blocks each having a plurality of memory transistors arranged in a matrix, and provided corresponding to each memory array block and connected to a source of each memory transistor of the corresponding memory array block. Memory array according to the source line and the erase address given from the outside
Select the source line corresponding to the block, giving an erase voltage to the source line, and selectively block erase means for collectively erasing <br/> data in the corresponding memory array block, the read address supplied from the outside Reading means for reading data in the memory array block corresponding to the data, and erasing / erasing for erasing data and reading data in parallel.
In the read mode, the erase address and the read address
Memory array according to the erase address.
And a memory array corresponding to the read address
If the block matches, the selective block erase
Means for maintaining the erasing operation of the read means.
A non-volatile semiconductor memory, comprising: control means for prohibiting a read operation . 2. A plurality of menus, each of which is arranged in a matrix.
Multiple memory array blocks with memory transistors
When provided corresponding to each memory array block, the corresponding
Source of each memory transistor in the memory array block
Array connected to a source line connected to the memory cell and an externally applied erase address
Select the source line corresponding to the block and set the source line
By applying an erase voltage to the corresponding memory array block,
A selective block erasing means for batch erasing data, and a memory array corresponding to a read address given from outside.
Reading means for reading data in the data block, and erasing / erasing means for performing data erasing and data reading in parallel.
In the read mode, the erase address and the read address
Memory array according to the erase address.
And a memory array corresponding to the read address
If the block does not match, select the block
While maintaining the erasing operation of the reading means,
Activate the stage to store the memory address corresponding to the read address.
Control means for reading data in the ray block.
A non-volatile semiconductor memory. 3. The method according to claim 1, further comprising the step of externally erasing said selective block.
To the clearing means, and
An address for giving the read address to the read means.
Address input means , one end of which is connected to the erase address by the address input means.
And the other end is connected to the control means.
An address bus having one end connected to the read address from the address input means;
Address at least the memory array block.
To receive the block address, and the other end
A read address bus connected to the control means.
The nonvolatile semiconductor memo according to claim 1 or 2.
Ri.