KR100560634B1 - Non-volatile semiconductor memory - Google Patents

Abstract

A nonvolatile semiconductor memory device according to the present invention outputs two banks each consisting of a plurality of memory cells, sense amplifiers corresponding to the banks, and sense amplifier enable signals for driving the sense amplifiers. Including a control circuit, when one bank is performing a write operation, cell data can be read from another bank at the same time.

Description

Nonvolatile Semiconductor Memory Device {NON-VOLATILE SEMICONDUCTOR MEMORY}

1 is a cross-sectional view of a typical flash memory cell;

2 is a block diagram showing a conventional flash EEPROM device;

3 is a block diagram showing a flash EEPROM device according to a preferred embodiment of the present invention;

4 is a block diagram illustrating in detail the first latch and control circuit, the second latch and control circuit and the input / output interface shown in FIG. 3;

5 is a circuit diagram showing in more detail the control circuitry in the first latch and control circuit shown in FIG. 4;

6 is a circuit diagram showing in more detail the control circuitry in the second latch and control circuit shown in FIG. 4;

7 is a circuit diagram showing in detail the data output selection circuit shown in FIG.

FIG. 8 is a timing diagram when reading data from bank 1 of the EEPROM device shown in FIG. 3; FIG. And

FIG. 9 is a timing diagram when data is read from bank 1 while a write operation is performed in bank 2 of the EEPROM device shown in FIG. 3.

* Description of the symbols for the main parts of the drawings *

1: silicon substrate 2: source

3: drain 4: floating gate

5: control gate 10: cell array

12, 112, 122: row decoder 14, 114, 124: column decoder

20, 100: input / output interface 30: sector information storage circuit

32, 132: erase control circuit 34, 134: program control circuit

36, 136, 138: latch and control circuit
38, 140: high voltage generating circuit

110: bank 1 cell array 120: bank 2 cell array

210, 230: control circuit 220, 240: sense amplifier

250: data output selection circuit 260: data output buffer

The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a flash electrically erasable programmable read-only memory (EEPROM) device.

1 is a cross-sectional view of a typical flash memory cell.

Referring to FIG. 1, the flash EEPROM cell transistor is generally completely surrounded by an insulating film and is arranged between a source 2 and a drain 3 formed on the silicon substrate 1. An electrically floating gate 4 and a control gate 5 connected to a word line. Charge carriers (ie electrons) in the cell are injected into the floating gate through the insulating film when the cell is programmed. The operation of a flash EEPROM device is generally divided into three modes: program, erase, read.

The flash cell is programmed by hot electrons injected from the substrate into the floating gate. To induce such an effect, a high voltage (e.g., + 10V) is applied to the control gate 5 when the source 2 and the bulk 1 are grounded, and to the drain 3 Appropriate amount of voltage (e.g. 5-6V) is applied to generate hot electrons.

In the program mode, the floating gate accumulates hot electrons and blocks the flow of accumulated electrons. Accumulation of a large amount of blocked electrons on the floating gate causes an increase in the effective threshold voltage (eg, about 6-7V) of the cell transistor. If this increase is large enough, the cell transistor will remain in a non-conductive state when a read voltage is applied to the control gate 5 and the drain 3 during a read operation. In this programmed state the cell will be stored as a logic '0' (OFF cell). The programmed state of such cells is maintained even if the power supply is interrupted.

Flash cell transistor erase removes the charge accumulated in the floating gate of the cell. The erasure of the flash cell can be achieved by drawing a negative high voltage (e.g. -10V) and bulk to the control gate 5, for example, while floating the source 2 and drain 3 of the cell. It can be performed by applying a positive voltage (e.g., 5-6V). This causes cold electron tunneling (ie, Fowler-Nordheim tunneling), which leads to a reduction in the threshold voltage (eg, 1 to 3 V) of the cell transistor through the thin insulating film between the floating gate and the bulk. The erase voltage will be applied to the cell until the erase voltage is erased below the maximum acceptable threshold voltage. If the flash cell is erased this will be done in bulk. In this case, the cell will store a logic '1' (ON cell). Thus, the program / erase state (ie, 1 or 0) of the cell can be determined by monitoring the bit line current.

During a series of read operations, a memory cell whose threshold voltage is lowered by the erase operation is applied from the drain 3 when a constant voltage or a power supply voltage (for example, 4 to 5 V) is applied to the control gate 5. A current path is formed to the source 2, where the memory cell is said to be ON.

2 is a block diagram showing a conventional flash EEPROM device. Referring to FIG. 2, the flash memory device includes a nonvolatile EEPROM cell array 10, a row decoder 12, a column decoder 14, and an input / output interface 20. ), A sector information storage circuit 30, an erase control circuit 32, a program control circuit 34, a latch and control circuit 36, and a high voltage generation circuit 38.

The input / output interface 20 receives external input signals nCE, nOE, nWE, nBYTE, nRESET, nRY / BY, A0 to A19, DQ0 to DQ15, and controls signals and addresses to the respective control blocks. And interface data input / output with the latch and control circuit 36 and the outside. The high voltage generator 38 generates a high voltage (for example, 5 to 6 V, 10 V, etc.) using a power supply voltage (for example, 2.7 to 3.6 V). The erase control circuit 32 receives an external erase command signal, outputs a control signal so that the high voltage generator 38 generates a voltage suitable for the erase operation, and sends a signal indicating the erase operation to the row decoder 12. Output In addition, when the memory device is performing an erase operation, the device notifies that the device is in a BUSY state. Upon completion, the device automatically notifies the READY state to prepare for input of a command for the next operation. The sector information storage circuit 30 has information on a sector to be erased during an erase operation of the memory device, that is, information on whether or not to erase the memory device. The sector information storage circuit 30 stores information about an erase sector on the erase control circuit 32 and the program control circuit 34. To provide.

The program control circuit 34 controls a series of program operations. In response to an external program command signal, the high voltage generator 38 outputs a control signal to generate a voltage suitable for a program operation. In addition, when the memory device is performing a program operation, the device notifies that the device is in a BUSY state, and upon completion, the device automatically informs the READY state to prepare for input of a command for the next operation. The latch and control circuit 36 senses data of the cell array 10 through a sense amplifier (not shown) in a read mode and outputs the data to the input / output interface 20, and in the program mode, the input / output interface. Data input from 20 is provided to the cell array 10.

Most flash memory devices using the latest high density technologies employ segmented cell array structures to reduce chip size. That is, the bulk and the cells are divided into a number of sectors, and the sources of cells in the sector are commonly connected to the corresponding bulk. This structure allows all cells in a sector (eg 16k or 64k byte capacity) to be erased simultaneously.

The erase operation is performed sector by sector, and the time required is several hundred microseconds (μsec) to several seconds (sec) or more per sector, so that no other operation (for example, a read operation) is performed while the erase operation is performed. I could not. Recently, when an erase operation for a sector is requested through an erase-suspend & resume operation, if another operation is requested for another sector (for example, a read operation), the erase operation is temporarily stopped. After performing another operation (eg, a read operation), the erase operation may be performed again. However, this is a very cumbersome operation, and the operation speed of the nonvolatile semiconductor memory device is not improved.

Accordingly, an object of the present invention is to divide a memory cell array into a plurality of banks including a plurality of sectors, and to perform a read, program, and erase control for each bank separately. To provide.

Another object of the present invention is to provide a nonvolatile semiconductor memory device capable of simultaneously performing a second operation for another bank in parallel when a first operation for one bank is being performed.

According to a feature of the present invention for achieving the object of the present invention as described above, the nonvolatile semiconductor memory device comprises: at least two banks each consisting of a plurality of memory cells; Sense amplifiers each corresponding to the banks, each sensing amplifier amplifying data from the corresponding bank in response to a corresponding control signal; A control for outputting the control signal for driving a sense amplifier corresponding to the read enable signal and the write enable signal among the sense amplifiers in response to the read enable signal and the write enable signal corresponding to the banks; Circuit and; An output selector circuit for selectively outputting data from the sense amplifier corresponding to the read enable signal of the sense amplifiers, wherein the control circuitry comprises a second bank when one of the banks is write enabled. When the read enable signal corresponding to the signal is applied, the control signal for enabling the sense amplifier corresponding to the read enable signal is output.

In a preferred embodiment, the control circuit is adapted to drive the sense amplifier corresponding to the bank in response to the read enable signal and the write enable signal corresponding to one of the banks. A first control circuit for outputting; And a second control circuit outputting the control signal for driving the sense amplifier corresponding to the bank in response to the read enable signal and the write enable signal corresponding to one of the other banks. .

In a preferred embodiment, the first and second control circuits comprise: a first detection circuit for detecting whether the read enable signal is activated; A second detection circuit for detecting whether the write enable signal is activated; And a logic circuit for outputting the control signal when at least one detection signal is input from the first and second detection circuits.

By such a device, read, program and erase operations are performed separately for each bank in a nonvolatile memory device including at least two banks. Therefore, a nonvolatile memory device capable of simultaneously reading memory cell data from another bank when one bank is performing a write operation may be implemented. As a result, the operation speed of the nonvolatile semiconductor memory device is improved.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 9.

3 is a block diagram illustrating a flash EEPROM device according to a preferred embodiment of the present invention. The flash memory device includes an input / output interface 100 and a first bank 110 and a second bank 120 each including a plurality of sectors each consisting of a plurality of nonvolatile EEPROM cells. Row decoder 112, column decoder 124, latch and control circuit 136 for the bank 100, and row decoder 122, column decoder 124, latch and control circuit for the second bank ( 138, a sector information storage circuit 130, an erase control circuit 132, a program control circuit 134, and a high voltage generation circuit 140.

The input / output interface 100 receives external input signals nCE, nOE, nWE, nBYTE, nRESET, nRY / BY, A0 ~ A19, DQ0 ~ DQ15, and supplies control signals and addresses to the respective control blocks. And interface data input / output with the latch and control circuits 136 and 138. The high voltage generation circuit 140 generates high voltages (eg, 5 to 6V, 10V, etc.) using a power supply voltage (eg, 2.7 to 3.6V). The erase control circuit 132 receives an external erase command and outputs a control signal such that the high voltage generation circuit 140 generates a voltage suitable for an erase operation, and outputs a signal informing of the erase operation to the row decoders 112 and 122. ) In addition, when the memory device is performing an erase operation, the device notifies that the device is in a BUSY state. Upon completion, the device automatically notifies the READY state to prepare for input of a command for the next operation. The erase control circuit 132 has information on a sector to be erased during an erase operation of the memory device, that is, information on whether or not to erase the memory device. To provide.

The program control circuit 134 controls a series of program operations. In response to an external program command signal, the high voltage generator 38 outputs a control signal to generate a voltage suitable for a program operation. In addition, when the memory device is performing a program operation, the device notifies that the device is in a BUSY state, and upon completion, the device automatically informs the READY state to prepare for input of a command for the next operation. The latch and control circuit 136 senses data of the bank 1 110 through a sense amplifier (not shown) in the read mode and outputs the data to the input / output interface 100, and in the program mode, the input / output. The data input from the interface 100 is provided to the bank 1 110. The latch and control circuit 138 senses data of the bank 2 120 through a sense amplifier (not shown) in a read mode and outputs the data to the input / output interface 100, and in the program mode, the input / output interface. Data input from 100 is provided to the bank 2 120.

4 is a block diagram illustrating in detail a first latch and control circuit, a second latch and control circuit, and an input / output interface shown in FIG. 3.

Referring to FIG. 4, the first latch and control circuit 136 includes a sense amplifier 220 and a control circuit 210 for controlling the sense amplifier 220. The second latch and control circuit 138 includes a sense amplifier 240 and a control circuit 230 for controlling the sense amplifier 240. The input / output interface 100 includes a data select output circuit 250 and a data output buffer 260.

The sense amplifiers 220 and 240 have a difference between a potential of a bit line and a potential of a reference bit line, which are maintained at a precharge level or developed at a ground voltage level according to the threshold voltage of a selected cell transistor in a read mode. Detect and amplify.

The control circuit 210 read-in signal ATD_READ that is activated at an address transition or chip enable in a read mode, and write-in enabled at an address transition or a chip enable in a write mode. Able signal ATD_WRITE, bank 1 operation signal BANKBUSY1 that is activated when bank 1 110 is in write mode (program mode or erase mode), signal RDBASEL1 indicating that bank 1 is selected in read mode, in write mode It accepts a signal WTBASEL1 indicating that bank 1 is selected, and generates a sense amplifier enable signal SAE1 for enabling the sense amplifier 220.

The control circuit 230 is a bank 2 operation signal BANKBUSY2 that is activated when the read enable signal ADT_READ, the write enable signal ADT_WRITE, and the bank 2 120 are in a write mode (program mode or erase mode). And a sense amplifier enable signal SAE2 for receiving the signal RDBASEL2 indicating that bank 2 is selected in a read mode and the signal WTBASEL2 indicating bank 2 being selected in a write mode and enabling the sense amplifier 240. Will occur).

The read mode bank 1 select signal RDBASEL1 and the read mode bank 2 select signal RDBASEL2 are not activated at the same time, and the write mode bank 1 select signal WTBASEL1 and the write mode bank 2 select signal WTBASEL2 are not simultaneously activated. It is not activated at the same time. Even when the bank operation signals BANKBUSY1 and BANKBUSY2 are simultaneously activated, only the write mode bank selection signal corresponding to the bank in which the write mode is performed among the write mode bank selection signals WTBASEL1 and WTBASEL2 is activated.

The sense amplifier 220 senses cell data of a corresponding bank at a rising edge of the sense amplifier enable signal SAE1, and detects the sensed cell data signal DOUT1 at a falling edge. The data output selection circuit 250 of the input / output interface 100 transmits the data. The sense amplifier 240 senses cell data of a corresponding bank at the rising edge of the sense amplifier enable signal SAE2, and detects the sensed cell data signal DOUT2 at the falling edge of the input / output interface 100. The data output selection circuit 250 transmits the data.

The data output selection circuit 250 selectively outputs one of the signals DOUT1 and DOUT2 input from the sense amplifiers 220 and 240 in response to the read mode bank 2 selection signal RDBASEL2. That is, a signal input from the sense amplifier 220 is output when the selection signal RDBASEL2 is at a low level, and a signal input from the sense amplifier 240 when the selection signal RDBASEL2 is at a high level. Outputs

FIG. 5 is a circuit diagram illustrating the control circuit in the first latch and control circuit shown in FIG. 4 in more detail.

Referring to FIG. 5, the control circuit 210 includes four inverters 312, 314, 322, 328, two NAND gates 316, 320, and three NOR gates 318, 324, 326. The inverter 312 receives the read enable signal ADT_READ and outputs the inverted signal, and the inverter 314 receives the bank 1 operation signal BANKBUSY1 and outputs the inverted signal, and the inverter 322 receives the read enable signal ADT_WRITE and outputs the inverted signal.

The NAND gate 316 receives an NAND operation of the read mode bank 1 selection signal and the output of the inverter 314, and the NAND gate 320 performs the bank 1 operation signal BANKBUSY1 and the write mode bank 1. The selection signal WTBASEL1 is received and calculated.

The NOR gate 318 receives the output of the inverter 312 and the NAND gate 316, respectively, and performs a NOR operation, and the NOR gate 324 outputs the NAND gate 320 and the inverter 322. Accept each and perform a NOR operation.

The NOR gate 326 receives NOR outputs of the NOR gates 318 and 324, respectively, and the inverter 328 receives an output of the NOR gate 326, thereby inverting a signal, that is, a sense amplifier. Outputs the enable signal SAE1.

The sense amplifier enable signal SAE1 has the read enable signal ATD_READ and the read mode bank 1 select signal RDBASEL1 at a high level, a bank 1 operation signal BANKBUSY1, and a write mode bank 1 select signal WTBASEL1. ) And the write enable signal ADT_WRITE are activated to a high level when both of them are at a low level. In addition, the read enable signal ADT_READ and the read mode bank 1 select signal RDBASEL1 are at a low level, and the bank 1 operation signal BANKBUSY1, the write mode bank 1 select signal WTBASEL1, and the write enable signal ATD_WRITE ) Are all activated at a high level.

FIG. 6 is a circuit diagram illustrating the control circuit in the second latch and control circuit shown in FIG. 4 in more detail.

Referring to FIG. 6, the control circuit 230 includes four inverters 332, 334, 342, 348, two NAND gates 336, 340, and three NOR gates 338, 344, 346. The inverter 332 receives the read enable signal ADT_READ and outputs an inverted signal. The inverter 334 receives the bank 2 operation signal BANKBUSY2 and outputs the inverted signal. 342 receives the read enable signal ADT_WRITE and outputs the inverted signal.

The NAND gate 336 accepts the read mode bank 2 selection signal and the output of the inverter 334, and the NAND gate 340 performs the bank 2 operation signal BANKBUSY2 and the write mode bank 2. Receives a selection signal WTBASEL2 and performs a NAND operation.

The NOR gate 338 receives the output of the inverter 332 and the NAND gate 336, respectively, and performs a NOR operation, and the NOR gate 344 outputs the NAND gate 340 and the inverter 342. Accept each and perform a NOR operation.

The NOR gate 346 receives the outputs of the NOR gates 338 and 344, respectively, and performs a NOR operation, and the inverter 348 receives the output of the NOR gate 346 and inverts the signal, that is, a sense amplifier. Outputs the enable signal SAE2.

The sense amplifier enable signal SAE2 has the read enable signal ATD_READ and the read mode bank 2 select signal RDBASEL2 at a high level, a bank 2 operation signal BANKBUSY2, and a write mode bank 2 select signal WTBASEL2. ) And the write enable signal ADT_WRITE are activated to a high level when both of them are at a low level. The read enable signal ATD_READ and the read mode bank 2 select signal RDBASEL2 are at a low level, and the bank 2 operation signal BANKBUSY2, the write mode bank 2 select signal WTBASEL2, and the write enable signal ATD_WRITE Are all high level when they are high level.

FIG. 7 is a circuit diagram showing in detail the data output selection circuit shown in FIG. 4.

Referring to FIG. 7, the data output selection circuit 250 includes an inverter 352 and three NAND gates 354, 356, and 358. The inverter 352 receives the read mode bank 2 selection signal RDBASEL2 and outputs an inverted signal. The NAND gate 354 receives a NAND operation of the output signal DOUT1 of the sense amplifier 220 and the output signal of the inverter 352, and the NAND gate 356 receives the read mode bank 2 selection signal ( RDBASEL2 and the output signal DOUT2 of the sense amplifier 240 are received and NAND-operated. The NAND gate 358 receives a NAND operation of the output signals of the NAND gates 354 and 356.

That is, the data output selection circuit outputs a signal input from the sense amplifier 220 when the selection signal RDBASEL2 is at a low level, and outputs the signal from the sense amplifier 220 when the selection signal RDBASEL2 is at a high level. And outputs a signal input from 240.

4 and 8, an operation in the case of reading data from the bank 1 110 in the EEPROM device according to the preferred embodiment of the present invention will be described.

FIG. 8 is a timing diagram when reading data from bank 1 of the EEPROM device shown in FIG. 3. When data is read from the bank 1 110, the read enable signal ATD_READ is activated by address transition or chip enable while the read mode bank 1 select signal RDBASEL1 is activated. The sense amplifier enable signal SAE1 is activated by the signal ADT_READ to drive the sense amplifier 220. The signal DOUT1 output from the sense amplifier 220 is transferred to the data output selection circuit 250. At this time, since the read mode bank 2 select signal RDBASEL2 is at a low level, the output signal DOUT1 is transmitted to the data output buffer 260.

Meanwhile, when reading data from the bank 2 120, the data may be read from the bank 2 120 in the same manner as described above. That is, the read mode bank 2 selection signal RDBASEL2 is activated to activate the read enable signal ATD_READ, and the sense amplifier enable signal SAE2 is activated to drive the sense amplifier 240. The data output selection circuit 250 transfers the output signal from the sense amplifier 240 to the data output buffer 260.

Next, referring to FIGS. 4 and 9, an operation when data is read from the bank 1 110 while a write operation is performed in the bank 2 120 of the EEPROM device according to the preferred embodiment of the present invention will be described. .

FIG. 9 is a timing diagram when data is read from bank 1 while a write operation is performed in bank 2 of the EEPROM device shown in FIG. 3. As the write enable signal ATD_WRITE is activated by the verify start signal while the bank operation signal BANKBUSY2 and the write mode bank select signal WTBASEL2 are activated, the sense amplifier enable signal SAE2 is activated. The sense amplifier 240 is driven. Meanwhile, when the write mode bank 2 select signal WTBASEL2 is activated and the read mode bank 1 select signal RDBASEL1 is activated, the read enable signal ATD_READ is activated and the sense amplifier enable signal SAE1 is activated. do. The sense amplifier 220 senses and amplifies the cell data of the bank 1 110 by the sense amplifier enable signal SAE1. The output signal DOUT1 of the sense amplifier 220 is transmitted to the data output selection circuit 250. At this time, since the read mode bank 2 select signal RDBASEL2 is at a low level, the output signal DOUT1 is transmitted to the data output buffer 260.

On the contrary, when data is read from the bank 2 120 while the write mode is performed in the bank 1 110, the operation is performed in the same manner as described above.

As described above, the EEPROM device according to the preferred embodiment of the present invention includes two banks 110 and 120, each of which consists of a plurality of memory cells, and sense amplifiers 220 and 240 respectively corresponding to the banks. And control circuits 210 and 220 for outputting sense amplifier enable signals for driving the sense amplifiers 220 and 240 so that when one bank is performing write operations, You can read the data.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to encompass all such modifications and similar constructions.

According to the present invention as described above, the read, program and erase operations are separately performed for each bank in the nonvolatile memory device including at least two banks. Therefore, when one bank is performing a write operation, memory cell data can be read from another bank at the same time. As a result, the operation speed of the nonvolatile semiconductor memory device is improved.

Claims (5)

A first bank 110 and a second bank 120 each including a plurality of memory cells; A first sense amplifier (220) and a second sense amplifier (240) for sensing and amplifying data of the first bank (110) and the second bank (120), respectively, in response to control signals (SAE1, SAE2); The control signals SAE1 and SAE2 for controlling whether the first sense amplifier 220 and the second sense amplifier 240 are activated in response to the read enable signal ADT_READ and the write enable signal ATD_WRITE. A control circuit for outputting; And And an output selection circuit 250 for selectively outputting data from the sense amplifier corresponding to the read enable signal ADT_READ among the first sense amplifier and the first sense amplifiers. Memory device. The method of claim 1, The control circuit, A first control circuit (210) for outputting the control signal for driving the first sense amplifier in response to the read enable signal and the write enable signal corresponding to the first bank; And a second control circuit 230 for outputting the control signal for driving the second sense amplifier in response to the read enable signal and the write enable signal corresponding to the second bank. Nonvolatile Semiconductor Memory Device. The method of claim 1, The first and second control circuits 210 and 230, A first detection circuit detecting whether the read enable signal ADT_READ is activated; A second detection circuit for detecting whether the write enable signal ADT_WRITE is activated; And a logic circuit for outputting the control signal when at least one detection signal is input from the first and second detection circuits. The method of claim 1, And the read enable signal (ATD_READ) and the write enable signal (ATD_WRTIE) are signals detected from an instruction and the bank address. The method of claim 4, wherein And the write enable signal (ATD_WRITE) is activated when the command instructs writing and erasing.

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