KR19990013057A - Read and write method of flash memory device for selectively storing single bit data and multiple bit data on same chip - Google Patents

Abstract

A flash memory device according to the present invention comprises: a cell array having a plurality of array blocks having first strings of electrically erasable and programmable memory cells capable of selectively storing multi-bit data and single-bit data; A reference cell array configured to store data information for determining which of the single bit data and the multi-bit data are stored, wherein a second string of reference memory cells is arranged to correspond to each of the array blocks; Wherein the program method comprises simultaneously reading data of a memory cell addressed by an address signal and information bits of a reference memory cell of the reference cell array; Determining whether data of the reference memory cell is information related to single bit data or information related to multi-bit data; Performing a series of read operations for reading a next state when the determined result is information related to multi-bit data; And outputting the read data when the determined result is information related to the single bit data.

Description

Data reading and writing method of flash memory device selectively storging single bit data and multi bit data on chip

The present invention relates to a flash memory device, and more particularly, to a method of reading and writing a flash memory device for selectively storing single-bit data and multi-bit data in accordance with the accuracy of the data required for the same chip.

1 is a cross-sectional view showing the structure of a flash memory cell. As shown in Fig. 1, a flash memory cell has a source 3 and a drain 4 formed of N + impurities with a channel region interposed therebetween on a surface of a P-type semiconductor substrate 2, and 100 kHz on the channel region. A floating gate 6 formed with the following thin insulating film 7 interposed therebetween, and an insulating film (for example, an ONO film) 9 on the floating gate 6. In addition, a control gate 8 is formed. Power terminals Vs are applied to the source 3, the drain 4, the control gate 8, and the semiconductor substrate 2 to apply voltages required for program, erase, and read operations, respectively. ), (Vd), (Vg), and (Vb) are connected.

According to a conventional flash memory program operation, a flash memory cell is programmed by causing hot electron injection to the floating gate 8 in the channel region adjacent to the drain region 4. The electron injection grounds the source region 3 and the P-type semiconductor substrate 2, applies a high high voltage (eg, + 10V) to the control gate electrode Vg, and then drains the drain region. This is achieved by applying a suitable amount of voltage (for example, 5V to 6V) to generate hot electrons in (4). When a flash memory cell is programmed according to this voltage application condition, that is, a negative charge is sufficiently accumulated in the floating gate 6, (-) accumulated (or trapped) in the floating gate 6 The charge increases the threshold voltage of the programmed flash memory cell during a series of read operations.

Typically, the voltage application condition of the read operation applies a positive voltage (e.g., 1V) to the drain region 4 of the flash memory cell, and applies a predetermined voltage (e.g., to its control gate 8) Power supply voltage, or about 4.5V), and 0V to its source region 3. When a read operation is performed in accordance with the above conditions, its threshold voltage is increased by the hot electron injection method described above, that is, the programmed flash memory cell is moved from its drain region 4 to its source region 3. Injection of current is prevented. At this point, the programmed flash memory cell is said to be off, and its threshold voltage typically has a distribution between about 6V and 7V.

Subsequently, according to the erase operation of the flash memory cell, the memory cell is erased by generating F-N tunneling (Fowler-Nordheim tunneling) to the control gate 8 in the semiconductor substrate 2, that is, the bulk region. In general, the FN tunneling applies a negative high voltage (e.g., -10V) to the control gate 8 and generates FN tunneling between the bulk region 2 and the control gate 8. By applying an appropriate amount of voltage (eg 5V). At this time, its drain region 4 is maintained in a high impedance state (e.g., a floating state) in order to maximize the effect of the erase. When voltages corresponding to such an erasing condition are applied to corresponding power terminals Vg, Vd, Vs, and Vb, a strong electric field is formed between the control gate 8 and the bulk region 2. do. This results in the F-N tunneling described above, as a result of which negative charge in the floating gate 6 of the programmed cell is released into its source region 3.

Typically, the F-N tunneling occurs when an electric field of 6-7 MV / cm is formed between the insulating film 7. This is possible because the thin insulating film 7 of 100 kPa or less is formed between the floating gate 6 and the bulk region 2. The discharge (or discharge) of the negative charge from the floating gate 6 to the bulk region 2 by the erase method according to the FN tunneling means that the erase of the erased flash memory cell is performed during a series of read operations. It serves to lower the solder voltage.

In a general flash memory cell array configuration, each bulk area is connected to a plurality of cells together for high integration of the memory device, so that when the erase operation is performed according to the above-described erase method, the plurality of memory cells are simultaneously erased. . The erasing unit is determined according to the area in which each bulk area 2 is separated. {For example, 64K byte: hereinafter referred to as a sector.} During a series of read operations, a flash memory cell whose threshold voltage is lowered by the erase operation is applied with a constant voltage to the control gate 8. In this case, a current path is formed from the drain region 4 to the source region 3. Such a flash memory cell is said to be on and its threshold voltage has a distribution between about 1V and 3V. Table 1 shows the voltage levels applied to the respective power supply terminals Vg, Vd, Vs, and Vb during the program, erase, and read operations of the flash memory cell.

TABLE 1

Operation mode Vg Vd Vs Vb program + 10V + 5V to + 6V 0 V 0 V Cattle -10V Floating Floating + 5V Reading + 4.5V + 1V 0 V 0 V

Single bit data is stored in the manner described above in electrically erasable and programmable flash memory cells. In addition, multi bit data is programmed by iteratively performing the same method as the programming method of the single bit data described above, as is well known to those skilled in the art. At this time, the distribution of its threshold voltages representing the state of the multi-bit data is distributed more narrowly than that of the single-bit data. Therefore, it may be important to program a multi-bit data and a technique for maintaining it.

In general, semiconductor memory devices are classified into NAND and NOR types, particularly in the case of electrically erasable and programmable nonvolatile semiconductor memory devices. In the NAND flash memory device, memory cells of a cell array are arranged in series with respect to a bit line, and in the NOR flash memory device, memory cells of a cell array are arranged in parallel with respect to a bit line. The NAND flash memory device has excellent characteristics in terms of integration degree, and the NOR flash memory device is a device having excellent characteristics of random access time.

Since the NAND flash memory device is excellent in terms of integration, it is commonly used as a large-capacity medium such as a hard disk or a film replacement for a digital camera. If it is realized as a flash memory cell of multi-bit data that can store a plurality of data in one cell, it can have several advantages in production cost. However, when implementing a flash memory device for storing multi-bit data, it is necessary to store a plurality of data states in a single cell, and thus requires technical skills for maintaining each state data such as reliability problems. Similarly, when data accuracy is required, problems arise that make it difficult to use.

Accordingly, an object of the present invention is to provide a method of reading and writing an electrically erasable and programmable flash memory device that can use a single bit data and multiple bit data in the same chip.

1 is a cross-sectional view showing the structure of an electrically erasable and programmable flash memory cell;

2 is a block diagram showing the configuration of a flash memory device according to a preferred embodiment of the present invention;

FIG. 3A shows the distribution of the threshold voltages of a memory cell and a reference cell during multi-bit data programming; FIG.

3B shows the distribution of the threshold voltages of a memory cell and a reference cell during single bit data programming;

4A illustrates a distribution of threshold voltages of a memory cell and a reference cell during a multi-bit data read operation;

4B is a view illustrating distribution of the threshold voltages of a memory cell and a reference cell during a single bit data read operation;

* Explanation of symbols on the main parts of the drawings

100: memory cell array 120: reference cell array

140: row decoder circuit 160: page buffer

According to one aspect of the present invention for achieving the above object, there is provided a plurality of array blocks having first strings of electrically erasable and programmable memory cells capable of selectively storing multi-bit data and single-bit data. One cell array; A reference cell array configured to store data information for determining which of the single bit data and the multi-bit data are stored, wherein a second string of reference memory cells is arranged to correspond to each of the array blocks; A data reading method of a nonvolatile semiconductor memory device, comprising: simultaneously reading data of a memory cell addressed by an address signal and information bits of a reference memory cell of the reference cell array; Determining whether data of the reference memory cell is information related to single bit data or information related to multi-bit data; Performing a series of read operations for reading a next state when the determined result is information related to multi-bit data; And outputting the read data when the determined result is information related to the single bit data.

In this embodiment, the information of the single bit data stored in the reference memory cell is single bit data of state '1', and the information of the multi bit data stored in the reference memory cell is single bit data of state '0'. It features.

According to another aspect of the invention, there is provided a cell array comprising: a cell array having a plurality of array blocks having first strings of electrically erasable and programmable memory cells capable of selectively storing multi-bit data and single-bit data; A reference cell array configured to store data information for determining which of the single bit data and the multi-bit data are stored, wherein a second string of reference memory cells is arranged to correspond to each of the array blocks; A data writing method of a nonvolatile semiconductor memory device, comprising: receiving a command for notifying information of single-bit data or multi-bit data; Reading information bits stored in a reference memory cell of the second string corresponding to the selected block to determine which area of the single bit data and the multi bit data is selected by the address of the array blocks; Determining whether the read information bits match the command; Generating a fail flag signal to increase the address if the determination result does not match; Performing a program operation corresponding to the increased address; And performing a program operation according to data to be written corresponding to the command when the result of the determining step is identical.

In this embodiment, the information of the single bit data stored in the reference memory cell is single bit data of state '1', and the information of the multi bit data stored in the reference memory cell is single bit data of state '0'. It features.

By this method, single-bit data and multi-bit data can be mixed and stored or read in the memory area of the same chip.

Reference drawings according to embodiments of the present invention will be described in detail with reference to FIGS. 2 to 4.

2 is a block diagram showing a schematic configuration of a flash memory device according to the present invention. 3A and 3B are diagrams showing the distribution of the threshold voltages of memory cells required for storing multi-bit data and single-bit data. 4A and 4B are diagrams showing distributions of threshold voltages of memory cells required when erasing multi-bit data and single-bit data.

Referring to FIG. 2, a flash memory device includes a memory cell array 100, a reference cell array 120, a row decoder circuit 140, and a page buffer. page buffer) (160). The array 100 is composed of a plurality of array blocks (Block_n, n is an integer greater than or equal to 1) separated in a row direction. Each of the array blocks Block_n consists of 16 rows, that is, 16 word lines, in the preferred embodiment of the present invention. Here, each row constitutes one page. The array 100 is provided with bit lines in a column direction to intersect word lines arranged in each of the array blocks Block_n, and each of the bit lines is connected to the page buffer 160.

Each of the array blocks Block_n includes a plurality of strings (string_m, m is an integer greater than or equal to 1), and each of the strings string_m includes 16 flash memory cells M1 in an embodiment of the present invention. ), (M16), a string selection transistor (referred to as SST), and a ground selection transistor (referred to as GST). The drain of the string select transistor SST of each of the strings string_m is connected to a corresponding bit line, the source of the ground select transistor GST is grounded, and the memory cells M1 to M16 are The select transistors SST and GST are connected in series. The memory cells M1-M16 are, as is well known, electrically erasable and programmable transistors having a floating gate and a control gate.

The reference cell array 120 includes the same cells as the string of the array 100 and includes one reference string corresponding to each of the array blocks Block_n. Each reference string is for storing information of whether the data stored in the cells of the array blocks Block_n is single bit data or multi bit data, and the information about them is stored as single bit data. The row decoder circuit 140 selects one of the array blocks Block_n and drives one of the rows of the selected array block to a voltage required for a write / read operation. The page buffer 160 senses and stores data stored in the memory cell array 100 during a read operation, and drives data from the outside into the cells of the memory cell array 100 during a write operation.

The write and read operations of the present invention will now be described with reference to FIGS. 3 and 4. First, a case in which specific data is written to, or programmed in, a selected cell of the memory cell array 100 by an external controller will be described. A code that is reliable in writing a multi-bit data for mass storage data by a command externally applied to a memory cell in the same erased memory cell array 100 and a reference cell in the reference cell array 120. The use of whether to write a single bit of data for storage data is distinguished. Then, one of the pages in the array block addressed by the address signal applied successively is selected. Here, it is well known to those who have acquired general knowledge in this field that program units of a general nonvolatile semiconductor memory device are performed in units of pages.

Subsequently, when a program operation is performed on data continuously applied to the cells of the selected page of the memory cell array 100, whether the reference cell in the reference cell array 120 is single bit data or multi bit data. Will be programmed. If the data to be written is multi-bit data, a number of states are programmed into the cells of the selected page according to programming techniques well known to those skilled in the art. In the same process, information for discriminating whether a multi-bit data write operation or a single-bit data write operation is programmed into the selected reference cell in the reference cell array 120 is also programmed.

Here, the characteristic is that the information in the reference cell array 120, i.e., whether it is multi-bit data or single-bit data is stored as single-bit data so that the program operation only up to a designated state ('01' state in the embodiment). Proceeds and stops the program operation on it when the program is completed. Subsequently, only the cells in the memory cell array 100 undergo a program operation in the next state. If the program is executed in another page in the existing array block, the information stored in the reference cell in the selected array block is read out prior to the program operation so that the data in the array block is multi-bit data identical to the input command or single-bit data. It is determined whether or not to notify the write operation. At this time, if the determined result is identical, the program operation is continued. If the determined result and the command do not match, the fail flag data is output to the controller and the address is changed and the data is written. Proceed with the process.

The following describes the reading process based on FIGS. 4A and 4B. Cell data in the memory cell array 100 and cell data in the reference cell array 120 are simultaneously read by a first read reference, as shown in FIG. 4A. In this case, according to the read result of the reference cell data, whether the cell data in the memory cell array 100 is single bit data (in the embodiment, the reference cell data is in a '1' state) or multi-bit data (in the embodiment, the reference cell). Data is '0' state).

Accordingly, as the read standard in the memory cell array 100 is turned on / off only in the case of multi-bit data, as shown in FIG. 4B, the two read state data are detected by changing to the second read standard. I can do it. That is, multi-bit data sensing with states according to four threshold voltages is enabled. If the cell data in the reference cell array 120 is a '1' state indicating that the bit data is single bit data, since the cell read operation in the memory cell array has already been terminated, the read operation may be effectively reduced by stopping the read operation. have.

As described above, the reliability of various data can be improved by automatically distinguishing the operation of the multi-bit data and the single-bit data by reference cell data in one-chip, and enabling the operation to be used in the same cell in one chip. It can increase.

Claims (4)

A cell array having a plurality of array blocks having first strings of electrically erasable and programmable memory cells capable of selectively storing multi-bit data and single-bit data; A reference cell array configured to store data information for determining which of the single bit data and the multi-bit data are stored, wherein a second string of reference memory cells is arranged to correspond to each of the array blocks; A data reading method of a nonvolatile semiconductor memory device, comprising: Simultaneously reading data of a memory cell addressed by an address signal and information bits of a reference memory cell of the reference cell array; Determining whether data of the reference memory cell is information related to single bit data or information related to multi-bit data; Performing a series of read operations for reading a next state when the determined result is information related to multi-bit data; And outputting the read data when the determined result is information related to the single bit data. The method of claim 1, Non-volatile memory, characterized in that the information of the single bit data stored in the reference memory cell is a single bit data of the state '1', the information of the multi-bit data stored in the reference memory cell is a single bit data of the state '0' How to output data from the device. A cell array having a plurality of array blocks having first strings of electrically erasable and programmable memory cells capable of selectively storing multi-bit data and single-bit data; A reference cell array configured to store data information for determining which of the single bit data and the multi-bit data are stored, wherein a second string of reference memory cells is arranged to correspond to each of the array blocks; A data writing method of a nonvolatile semiconductor memory device, comprising: Receiving a command for notifying information of single-bit data or multi-bit data; Reading information bits stored in a reference memory cell of the second string corresponding to the selected block to determine which area of the single bit data and the multi bit data is selected by the address of the array blocks; Determining whether the read information bits match the command; Generating a fail flag signal to increase the address if the determination result does not match; Performing a program operation corresponding to the increased address; And performing a program operation according to data to be written corresponding to the command when the result of the determining step is identical. The method of claim 3, wherein Non-volatile memory, characterized in that the information of the single bit data stored in the reference memory cell is a single bit data of the state '1', the information of the multi-bit data stored in the reference memory cell is a single bit data of the state '0' How to write data on the device.