JPH11242899A - Semiconductor storage circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten test time and also to enhance the productivity by making items of an error-correcting code generating logic odd numbered terms and changing the address arrangement of a bit map to enable check data to be written in a user area and a correcting area simultaneously. SOLUTION: In a semiconductor memory circuit having the error correcting circuit of storage data, a logic generating a 6-bit error-correcting code is composed of 15 terms of D00 to D31. The address arrangement of a bit map is made an address arrangement capable of writing check data for bit interference of test data in a user area and an ECC area simultaneously by making it a prescribed bit map address continuation while making values of outputs 00 to 05 high levels all or low levels. Thus, a write time at the time of checking bit interferences of ROM cells and a test time are shortened and also even when the defective bit of one bit is present in the 6 bits of the ECC, the ROM is not erroneously judged as a defective product and the yield is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit having an error correction circuit for correcting data errors in a semiconductor memory circuit.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing an example of a conventional ECC (error correction code) code generation logic circuit.

Conventionally, to perform 1-bit correction of 32-bit data, a 6-bit ECC (error correction) code is required. In order to make the number of ECC code generation stages uniform, the generation logic of each bit consists of 14 terms. It is composed of a generation logic circuit.

FIG. 5 is a block diagram showing the DCCs of the ECC code generation logic circuit of FIG. 4 (addresses N, N + 1, N + 2, N +
3 (N is an integer) from O0 to O5.

FIG. 6 shows a user data area of 16 addresses per word line (hereinafter referred to as "user area") and an ECC code data area of 4 addresses (hereinafter referred to as "ECC area").
And 4 word lines (word lines 1-4)
And the bit interference check data of the ROM cell (bit pattern example 1 in FIG. 5)
And writing of bit pattern example 2) in user area and ECC
FIG. 9 shows a data array when the data array is simultaneously performed on the region.

The bit pattern example 1 shown in FIG. 5 is applied to the word lines 2 and 4 shown in FIG.
In the case of the bit data inputs D00 to D31 and the bit pattern example 2, the 32-bit data inputs D00 to D31 at the time of writing the checker data to the word lines 1 and 3 in FIG.
, Respectively.

The address arrangement of each bit in the user area in FIG. 6 is usually serially arranged as 0, 1, 2, 3,..., D, e, f, and the address arrangement of each bit in the ECC area is 0. , 4, 8, and c are arranged at every fourth address.

In the conventional example, ECC codes of O0 to O5 of the bit pattern example 1 and the bit pattern example 2 of FIG. 5 are generated, and have a bit map configuration as shown in FIG.
When writing the checker data at the time of checking the bit interference of a ROM (read only memory) cell and simultaneously writing into the user area and the ECC area, a data array as shown in FIG. 6 is obtained. The checker data cannot be written to the area at the same time, and the test is executed by writing the checker data separately.

[0009]

The above-described prior art has the following problems.

The first problem is that in the bit interference check of the ROM cell, it is necessary to perform the writing process separately for the user area and the ECC area, which requires a long test time and leads to an increase in the cost for the inspection. It is.

The reason is that the ECC code generation logic is
Since the check is performed using even-numbered terms, there is no combination in which ECC codes are all High or all Low when writing checker data as a bit interference check. Further, due to the bit map configuration as shown in FIG. 6, there is a problem that checker data cannot be simultaneously written in the user area and the ECC area.

A second problem is that a semiconductor memory circuit with an error correction circuit in which 32 bits of data are normal and 6 bits of ECC have an interference failure of 1 bit can be regarded as a non-defective product due to the configuration of ECC. Inspection of a conventional semiconductor memory circuit with an error correction circuit, in which 32 bits are normal and ECC 6 bits have 1-bit interference failure, is determined to be defective and causes a reduction in yield. .

The reason is that the ECC function can correct a defect of 1 bit out of 38 bits of 32 bits of data and 6 bits of ECC, and if there is a defective bit of 1 bit out of 32 bits of data and 6 bits of ECC is normal. This is because the configuration is such that, even if a defective bit of data is corrected, even if 32 bits of data are normal and one bit out of 6 ECC bits is present, normal data is not affected. That is, in the inspection by the ECC function, even if there is a defective bit of up to 1 out of 38 bits including the data of 32 bits and the ECC of 6 bits, it can be regarded as a good product.

However, when inspecting a conventional semiconductor memory circuit with an error correction circuit, checker data for checking bit interference cannot be simultaneously written in both the data cell and the ECC cell, and the check for interference failure of the ECC cell is not possible. In order to perform the inspection, checker data is directly written only in the ECC cell, and then read and inspected. Originally, when 32 bits of data are normal and there is a defect of 1 bit out of 6 bits of ECC, it can be regarded as a defective product due to the above-described inspection method, though the ECC function can be regarded as a good product. I was

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and has as its object to perform an interference test between a user cell and an error correction code cell of a semiconductor storage circuit having a built-in error correction function for stored data. In this case, it is an object of the present invention to provide a semiconductor memory circuit which prevents an increase in test time and a decrease in yield due to two or more write operations, and improves reliability and productivity.

[0016]

In order to achieve the above object, the present invention provides a semiconductor memory device having an error correction circuit for correcting an error in stored data.
The error correction code generation logic is set to an odd term, and the address arrangement is such that the bit interference checker data, which is test data, is simultaneously written in the user area and the error correction code area.

[0017]

Embodiments of the present invention will be described below. According to a preferred embodiment of the present invention, in a semiconductor storage circuit having an error correction circuit for correcting an error in stored data in a preferred embodiment, an error correction code generation logic is an odd term, and a user area and an error correction code area of the semiconductor storage circuit are In this case, the test data is written at the same time, but the error correction code generation logic has 15 items for performing 1-bit correction of 32-bit data. And
In the embodiment of the present invention, the address arrangement is such that the bit interference checker data as test data is simultaneously written in the user area and the error correction code area of the semiconductor memory circuit.

According to the embodiment of the present invention, the number of terms of the ECC code generation logic at the time of the ROM cell bit interference check is changed from the conventional even-numbered term 14 to the odd-numbered term 15 and the address of the bit map is changed. By changing the arrangement, the checker data can be simultaneously written in the user area and the ECC area, and the test time is reduced. For example, if a write time of 10 μs is required for one address, the capacity of 5
The writing time of one area at the time of 12 Kbytes is 5.
Although 12 seconds are required, in the present invention, 2.56 seconds, which is a half, is sufficient.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an EC code generation logic circuit according to one embodiment of the present invention. Referring to FIG. 1, in one embodiment of the present invention, logic for generating a 6-bit ECC code is configured by 15 terms.

FIG. 2 shows the DCCs D00-D31, O0-O of the ECC code generation logic circuit of one embodiment of the present invention shown in FIG.
5 shows a bit pattern example 1 and a bit pattern example 2 for No. 5;

FIG. 3 shows an address arrangement of a bit map according to an embodiment of the present invention, and data when the checker data is simultaneously written into the user area and the ECC area according to FIG.

As shown in FIG. 2, in the example 1 of the bit pattern, the values of the outputs O0 to O5 are all at the high level, and in the example 2 of the bit pattern, the values of the outputs O0 to O5 are all at the low level. In these two cases, a bitmap address configuration (0, 4, 1, 5, 2, 2, etc.) as shown in FIG.
, B, f), the checker data is simultaneously written into the user area and the ECC area.

[0023]

As described above, according to the present invention,
The number of terms of the ECC code generation logic at the time of checking the bit interference of the ROM cell is changed from the conventional even number of 14 items to the odd number of 15 items, and by changing the address arrangement of the bit map, the user area and the ECC area are changed. At the same time, checker data can be written at the same time, which is effective in reducing the test time.

Further, according to the present invention, simultaneous writing eliminates an erroneous determination of determining a defective product even when one defective bit out of six ECC bits is present.

As an effect of the present invention, for example, when a write time of 10 μs per address is required, a capacity of 512 K
In the conventional example, the writing time for one area at the time of byte is required to be 5.12 seconds, but in the present invention, it can be reduced to 2.56 seconds which is a half.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an ECC generation circuit logic according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of generating a correction code according to an embodiment of the present invention.

FIG. 3 is a diagram schematically showing a bit cell arrangement in one embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a conventional ECC generation circuit logic.

FIG. 5 is a diagram showing an example of a conventional correction code generation.

FIG. 6 is a diagram schematically showing a conventional bit cell arrangement.

Claims (4)

[Claims] In a semiconductor memory circuit having an error correction circuit for correcting an error in stored data, an error correction code generation logic is set to an odd term, and test data is written to a user area and an error correction code area of the semiconductor memory circuit. A semiconductor memory circuit characterized by being configured to be embedded therein. 2. The semiconductor memory circuit according to claim 1, wherein said error correction code generation logic is 15 for performing 1-bit correction of 32-bit data. 3. The semiconductor memory circuit according to claim 1, wherein an address arrangement for simultaneously writing bit interference checker data as test data in a user area and an error correction code area of said semiconductor memory circuit is provided. . 4. An address arrangement comprising an error correction code generation logic circuit for generating an error correction code in an odd number term, wherein check data for bit interference check can be simultaneously written in a user cell area and an error correction code cell. A semiconductor memory circuit characterized by the above-mentioned.