JPH11282763A - Device and method for storage device monitoring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and method for storage device monitoring which performs monitoring of an address bus with a simple structure and low expenses. SOLUTION: A vertical parity operation is performed in a parity operation circuit 40 with data 37 and an address 32 as objects at the time of data writing, the result of vertical parity operation of this 'address + data' is added to writing data 37 as a parity bit 39 and written in a single port memory. 30. At the time of reading the data, the parity bit 39, which is read at the same time as the data 37 read from the single port memory 30, and the vertical parity operation result of a read memory address as the address 32 given to the single port memory 30 held in an address holding circuit 36 and read-out data 37 are compared at a parity comparison circuit 42, and address bus monitoring is performed by notifying it as a monitoring result 41.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device monitoring method and method for monitoring a memory access abnormality.
More specifically, the present invention relates to a storage device monitoring device and method for monitoring an address bus.

[0002]

2. Description of the Related Art Conventionally, in an information processing system, a control device such as a central processing unit performs a predetermined process according to information stored in a storage device to realize a desired function. However, if the storage information at an address read from the storage device is different from the write information at the time of writing to that address, an error occurs in the processing result by the control device, and other memory data is destroyed. Will be lacking. Therefore, in order to ensure the reliability of the storage information stored in such a storage device,
Parity and error correction code (Error Corr
ecting Code (ECC) is generated and added. Thus, it is possible to efficiently remove a soft error in a DRAM (Dynamic Random Access Memory), which is a main component of the storage device, and a noise on a data signal line directly connected to the DRAM.

When writing data to a storage device as described above, a write enable signal (or a write control signal), a storage device address for specifying a data write destination, and data to be written are given to the storage device. . When data is read from a storage device, read data can be obtained by giving a read enable signal (or a read control signal) and a storage device address for specifying a data read destination to the storage device. it can.

When the storage device is a single-port memory, a pair of an address bus for specifying a memory address and a pair of data buses for reading or writing data are provided. In order to ensure the reliability of such a storage device, it has been performed to generate a parity and add the parity to write data. That is, at the time of writing to the single port memory, the result is set as a parity bit by a vertical parity operation of the write data and added to the write data. Therefore, assuming that one parity bit is calculated for an A-bit data bus, (A + 1) -bit data is written to a single-port memory. When reading from the single-port memory, one parity bit included in the (A + 1) -bit read data and the read A bit are read.
By comparing the bit parity data with the result of the vertical parity calculation, it is possible to monitor whether or not the memory access is normal.

[0005] The storage device accesses a storage location specified by a write address or a read address. However, if one of the write address or the read address is disconnected, for example, the disconnection of the address bus cannot be detected when the data bus itself is normal due to the parity bit as described above. There is.

To cope with such a problem, there has been proposed a storage device monitoring device which monitors an address bus.

FIG. 6 schematically shows the outline of the configuration of such a conventionally proposed storage device monitoring apparatus. The storage device monitoring device 10 includes a parity generation / inspection circuit 12 for generating and checking a parity of an address bus 11, a check bit generation / inspection circuit 14 for generating and checking a check bit of a data bus 13, and a parity generation / checking circuit 14. A checker circuit 12 and a memory unit 15 for storing parity and write data of the address bus generated by the checker circuit 14 and the check bits thereof; The memory unit 15 generates a parity for each entry specified by the address bus 11.
A parity storage unit 16 for storing the parity of the address bus generated by the check circuit 12, and a data / check bit storage unit 17 for storing write data and check bits for the write data generated by the check bit generation / check circuit 14. And

The parity generating / checking circuit 12 generates a parity of the address bus 11 at the time of writing data and outputs it to the parity storage section 16 as a memory address parity 18. On the other hand, when reading data, the address bus 11
The parity of the above read address bus is compared with the memory address parity 18 read out simultaneously with the read data from the parity storage unit 16 and a comparison result 19 is output to the outside. The check bit generation / inspection circuit 14 generates a check bit of the data bus 13 at the time of data writing, and outputs it as access data 20 to the data check bit storage unit 15 together with the write data. on the other hand,
At the time of data reading, the presence / absence of a bit error is detected based on the check bit of the read access data 20 and the read data, and the detection result 21 is output to the outside. At this time, if the error is correctable, the data is corrected by the check bit, and the corrected data is output to the data bus 13.

As described above, the storage device monitoring device shown in FIG. 6 stores the memory address parity in each entry constituting the memory. At the time of data writing, parity data is created for an address supplied from the outside, and a check bit generation / inspection circuit generates a check bit for the data, and writes this together with the data to the memory. When reading data, the presence or absence of a parity error is detected based on an address supplied from the outside and an address parity obtained from a memory, and the data is checked using a check bit. Also, a check bit can be generated for the address bus so that an error can be corrected.

A technique relating to such a storage device monitoring device is disclosed, for example, in Japanese Patent Application Laid-Open No. 7-105102, entitled "Memory Control Device".

In addition, Japanese Unexamined Patent Publication No. Hei 3-186954 discloses an "address error detection method". In a memory write, a check bit is generated from address parity bits and data generated for each address to be time-divisionally written to a memory, and the check bit is generated together with the data. A technique of detecting an address error due to a failure after the address switching circuit for time division at the time of memory writing by writing is disclosed.

[0012]

In such a conventional storage device monitoring apparatus, when a parity is generated only for data at the time of memory access, even if one of the address buses is disconnected, the data bus is monitored. However, there is a problem in that the monitoring result cannot detect an address bus abnormality as a political situation because of normal operation.

In the technology related to the storage device monitoring device disclosed in Japanese Patent Application Laid-Open No. 7-105102 and Japanese Patent Application Laid-Open No. 3-186954, the reliability around the storage device is improved by generating a check bit. However, it is difficult to apply to an application field that hinders the complexity of the device due to the delay time due to the check bit generation circuit and the addition of the generation circuit. That is, in recent information processing systems, central processing units and memory elements have become extremely fast due to improvements in integrated circuit technology and the like. Against this background, the functions required by the user have become more sophisticated, and a higher-speed central processing unit and memory device have been required. Therefore, in an application field in which high speed and miniaturization of the device are more important than improvement in reliability, a technology for improving the reliability around the storage device with a configuration as simple as possible is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a storage device monitoring apparatus and method for monitoring an address bus with a simple configuration at low cost.

[0015]

According to the first aspect of the present invention, (a) a data storage location, an address bus for transmitting address information for specifying the storage location, and a storage location specified by the address information (B) a storage means having a data bus for transmitting write data at the time of writing or read data at the time of reading, and (b) storing a write address on the address bus and a write address on the data bus. Write data parity calculation means for performing parity calculation of each bit data; and (c) read data parity calculation means for performing parity calculation of each bit data of a read address on an address bus and a read data on a data bus at the time of data reading. , (D) calculation results by the write data parity calculation means It is provided with a monitoring means for monitoring the storage means based on the calculation result of the read data parity computing means in the storage device monitoring device.

That is, according to the first aspect of the present invention, when data is written to the storage means having the address bus and the data bus, each bit data on the address bus and the data bus is subjected to a parity operation. When data is read from the storage means, a parity operation is performed based on the read data and the read address, and monitoring of the storage means is performed based on the parity bits of each bit data of the address bus and the data bus at the time of writing and reading. I'm trying to do it.

According to the second aspect of the present invention, (a) a data storage location, an address bus for transmitting address information specifying the storage location, and a write time corresponding to the storage location specified by the address information Storage means having a data bus for transmitting write data or read data at the time of reading; (b) parity calculating means for performing a vertical parity calculation of each bit data on the address bus and the data bus; At the time of a write operation to the storage means, a data write which writes the write data on the data bus and the result of the vertical parity operation calculated by the parity operator to the storage location of the storage means specified by the write address information on the address bus. And (d) an address buffer during a read operation from the storage means. Data reading means for reading the read data read from the storage location of the storage means specified by the above read address information, and the vertical parity calculation result by the parity calculation means written at the same time when the read data is written. (E) the vertical parity calculation result read by the data reading means, the address information at the time of the read operation from the storage means calculated by the parity calculation means, and the read data read by the data reading means. And a monitoring means for monitoring the storage means based on the vertical parity calculation result.

That is, in the second aspect of the present invention, the vertical parity of each bit data on the address bus and the data bus accessed by the storage means having the address bus and the data bus is calculated. During a write operation to the storage means, the result of the vertical parity operation is stored as a parity bit together with the data on the data bus at the storage location of the storage means specified by the address data on the address bus. In a read operation from the storage means, the storage data is read from the storage location of the storage means specified by the address data on the address bus, and the stored parity bits are read at the same time. The storage means is monitored based on the parity bit and the result of the vertical parity operation between the address data and the read data at the time of reading.

According to a third aspect of the present invention, in the storage device monitoring apparatus according to the first aspect, the data write data parity calculation means and the read data parity calculation means each calculate a parity in a predetermined bit length unit, and Is characterized in that the storage means is monitored based on the parity calculation results by the data write data parity calculation means and the read data parity calculation means in bit length units.

That is, according to the third aspect of the present invention, the parity bits of each bit data on the address bus and the data bus at the time of reading and at the time of writing are compared in units of a predetermined bit length.

According to a fourth aspect of the present invention, in the storage device monitoring device according to the first to third aspects, the storage means is a single port memory.

In other words, according to the fourth aspect of the present invention, since the single port memory has only one pair of the address bus and the data bus, all accesses to the single port memory can be monitored.

According to the fifth aspect of the present invention, (a) a data storage location, an address bus for transmitting address information specifying the storage location, and a write time corresponding to the storage location specified by the address information Vertical parity operation for calculating a vertical parity between a first address of a storage means having a data bus for transmitting write data or read data at the time of reading, and predetermined data to be written to the first address Steps and
(B) a first writing step of writing the vertical parity calculation result calculated in the first vertical parity calculation step and predetermined data to a first address of the storage means;
(C) a second vertical parity calculation step of calculating a vertical parity between a second address obtained by inverting one bit of the first address and predetermined data to be written to the second address; The second address of the means to the second
A second writing step of writing the vertical parity calculation result calculated in the vertical parity calculation step and predetermined data, and (e) a reading step of reading storage information and a parity bit of a first address of the storage means;
(F) a comparison step of comparing the parity bit read in this read step with a vertical parity operation result of the storage information and the read address read in the read step; (g) a read step in this comparison step If the parity bit read out in step 1 does not match the result of the vertical parity operation between the storage information read out in the reading step and the read address, one bit of the first address inverted in the second writing step And a notification step of notifying the storage device as abnormal.

That is, according to the fifth aspect of the present invention, the vertical parity between the first address of the storage means having the address bus and the data bus and the predetermined data to be written to the first address is calculated. This predetermined data and the result of the vertical parity operation are written to the address 1. Next, using an address obtained by inverting only one bit of the first address as a second address, a vertical parity is calculated by using the same predetermined data used in the first writing step and the second address, and stored. The predetermined data and the result of the vertical parity operation are written to the second address of the means. Then, the storage data at the first address is read, and at the same time, the written vertical parity bits are read. The read vertical parity bit is compared with the vertical parity calculation result between the read address and the read data. If the vertical parity bit does not match, the inverted one bit of the first address is regarded as abnormal as the second address. Notice.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows an outline of a configuration of a storage device monitoring apparatus according to an embodiment of the present invention. This storage device monitoring device monitors a single port memory 30 in which an address bus for designating a storage location of storage information and a data bus which is a transmission path of the storage information are paired, and monitors access to the single port memory 30. Memory control unit 3 to perform
1 is provided. The memory control unit 31 specifies a memory control signal generation circuit 33 that outputs a memory control signal 32 for performing write control or read control on the single-port memory 30 and a storage location of storage information of the single-port memory 30. An address generation circuit 35 that outputs the address 34 and an address holding circuit 36 that holds the address output by the address generation circuit 35 in accordance with the memory control signal 32 are provided.

Further, the storage device monitoring device includes a data processing circuit 38 for inputting or outputting data 37 to or from the single port memory 30 in accordance with the address generated by the address generation circuit 35; Parity 39 of output data 37 or data 37 read from single port memory 30
And a parity comparison circuit 42 that compares the parity 39 by the parity calculation circuit 40 with the parity read from the single port memory 30 and notifies the monitoring result 41 to an external device (not shown). I have.

The parity comparing circuit 42 outputs the parity bit 39 calculated by the parity calculating circuit 40 at the time of data writing to the single port memory 30 as it is. In addition, a parity bit read from the single port memory 30 is input when data is read, and the parity bit is compared with a parity bit calculated by the parity calculation circuit 40 based on the read data.

The storage device monitoring apparatus having such a configuration performs a vertical parity operation in the parity operation circuit 40 on the data 37 and the address 32 at the time of writing data, and calculates the result of the vertical parity operation of "address + data". The data is added to the write data 37 as a parity bit 39 and written to the single port memory 30. At the time of data reading, the parity bit 39 read at the same time as the data 37 read from the single port memory 30 and the read memory address as the address 32 given to the single port memory 30 held by the address holding circuit 36 And the vertical parity operation result of the read data 37 in the parity comparison circuit 42,
By notifying an external device (not shown) as the monitoring result 41, the address bus is monitored.

Next, in order to clarify the operation principle of such a storage device monitoring device, the operations at the time of data writing and data reading will be described.

FIG. 2 shows only portions related to the write operation in order to explain the data write operation in the storage device monitoring apparatus shown in FIG. However,
The same parts as those of the storage device monitoring apparatus shown in FIG. Single port memory 30
When writing data to the memory, the memory control signal generation circuit 33 outputs a memory control signal 44 indicating that write control is performed, and the address generation circuit 35
(M is a natural number) addresses 34 and the data processing circuit 3
8 to n (n is a natural number) data 45 are output to the single-port memory 30. At this time, the m addresses 34 pass through the address holding circuit 36 as they are and are also output to the parity operation circuit 40, and are (m + n) with the n data 45 output from the data processing circuit 38.
This is input to the parity operation circuit 40 which performs the vertical parity operation of this book.

In the parity calculation circuit 40, even in an odd parity calculation in which a parity bit is added so that the number of “1” s of each of the (m + n) bits becomes an odd number, the “1” of each of the (m + n) bits is obtained. An even parity operation for adding a parity bit so that the number becomes an even number may be used, and the configuration can be easily performed by an exclusive OR operation for each bit.
One parity bit 46 generated in the parity operation circuit 40 is written together with n write data 45 as (n + 1) data in the storage location of the single port memory 30 specified by the address 34.

FIG. 3 shows only a portion related to the read operation for explaining the data read operation in the storage device monitoring apparatus shown in FIG. However,
The same parts as those of the storage device monitoring apparatus shown in FIG. Single port memory 30
When data is read from the memory, the memory control signal generation circuit 33 outputs a memory control signal 48 indicating that read control is performed, and the address generation circuit 35 outputs m addresses 34 to the single port memory 30. In response to the read control of the memory control signal 33, the single port memory 30 stores m addresses 34
It outputs n pieces of read data 49 and one parity bit 50, which are storage information of the storage location specified by the above.

The address holding circuit 36 holds m read addresses by a memory control signal 48 indicating read control generated by the memory control signal generation circuit 33. Since a predetermined access time is required from outputting an address to obtaining read data, a parity check of “address + data” can be performed by avoiding switching of an address after reading data. The held address value is updated each time a memory control signal 48 indicating read control is input. At the time of data reading, the address held in the address holding circuit 36 is output to the parity operation circuit 40.

The parity operation circuit 40 performs (m + n) vertical parity operations from the m addresses held by the address holding circuit 36 and the n read data 49 read from the single port memory 30. The read parity calculation result 51 is used as the parity comparison circuit 4
Output to 2.

In the parity comparison circuit 42, the read parity calculation result 51 calculated by the parity calculation circuit 40 is compared with the parity bit 50 read at the time of data reading, and the monitoring result 41 is output. When the read parity calculation result 51 matches the parity bit 50 from the single port memory 30, (m + n) vertical parity calculation results at the time of data writing are obtained.
This indicates that the (m + n) vertical parity calculation results at the time of reading match. Therefore, both the m addresses and the n data are normally stored in the single port memory 30.
To notify an external device (not shown) of a monitoring result indicating that the write operation and the read operation have been normally performed. On the other hand, when the read parity operation result 51 and the parity bit 50 from the single port memory 30 do not match, it is determined that normal access to the single port memory 30 could not be performed, and an external device (not shown) is notified to that effect. In such a case, the external device takes measures such as discarding the read data or invalidating the read processing itself.

Next, monitoring of the address bus by adding such a parity bit will be described in detail.

FIG. 4 shows an outline of an address bus monitoring procedure in the storage device monitoring apparatus shown in FIG. First, in order to detect an abnormal signal line among the m address buses, an m-bit address “a ₁ a ₂ ... _Am ” is output to the single port memory 30 and predetermined data Y is written. (Step S50). This write data is n bits, and this write data is used consistently in the address bus monitoring procedure. Next, of the m-bit address bus, 1-bit a _x (X = 1, 2, 2)
.., M) are inverted to a _x ′, and the same n-bit data Y is written again to the m-bit address “a ₁ ... A _X ′... _Am ” (step S51). As a result, if there is a fixedly failed signal line in the address bus, the parity bits written simultaneously with the data Y in step S50 and step S51 will always be different. Therefore, the storage data of the same m-bit address "a ₁ a ₂ ... A _m " as in the original step S50 is read again (step S52), and the parity comparison is performed (step S53).

[0040] When the parity matches in step S53: (Step S53 Y), the series of steps as the value corresponding to X th bit of the address signal lines which could not be anyway abnormality detection when the a _X finish. Further, the value corresponding to the X-th address signal line is inverted to a _X ′, and the monitoring procedure from step S50 is repeated again to fix “0” or “1” to the X-th address signal line. It can be determined that there was no abnormality such as fixing. On the other hand, when the parities do not match in step S53 (step S53: N), it is notified to the outside that the X-th address signal line is abnormal (step S54).

Next, the above-described address monitoring procedure will be specifically described. In the following, in order to clarify the principle of operation,
Description will be made assuming that the number of address buses is four (that is, m = 4) and the number of data buses is four (that is, n = 4). In addition, in order to explain the operation of the storage device monitoring device shown in FIGS. 2 and 3, observed values at each observation point are specifically shown. The following nine observation points (four points for the write operation and five points for the read operation) are described below.

Point A: Output address of the memory control unit 31 at the time of data writing Point B: Input address of the single port memory 30 at the time of data writing Point C: Input data of the single port memory 30 at the time of data writing Point D: Data writing Input parity bit of the single port memory 30 at the time E point: output address of the memory control unit 31 at the time of data reading F point: input address of the single port memory 30 at the time of data reading G point: of the parity operation circuit 40 at the time of data reading Input data point H: operation result of the parity operation circuit 40 at the time of data reading J point: output parity bit of the single port memory 30 at the time of data reading

Further, between points A and B in FIG. 2 and in FIG.
One of the four address buses is disconnected between point E and point F, and the single port memory 30 is connected to the power supply line for some reason. Is fixedly input.
The parity calculation circuit 40 performs odd parity calculation.

In such a storage device monitoring apparatus, the address bus is observed for the single port memory 30 in the following procedure.

Step 1: Write data [0001] to address [0000]. Step 2: Write data [0001] to address [0001]. Step 3: Read address [0000].

FIG. 5 shows the states of the nine observation points shown in FIGS. 2 and 3 in accordance with Procedures 1 to 3. That is, the states of the observation points A, B, C, and D at the time of the write operation to the single-port memory 30 of FIG. 2 shown in the procedure 1 and the procedure 2, and at the time of the read operation to the single-port memory 30 of FIG. The state of observation points E, F, G, H, and J points is shown.
In the figure, "" indicates that the input of the single port memory 30 is fixed at "1" and is erroneously recognized due to the disconnection of the address line as described above.

As a result of the procedure 1, at the point A, the address is "0000" outputted by the address generation circuit 35, but at the point B, the LSB (Least Significant) of the address line is obtained.
ant Bit) is fixed to “1”, so that “0001” (FIG. 5)
Then, the single port memory 30 is set to “000”).
Will be recognized. At point C, the data processing circuit 3
The write data “0001” generated by 8 is input to the single port memory 30 as it is, and at the same time, “0” is input at the point D by the odd parity calculation performed by the parity calculation circuit 40.

Subsequently, as a result of the procedure 2, at the point A, the address is "0001" outputted by the address generating circuit 35, but at the point B, the LSB of the address line is fixed at "1", so that the address is "0001" (FIG. In 5,
") As the single-port memory 30. At point C, the write data" 0001 "generated by the data processing circuit 38 is directly input to the single-port memory 30, and at the same time, the parity operation circuit 4
"1" at point D due to the odd parity operation calculated at 0
Is entered. In the procedure so far, the same data is written to the same address, but different parity bits are written.

Further, as a result of the procedure 3, at the point E, the address is "0000" outputted by the address generation circuit 35, but at the point F, the LSB of the address line is fixed at "1", so that the address is "0001" (FIG. 5). Then, "000
)) As the single-port memory 30. At the point G, the address [000] in the procedure 2
1], and the parity bit “1” is also output at the point J.
On the other hand, at the point H, the address “000” at the time of data reading is used.
“0” is output as the result of the vertical parity operation calculated in the parity operation circuit 40 from “0” and the read data “0001”.
At 2, the H point and the J point are compared, and the parity bits at the H point and the J point do not match.
To notify an address bus abnormality. Here, the 0th bit, which is the difference between the address buses in procedure 2 and procedure 3, can be detected as abnormal.

In this embodiment, the monitoring of the address bus has been described. However, as for the monitoring of the data bus, the data bus can be easily monitored by comparing the parity bits after the write and read operations for the same address, as in the prior art. .

In this embodiment, the parity bits of the address bus and the data bus are generated and written in addition to the write data. However, the parity bit of the data bus alone is generated and further written into the write data. Can be added to Thus, when the above-described abnormality can be detected, by comparing the parity bit of the data bus alone, it is possible to easily determine whether the detected abnormality is the address bus or the data bus. . As a result, when an abnormality is detected, it is possible to take immediate action.

Further, in this embodiment, the parity bits of the address bus and the data bus are generated and added to the write data. However, the parity bits are divided into arbitrary bit lengths and the parity bits are generated respectively. You may write it.

[0053]

As described above, according to the first aspect of the present invention, the vertical parity calculation result at the time of writing to the address bus and the data bus is compared with the vertical parity calculation result at the time of reading from the storage means. By doing so, the monitoring of the storage means is performed, so that an abnormality in the address bus can be detected with a simple configuration and at low cost. Further, the abnormality can be detected without performing a mechanical test on all of the address bus and the data bus.

According to the second aspect of the present invention, the result of the vertical parity operation of the address bus and the data bus is stored together with the write data at the time of writing to the storage means. The same storage means as the configuration can be used, and the address bus can be monitored.

According to the third aspect of the present invention, the vertical parity operation of the address bus and the data bus is performed in units of a predetermined bit length. In this way, an abnormal part can be quickly identified.

According to the fourth aspect of the present invention, since the single port memory has only one pair of the address bus and the data bus, all accesses to the single port memory can be monitored.

According to the fifth aspect of the present invention, by setting each bit repeatedly as "1" and "0" for the signal line of each address bus, an abnormal portion of the address bus can be immediately specified. Will be able to do it.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an outline of a configuration of a storage device monitoring device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining a write operation of the storage device monitoring device according to the embodiment.

FIG. 3 is an explanatory diagram for explaining a read operation of the storage device monitoring apparatus according to the embodiment;

FIG. 4 is a flowchart showing an outline of an address bus monitoring procedure of the storage device monitoring apparatus in the embodiment.

FIG. 5 is a state explanatory diagram showing a state at each observation point of the storage device monitoring apparatus in the embodiment.

FIG. 6 is a block diagram showing an outline of a configuration of a storage device monitoring device proposed conventionally.

[Explanation of symbols]

 Reference Signs List 30 single-port memory 31 memory control unit 32 memory control signal 33 memory control signal generation circuit 34 address bus 35 address generation circuit 36 address holding circuit 37 data bus 38 data processing circuit 39 parity bit 40 parity operation circuit 41 monitoring result 42 parity comparison circuit

Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI G06F 13/36 520 G06F 13/36 520C G11C 29/00 631 G11C 29/00 631D 657 657E

Claims (5)

[Claims] 1. A data storage location, an address bus for transmitting address information for specifying the storage location, and write data for writing or read data for reading corresponding to the storage location specified by the address information. Storage means having a data bus for transmitting data, write data parity calculation means for performing parity calculation of each bit data of a write address on an address bus and write data on the data bus at the time of data writing, and Read data parity operation means for performing a parity operation of each bit data of a read address on an address bus and read data on a data bus, an operation result by the write data parity operation means, and an operation result by the read data parity operation means On the basis of A storage device monitoring device, comprising: a monitoring unit that monitors the storage unit. 2. A data storage location, an address bus for transmitting address information for specifying the storage location, and write data for writing or read data for reading corresponding to the storage location specified by the address information. Storage means having a data bus for transmitting the data bus; parity operation means for performing a vertical parity operation of each bit data on the address bus and the data bus; and A data writing unit that writes the write data on the data bus and a vertical parity calculation result calculated by the parity calculator in a storage location of the storage unit specified by the write address information; and a read operation from the storage unit. Sometimes read address information on the address bus Read data read from the storage location of the storage means specified by
A data reading means for reading the vertical parity calculation result by the parity calculation means which is written simultaneously when the read data is written; a vertical parity calculation result read by the data reading means; Monitoring means for monitoring the storage means based on the calculated address information at the time of the read operation from the storage means and the vertical parity calculation result of the read data read by the data reading means. A storage device monitoring device characterized by the above-mentioned. 3. The data write data parity calculation means and the read data parity calculation means calculate parity in a predetermined bit length unit, respectively, and the monitoring means checks the data write data parity calculation means in the bit length unit. 2. The storage device monitoring device according to claim 1, wherein the storage unit is monitored based on a parity operation result by the read data parity operation unit. 4. The storage device monitoring apparatus according to claim 1, wherein said storage means is a single port memory. 5. A data storage location, an address bus for transmitting address information for specifying the storage location, and write data for writing or read data for reading corresponding to the storage location specified by the address information. A first parity calculation step for calculating a vertical parity between a first address of a storage means having a data bus for transmitting the data and predetermined data to be written to the first address; A first write step of writing the vertical parity calculation result calculated in the first vertical parity calculation step and the predetermined data to the address of the first address; a second address obtained by inverting one bit of the first address; A second vertical parity operation for calculating a vertical parity with the predetermined data to be written to the second address. A second writing step of writing the vertical parity calculation result calculated in the second vertical parity calculation step and the predetermined data to a second address of the storage unit; and a first address of the storage unit. A read step of reading the storage information and the parity bit of the read information; a comparison step of comparing the parity bit read in the read step with a vertical parity operation result of the stored information read in the read step and the read address; In the comparison step, when the parity bit read in the reading step does not match the vertical parity operation result of the storage information and the read address read in the reading step, the first writing is performed in the second writing step. Notify the inverted one bit of the address as abnormal Memory monitoring method characterized by comprising a notification step.