JPH0689236A - Random access memory monitor circuit - Google Patents

Abstract

PURPOSE:To provide the RAM monitor circuit of a small scale, which can correctly monitor an operation on the monitor circuit of a random access memory which can read/write data where one word is one bit. CONSTITUTION:A first parity generation means 10 generating the parity of input data of one bit and an address into which data is written, a second parity generation means 20 generating the parity of data on one bit which is read from the random access memory 100, and the address from which data is read, and a coincidence detection means 30 detecting the coincidence of parity which is generated in the first parity generation means 10 and written into the memory 100, and parity generated in the second parity generation means 20 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random access memory monitoring circuit for reading / writing 1-bit data of 1 word.

In recent years, microprocessors have been used for various communication devices, and various controls have been performed by software. In such software control,
Random access memory is used with microprocessors.

Further, the random access memory is used not only for such control relationship but also as a buffer for temporarily storing data when transmitting / receiving data.

It is required to enhance the reliability of such various communication devices, and each device has a self-diagnosis function. One of such self-diagnosis functions of the apparatus is memory operation monitoring.

For example, read / write to a random access memory
There is a parity check as one method of detecting a writing data error. FIG. 3 is a diagram for explaining the parity check. (A) is an example in which one word is composed of 8-bit data D1 to D8 and 1-bit parity bit P.

Here, this is an example of odd parity. Since a is eight and "1" is even, the parity bit P is "0" and b is four and "1" is even. Since the parity bit P is "0" and the number "1" of c is 5 and is an odd number, the parity bit P is "1".

In (B), one word is 1-bit data, and the error cannot be detected by obtaining the parity for each word as described in (A). Like this one
There is a demand for a monitoring circuit that can reliably monitor the operation of a random access memory that reads / writes 1-bit word data with a small circuit.

[0008]

2. Description of the Related Art FIG. 4 is a diagram for explaining a conventional example. In the figure, 100 is a random access memory (hereinafter referred to as RAM), 11A and 21A are inverters, and 31 is an exclusive OR circuit.

In this circuit, 1-bit data is transferred to RAM1
00, and the data inverted by the inverter 11A is written. For reading, the written data is read after being inverted on the writing side, is inverted again by the inverter 21A to restore the original data, and the exclusive OR circuit 31 detects the coincidence with the read data. .

The exclusive OR circuit 31 outputs "0" when two pieces of data match and outputs "1" when they do not match. When an error occurs, an alarm signal of level "1" is output. Output.

[0011]

In the above-mentioned conventional example, when the input data is a series of "1" or a series of "0", the RAM 100 is a failure and the output is a series of "1" or "0". If "," a failure of the RAM 100 cannot be detected in some cases.

It is an object of the present invention to realize a RAM monitoring circuit which is a small-scale circuit capable of accurately monitoring the operation of a RAM that reads / writes 1-bit data of 1 word.

[0013]

FIG. 1 is a block diagram for explaining the principle of the present invention. In the figure, 100 is a RAM for reading and writing 1-bit data of 1 word.
Is a first parity generating means for generating a parity between 1-bit input data and an address for writing the data, and 20 is a parity generating means for the 1-bit data read from the RAM 100 and the address from which the data is read. It is the second parity generating means.

Further, 30 is the first parity generation circuit 10
And the parity that was generated in
It is a coincidence detecting means for detecting coincidence with the parity generated in the second parity generation circuit 20, and generates parity of 1-bit data and address on the read / write side and detects the coincidence of the parity.

[0015]

On the writing side, the 1-bit data is written and the parity of the 1-bit input data and the address is generated by the first parity generating means 10 to generate the RAM 100.
Write in.

On the read side, the second parity generating means 2
Parity between 1-bit data read at 0 and a read address is generated, and the coincidence detection means 30 detects that the parity generated in the first parity generation circuit and written in the RAM 100 matches. By R
The operation of the AM 100 is monitored.

[0017]

FIG. 2 is a diagram for explaining an embodiment of the present invention.
In the figure, the first parity generating means 10 explained in FIG. 1 is an exclusive OR circuit (hereinafter referred to as an EOR circuit) 11, a flip-flop circuit (hereinafter referred to as an FF circuit) 12, and a negative OR circuit (hereinafter referred to as a NOR circuit). The first parity generating means 10 has the same configuration as the second parity generating means 20, and the EOR circuits 21, F
This is an example in which the F circuit 22 and the NOR circuit 23 are used and the EOR circuit 31 is used as the coincidence detecting means 30.

Here, it is assumed that 1-bit data is input first and then input to the address. First, when the data position signal "1" indicating the data position is input to one input terminal, the NOR circuit 13 outputs "0" regardless of the signal of the other input terminal. The EOR circuit 11 outputs "0" when the two input data match, and the exclusive logic of 1-bit data which is the first input data and "0" output from the NOR circuit 13 The sum is taken by the EOR circuit 11.

That is, when the 1-bit input data is "0", "0" is output, and when the input data is "1", "1" is output. This output is input by the FF circuit 12, and its inverted output is input to the NOR circuit 13.

Since the data position signal is "0" after the next bit, the NOR circuit 13 operates in the FF circuit 1.
The inverted signal of the inverted output of 2 is output. EOR circuit 1
1 receives this signal as an input and takes the exclusive OR with the first bit of the address bit which is the next input data. If the address bit is "1", the FF circuit 12
If the input data is "0", the state of the FF circuit 12 is maintained as it is.

Thus, each time "1" is input,
Parity is generated by inverting the state. Generation of parity on the output side is the same operation.

In this way, even for data of 1 bit for 1 word, the parity with the address is generated and written in the RAM 100. On the read side, the parity of the read 1 bit of data and the read address is obtained, and the EOR is obtained.
The operation of the RAM can be monitored by comparing the two parities in the circuit 31 and outputting an alarm signal "1" when they do not match.

[0023]

According to the present invention, the parity of 1-bit data and the address of 1 word is generated, and the parity of the write side and the parity of the read side are compared with each other to accurately monitor the operation of the RAM. A small-scale monitoring circuit that can be implemented can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

FIG. 3 is a diagram explaining a parity check.

FIG. 4 is a diagram illustrating a conventional example.

[Explanation of symbols]

 100 RAM 10 1st parity generation means 11, 21, 31 EOR circuit 12, 22 FF circuit 13, 23 NOR circuit 11A, 21A Inverter 20 1st parity generation means 30 Match detection means

Claims (1)

[Claims] 1. A monitoring circuit of a random access memory (100) for reading / writing 1-bit data of 1 word, wherein a parity is generated between 1-bit input data and an address to write the data. Parity generating means (10)
Second parity generating means (20) for generating parity between 1-bit data read from the random access memory (100) and an address from which the data is read.
And a match for detecting a match between the parity generated by the first parity generating means (10) and written in the memory (100) and the parity generated by the second parity generating means (20). A first means (10) for generating a parity of 1-bit input data and a write address, which is written in the random access memory (100) to generate a second parity. The parity of the 1-bit data read by the means (20) and the read address is generated, and the parity generated in the first parity generation circuit (10) and written in the memory (100) matches. The coincidence detection means (30) detects that the random access memory monitoring circuit.