JP2011134363A - Interface circuit, parity bit allocation method, and semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interface circuit which memorizes data which contains a parity bit even if a defective cell is in the parity bit cell of a memory cell array; and to provide a parity bit allocation method and a semiconductor memory. <P>SOLUTION: The allocation circuit 1c is prepared between a core logic 2 and the semiconductor memory 3. In the allocation circuit 1c, a write circuit part 10 is formed for each bit line to output parity bits D9-D12 in write data WD to a bit line in which a defective memory cell is not formed but a normal memory cell is formed, based on bit line selection information SL which shows whether it is a bit line in which the defective memory cell is formed in the memory cell on the bit line. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an interface circuit, a parity bit allocation method, and a semiconductor memory device.

Conventionally, in a semiconductor memory device, even when a defective cell is generated in a memory cell array, a redundant circuit is mounted in order to relieve the defective cell, thereby improving the manufacturing yield.
In addition, a semiconductor memory device includes a memory having an ECC function by providing a dedicated area for parity bits in addition to a regular bit area in a memory cell array. In this case, the 1-bit error in the regular area on the word line is relieved using the parity bit stored in the parity bit area on the word line.

  When a defective cell is generated in a bit cell in the parity bit dedicated area, it has been proposed to use it as a semiconductor memory device used only for regular bit data having no parity bit. (Patent Document 1)

JP-A-10-106285

  However, in a semiconductor memory device having a dedicated area for parity bits, when a defective cell occurs in a bit cell in the parity bit area, it cannot be shipped as a product and discarded as a defective product.

  By the way, in a semiconductor device provided with a parity bit dedicated area, when a defective cell is generated in a bit cell in the parity bit dedicated area, it is necessary to replace the semiconductor memory device used only for regular bit data with a manufacturing yield. Excellent in improving. However, it cannot be used as a semiconductor memory device that can be provided with an ECC function by using an parity bit dedicated area and an parity bit. Therefore, there is a demand for a semiconductor memory that can provide an ECC function by providing a bit cell in a new dedicated tibit area by some method when a defective cell occurs in a bit cell in the parity bit dedicated area.

  The purpose of this parity bit allocation circuit and parity bit allocation method is to be able to store data including parity bits even if a defective cell occurs in a parity bit cell in a memory cell array of a semiconductor memory device.

  According to one aspect of the present invention, for each bit line, based on bit line information indicating whether or not a memory cell on the bit line is a defective memory cell, a parity bit in the write data is A write circuit unit for outputting to the bit line is provided.

  According to one aspect of the present invention, yield can be improved.

The block circuit diagram of a memory interface. 1 is a schematic diagram of a cell array of a semiconductor memory. Explanatory drawing for demonstrating the regular bit and parity bit of write data. Explanatory drawing for demonstrating rearrangement of write data. Explanatory drawing for demonstrating rearrangement of read data. The block circuit diagram for demonstrating the data area determination circuit for write. The block circuit diagram for demonstrating the data area determination circuit for a read.

Hereinafter, a first embodiment will be described with reference to FIGS.
In FIG. 1, a memory interface 1 as an interface circuit is provided between a core logic 2 (CPU) and a semiconductor memory 3. The memory interface 1 includes a command buffer 1a, an address buffer 1b, and an allocation circuit 1c.

  The command buffer 1 a receives various commands CNT such as a write command and a read command from the core logic 2 and outputs the command CNT to the semiconductor memory 3. The address buffer 1 b receives the address data Ad from the core logic 2 and outputs the address data Ad to the semiconductor memory 3.

  The allocation circuit 1c receives the user data Du generated by the core logic 2, generates error correction code data Dp for the user data Du, adds the error correction code data Dp to the user data Du, and writes the write data WD. Generate. The allocation circuit 1 c outputs the write data WD to the semiconductor memory 3 in synchronization with the write command CNT and the address data Ad, and stores the data in the semiconductor memory 3.

  The allocation circuit 1c reads the write data WD stored in the semiconductor memory 3 as read data RD based on the read command CNT and the address data Ad. The allocation circuit 1 c extracts the user data Du from the read data RD that has been read and outputs the user data Du to the core logic 2.

  The core logic 2 outputs user data Du to be stored in the semiconductor memory 3 to the allocation circuit 1c. In this embodiment, the user data Du is composed of 8-bit regular bit data (hereinafter simply referred to as regular bits) D1 to D8.

  The allocation circuit 1c generates error correction code data Dp for the 8 regular bits D1 to D8. In this embodiment, the error correction code data Dp is composed of 4-bit parity bit data (hereinafter simply referred to as parity bits) D9 to D12.

The allocation circuit 1c generates the write data WD by adding the generated parity bits D9 to D12 to the regular bits D1 to D8.
Therefore, in the present embodiment, the write data WD is composed of 12-bit bit data consisting of 8-bit regular bits D1 to D8 and 4-bit parity bits D9 to D12, as shown in FIG.

  For convenience of explanation, each bit of the 12-bit write data WD is collectively referred to as a write bit, and the sign of each write bit is the sign of the corresponding regular bit D1 to D8 and parity bit D9 to D12. Shall be attached.

The semiconductor memory 3 has a memory cell array 5 in which a plurality of memory cells are arranged in a matrix, and stores the write data WD generated by the allocation circuit 1c.
FIG. 2 is a schematic diagram for explaining the memory cell array 5 of the semiconductor memory 3. In the present embodiment, the memory cell array 5 includes twelve bit lines BL1 to BL12 and n (eight in this embodiment) corresponding to the write data WD consisting of 12 write bits D1 to D12. Word lines WL1 to WL8 are wired in a lattice pattern, and memory cells C are formed at the intersecting portions.

  In the memory cell array 5, the allocation circuit 1c has a function of generating the error correction code data Dp, and the write data WD obtained by adding the error correction code data Dp to the user data Du is stored. Therefore, the regular bits D1 to D8 are stored. Is divided into a regular bit dedicated area Z1 for storing the parity bit and a parity bit dedicated area Z2 for storing the parity bits D9 to D12.

  More specifically, in the memory cell array 5, 12 memory cells C are arranged in the row direction, and 8 memory cells C are arranged in the column direction. The memory cells C in each row arranged in the row direction are connected to the corresponding first to eighth word lines WL1 to WL8, respectively, and the memory cells C in each column arranged in the column direction correspond to the corresponding first To twelfth bit lines BL1 to BL12, respectively. Then, each memory cell C connected to the first to eighth bit lines BL1 to BL8 is a memory cell C in the regular bit dedicated area Z1, and each memory cell connected to the ninth to twelfth bit lines BL9 to BL12. Let C be a memory cell C in the parity bit dedicated area Z2.

  That is, the regular bits D1 to D8 in the write data WD are respectively stored in the corresponding memory cells C in the row selected by the word line via the first to eighth bit lines BL1 to BL8. Further, the parity bits D9 to D12 in the write data WD are respectively stored in the corresponding memory cells C of the row selected by the word line via the ninth to thirteenth bit lines BL9 to BL12.

  For example, when the word line WL1 is selected based on the address data Ad, the 12 bit write bits D1 to D12 correspond to the bit lines BL1 to D12 on the word line WL1, that is, the memory cells C in the first row. Each is stored via BL12.

  When reading the write data WD stored in the memory cells C in each row, one word line is selected, and the write bits D1 to D12 stored in the memory cells C in the selected row are set. The data is output to the corresponding bit lines BL1 to BL12. These write bits D1 to D12 are output as read data RD to the allocation circuit 1c via the corresponding bit lines BL1 to BL12.

  For example, when the word line WL1 is selected based on the address data Ad, the 12-bit write bits D1 to D12 stored on the word line WL1, that is, in each memory cell C in the first row, The data is output as read data RD to the allocation circuit 1c via the lines BL1 to BL12.

The allocation circuit 1 c has a writing circuit unit 10 that stores user data Du from the core logic 2 as write data WD in the semiconductor memory 3.
The write circuit unit 10 includes a write data buffer 11, a first parity bit generation circuit 12, a write regular bit buffer 13, a write parity bit buffer 14, and a write data area determination circuit 15.

  The write data buffer 11 receives user data Du consisting of regular bits D1 to D8 from the core logic 2. The write data buffer 11 outputs the regular bits D1 to D8 to the first parity bit generation circuit 12 and the write regular bit buffer 13.

  When the first parity bit generation circuit 12 receives the regular bits D1 to D8, the first parity bit generation circuit 12 generates error correction code data Dp including 4-bit parity bits D9 to D12 so that the errors of the regular bits D1 to D8 can be corrected. The error correction code data Dp is output to the write parity bit buffer 14.

  The write regular bit buffer 13 outputs 8-bit regular bits D1 to D8, and the write parity bit buffer 14 outputs 4-bit parity bits D9 to D12 to the write data area determination circuit 15, respectively.

The write data area determination circuit 15 inputs 8-bit regular bits D1 to D8 and 4-bit parity bits D9 to D12 as 12-bit write data WD.
The write data area determination circuit 15 is connected to each of the bit lines BL1 to BL12. The write data area determination circuit 15 rearranges the arrangement order of the 12 write bits D1 to D12 constituting the input write data WD based on the bit line selection information SL from the fuse circuit 7. Are output to the corresponding bit lines BL1 to BL12, respectively.

  More specifically, it is necessary to store the 4-bit parity bits D9 to D12 in the 12-bit write data WD in a normal memory cell C that is not a defective memory cell C. Therefore, the write data area determination circuit 15 distributes the parity bits D9 to D12 in the write data WD so that they are output to the bit line in which the normal memory cell C is formed.

The bit line selection information SL is information for distributing the parity bits D9 to D12 to the bit lines in which normal memory cells C are formed.
For example, as shown in FIG. 2, in the memory cell array 5, the memory cell C1 on the eleventh bit line BL11 in the parity bit dedicated area Z2 in the first row and the fourth bit line BL4 in the regular bit dedicated area Z1 in the third row. The upper memory cell C2, the memory cell C3 on the tenth bit line BL10 in the parity bit dedicated area Z2 in the sixth row, and the memory cell C4 on the ninth bit line BL9 in the seventh parity bit dedicated area Z2 Suppose that it is a defective memory cell.

  At this time, when the memory cell C2 on the fourth bit line BL4 in the regular bit dedicated area Z1 in the third row is a defective memory cell, each memory cell C in the parity bit dedicated area Z2 in the third row is a normal memory cell. Therefore, the parity bits D9 to D12 are stored normally.

  Therefore, when the write data WD stored in the regular bit dedicated area Z1 and the parity bit dedicated area Z2 in the third row are read as read data RD, even if the memory cell C2 is a defective memory cell, the parity bit D9 Since .about.D12 are normally stored, error correction can be performed and the regular bits D1 to D8 before writing can be restored.

  On the other hand, when the memory cells C1, C3, and C4 in the parity bit dedicated area Z2 are defective memory cells, the parity bits D9 to D12 are not normally stored, so that error correction cannot be performed. That is, the semiconductor memory 3 cannot be used as a memory having the ECC function using the parity bits D9 to D12.

  Therefore, the write data area determination circuit 15 does not use the memory cells C1, C3, and C4 in the parity bit dedicated area Z2, that is, in any case, the fourth bit line BL4, the ninth bit line BL9, the tenth bit. The 4-bit parity bits D9 to D12 in the write data WD are not output to the bit line BL10 and the eleventh bit line BL11.

  In other words, the write data area determination circuit 15 outputs the 4-bit parity bits D9 to D12 in the write data WD to the bit line in which normal memory cells in which no defective memory cells are formed are formed. I am doing so. Here, four of the first to third, fifth to eighth, and twelfth bit lines BL1 to BL3, BL5 to BL8, and BL12 are selected, and normal memory cells on the selected bit line are assigned parity. Store in bits D9-D12.

  As a result, the parity bits D9 to D12 stored in each row are stored in normal memory cells. Then, using the parity bits D9 to D12 stored in the normal memory cells, the regular bits D1 to D8 stored in one defective memory cell among the 8 bits can be error-corrected, and the regular bits D1 to D1 before writing can be corrected. D8 can be restored.

  Therefore, in advance, for each of the bit lines, a bit line in which no defective memory cell is formed in the memory cells on the bit line is obtained by inspection, and parity bits D9 to D12 are output from the obtained bit lines. Four bit lines are selected. Then, the parity bits D9 to D12 of each write data WD are distributed and output to the selected four bit lines so that the normal memory cells C store the parity bits D9 to D12.

  Bit line selection information SL for distributing and outputting the parity bits D9 to D12 to the four bit lines is stored in the fuse circuit 7 in advance. Then, the write data area determination circuit 15 receives the bit line selection information SL from the fuse circuit 7, and based on the bit line selection information SL, sets the parity bits D9 to D12 of each write data WD to normal memory cells. I try to remember it.

  Incidentally, in this embodiment, when there are defective memory cells C1 to C4 in the memory cell array 5 shown in FIG. 2, the write data area determination circuit 15 uses the third bit line BL3 based on the bit line selection information SL. , The fifth bit line BL5, the eighth bit line BL8, and the twelfth bit line BL12 are selected. Then, as shown in FIG. 4, based on the bit line selection information SL, the parity bit D9 is on the third bit line BL3, the parity bit D10 is on the fifth bit line BL5, and the parity bit D11 is on the eighth bit line BL8. The arrangement of the bits D1 to D12 of the write data WD is rearranged so that the parity bit D12 is output to the twelfth bit line BL12.

  The allocation circuit 1c includes a read circuit unit 20 that inputs the write data WD stored in the semiconductor memory 3 as read data RD and outputs the read data RD as user data Du to the core logic 2.

  The read circuit unit 20 includes a read data area determination circuit 21, a read regular bit buffer 22, a read parity bit buffer 23, a second parity bit generation circuit 24, a parity bit comparison circuit 25, a data correction circuit 26, and a read data buffer. 27.

  The read data area determination circuit 21 is connected to each of the bit lines BL1 to BL12. The read data area determination circuit 21 inputs the write data WD (write bits D1 to D12) stored in each memory cell C of the selected row as read data RD via the corresponding bit lines BL1 to BL12. Is done.

  The read data area determination circuit 21 outputs the rearranged write data WD (write bits D1 to D12) from the corresponding bit lines BL1 to BL12 by the write data area determination circuit 15 of the write circuit unit 10. Therefore, this is a circuit for rearranging them.

  Then, based on the bit line selection information SL from the fuse circuit 7, the read data area determination circuit 21 determines the arrangement of the bits D1 to D12 of the write data WD (read data RD) as shown in FIG. The data is rearranged in the arrangement before the rearrangement by the write data area determination circuit 15.

  The read data area determination circuit 21 extracts 8-bit regular bits D1 to D8 (user data Du) from the rearranged write data WD (read data RD) and outputs the extracted bits to the read regular bit buffer 22. Four parity bits D 9 to D 12 (error correction code data Dp) are extracted and output to the read parity bit buffer 23.

  The read regular bit buffer 22 outputs the regular bits D1 to D8 to the second parity bit generation circuit 24 and the data correction circuit 26. The second parity bit generation circuit 24 generates error correction code data Dp including 4-bit parity bits D9 to D12 for error correction with respect to the extracted regular bits D1 to D8, and the parity bits D9 to D12 (error correction). The code data Dp) is output to the parity bit comparison circuit 25.

  The parity bit comparison circuit 25 inputs the 4-bit parity bits D9 to D12 extracted by the read data area determination circuit 21 from the read parity bit buffer 23. The parity bit comparison circuit 25 then generates four parity bits (generated parity bits) D9 to D12 generated by the second parity bit generation circuit 24 and four parity bits (generated by the read data area determination circuit 21). Read parity bits) D9 to D12 are compared.

  When the generated parity bits D9 to D12 and the read parity bits D9 to D12 match, the parity bit comparison circuit 25 determines that the 8-bit regular bits D1 to D8 extracted by the read data area determination circuit 21 are normal. The normal regular bit read from the memory cell is determined. Then, the parity bit comparison circuit 25 outputs a determination result indicating that the extracted regular bits D1 to D8 are normal regular bits to the data correction circuit 26.

  On the other hand, the parity bit comparison circuit 25 compares the 8-bit regular bits D1 to D8 extracted by the read data area determination circuit 21 when the generated parity bits D9 to D12 and the read parity bits D9 to D12 do not match. Among them, any one regular bit is determined as an error regular bit read from a defective memory cell. Then, the parity bit comparison circuit 25 generates a data correction circuit based on the determination result that the extracted regular bits D1 to D8 are error regular bits and the 4-bit parity bits D9 to D12 extracted by the read data area determination circuit 21. 26.

  When the data correction circuit 26 determines that the regular bits D1 to D8 extracted by the parity bit comparison circuit 25 are normal, the 8-bit regular bits D1 to D8 from the read regular bit buffer 22 are directly used as user data Du as a read data buffer. 27.

  On the other hand, if the regular bits D1 to D8 extracted by the parity bit comparison circuit 25 are determined to be error regular bits, the regular bits D1 to D8 from the read regular bit buffer 22 are read data input from the parity bit comparison circuit 25. Error correction is performed using the read parity bits D9 to D12 (error correction code data Dp) extracted by the area determination circuit 21. Then, the data correction circuit 26 outputs the corrected regular bits D1 to D8 obtained by error correction to the read data buffer 27 as user data Du.

  The read data buffer 27 receives the user data Du consisting of the extracted parity bits D9 to D12 input from the data correction circuit 26 or the user data Du consisting of the regular bits D1 to D8 after error correction to the core logic 2. Output.

  Therefore, even if there are some defective memory cells in the semiconductor memory 3, since the parity bits D9 to D12 are not stored in the defective memory cells, the core logic 2 reads out the user data Du stored in the semiconductor memory 3 again. can do.

Next, specific circuit configurations of the write data area determination circuit 15 of the write circuit section 10 and the read data area determination circuit 21 of the read circuit section 20 will be described.
(Write Data Area Determination Circuit 15)
As shown in FIG. 6, the write data area determination circuit 15 includes first to fourth write bit shift circuits 31 to 34.
(First Write Bit Shift Circuit 31)
The first write bit shift circuit 31 is a parallel input parallel output type annular shift register, and in the present embodiment, the first write bit shift circuit 31 is configured by a 9-bit shift register including nine flip-flop circuits (FF circuits) 31a to 31i. Yes. In response to the clock signal CLK, the first write bit shift circuit 31 responds to the clock signal CLK with the bit data input to each of the FF circuits 31a to 31i (the ninth FF circuit 31i is the first FF circuit 31a). Shift to.

  As shown in FIG. 6, the first write bit shift circuit 31 includes 8-bit regular bits D1 to D8 from the write regular bit buffer 13 and 4-bit parity bits D9 to D12 from the write parity bit buffer 14. 1-bit parity bit D12 is input.

  More specifically, the last parity bit D12 among the parity bits D9 to D12 is input to the first FF circuit 31a. From the second FF circuit 31b to the last ninth FF circuit 31i, the first regular bit D1 to the last regular bit D8 in the regular bits D1 to D8 are sequentially input.

The first write bit shift circuit 31 receives the clock signal CLK, inputs three clock signals CLK based on the bit line selection information SL from the fuse circuit 7, and then ends the shift operation. At this time, the parity bit D12 input to the first FF circuit 31a at the time of setting is shifted to the fourth FF circuit 31d. The first write bit shift circuit 31 outputs the bit data of the FF circuits 31 a to 31 i shifted by the three clock signals CLK to the second write bit shift circuit 32.
(Second write bit shift circuit 32)
The second write bit shift circuit 32 is also a parallel input / parallel output type annular shift register, and in this embodiment, is constituted by a 10-bit shift register including ten FF circuits 32a to 32j. In response to the clock signal CLK, the second write bit shift circuit 32 responds to the clock signal CLK with the bit data input to each of the FF circuits 32a to 32j (the 10th FF circuit 32j is the first FF circuit 32a). Shift to.

  As shown in FIG. 6, the second write bit shift circuit 32 includes bit data of the FF circuits 31a to 31i of the first write bit shift circuit 31, and four parity bits D9 to D9 from the write parity bit buffer 14. One parity bit D11 in D12 is input.

  More specifically, the parity bit D11 is input to the leading FF circuit 32a. From the second FF circuit 32b to the last tenth FF circuit 32j, the bit data from the first FF circuit 31a of the first write bit shift circuit 31 to the bit data of the last ninth FF circuit 31i are in order. Respectively.

  The second write bit shift circuit 32 receives the clock signal CLK, inputs two clock signals CLK based on the bit line selection information SL from the fuse circuit 7, and then ends the shift operation. At this time, the parity bit D11 input to the first FF circuit 32a at the time of setting is shifted to the third FF circuit 32c. Also, the parity bit D12 input to the fifth FF circuit 32e at the time of setting is shifted to the seventh FF circuit 32g.

The second write bit shift circuit 32 outputs the bit data of the FF circuits 32 a to 32 j shifted by the two clock signals CLK to the third write bit shift circuit 33.
(Third write bit shift circuit 33)
The third write bit shift circuit 33 is also a parallel input parallel output type annular shift register, and in the present embodiment, is constituted by an 11 bit shift register comprising 11 flip-flop circuits (FF circuits 33a to 33k). ing. The third write bit shift circuit 33 responds to the clock signal CLK with the bit data input to the FF circuits 33a to 33k in the subsequent stage FF circuit (the eleventh FF circuit 33k is the first FF circuit 33a). Shift to.

  As shown in FIG. 6, the third write bit shift circuit 33 includes bit data of the FF circuits 32 a to 32 j of the second write bit shift circuit 32, and 4-bit parity bits D <b> 9 to D <b> 9 from the write parity bit buffer 14. One parity bit D10 in D12 is input.

  More specifically, the parity bit D10 is input to the leading FF circuit 33a. From the second FF circuit 33b to the last eleventh FF circuit 33k, the bit data of the tenth FF circuit 32j from the first FF circuit 32a of the second write bit shift circuit 32 are sequentially ordered. Respectively.

  The third write bit shift circuit 33 receives the clock signal CLK, inputs one clock signal CLK based on the bit line selection information SL from the fuse circuit 7, and then ends the shift operation. At this time, the parity bit D10 input to the first FF circuit 33a at the time of setting is shifted to the second FF circuit 33b.

  The parity bit D12 input to the eighth FF circuit 33h at the time of setting is shifted to the ninth FF circuit 33i. Further, the parity bit D11 input to the fourth FF circuit 33d at the time of setting is shifted to the fifth FF circuit 33e.

The third write bit shift circuit 33 outputs the bit data of the FF circuits 33 a to 33 k shifted by one clock signal CLK to the fourth write bit shift circuit 34.
(Fourth Write Bit Shift Circuit 34)
The fourth write bit shift circuit 34 is also a parallel input / parallel output type annular shift register, and in the present embodiment, is constituted by a 12-bit shift register including twelve FF circuits 34a to 34l. The fourth write bit shift circuit 34 responds to the clock signal CLK with the bit data input to the FF circuits 34a to 34l in the subsequent stage FF circuit (the twelfth FF circuit 34l is the first FF circuit 34a). Shift to. The output terminals of the FF circuits 34a to 34l are connected to the corresponding bit lines BL1 to BL12, respectively.

  As shown in FIG. 6, the fourth write bit shift circuit 34 includes the bit data of the FF circuits 33a to 33k of the third write bit shift circuit 33 and the parity bit D9 of 4 bits from the write parity bit buffer 14. One parity bit D9 in D12 is input.

  More specifically, the parity bit D9 is input to the leading FF circuit 34a. From the second FF circuit 34b to the last twelfth FF circuit 341, the bit data of the last eleventh FF circuit 33k is sequentially ordered from the bit data of the first FF circuit 33a of the third write bit shift circuit 33. Respectively.

  The fourth write bit shift circuit 34 receives the clock signal CLK, inputs two clock signals CLK based on the bit line selection information SL from the fuse circuit 7, and then ends the shift operation. At this time, the parity bit D9 input to the first FF circuit 34a at the time of setting is shifted to the third FF circuit 34c.

  The parity bit D12 input to the 10th FF circuit 34j at the time of setting is shifted to the 12th FF circuit 34l. Further, the parity bit D11 input to the sixth FF circuit 34f at the time of setting is shifted to the eighth FF circuit 34h. Furthermore, the parity bit D10 input to the third FF circuit 34c at the time of setting is shifted to the fifth FF circuit 34e.

  The fourth write bit shift circuit 34 outputs the bit data of the FF circuits 34a to 34l shifted by the two clock signals CLK to the corresponding bit lines BL1 to BL12, respectively.

  The FF circuits 34a to 34l are connected in order from the first FF circuit 34a to the last twelfth FF circuit 34l in order from the first bit line BL1 to the twelfth bit line BL12. The 34l bit data is output to the corresponding first to twelfth bit lines BL1 to BL12, respectively.

  Therefore, the parity bit D9 shifted to the FF circuit 34c, the parity bit D10 shifted to the FF circuit 34e, the parity bit D11 shifted to the FF circuit 34h, and the parity bit D12 shifted to the FF circuit 34l are normal. Output to the third, fifth, eighth, and twelfth bit lines BL3, BL5, BL8, and BL12 to which the memory cell C is connected.

  That is, the regular bits D1 to D8 from the write regular bit buffer 13 and the parity bits D9 to D12 from the write parity bit buffer 14 are arranged in the first to fourth write bit shift circuits 31 to 34, respectively. Based on the bit line selection information SL, as shown in FIG. 4, the parity bits D9 to D12 are rearranged and output to the bit lines BL3, BL5, BL8, and BL12 to which the normal memory cells C are connected.

Next, a specific circuit configuration of the read data area determination circuit 21 of the read circuit unit 20 will be described.
(Read Data Area Determination Circuit 21)
As shown in FIG. 7, the read data area determination circuit 21 includes first to fourth read bit shift circuits 41 to 43.
(First read bit shift circuit 41)
The first read bit shift circuit 41 is a parallel input / parallel output type annular shift register, and in the present embodiment, is constituted by a 12-bit shift register including 12 flip-flop circuits (FF circuits) 41a to 41l. Yes. In response to the clock signal CLK, the first read bit shift circuit 41 responds to the clock signal CLK with the bit data input to each of the FF circuits 41a to 41l, and the first FF circuit 41a is the twelfth FF circuit 41l. Shift to.

  In each FF circuit 41a to 41l, the first bit line BL1 to the twelfth bit line BL12 are sequentially connected from the first FF circuit 41a to the last twelfth FF circuit 41l. Each FF circuit 41a to 41l has a write bit of write data WD stored in the memory cell C via the corresponding first to twelfth bit lines BL1 to BL12 (to the write data area determination circuit 15). Each write bit) rearranged in this manner is input.

  That is, the parity bit D9 is input to the third FF circuit 41c via the third bit line BL3, and the parity bit D10 is input to the fifth FF circuit 41e via the fifth bit line BL5. The parity bit D11 is input to the eighth FF circuit 41h via the eighth bit line BL8, and the parity bit D12 is input to the twelfth FF circuit 41l via the twelfth bit line BL12.

  Incidentally, in the FF circuits excluding the five FF circuits 41c, 41e, 41h, and 41l, the regular bits D1 to D8 are input from the first FF circuit 41a to the eleventh FF circuit 41k in order.

  The first read bit shift circuit 41 receives the clock signal CLK, inputs two clock signals CLK based on the bit line selection information SL from the fuse circuit 7, and then ends the shift operation. At this time, the parity bit D9 input to the third FF circuit 41c at the time of setting is shifted to the first FF circuit 41a.

  The parity bit D10 input to the fifth FF circuit 41e is supplied to the third FF circuit 41c, and the parity bit D11 input to the eighth FF circuit 41h is supplied to the sixth FF circuit 41f and the twelfth FF. The parity bit D12 input to the circuit 41l is shifted to the tenth FF circuit 41j.

Then, the first read bit shift circuit 41 outputs the bit data (parity bit D9) shifted to the first FF circuit 41a to the read parity bit buffer 23. The first read bit shift circuit 41 outputs each bit data of the twelfth FF circuit 41l from the second FF circuit 41b to the second read bit shift circuit 42.
(Second read bit shift circuit 42)
Similarly, the second read bit shift circuit 42 is a parallel input parallel output type annular shift register, and in the present embodiment, the second read bit shift circuit 42 includes an 11-bit shift register including 11 FF circuits 42a to 42k. In response to the clock signal CLK, the second read bit shift circuit 42 responds to the clock signal CLK with the bit data input to the FF circuits 42a to 42k, and the first FF circuit 42a is the 11th FF circuit 42k. ).

  As shown in FIG. 7, the FF circuits 42 a to 42 k are respectively connected in order from the second FF circuit 41 b to the twelfth FF circuit 41 l of the first read bit shift circuit 41. Accordingly, the parity bit D10 is input to the second FF circuit 42b, the parity bit D11 is input to the fifth FF circuit 42e, and the parity bit D12 is input to the ninth FF circuit 42i.

  The second write bit shift circuit 42 receives the clock signal CLK, inputs one clock signal CLK based on the bit line selection information SL from the fuse circuit 7, and then ends the shift operation. At this time, the parity bit D10 input to the second FF circuit 42b at the time of setting is shifted to the first FF circuit 42a. Further, the parity bit D11 input to the fifth FF circuit 42e at the time of setting is shifted to the fourth FF circuit 42d. Further, the parity bit D12 input to the ninth FF circuit 42i at the time of setting is shifted to the eighth FF circuit 42h.

Then, the second read bit shift circuit 42 outputs the bit data (parity bit D10) shifted to the first FF circuit 42a to the read parity bit buffer 23. The second read bit shift circuit 42 outputs each bit data of the eleventh FF circuit 42k from the second FF circuit 42b to the third read bit shift circuit 43.
(Third read bit shift circuit 43)
The third read bit shift circuit 43 is also a parallel input / parallel output type annular shift register, and in the present embodiment, is constituted by a 10-bit shift register including ten FF circuits 43a to 43j. In response to the clock signal CLK, the third read bit shift circuit 43 receives the bit data input to the FF circuits 43a to 43j in response to the clock signal CLK, and the first FF circuit 43a is the 10th FF circuit 43j. ).

  As shown in FIG. 7, the FF circuits 43a to 43j are connected in order from the second FF circuit 42b to the eleventh FF circuit 42k of the second read bit shift circuit 42, respectively. Accordingly, the parity bit D11 is input to the third FF circuit 43c, and the parity bit D12 is input to the seventh FF circuit 43g.

  The third read bit shift circuit 43 receives the clock signal CLK, inputs two clock signals CLK based on the bit line selection information SL from the fuse circuit 7, and then ends the shift operation. At this time, the parity bit D11 input to the third FF circuit 43c at the time of setting is shifted to the first FF circuit 43a. Further, the parity bit D12 input to the seventh FF circuit 43g at the time of setting is shifted to the fifth FF circuit 43e.

  The third read bit shift circuit 43 outputs the bit data of the FF circuits 43a to 43j shifted by the two clock signals CLK to the fourth read bit shift circuit 44.

Then, the third read bit shift circuit 43 outputs the bit data (parity bit D11) shifted to the first FF circuit 43a to the read parity bit buffer 23. The third read bit shift circuit 43 outputs each bit data of the tenth FF circuit 43j from the second FF circuit 43b to the fourth read bit shift circuit 44.
(Fourth read bit shift circuit 44)
The fourth read bit shift circuit 44 is also a parallel input parallel output type annular shift register, and in this embodiment, is constituted by a 9-bit shift register including nine FF circuits 44a to 44i. In response to the clock signal CLK, the fourth read bit shift circuit 44 responds to the clock signal CLK with the bit data input to the FF circuits 44a to 44i, and the first FF circuit 44a is the ninth FF circuit 44i. ).

  As shown in FIG. 7, the FF circuits 44 a to 44 i are respectively connected in order from the second FF circuit 43 b to the tenth FF circuit 43 j of the third read bit shift circuit 43. Accordingly, the parity bit D12 is input to the fourth FF circuit 44d.

  The fourth read bit shift circuit 44 receives the clock signal CLK, inputs three clock signals CLK based on the bit line selection information SL from the fuse circuit 7, and then ends the shift operation. At this time, the parity bit D12 input to the fourth FF circuit 44d at the time of setting is shifted to the first FF circuit 44a.

The write data WD (write bits D1 to D12) are input from the second FF circuit 44b to the ninth FF circuit 44i in the order before being stored in the semiconductor memory 3.
Then, the fourth read bit shift circuit 44 outputs the bit data (parity bit D12) shifted to the first FF circuit 44a to the read parity bit buffer 23. The fourth read bit shift circuit 44 outputs the bit data of the second FF circuit 44b to the ninth FF circuit 44i to the read regular bit buffer 22.

  Therefore, the arrangement of the bits D1 to D12 of the write data WD (read data RD) output from the first to twelfth bit lines BL1 to BL12 is determined by the first to fourth read bit shift circuits 41 to 44, respectively. As shown in FIG. 5, the first to fourth write bit shift circuits 31 to 34 are rearranged in the arrangement before the rearrangement.

  As a result, the regular bits D1 to D8 arranged before writing are inputted to the regular bit buffer 22 for reading, and the parity bits D9 to D12 arranged before writing are inputted to the parity bit buffer 23 for reading.

As described above, according to the present embodiment, the following effects can be obtained.
(1) According to the present embodiment, in the write circuit unit 10 (write data area determination circuit 15), a write to a bit line in which a normal memory cell C in which a defective memory cell is not formed is formed. The parity bits D9 to D12 of 4 bits in the data WD are output.

  Originally, even if there is a defective memory cell in the memory cell C in the parity bit dedicated area Z2 for storing the parity bits D9 to D12 generated for the regular bits D1 to D8, the memory cell in the regular bit dedicated area Z1 The parity bits D9 to D12 can be stored in C.

Therefore, in the semiconductor memory 3, even if there is a defective memory cell in the memory cell C in the parity bit dedicated area Z2, it can be used as a memory having an ECC function using the parity bits D9 to D13.
(2) According to the present embodiment, the read circuit section 20 (read data area determination circuit 21) reads the bit data arrangement of the read data RD read from each bit line before writing it to the semiconductor memory 3. Rearranged in the arrangement of each bit data of the write data WD.

  Therefore, the regular bits D1 to D8 and the parity bits D9 to D12 can be extracted even when the write data area determination circuit 15 distributes the data to the bit line in which the normal memory cell C is formed.

As a result, since the parity bits D9 to D12 stored in each row are stored in the normal memory cell C and can be reliably extracted, the parity bits D9 to D12 stored in the normal memory cell C are used to generate a defective memory. The regular bits D1 to D8 stored in the cells C1 to C4 can be error-corrected and restored to the regular bits D1 to D8 before writing.
(3) According to the present embodiment, the read circuit unit 20 uses the regular bits D1 to D8 extracted by the read data area determination circuit 21 to generate new parity bits (generated parity bits) in the second parity bit generation circuit 24. Bits) D9 to D12. Then, the parity bits (extracted parity bits) D9 to D12 extracted by the read data area determination circuit 21 are compared with the generated parity bits D9 to D12.

  When the generated parity bits D9 to D12 coincide with the read parity bits D9 to D12, the extracted regular bits D1 to D8 are the normal user data Du read from the normal memory cell C. Output as.

  On the other hand, when the generated parity bits D9 to D12 and the read parity bits D9 to D12 do not match, any one of the extracted regular bits D1 to D8 has a defective memory cell C1 to C4. It is determined that this is an error regular bit read from. At this time, the read regular bits D1 to D8 are error-corrected using the read parity bits D9 to D12. Then, the error-corrected regular bits D1 to D8 are output as normal user data Du.

  That is, even if the regular bits D1 to D8 are stored in the defective memory cells C1 to C4, since the parity bits D9 to D12 are stored in the normal memory cell C, the original logic data Du is restored to the core logic. 2 can be output.

In addition, you may implement the said embodiment in the following aspects.
In the above embodiment, the user data Du is composed of the 8-bit regular bits D1 to D8, and the parity data Dp is composed of the 4-bit parity bits D9 to D12, but the user data Du and the parity data Dp The number of bits is not particularly limited, and may be changed as appropriate.

  In the above embodiment, the first parity bit generation circuit 12 is provided in the allocation circuit 1c of the memory interface 1, and the user data Du (regular bits D1 to D8) from the core logic 2 is provided in the first parity bit generation circuit 12. Parity bit data Dp (parity bits D9 to D12) is generated.

  When the core logic 2 generates and outputs the parity data Dp (parity bits D9 to D12) for the user data Du (regular bits D1 to D8) together with the user data Du (regular bits D1 to D8). The first parity bit generation circuit 12 of the allocation circuit 1c may be omitted. In this case, the parity bit data Dp (parity bits D9 to D12) is directly input from the write data buffer 11 to the write parity bit buffer 14.

  In the above embodiment, the write data area determination circuit 15 that rearranges the write data WD based on the bit line selection information SL is configured by the first to fourth write bit shift circuits 31 to 34, and is regular. Bits D1 to D8 and parity bits D9 to D12 are bit-shifted by the first to fourth write bit shift circuits 31 to 34 so that their arrangement is rearranged.

  A gate circuit (for example, a transfer gate circuit) is provided between the write regular bit buffer 13 and the write parity bit buffer 14 and the first to twelfth bit lines BL1 to BL12. Then, the regular bits D1 to D8 and the parity bits D9 to D12 of the write regular bit buffer 13 and the write parity bit buffer 14 may be output to the corresponding bit lines BL1 to BL12 via the gate circuit.

  In the above embodiment, similarly, the read data area determination circuit 21 that rearranges the read data RD based on the bit line selection information SL is configured by the first to fourth read bit shift circuits 41 to 44. The read data RD is bit-shifted by the first to fourth read bit shift circuits 41 to 44 to rearrange the arrangement.

  A gate circuit (for example, a transfer gate circuit) is provided between the first to twelfth bit lines BL1 to BL12 and the read regular bit buffer 22 and the read parity bit buffer 23. The read data RD output from the bit lines BL1 to BL12 may be output to the corresponding read regular bit buffer 22 and read parity bit buffer 23 via the gate circuit.

  In the above embodiment, the memory interface 1 as an interface circuit is provided between the core logic 2 and the semiconductor memory 3. This may be implemented by being incorporated in the semiconductor memory 3.

1 Memory interface (interface circuit)
1c Allocation circuit 2 Core logic 3 Semiconductor memory (semiconductor memory device)
DESCRIPTION OF SYMBOLS 5 Memory cell array 7 Fuse circuit 10 Write circuit part 11 Write data buffer 12 1st parity bit generation circuit (1st parity generation circuit)
DESCRIPTION OF SYMBOLS 13 Write regular bit buffer 14 Write parity bit buffer 15 Write data area determination circuit 20 Read circuit section 21 Read data area determination circuit 22 Read regular bit buffer 23 Read parity bit buffer 24 Second parity bit generation circuit ( Second parity generation circuit unit)
25 Parity bit comparison circuit (comparison judgment circuit part)
26 data correction circuit (data correction circuit)
27 Read data buffer 31-34 First to fourth write bit shift circuits 41 to 43 First to fourth read bit shift circuits BL1 to BL12 First to twelfth bit lines C Memory cells C1 to C4 Defective memory cells D1 ~ D8 Regular bit data D9 ~ D12 Parity bit data Du User data Dp Parity data RD Read data SL Bit line selection information (bit line information)
WD write data

Claims (6)

An interface circuit that outputs each bit of write data consisting of a regular bit and a parity bit for the regular bit to a corresponding bit line of the semiconductor memory device,
For each of the bit lines, the parity bit in the write data is output to the bit line based on bit line information indicating whether or not the memory cell on the bit line is a defective memory cell. An interface circuit comprising a circuit unit. The interface circuit according to claim 1,
The write circuit unit includes:
A first parity generation circuit for generating a parity bit for the regular bit from the input regular bit;
An interface circuit, comprising: a rearrangement circuit for rearranging an arrangement of the bits of the write data including the regular bits and the parity bits. The interface circuit according to claim 1 or 2,
Each bit output from each bit line is input, and each bit is rearranged in the bit arrangement of the write data before the writing circuit unit outputs to each bit line based on the bit line information. An interface circuit comprising a read circuit unit for outputting read data. The interface circuit according to claim 3, wherein
The readout circuit unit includes:
A second parity generation circuit unit for generating a second parity bit based on the regular bits extracted from the read data;
A comparison determination circuit unit that compares the parity bit extracted from the read data with the second parity bit generated by the parity generation circuit unit to determine whether they match,
An interface circuit comprising: a data correction circuit unit that performs error correction on the extracted regular bit based on the extracted parity bit when the comparison determination circuit unit determines that they do not match. A parity bit allocation method for inputting write data consisting of regular bits and parity bits for the regular bits, and outputting each bit of the write data to a corresponding bit line of a semiconductor memory device,
For each bit line, the parity bit in the write data is converted into a defective memory cell based on bit line information indicating whether or not the memory cell on the bit line is a defective memory cell. A parity bit allocating method characterized in that output is made to a bit line in which no normal memory cell is formed.   A semiconductor memory device comprising the interface circuit according to claim 1.

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