US8131954B2 - Memory device and data reading method - Google Patents
Memory device and data reading method Download PDFInfo
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- US8131954B2 US8131954B2 US12/338,420 US33842008A US8131954B2 US 8131954 B2 US8131954 B2 US 8131954B2 US 33842008 A US33842008 A US 33842008A US 8131954 B2 US8131954 B2 US 8131954B2
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- data
- main data
- logic level
- flag bits
- bit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
Definitions
- the invention relates to a memory device, and more particularly to an NAND flash with odd flag bits.
- the data stored in an NAND flash may comprise main data and annotated data, wherein each annotated data is an auxiliary data of the main data.
- the auxiliary data may be an error correction code or a memory cell failed symbol, wherein the auxiliary data is designed by its manufacturer according different practical applications.
- an NAND flash After a wafer sorting process is performed, an NAND flash needs an additional redundancy circuit to replace a failed cell therein, so that the NAND flash may be operated normally.
- Park U.S. Pat. No. 5,694,359 discloses a Flash memory device, which has a repair circuit for replacing a failed cell of main memory cell arrays with a spare cell.
- damaged auxiliary data also needs an additional redundancy circuit for repair even though the memory cells used by the auxiliary data occupies a minimal part of the total memory array.
- An exemplary embodiment of such a memory device comprises a memory array, a determining circuit and a data reading circuit.
- the memory array comprises a plurality of page units, each comprising a main data and an auxiliary data corresponding to the main data, wherein the auxiliary data comprises a plurality of flag bits.
- the determining circuit generates a determination bit according to the flag bits.
- the data reading circuit obtains information corresponding to the main data according to the determination bit.
- Memory data is read from a memory array, wherein the memory data comprises a main data and an auxiliary data corresponding to the main data, and the auxiliary data comprises a plurality of flag bits.
- a determination bit is generated according to the flag bits.
- Information corresponding to the main data is obtained according to the determination bit.
- FIG. 1 shows a memory device according to an embodiment of the invention
- FIG. 2A shows data stored in a page unit according to an embodiment of the invention
- FIG. 2B shows data stored in a page unit according to another embodiment of the invention.
- FIG. 3 shows a data reading method according to an embodiment of the invention.
- FIG. 1 shows a memory device 100 according to an embodiment of the invention.
- the memory device 100 comprises a memory array 110 , a page buffer 120 , a determining circuit 130 and a data reading circuit 140 .
- the memory array 110 is an NAND flash which is formed by a plurality of multi level cells, and the memory array 110 may be divided into a plurality of page units, such as a page 111 , a page 112 and so on.
- each page unit may comprise a main data and an auxiliary data corresponding to the main data, wherein the auxiliary data is a multi-bit data.
- a main data D 1 and an auxiliary data D 2 may be transmitted to the page buffer 120 when the memory array 110 is read by the data reading circuit 140 .
- the determining circuit 130 may generate a determination bit D 3 according the auxiliary data D 2 from the page buffer 120 .
- the data reading circuit 140 may receive the main data D 1 via the page buffer 120 and obtain a content of the main data according to the determination bit D 3 , indicating whether the main data D 1 is a one-bit data or a two-bit data.
- the two-bit data “00” and “01” may be regarded as the one-bit data “0” and “1”, respectively.
- FIG. 2A shows data 200 stored in a page unit according to an embodiment of the invention.
- the data 200 comprises a main data D 1 and an auxiliary data D 2 , wherein no damage has occurred in the auxiliary data D 2 .
- the auxiliary data D 2 is formed by five flag bits b 1 -b 5 .
- the flag bit is used to indicate that the main data D 1 is a two-bit data when the flag bit is “1” and the main data D 1 is a one-bit data when the flag bit is “0”.
- a determining circuit (such as the determining circuit 130 of FIG. 1 ) may determine that all flag bits within the auxiliary data D 2 are “1” when reading the auxiliary data D 2 .
- the determining circuit may generate a determination bit which has a logic level “1”.
- a data reading circuit (such as the data reading circuit 140 of FIG. 1 ) may obtain the information indicating that the main data D 1 is a two-bit data.
- FIG. 2B shows data 250 stored in a page unit according to another embodiment of the invention.
- the data 250 comprises a main data D 1 and an auxiliary data D 2 , wherein some damages has occurred in the auxiliary data D 2 .
- the failed memory cell may not be programmed to ‘1’.
- the main data D 1 is a two-bit data and the auxiliary data D 2 is formed by five flag bits b 1 -b 5 , wherein some damage has occurred in the flag bits b 3 and b 4 .
- the flag bits b 3 and b 4 may not be programmed to “1” when the auxiliary data D 2 is programmed to indicate the main data D 1 is a two-bit data.
- a determining circuit (such as the determining circuit 130 of FIG. 1 ) may obtain a first number indicating an amount of the flag bits having the logic level “1” and a second number indicating an amount of the flag bits having the logic level “0” when reading the auxiliary data D 2 .
- the first number is equal to 3 and the second number is equal to 2.
- the determining circuit may generate a determination bit with the logic level “1”.
- a data reading circuit (such as the data reading circuit 140 of FIG. 1 ) may obtain the information indicating that the main data D 1 is a two-bit data according to the determination bit.
- the determining circuit may generate a determination bit with the logic level “0” due to the second number being larger than the first number.
- the determining circuit may determine the logic level of the determination bit according the first number and the second number. Therefore, a flash memory will not need an additional redundancy circuit (such as a repair circuit or any additional memory cell) to replace the failed memory cell of the flash memory which is used to store the auxiliary data D 2 .
- the memory cells storing the auxiliary data D 2 may also not be tested by a wafer sorting process.
- FIG. 3 shows a data reading method according to an embodiment of the invention.
- a page buffer reads a memory data from a memory array (such as an NAND flash formed by a plurality of multi level cells), wherein the memory data comprises a main data and an auxiliary data corresponding to the main data.
- the auxiliary data comprises a plurality of flag bits, wherein an amount of the flag bits is an odd number.
- a determining circuit generates a one-bit determination data (i.e. a determination bit) according to the flag bits.
- the determining circuit may determine a logic level of the determination bit according to a first number and a second number, wherein the first number indicates an amount of the flag bits having a logic level “1” and the second number indicates an amount of the flag bits having a logic level “0”.
- a data reading circuit may receive the main data, obtain the information of the main data according to the determination bit, and obtain the main data according to the information.
- the determination bit indicates a bit length of the main data
- the data reading circuit may obtain the main data according to the information indicating the bit length of the main data.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
Claims (17)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW097100537A TWI404076B (en) | 2008-01-07 | 2008-01-07 | Memory devices and data read method |
TW97100537A | 2008-01-07 | ||
TW97100537 | 2008-01-07 |
Publications (2)
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US20090177851A1 US20090177851A1 (en) | 2009-07-09 |
US8131954B2 true US8131954B2 (en) | 2012-03-06 |
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US12/338,420 Active 2030-06-05 US8131954B2 (en) | 2008-01-07 | 2008-12-18 | Memory device and data reading method |
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US (1) | US8131954B2 (en) |
JP (1) | JP2009163863A (en) |
TW (1) | TWI404076B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2011123964A (en) * | 2009-12-11 | 2011-06-23 | Toshiba Corp | Semiconductor memory |
JP2013164888A (en) | 2012-02-10 | 2013-08-22 | Toshiba Corp | Semiconductor storage device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5694359A (en) | 1995-12-29 | 1997-12-02 | Hyundai Electronics Industries Co., Ltd. | Flash memory device |
US20080104309A1 (en) * | 2006-10-30 | 2008-05-01 | Cheon Won-Moon | Flash memory device with multi-level cells and method of writing data therein |
US20080151618A1 (en) * | 2006-12-24 | 2008-06-26 | Sandisk Il Ltd. | Flash memory device and system with randomizing for suppressing errors |
US20080162789A1 (en) * | 2007-01-03 | 2008-07-03 | Choi Jin-Hyeok | Memory system with backup circuit and programming method |
US20080215798A1 (en) * | 2006-12-24 | 2008-09-04 | Sandisk Il Ltd. | Randomizing for suppressing errors in a flash memory |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0757483A (en) * | 1993-08-10 | 1995-03-03 | Fujitsu Ltd | Checking method and operational method for data |
JP3987224B2 (en) * | 1999-01-13 | 2007-10-03 | ジェコー株式会社 | Data processing method |
JP4282197B2 (en) * | 2000-01-24 | 2009-06-17 | 株式会社ルネサステクノロジ | Nonvolatile semiconductor memory device |
US6614685B2 (en) * | 2001-08-09 | 2003-09-02 | Multi Level Memory Technology | Flash memory array partitioning architectures |
JP3875153B2 (en) * | 2002-07-04 | 2007-01-31 | Necエレクトロニクス株式会社 | Nonvolatile semiconductor memory device and its rewrite prohibition control method |
TWI266329B (en) * | 2002-07-11 | 2006-11-11 | Amic Technology Corp | FIFO with ECC function |
JP2004079138A (en) * | 2002-08-22 | 2004-03-11 | Renesas Technology Corp | Nonvolatile semiconductor memory device |
JP5130646B2 (en) * | 2005-06-06 | 2013-01-30 | ソニー株式会社 | Storage device |
KR100732628B1 (en) * | 2005-07-28 | 2007-06-27 | 삼성전자주식회사 | Flash memory device capable of multi-bit data and single-bit data |
US8307148B2 (en) * | 2006-06-23 | 2012-11-06 | Microsoft Corporation | Flash management techniques |
-
2008
- 2008-01-07 TW TW097100537A patent/TWI404076B/en active
- 2008-12-18 US US12/338,420 patent/US8131954B2/en active Active
- 2008-12-18 JP JP2008321751A patent/JP2009163863A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5694359A (en) | 1995-12-29 | 1997-12-02 | Hyundai Electronics Industries Co., Ltd. | Flash memory device |
US20080104309A1 (en) * | 2006-10-30 | 2008-05-01 | Cheon Won-Moon | Flash memory device with multi-level cells and method of writing data therein |
US20080151618A1 (en) * | 2006-12-24 | 2008-06-26 | Sandisk Il Ltd. | Flash memory device and system with randomizing for suppressing errors |
US20080215798A1 (en) * | 2006-12-24 | 2008-09-04 | Sandisk Il Ltd. | Randomizing for suppressing errors in a flash memory |
US20080162789A1 (en) * | 2007-01-03 | 2008-07-03 | Choi Jin-Hyeok | Memory system with backup circuit and programming method |
Also Published As
Publication number | Publication date |
---|---|
TW200931438A (en) | 2009-07-16 |
TWI404076B (en) | 2013-08-01 |
US20090177851A1 (en) | 2009-07-09 |
JP2009163863A (en) | 2009-07-23 |
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