JP2008234424A - Memory control circuit, storage system, information processor, and memory control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that error correction against any word line failure is high in probability to be impossible, and that reliability is low in using an error correction code incapable of correcting errors across a plurality of blocks. <P>SOLUTION: Write data rearrangement circuits 6-1 to 6-3 rearrange data including an error correction code belonging to the same block so that the data can be written in the same failure unit bits of a memory element, and output the rearranged data as write data, and the rearranged write data corresponding to a word line failure mode are written in a memory 110 so that the data of one block can be included in the same failure unit. Read data read from the memory 110 are rearranged in the original line by read data rearrangement circuits 8-1 to 8-3, and error detection and correction are operated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory control circuit, a storage system, an information processing apparatus, and a memory control method, and more particularly to a memory control circuit, a storage system, an information processing apparatus, and a memory control method that use an error correction code.

  An example of a technique related to memory control using a conventional error correction code is described in Patent Document 1. This conventional technique rearranges write data so that a block of error correction codes generated in an ASIC group is not assigned to the same element in the DIMM. This improves the possibility of error detection and the like.

JP 2006-4133 A

  In the conventional technique described above, there is a problem that when an error correction code that cannot correct an error across a plurality of blocks is used, there is a high possibility that error correction cannot be performed for a word line failure and reliability is low. This is because the write data is not rearranged in consideration of the failure unit corresponding to the word line failure mode of the memory element.

  An object of the present invention is to provide a memory control circuit, a storage system, an information processing apparatus, and a memory control method that solve the above problems.

  A first memory control circuit according to the present invention provides a memory configured of memory elements having the same word line failure mode to data bits of the same block including an error correction code and capable of error correction. There is means for rearranging the data so as to be stored in a fault unit corresponding to the line fault mode and outputting the rearranged data to the memory.

  The second memory control circuit of the present invention is the first memory control circuit, wherein the rearrangement of the rearranged data read from the memory is restored, and error correction is performed by the error correction code. Have

  A third memory control circuit according to the present invention is the second memory control circuit, wherein the rearrangement is performed on a plurality of word failure line mode types, and rearranged data is generated and held in advance. And means for outputting the rearranged data for the type value of one word failure line mode to the memory.

  A fourth memory control circuit according to the present invention is the third memory control circuit, a failure mode value storage circuit for storing in advance a type value of one word failure line mode, and error correction by inputting write data. An error correction code generation circuit for adding and outputting a code; and a write data rearrangement circuit for performing the rearrangement of the write data and the error correction code for each type of word failure line mode and outputting the rearranged data. , A write data selection circuit for selecting and outputting the rearranged data corresponding to one word failure line mode type according to the type value, and inputting the rearranged data from the write data selection circuit, A write data control circuit for outputting to the memory in batches, and the rearranged data read from the memory. Read data control circuit that inputs and outputs in one or a plurality of times, and the rearranged data from the read data control circuit is restored to the original for each word failure line mode type, and the read data is returned A read data rearrangement circuit that outputs the read data, a read data selection circuit that selects and outputs the return read data corresponding to the type of one word failure line mode according to the type value, and the read data selection based on the error correction code And an error detection / correction circuit that detects and corrects error in the return read data from the circuit.

  A fifth memory control circuit according to the present invention is the fourth memory control circuit, comprising a write data register between the write data selection circuit and the write data control circuit, and the read data control circuit and the read data control circuit. A read data register is included between the data rearrangement circuit.

  In the memory system of the present invention, the memory control circuit of 1, 2, 3, 4, or 5 and the data bit of the same block from the memory control circuit are failed corresponding to the word line failure mode of the memory element. And writing to the unit.

  The information processing apparatus according to the present invention outputs a write request including write data to the storage system and the memory control circuit, outputs a read request to the memory control circuit, and inputs read data from the memory control circuit And including.

  According to a first memory control method of the present invention, a memory control circuit outputs data bits of the same block including an error correction code and capable of error correction to a memory composed of memory elements having the same word line failure mode. The method includes rearrangement so as to store in a failure unit corresponding to the word line failure mode of the memory element and outputting the rearranged data to the memory.

  The second memory control method of the present invention is the first memory control method, wherein the memory control circuit restores the rearrangement of the rearranged data read from the memory, and uses the error correction code. Includes procedures for error correction.

  The third memory control method of the present invention is the second memory control method, wherein the memory control circuit performs the rearrangement for a plurality of word failure line mode types to generate post-reorder data, and And outputting the rearranged data for one word failure line mode type value held in the memory to the memory.

  The fourth memory control method of the present invention includes a procedure in which the memory writes data bits of the same block from the memory control circuit in a failure unit corresponding to a word line failure mode of the memory element.

  The present invention has an effect that error correction is possible even if a word line failure occurs, and reliability is improved. This is because the data block of the same block capable of error correction is stored in a failure unit corresponding to the word line failure mode of the memory element.

  Next, the best mode for carrying out the present invention will be described. The present invention relates to a memory control circuit using a memory composed of a plurality of memory elements having a certain word line failure mode due to an internal circuit configuration. The memory control circuit of the present invention writes an ECC (error correction code) to data consisting of a plurality of bytes to the memory. This ECC is a code that can correct a multi-bit error but cannot correct an error across a plurality of blocks. Here, the block may be one byte or a plurality of bytes. It is sufficient that the blocks are used in a unified manner. According to the present invention, data belonging to the same block is rearranged so as to be written to the same failure unit bit of the memory element. The present invention adopts a configuration that enables error correction by this rearrangement.

  Next, the configuration of the memory element will be described with reference to the drawings. FIG. 2 is an explanatory diagram showing an example of the configuration of the memory element. Referring to FIG. 2, the memory element is 4 [bits] × n [words]. Each bit of 4 [bits] is DQ0, DQ1, DQ2, and DQ3, respectively.

  In a memory element having the word line failure mode A type, <DQ0, DQ1> is a first failure unit, and <DQ2, DQ3> is a second failure unit. In a memory element having the word line failure mode B type, <DQ0, DQ2> is a first failure unit, and <DQ1, DQ3> is a second failure unit. In a memory device having a word line failure mode C type, <DQ0, DQ3> is a first failure unit and <DQ1, DQ2> is a second failure unit. That is, the failure unit is 2 [bits].

  Next, an A type memory element will be described in detail as an example. The decoder 300 connects the word line WSEL0 to the memory cells DQ0 and DQ1. Further, the word line WSEL1 from the decoder 300 is connected to the memory cells DQ1 and DQ2. The word lines WSEL0 and WSEL1 are signals for selecting the same word.

  When the word line WSEL0 fails, a failure occurs in units of <DQ0, DQ1>, and when the word line WSEL1 fails, a failure occurs in units of failure of <DQ2, DQ3>. In this way, each failure unit is independent. Similarly, B-type and C-type memory elements also have a failure in each failure unit.

  Next, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the storage system according to the first embodiment of this invention. Referring to FIG. 1, the storage system includes a memory control circuit 100 and a memory 110. The memory 110 is composed of memory elements having the same word line failure mode (for example, A type) described in FIG. The memory element is, for example, 4 [bits] × n [words]. The memory 110 includes three memory elements, a first memory element, a second memory element, and a third memory element.

  The memory control circuit 100 includes a command / address control circuit 101, an ECG circuit 102, a write data control circuit 103, an ECC circuit 104, a read data control circuit 105, write data rearrangement circuits 6-1 to 6-3, and read data rearrangement. Circuits 8-1 to 8-3, a write data selection circuit 107, a read data selection circuit 109, and a failure mode value storage circuit 111 are included.

  Next, the operation of the first exemplary embodiment of the present invention will be described with reference to the drawings. 3, 4, and 5 are explanatory diagrams showing operations when the word line failure modes are A type, B type, and C type, respectively. At the time of initial startup or the like, the failure mode value storage circuit 111 has a failure mode value (identifies A type, B type, and C type) for selecting a word line failure mode corresponding to the memory elements constituting the memory 110. Is set. The failure mode value storage circuit 111 always outputs a selection signal based on the failure mode value. Hereinafter, in order to simplify the description, one block is assumed to be 1 [byte] (= 8 [bit]).

  When a data write request (with a write command, address, and write data) is output from the external device (eg, processor) to the memory 110, the command / address control circuit 101 inputs the write command write command and address. The address and write command are output to the memory 110, and the write command is output to the write data control circuit 103.

  The ECG circuit 102 (which is an error correction code generation circuit) receives write data, generates redundant data (error correction code), and outputs write data and redundant data (FIGS. 3, 4, and 4). FIG. 5 step S1). The write data rearrangement circuit 6-1 rearranges the write data corresponding to the case where the word line failure mode is A type, and outputs the rearranged write data (step S2 in FIG. 3).

  The write data rearrangement circuit 6-2 rearranges the write data corresponding to the case where the word line failure mode is the B type, and outputs the rearranged write data (step S2 in FIG. 4). The write data rearrangement circuit 6-3 rearranges the write data corresponding to the case where the word line failure mode is the C type, and outputs the rearranged write data (step S2 in FIG. 5).

  That is, the write data rearrangement circuit 6-1, the write data rearrangement circuit 6-2, and the write data rearrangement circuit 6-3 write data belonging to the same block to the same failure unit bit of the memory element. Are output as write data after rearrangement.

  Next, the write data selection circuit 107, in accordance with the selection signal from the failure mode value storage circuit 111, from the write data rearrangement circuit 6-1, the write data rearrangement circuit 6-2, and the write data rearrangement circuit 6-3. One of the rearranged write data is selected and output (step S2 in FIGS. 3, 4, and 5). When the rearranged data is expressed in 4-bit units, the rearranged data is arranged as 4-bit data <B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11>.

  Next, the write data control circuit 103 divides the rearranged write data into four times based on the write command, and outputs it to the memory 110 together with the control signal. That is, the write data control circuit 103 performs the first packet data <B0, B2, B4>, the second packet data <B1, B3, B5>, the third packet data <B6, B8, B10>, the fourth packet data < It is divided into four packet data B7, B9, B11> and output.

  For example, in the case of type A, the rearranged write data is represented by first packet data <bits 0, 1, 8, 9, 16, 17, 24, 25, 32, 33, 40, 41>, second packet data < Bits 2, 3, 10, 11, 18, 19, 26, 27, 34, 35, 42, 43>, third packet data <bits 4, 5, 12, 13, 20, 21, 28, 29, 36, 37, 44, 45>, fourth packet data <bits 6, 7, 14, 15, 22, 23, 30, 31, 38, 39, 46, 47> (step S3 in FIG. 3). For types B and C, rearranged write data is output as shown in FIGS. 4 and 5, respectively (step S3 in FIGS. 4 and 5).

  Next, the memory 110 receives the first packet data, the second packet data, the third packet data, and the fourth packet data from the write data control circuit 103 based on the control signal, the write command, and the address, respectively, at an address i, Write (write) to address i + 1, address i + 2, and address i + 3 (step S3 in FIGS. 3, 4, and 5).

  In the case of the A type, <bits 0, 2, 4, 6,> are included in DQ0 of the first memory element, <bits 1, 3, 5, 7> are included in DQ1, and DQ2 is included in DQ2. , <Bits 8, 10, 12, 14> and <bits 9, 11, 13, 15> are written to DQ3. In this way, one block of data is written so as to be included in the same failure unit. Similarly, in the second memory element and the third memory element, one block of data is written so as to be included in the same failure unit (step S3 in FIG. 3).

  Similarly, in the B type and C type, one block of data is written so as to be included in the same failure unit (step S3 in FIGS. 4 and 5).

  Next, when a data read request (read command and address) is output from the external device to the memory 110, the command / address control circuit 101 inputs the read command and address of the read request, and sends the address and read command to the memory 110. The read command is output to the read data control circuit 105.

  Next, the memory 110 sequentially stores the first packet data, the second packet data, the third packet data, and the fourth packet data from the address i, the address i + 1, the address i + 2, and the address i + 3 based on the read command and the address, respectively. Read (read) (FIG. 3, FIG. 4, FIG. 5 step S4).

  Next, the read data control circuit 105 includes first packet data <B0, B2, B4>, second packet data <B1, B3, B5>, third packet data <B6, B8, B10>, and fourth packet data. The four packet data <B7, B9, B11> are sequentially input, and are output in alignment as <B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11> (FIG. 3, FIG. 4, FIG. 5 Step S5).

  Next, the read data rearrangement circuit 8-1 rearranges the read data corresponding to the case where the word line failure mode is the A type, and outputs the read data as rearranged read data (step S6 in FIG. 3).

  The read data rearrangement circuit 8-2 rearranges the read data corresponding to the case where the word line failure mode is the B type, and outputs the read data as rearranged read data (step S6 in FIG. 4). The read data rearrangement circuit 8-3 rearranges the read data corresponding to the case where the word line failure mode is the C type, and outputs the read data as rearranged read data (step S6 in FIG. 5).

  That is, the read data rearrangement circuit 8-1, the read data rearrangement circuit 8-2, and the read data rearrangement circuit 8-3 are rearranged in the same order as the output of the ECG circuit 102, and the read data after rearrangement. (Return read data) is output (step S6 in FIGS. 3, 4, and 5).

  Next, in accordance with the selection signal from the failure mode value storage circuit 111, the read data selection circuit 109 receives from the read data rearrangement circuit 8-1, the read data rearrangement circuit 8-2, and the read data rearrangement circuit 8-3. Is selected and output (step S6 in FIG. 3, FIG. 4, FIG. 5).

  Next, the ECC circuit 104 (which is an error detection / correction circuit) inputs read data after rearrangement from the read data selection circuit 109, performs error detection and error correction based on the redundant data, and does not include redundant data. Data is output to an external device (FIG. 3, 4, 5 step S7).

  As described above, even if a word line failure occurs in the A type memory element and DQ0, 1 (or DQ2, 3) becomes a fixed failure, the A type is set in the failure mode value storage circuit 111. In this case, a correctable data block is assigned to DQ0, 1 (or DQ2, 3), so that the read data can be corrected.

  Similarly, even if a word line failure occurs in the B type memory element and DQ0, 2 (or DQ1, 3) has a fixed failure, the B type is set in the failure mode value storage circuit 111. In this case, since a correctable data block is assigned to DQ0, 2 (or DQ1, 3), the read data can be corrected.

  Similarly, even if a word line failure occurs in a C-type memory element and DQ0, 3 (or DQ1, 2) has a fixed failure, the C-type is set in the failure mode value storage circuit 111. In this case, a correctable data block is assigned to DQ0, 3 (or DQ1, 2), so that the read data can be corrected.

  As described above, in the first embodiment of the present invention, the data bits of the same block that can be error-corrected are stored in the failure unit corresponding to the word line failure mode of the memory element. Even if a failure occurs, error correction is possible, and the reliability is improved.

  Further, according to the first embodiment of the present invention, the memory element fails due to the configuration in which the failure mode value for selecting the word line failure mode corresponding to the memory elements constituting the memory 110 is initially set. Even if a memory element of a new word line failure mode different from the previous one is replaced with the memory 110, if the failure mode value is changed to a value corresponding to the new word line failure mode, the memory elements other than the memory 110 are used as they are. There is an effect that can be done. That is, the first embodiment of the present invention has an effect of increasing availability.

  In the above description, the memory element of 4 [bits] × n [words] has been described. However, if an element of 8 [bits] × n [words] is used and the failure unit is 4 [bits], ( The number of combinations selected from 8 to 4) / 2 types of word line failure modes. That is, [8! / {4! * (8-4)! }] / 2 = 35 types of word line failure modes exist. Therefore, the write data rearrangement circuits 6-1 to 6-35, the read data rearrangement circuits 8-1 to 8-35, the 35-way write data selection circuit 107, and the 35-way read data selection circuit 109 are required. In this way, it is possible to deal with a multi-bit memory element.

  Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 6 is a block diagram showing the configuration of the second exemplary embodiment of the present invention. Referring to FIG. 6, the second embodiment of the present invention includes a write data register 200 between the write data selection circuit 107 and the write data control circuit 103, compared to the first embodiment of the present invention. A read data register 201 is included between the read data control circuit 105 and the read data rearrangement circuits 8-1 to 8-3.

  The write data register 200 holds the rearranged write register, and the read data register 201 holds read data from the read data control circuit 105. In the second embodiment of the present invention, the delay time of one clock is shortened by the configuration including the write data register 200 and the read data register 201 in the middle, so the second embodiment of the present invention of the present invention. Compared to the above, it is possible to operate at a high frequency, and the performance is improved. In addition, a plurality of registers can be appropriately added at arbitrary positions according to the operating frequency.

  Next, a third embodiment of the present invention will be described. The third embodiment of the present invention is an information processing apparatus including the memory control circuit 100, the memory 100, and a processor (not shown) as an external device according to the first and second embodiments of the present invention. is there. Since the information processing apparatus according to the third embodiment of the present invention includes the memory control circuit 100 and the memory 100 according to the first and second embodiments, the information processing apparatus is the same as the first and second embodiments. This has the effect of improving reliability and improving availability.

1 is a block diagram showing a configuration of a storage system according to a first embodiment of this invention. Explanatory drawing which shows an example of a structure of a memory element. Explanatory drawing which shows operation | movement in case word line failure mode is A type. Explanatory drawing which shows operation | movement in case word line failure mode is B type. Explanatory drawing which shows operation | movement in case word line failure mode is C type. The block diagram which shows the structure of the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Memory control circuit 101 Command / address control circuit 102 ECG circuit 103 Write data control circuit 104 ECC circuit 105 Read data control circuit 110 Memory 111 Failure mode value storage circuit 6-1 Write data rearrangement circuit 6-2 Write data rearrangement circuit 6-3 Write Data Rearrangement Circuit 8-1 Read Data Rearrangement Circuit 8-2 Read Data Rearrangement Circuit 8-3 Read Data Rearrangement Circuit WSEL0 Word Line WSEL1 Word Line 200 Write Data Register 201 Read Data Register 300 Decoder

Claims (11)

For a memory composed of memory elements having the same word line failure mode, data bits of the same block including an error correction code and capable of error correction are stored in a failure unit corresponding to the word line failure mode of the memory element. A memory control circuit comprising means for rearranging and outputting to the memory as rearranged data. 2. The memory control circuit according to claim 1, further comprising means for restoring the rearrangement of the rearranged data read from the memory and performing error correction using the error correction code. Means for generating the rearranged data by performing the rearrangement for a plurality of word failure line mode types, and outputting the rearranged data for one word fault line mode type value held in advance to the memory 3. The memory control circuit according to claim 2, further comprising: A failure mode value storage circuit for storing a type value of one word failure line mode in advance, an error correction code generation circuit for inputting and outputting write data, adding an error correction code, the write data, and the error correction code A write data rearrangement circuit that performs the rearrangement for each word failure line mode type and outputs the rearranged data, and a rearrangement data corresponding to one word failure line mode type according to the type value. A write data selection circuit for selecting and outputting, a write data control circuit for inputting the rearranged data from the write data selection circuit, outputting the data to the memory in one or more times, and reading from the memory A read data control circuit that inputs and outputs the rearranged data in one or more batches; A read data rearrangement circuit for returning the rearranged data from the read data control circuit to the respective word failure line mode types and outputting them as return read data, and one word failure according to the type value A read data selection circuit for selecting and outputting return read data corresponding to the line mode type, and an error detection / correction circuit for detecting and correcting an error of the return read data from the read data selection circuit based on an error correction code; 4. The memory control circuit according to claim 3, further comprising: 5. The write data register is included between the write data selection circuit and the write data control circuit, and a read data register is included between the read data control circuit and the read data rearrangement circuit. Memory control circuit. 6. The memory control circuit according to claim 1, and the memory for writing data bits of the same block from the memory control circuit in a failure unit corresponding to a word line failure mode of the memory element. And a storage system comprising: The storage system according to claim 6, and a processor that outputs a write request including write data to the memory control circuit, outputs a read request to the memory control circuit, and inputs read data from the memory control circuit. An information processing apparatus including the information processing apparatus. The memory control circuit corresponds to the data line of the same block including the error correction code and capable of error correction corresponding to the word line failure mode of the memory element with respect to the memory configured by the memory elements having the same word line failure mode. A memory control method comprising a procedure of rearranging data to be stored in a failure unit and outputting the data as rearranged data to the memory. 9. The memory control method according to claim 8, further comprising a procedure in which the memory control circuit restores the rearrangement of the rearranged data read from the memory and performs error correction using the error correction code. A memory control circuit performs the rearrangement for a plurality of word failure line mode types to generate rearranged data, and stores the rearranged data for one word failure line mode type value held in advance. The memory control method according to claim 9, further comprising a procedure of outputting to a memory. The memory control method, wherein the memory includes a procedure of writing data bits of the same block from the memory control circuit into a failure unit corresponding to a word line failure mode of the memory element.

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