JP2000207290A - Memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To actualize the memory device which generates no multi-bit error, even if some bit of a driver or receiver goes out of order. SOLUTION: In order that more than one bits in one word as a correction unit of error correction ECC are not written in the same data bit of the same DRAM, words are put together as one word, and the bit assignment of the data are changed. Consequently, even if some of the bits of the driver 4 or receiver 6 goes out of order, no multi-bit error is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multi-bit width DR.
The present invention relates to a memory device suitable for use in an AM or the like.

[0002]

2. Description of the Related Art Conventionally, in a memory device using a plurality of DRAMs (Dynamic Random Access Memory), when one of the DRAMs fails, if it can be detected as a single bit data error, one of them is used. There is known a technology including an error correction circuit ECC that automatically corrects bit error data and detects an error in the case of a two-bit error.

[0003]

In a memory device having a multi-bit width DRAM as a storage element, FIG.
As shown in the figure, since multiple bits in one word are stored in the same data bit of the same DRAM, if a certain bit of the driver or receiver fails, a multi-bit error occurs when rearranging to the original data. However, there is a problem that even with the error correction circuit ECC, the multi-bit error cannot be corrected. The present invention has been made in view of such circumstances, and has as its object to provide a memory device that does not cause a multiple-bit error even when a certain bit of a driver or a receiver fails.

[0004]

According to a first aspect of the present invention, there is provided a memory device comprising a storage element for storing data having a plurality of bit widths. In order to avoid storing multiple bits in one word as an error correction unit,
It is characterized in that it comprises a changing means for changing a bit assignment to combine a plurality of words into one.

According to the second aspect of the present invention, the changing means, when storing a plurality of words composed of data having a plurality of bit widths, one bit at a time from the head bit of each word. A writing unit is provided which takes out the data, rearranges the data into one word, and sequentially writes the data into storage elements respectively corresponding to the plurality of words.

According to the third aspect of the present invention, when reading out a plurality of words composed of data having a plurality of bit widths, the changing means may change one bit from the first bit of the word read from the storage element. It is characterized by comprising reading means for restoring to a plurality of words by replacing the original bits for each bit.

According to the present invention, a bit assignment is changed to combine a plurality of words so that a plurality of bits in one word as an error correction unit are not stored in the same data bit of the same storage element. If a bit in the receiver fails, a multiple bit error does not occur.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. (1) Features of the present invention The present invention relates to a memory device having a dynamic random access memory (hereinafter referred to as DRAM) having data of a plurality of bit widths as a storage element. By combining a plurality of words and changing the bit assignment of data so that a plurality of bits in one word are not stored, a plurality of bit errors do not occur even if a driver or a receiver included in the memory device fails. It is characterized by doing so.

(2) Configuration FIG. 1 is a functional block diagram showing a configuration of a memory device according to one embodiment. In this figure, reference numeral 1 denotes a first data storage unit, which is not shown in a higher-level device (for example, a CP).
U) stores the data sent from it. Reference numeral 2 denotes a second data transmission unit that changes the bit assignment of the data stored in the first data storage unit 1 so that a plurality of bits in one word are not stored in the same data bit of the same DRAM and sends the data to the second data storage unit 3. This is a one-bit assignment changing unit. When data is stored in the second data storage unit 3, the data is stored in the DRAM 5 via the driver 4.

When data is transmitted from the memory device to the host device, the functional configuration is as shown in FIG. That is, the data stored in the DRAM 5 is transmitted to the receiver 6.
Through the third data storage unit 7. The second bit assignment changing unit 8 changes the bit assignment of the data stored in the third data storage unit 7, rearranges the original data, and stores the data in the fourth data storage unit 9. The data stored in the fourth data storage unit 9 is transferred to the host device.

(3) Operation Next, the operation of the memory device having the above configuration will be described. Here, the operation will be described on the assumption that the data width of the DRAM 5 has a 4-bit width. First, when data is sent from a higher-level device, as shown in FIG. 1, four words equal to the number of data widths of the DRAM 5 are stored in the first data storage unit 1. Then, the first bit assignment changing unit 2 takes out one bit at a time from the first bit of each word stored in the first data storage unit 1 and
The word is stored in order from the first word data of the first data storage unit 1, the second word of the second data storage unit 3 is stored in order from the second word data of the first data storage unit 1, The third word of the two data storage unit 3 is stored in order from the data of the third word of the first data storage unit 1, and the fourth word of the second data storage unit 3 is the fourth word of the first data storage unit 1.
Word data is stored in order. The data stored in the second data storage unit 3 in this manner is stored in the driver 4 in word units.
Data is stored in the same data bit of the same DRAM without storing a plurality of bits in one word.
5 can be stored.

On the other hand, when data is sent to the host device, as shown in FIG.
The data stored in M5 is 4 words in word units,
The data is stored in the third data storage unit 7. Then, the second bit assignment changing unit 8 changes the bit assignment of the data stored in the third data storage unit 7, rearranges the original data, and stores the data in the fourth data storage unit 9. The data stored in the fourth data storage unit 9 is transferred to the host device. By doing so, a plurality of bits in one word, which is the ECC correction unit, are not stored in the same data bit of the same DRAM. It will not be.

As described above, according to the conventional bit assignment changing method, when a plurality of bits in one word are stored in the same data bit of the same DRAM, when a certain bit of the driver or the receiver fails, the original data is lost. , A multi-bit error occurred and the error could not be corrected. However, according to the present invention, the same DRA
A plurality of words are combined into one and the bit assignment of data is changed so that a plurality of bits in one word which is a correction unit of the error correction ECC are not stored in the same data bit of M. Even if a bit of the receiver 6 fails, a multiple bit error does not occur.

[0014]

According to the present invention, a plurality of words are combined by changing a bit assignment so that a plurality of bits in one word serving as an error correction unit are not stored in the same data bit of the same storage element. Therefore, even if a certain bit of the driver or the receiver fails, a multiple bit error can be prevented.

[Brief description of the drawings]

FIG. 1 is a diagram showing a functional configuration of a memory device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a functional configuration of a memory device according to an embodiment of the present invention;

FIG. 3 is a diagram for explaining a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st data storage part 2 1st bit assignment change part 3 2nd data storage part 4 driver 5 DRAM 6 receiver 7 3rd data storage part 8 2nd bit assignment change part 9 4th data storage part

Claims (3)

[Claims] 1. A memory device comprising a storage element for storing data of a plurality of bit widths, wherein a plurality of bits in one word serving as an error correction unit are not stored in the same data bit of the same storage element. A memory device comprising changing means for changing an assignment to combine a plurality of words into one. 2. When storing a plurality of words consisting of data having a plurality of bit widths, the changing means takes out one bit at a time from the first bit of each word and rearranges them into one word to correspond to each of the plurality of words. 2. The memory device according to claim 1, further comprising a writing unit that sequentially writes the data into the storage elements. 3. A reading means for reading a plurality of words composed of data having a plurality of bit widths, wherein the changing means restores the original bits one by one from the first bit of the word read from the storage element and replaces the original bits with a plurality of words. The memory device according to claim 1, further comprising: