JP2010086120A - Error correction method and error detection method for memory, and controller using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an error correction and detection method of a memory for solving the problem that any address and data to be written in a memory are not correctly stored in the memory. <P>SOLUTION: A controller 2 includes: a processor 4; a memory controller; and a memory device, and configured to, when the processor performs write access to arbitrary data to an address, generate an error detection code CRC to be determined from the address and the arbitrary data and an error correction code ECC to be determined from the error detection code CRC and the arbitrary data, and to write the error detection code CRC and the error correction code ECC as well as the arbitrary data in the memory device, and to, when the processor performs read access to the arbitrary address, read the error correction code ECC and the error detection code CRC and the data written in the memory device, and to correct the errors of the error detection code CRC and the read data read based on the read error correction code ECC, and to detect whether there exists any error in the corrected error detection code CRC and read data. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an error correction method and error detection method for a memory used in a mission critical system in which a failure or stop of the system may cause a serious result in a system using a high-speed and large-capacity memory device. It relates to the controller used.

  High-speed and large-capacity memory devices are often used in computer systems and are used in various fields. Some of them are used for what is called mission-critical systems where a system outage of a few seconds can lead to major damage or a failure that can lead to a serious accident. In such a mission-critical system, it is important to increase availability so that the system is not stopped as much as possible, and to detect safety and reliability so that the abnormality is detected immediately and the abnormality is not propagated to others. As a method for increasing the former availability, there are known a multiplex system that performs majority voting and a system that always corrects errors using an error correction code. As the latter method of improving safety and reliability, there are known a method of always collating the output of a duplicated system and a system for detecting an error using an error detection code and suppressing the output of erroneous data. ing.

  Looking at how to improve the availability and reliability of memory systems, ECC (Error Correction Code) is famous as a high availability method, and adding several check bits to stored data Thus, 1-bit error correction and 2-bit error detection can be performed. As a high reliability method, an error detection code CRC (Cyclic Redundancy Check), which is used as a method for detecting that there is no error in a large amount of data strings in the field of communication or the like, is famous. By adding a check bit to the data string, it can be determined that there is no error of several bits. The well-known parity check is also a kind of CRC.

  In addition, for non-performance critical applications such as ROM (Read Only Memory), error detection is performed such that the same contents of data are stored in different areas of the ROM or in different chips and the contents are collated. A method is also used.

  In addition, if a block encoding method used in a CD (Compact Disc), a hard disk, or the like is used, it is possible to correct and detect errors of a plurality of consecutive bits.

  For example, in the cache memory used in the disk system disclosed in [Patent Document 1], in order to guarantee the completeness of the data (there is no error), the data string to which CRC is added is used as a memory that performs error correction by ECC. The configuration to store is shown. By doing so, the availability to withstand a 1-bit failure of the memory element is enhanced while maintaining high reliability.

  In addition, the data processing circuit disclosed in [Patent Document 2] shows a configuration in which high reliability and high availability are similarly improved by using an error correction function using matrix parity and CRC for a data string. ing.

JP 2002-23966 A JP 2000-59235 A

  The most common method of improving the reliability and availability for constructing a memory device of a computer system is a method of correcting a 1-bit error and correcting a 2-bit error using an error correction code ECC. Since the failure rate of one memory cell is very small and the probability that it is two is its square, it can be considered that there is almost no failure. Failure of two memory cells can be detected, and the probability of three or more is considered to be even lower. In the systems described in [Patent Document 1] and [Patent Document 2], a CRC is added to the data string and stored in the memory in order to ensure the completeness (no error) as the data string. When doing so, a memory with an ECC error correction function is used.

  As described above, in the conventional memory system, improvement of high reliability and high availability is an important issue, but as a general requirement, speeding up is also an important issue. In recent memory devices, not only data transfer synchronized with the clock, but also the use of both rising and falling edges of the clock, the speed has been remarkably advanced. The transfer time is less than 1 ns (one second of the ninth power of 10), and it is at a level that does not operate correctly unless analog level board simulation is performed. Further, the signal voltage applied with the miniaturization of the manufacturing process of the memory device has decreased to about 1 V (volt), and it has become necessary to operate within a very small margin. One of the high reliability methods is derating that operates under relaxed conditions. However, recent memory devices use a PLL (phase-locked loop), so they can only operate at high frequencies. It has become difficult to apply.

  When trying to build a highly reliable and highly available system on the premise of such memory devices that are becoming faster and lower in voltage, it has not been possible to assume that only the failure of the memory cells inside the memory device has been assumed to be a failure. It is sufficient, and it is necessary to assume a failure up to the connection signal between the memory and the memory controller that controls the memory. That is, even if any of the address lines, data lines, address strobe lines, clock lines, data strobe lines, and read / write control lines, which are memory device signals, is temporarily or permanently disconnected or short-circuited, It is necessary to correct the data or detect that it is an error.

  Among them, the data line and the data strobe line use both rising and falling edges of the clock, and therefore, the timing is severe with half the operation time compared to the other. The data strobe lines are prepared for every several data lines (usually 4 or 8 lines) to construct a data strobe group. That is, if this data strobe signal is not transmitted successfully, for example, 8-bit data may not be written at once, or strange data may be written. It has been a challenge to correct or detect errors including such cases. A circuit for realizing this must be simple enough to withstand high-speed transfer performance.

  An object of the present invention is to provide a memory error correction, error detection method, and control device using the same, which solve the problem that addresses and data to be written in the memory are not correctly stored in the memory.

  To achieve the above object, according to the present invention, in a controller including a processor, a memory control device, and a memory device, when the processor performs write access to arbitrary data at an arbitrary address, the memory control device Generates an error detection code CRC determined from the address and the arbitrary data, and an error correction code ECC determined from the error detection code CRC and the arbitrary data, and error detection is performed together with the arbitrary data. When the code CRC and the error correction code ECC are written in the memory device and the processor performs read access to an arbitrary address, the memory control device reads the error correction code ECC written in the memory device and the error detection The code CRC and data are read, and the read error is based on the read error correction code ECC. It corrects the error of the output code CRC and the read data, the read data and the corrected error detection code CRC is characterized in detecting whether there is an error.

  Furthermore, the controller of the present invention is characterized in that the number of bits of the error detection code CRC is larger than the number of error detection bits detectable by the error correction code ECC.

  In the controller of the present invention, the memory device is connected to the memory control device by a plurality of grouped signal lines, and the number of bits of the error detection code CRC is greater than the number of grouped signal lines. It is characterized by many.

  According to another aspect of the present invention, there is provided a memory error detection method including a processor, a memory control device, and a memory device, wherein the processor detects an error in a memory, and the processor performs arbitrary processing for an arbitrary address. When the memory controller performs write access, the memory control unit uses the error detection code CRC determined from the address and the arbitrary data, and the error correction code ECC determined from the error detection code CRC and the arbitrary data. Generating and writing an error detection code CRC and an error correction code ECC along with the arbitrary data to the memory device, and when the processor performs read access to an arbitrary address, the memory control device The written error correction code ECC, error detection code CRC and data are read and the read error correction code is read. Is characterized in that detecting an error in data read error detection code CRC and the read the basis of the code ECC.

  Furthermore, the memory error detection method of the present invention is characterized in that the number of bits of the error detection code CRC is larger than the number of error detection bits detectable by the error correction code ECC.

  Furthermore, in the memory error detection method of the present invention, the memory device is connected to the memory control device by a plurality of grouped signal lines, and the number of bits of the error detection code CRC is determined by the grouped signal. More than the number of lines.

  In order to achieve the above object, according to the present invention, there is provided a memory error correction method that includes a processor, a memory control device, and a memory device, and corrects a memory error. When the memory controller performs write access, the memory control unit uses the error detection code CRC determined from the address and the arbitrary data, and the error correction code ECC determined from the error detection code CRC and the arbitrary data. Generating and writing an error detection code CRC and an error correction code ECC along with the arbitrary data to the memory device, and when the processor performs read access to an arbitrary address, the memory control device The written error correction code ECC, error detection code CRC and data are read and the read error correction code is read. It is characterized in that to correct errors in data read error detection code CRC and the read the basis of the code ECC.

  Furthermore, the memory error correction method of the present invention is characterized in that the number of bits of the error detection code CRC is larger than the number of error detection bits detectable by the error correction code ECC.

  Furthermore, in the memory error correction method of the present invention, the memory device is connected to the memory control device by a plurality of grouped signal lines, and the number of bits of the error detection code CRC is determined by the grouped signal. More than the number of lines.

  Here, it is desirable that the number of CRC bits be greater than or equal to the number of bits constituting the data strobe group so that errors can be completely detected.

  The present invention writes the address and the error detection code CRC generated from the data together with the data to be written into the memory, so that an address line, a data line, an address strobe line, a data strobe line, a read / write control line, etc. That is, it can be determined that the address and data to be written to the memory are not correctly stored in the memory, or that the data cannot be read correctly. In particular, it is possible to reliably detect an abnormality in the address strobe signal by setting the number of CRC bits to be equal to or greater than the number of bits constituting the data strobe group.

  Furthermore, by adding an ECC to the data to be written and the CRC, a 1-bit memory cell error and an abnormality in one data line can be corrected, so that the availability can be improved.

  Further, since this memory control device can be constructed using simple circuits such as CRC and ECC, a high-speed memory device can be used.

  Embodiments of the present invention will be described below with reference to the drawings.

  The best mode for carrying out the present invention will be described below with reference to FIGS.

  FIG. 1 shows a configuration of a high-reliability controller 6 using a memory system according to the present invention. The high-reliability controller 6 includes a memory 1, a memory controller 2, and a processor 4, and the memory controller 2 and the memory 1 are connected by a signal line group 3. The memory controller 2 and the processor 4 are connected by a signal line group 5.

  The processor 4 operates in accordance with a program (not shown) in the processor 4 or a program on the memory 1 generated thereby. In general, data such as a sensor from the outside of the high-reliability controller 6 is input, arithmetic processing is performed based on a program, and the result is output to an actuator or the like to control the system. At this time, the processor 4 uses the signal line group 5 to write / read data to / from the memory controller 2 as necessary. In a general processor, as shown in FIG. 1, signals such as clock (CLK), address and data (AD), transfer start (BS), read / write control (RW), ready (RDY), error (ERR), etc. A line is used.

  The memory controller 2 is a device that accesses the actual memory 1 in response to a memory access request from the processor 4, and performs processing for converting the access request contents of the signal line group 5 into the signal line group 3 of the memory 1. Specifically, the memory 1 uses a plurality of clock synchronous dynamic memories. The signal line group 3 includes a clock (CLK), an address (A), a row address strobe (RAS), and a column address strobe (CAS). , Write read control (WE), data mask (DM), data strobe (DQS), data (DQ), and the like. These are signal lines of a general double data rate type synchronous dynamic memory. In particular, the data mask and the data strobe can control data in units of bytes. That is, when the data is 48 bits, the data mask and the data strobe are each composed of six signals.

  Next, the memory 1 is a memory that can be constructed by a general double data rate type synchronous dynamic memory. Here, the N data is configured to be accessible by designating the address A. The memory 1 stores Ne-bit ECC, Nc-bit CRC, and Nd-bit access data. The access data is preferably an access unit of the processor 4 or the memory controller 2 or a multiple of the access data. Here, 4 bytes (32 bits) are assumed. In that case, Nd is 32. Nc is the number of CRC bits generated from the address and data, and the number of bits is determined by the error detection capability to be applied. Here, it is only necessary to set the Hamming distance as large as possible for 64 bits or less in total of the address and data. As is generally known, the use of CRC of Nc bits guarantees the ability to detect burst errors up to Nc bits, that is, consecutive errors. In this case, Nc is set to 8 or more because there is a possibility that data becomes a burst error due to the data strobe and data mask. Ne is the number of ECC bits. If ECC can be used for general 1-bit error correction and 2-bit error detection, Ne can be 7 (Nd + Nc is 40 + α, which is a syndrome for specifying an error bit). 6 bits that can specify 0-63 and 1 parity bit for 2-bit error detection). Generally, a memory device is made of a multiple of 8 bits. To make the data width of the memory 1 a multiple of 8 bits, Nd is 32 and Ne is 7. As Nc is larger, error detection capability is higher. And

  FIG. 2 shows the connection relationship between the memory controller 2 and the memory 1 more specifically. The memory 1 is composed of memory devices 11, 12, and 13 having a data width of 16 bits. The clock is differential and two signal lines are connected to each memory device individually. This clock requires 125 MHz or more, and is currently being speeded up to 500 MHz year by year. The signals given in synchronization with this clock are address (A), row address strobe (RAS), column address strobe (CAS), and write / read control signal (WE). Connect with wires. The data mask (DMU, DML), data strobe (DQSU, DQSL), and data (DQ) connected to the memory controller in one-to-one correspondence in units of 8 bits use the rising and falling edges of the clock to double the frequency. Therefore, it is a critical path. In particular, the data strobe and data are bidirectional signals and can be said to be stricter signals.

  This memory interface is the same as a general synchronous dynamic memory having a double data rate, but time charts are shown in FIGS. 3 and 4 for explaining its severity.

  First, FIG. 3 shows the timing of data writing to the memory. The most important clock is given by differential signals (CLKP and CLKN). Hereinafter, the address A, the row address strobe RAS, the column address strobe CAS, and the write / read control signal WE are latched at the rising edge of the clock (CLKP). At time T1, a row address is set in the memory at address A, and at time T3, a column address is set in address A at the same time. Here, the row address strobe RAS, the column address strobe CAS, and the write / read control signal WE are low-active signals, which are signals indicating a predetermined operation at a low level. It can be seen that the memory is write-accessed to the memory area specified by the row address and column address specified at time T3. Then, after receiving the write data, the write data is written into the memory area. At this time, the write data is given by the data DQ and the data mask DML using the data strobe DQSL as a clock. The data strobe is a signal having the same frequency as the clock but not in phase, and is a signal that rises or falls at an effective timing of data and data mask. Normally, the data and the data strobe are in a high impedance state, and they are turned on after designating the write operation at time T3. The data mask is a signal that prevents the corresponding data from being written into the memory when it is at a high level. FIG. 3 shows 8 bits of data and one data mask and one data strobe, but there are 6 sets of these in the circuit shown in FIG. By grouping in units of 8-bit data in this way, the wiring delay of data, data mask, and data strobe can be minimized and data can be transferred at high speed.

  FIG. 4 shows the timing when reading is performed. The address, row address strobe, column address strobe, and write / read control signal are applied in the same manner as in the write operation, but the output timing of the read data is slightly different. In other words, during the write operation, the rising or falling edge of the data strobe comes to the center of the data or write mask. However, in the case of reading, the memory stores data at the same time as the rising or falling edge of the data strobe. Is supposed to be output. That is, the receiving memory controller needs to take in data from the received data strobe at a timing when the data is valid. In this case, data is taken in around the middle of the time T5 and the time T6 (more precisely, between the rising and falling edges of the data strobe). When the clock is 400 MHz, the period is 2.5 ns, the valid period of data is 1.25 ns, and the difference between the data strobe and the data fetching timing is 0.625 ns, so that it is necessary to control very high timing. The transmission speed of the electric signal is about 0.6 ns at 10 cm. The voltage drops to about 1.5v, and reflection needs to be considered. In this way, the memories are connected by signal lines that are very strict in terms of timing. Consider a case where at most one of these signal lines cannot be transmitted correctly. If the address, row address strobe, column address strobe, and write / read control signal are not correctly transmitted to the memory, data is written to or read from a memory area different from the designated address. When the data strobe or the data mask is not transmitted correctly, the data to be written is masked in units of 8 bits or the data to be masked is written. If the data is not transferred correctly, the data is erroneously written or read by 1 bit.

  The present invention has been made for the purpose of correcting or detecting these abnormal states. First, an error correction code ECC was added to detect and correct a 1-bit abnormality. Further, in order to detect consecutive abnormalities of 8 bits, an error detection code CRC using an 8th-order or higher generation polynomial is added to the address and data to be accessed. The realization method will be described below with reference to FIGS.

  FIG. 5 shows a circuit for generating write data to the memory in the memory controller 2. When the address A and the write data WD based on the memory access request from the processor 4 are given, the memory controller 2 outputs the address A as a signal to the memory 1 as it is and also inputs it to the CRC generation circuit 21. Here, for the sake of convenience, the configuration in which the address A is output as it is is described, but actually, a circuit for separating the row address and the column address is inserted. The CRC generation circuit 21 generates a 9-bit CRC from the data WD to be written and the address A. Here, for example, X (9) + X (7) + X (5) + X (4) + X (2) + X (1) +1 is used as a generator polynomial. Here, X (N) represents X to the Nth power. At this time, the Hamming distance is 4, so that it is possible to detect up to three arbitrary bit errors, and it is possible to detect nine consecutive bit errors.

  Next, the ECC generation circuit 22 generates an error correction code ECC from the CRC and the write data WD. Since write data WD is 32 bits and CRC is 9 bits, ECC is generated for 41-bit data. In order to provide a 1-bit error correction capability and a 2-bit error detection capability, a 7-bit ECC may be added. In general, a 7-bit ECC is composed of a 1-bit parity and a 6-bit syndrome. The 6-bit syndrome uniquely indicates a bit position where an abnormality has been detected, and is normally a value that is 0 when there is no abnormality.

  The CRC, ECC, and write data WD are output as data 31 to be written to the memory.

  Next, FIG. 6 shows a circuit for checking whether the data read from the memory 1 is correct and correcting it. When it is input as the data 31 read from the address A, the ECC check circuit 23 inputs the data 31 and checks the ECC. When a 2-bit error occurs, the ECC error is displayed. When a 1-bit error occurs, the syndrome is displayed as an ECC correction circuit. 24. The ECC check circuit 23 obtains a syndrome and parity from the data 31, and asserts an ECC error when the parity is 0 and the syndrome is not 0, that is, when there is a contradiction between the parity and the syndrome. The syndrome 6 bits may be sent as it is to the ECC correction.

  The ECC correction circuit 24 inverts predetermined bits of CRC and data DATA from the ECC check circuit 23 according to the value of the syndrome. The output of the ECC correction circuit 24 is input to the CRC check circuit 25 together with the address A to check whether the CRC is correct. The CRC check circuit is a circuit that determines that the CRC is correct when the address A and the data corrected by the ECC correction circuit 24 are divided by the generator polynomial used in the CRC generation circuit 21 and the remainder is zero. When the memory controller 2 reads the address A in response to an instruction from the processor 4, the data RD is sent to the processor 4 as correct read data when there is no ECC error and CRC error. When an ECC error or a CRC error occurs, for example, an interrupt (a signal connected to the port ERR of the processor 4 in FIG. 1) in which a memory error has occurred can be given to the processor 4 to recognize that the memory is abnormal. Since the highly reliable controller 6 can recognize that there is an abnormality in the memory, it outputs a down signal several times after the retry and stops.

  Here, the ECC generation circuit 22, the CRC generation circuit 21, the ECC check circuit 23, and the CRC check circuit 25 are each composed of a multi-stage exclusive OR operation element. Although they are not the same circuit, they are circuits that only obtain an exclusive OR for the number of input bits. Therefore, a 32-bit address and 32-bit data are the maximum inputs, and a 64-bit input is exclusive of two inputs. In logical OR, the result can be obtained in 6 stages. One 2-input exclusive logic can be operated in 0.1 ns or less, and an operation result can be obtained with a sufficient operation time.

  FIG. 7 shows an example of constructing a highly reliable and highly available system using two such highly reliable controllers. The two high-reliability controllers 61 and 62 receive the same input signal, perform the same processing, and output a down signal together with the output data to the high-reliability output control device 7. The down signal from the high-reliability controller 61 or 62 is a signal that inverts 0 and 1 at a fixed period when operating correctly, and a signal that indicates an abnormality when it becomes a constant value is generally used. . When the two high-reliability controllers 61 and 62 are operating normally, the output control device 7 outputs one of them. When either one of the high reliability controllers becomes abnormal, the output of the normal high reliability controller is selected and output. At that time, a signal requesting replacement of the failed high reliability controller is output.

  As described above, according to this embodiment, 9 bits of the error detection code CRC for the address and data are added, and 7 bits of the error correction code ECC is added to the CRC and data. It has become possible to correct or detect abnormalities in the wiring between the cell and the memory.

The figure which shows the structure of a highly reliable controller. The figure which shows the connection of a memory controller and a memory device. The figure which shows the write timing of memory. The figure which shows the read timing of a memory. The figure which shows the write data generation circuit of a memory controller. The figure which shows the read data error correction and detection circuit of a memory controller. A diagram showing a highly reliable and highly available system using a highly reliable controller.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory 2 Memory controller 4 Processor 6 High reliability controller 11, 12, 13 Memory device 21 CRC generation circuit 22 ECC generation circuit 23 Syndrome calculation circuit 24 ECC correction circuit 25 CRC check circuit

Claims (9)

In a controller comprising a processor, a memory control device, and a memory device,
When the processor performs write access to arbitrary data at an arbitrary address, the memory control device, the error detection code CRC determined from the address and the arbitrary data, the error detection code CRC and the arbitrary data An error correction code ECC determined from the data is generated, and an error detection code CRC and an error correction code ECC are written to the memory device together with the arbitrary data;
When the processor performs read access to an arbitrary address, the memory control device reads the error correction code ECC, error detection code CRC, and data written in the memory device, and reads the read error correction code ECC. And a controller for correcting an error in the read error detection code CRC and the read data and detecting whether there is an error in the corrected error detection code CRC and the read data. The controller of claim 1, wherein
The controller, wherein the number of bits of the error detection code CRC is larger than the number of error detection bits detectable by the error correction code ECC. The controller of claim 1, wherein
The controller, wherein the memory device is connected to the memory control device by a plurality of grouped signal lines, and the number of bits of the error detection code CRC is larger than the number of grouped signal lines. In a memory error detection method for detecting a memory error, comprising a processor, a memory control device, and a memory device,
When the processor performs write access to arbitrary data at an arbitrary address, the memory control device, the error detection code CRC determined from the address and the arbitrary data, the error detection code CRC and the arbitrary data An error correction code ECC determined from the data is generated, and an error detection code CRC and an error correction code ECC are written to the memory device together with the arbitrary data;
When the processor performs read access to an arbitrary address, the memory control device reads the error correction code ECC, error detection code CRC, and data written in the memory device, and reads the read error correction code ECC. A memory error detection method, comprising: detecting an error between the read error detection code CRC and the read data based on the method. The memory error detection method according to claim 4,
A memory error detection method, wherein the number of bits of the error detection code CRC is larger than the number of error detection bits detectable by the error correction code ECC. The memory error detection method according to claim 4,
The memory device is connected to the memory control device by a plurality of grouped signal lines, and the number of bits of the error detection code CRC is larger than the number of grouped signal lines. Detection method. In a memory error correction method for correcting a memory error, comprising a processor, a memory control device, and a memory device,
When the processor performs write access to arbitrary data at an arbitrary address, the memory control device, the error detection code CRC determined from the address and the arbitrary data, the error detection code CRC and the arbitrary data An error correction code ECC determined from the data is generated, and an error detection code CRC and an error correction code ECC are written to the memory device together with the arbitrary data;
When the processor performs read access to an arbitrary address, the memory control device reads the error correction code ECC, error detection code CRC, and data written in the memory device, and reads the read error correction code ECC. A memory error correction method, comprising: correcting an error between the read error detection code CRC and the read data based on: The memory error correction method according to claim 7,
A memory error correction method, wherein the number of bits of the error detection code CRC is larger than the number of error detection bits detectable by the error correction code ECC. The memory error correction method according to claim 7,
The memory device is connected to the memory control device by a plurality of grouped signal lines, and the number of bits of the error detection code CRC is larger than the number of grouped signal lines. Correction method.

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