CN111243652B - Parallel redundancy correction circuit - Google Patents
Parallel redundancy correction circuit Download PDFInfo
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- CN111243652B CN111243652B CN202010053416.5A CN202010053416A CN111243652B CN 111243652 B CN111243652 B CN 111243652B CN 202010053416 A CN202010053416 A CN 202010053416A CN 111243652 B CN111243652 B CN 111243652B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention provides a parallel redundancy correction circuit, comprising: the redundancy correction identification generation module is used for comparing an input word address with a word address where a preset redundancy correction bit is located; the correction array module is formed by combining a correction bit control array and a correction value array in a one-to-one correspondence manner; the correction bit control array is controlled by the redundancy correction mark, decodes the correction bit address and generates the correction bit address according to the decoding sequence of the correction bit address in parallel one by one; and the correction module is used for inputting each read word data into the correction bit control array according to the bit synchronization. The invention adopts a parallel processing mode to replace the traditional serial correction mode of correcting one by one according to the redundant bits, thereby reducing the time required in the correction process and correspondingly reducing the power consumption required; the parallel processing mode is adopted to simplify the circuit and layout design, reduce the layout area, and have obvious effect on high-capacity OTP application with more data bits needing redundancy correction.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a parallel redundancy correction circuit.
Background
One time programmable memory (OTP) may have a very small number of write failures or errors due to various reasons when writing data. The conventional countermeasure is to correct the data by using a redundancy method, and various specific ways are available. For example, when performing a bit write operation to a memory, 2 or more bits are written simultaneously to make them redundant to each other, but this approach consumes more area and power consumption. Another approach that is more common is to add a proportion of redundant words for correction beyond the capacity of the OTP, and map the bits and data that need correction into these corresponding redundant correction words. In normal data reading, the correction purpose is achieved by replacing the error bit and the error value in the read data with the correction bit and the correction value set in the redundancy correction word. Therefore, optimization of the redundancy correction circuit becomes a method for improving performance index of the OTP module, such as power consumption, delay and reliability.
In a conventional redundancy correction operation, an input address and a preset redundancy correction address need to be compared to confirm whether the input address needs to be corrected. And after confirming that the data needs to be corrected, replacing the input value by the redundancy correction value to finish the data modification of the input address. If the number of redundancy correction bits preset in the OTP is larger, each input address needs more time to complete comparison with all redundancy correction bit addresses and correction of input values, and the larger the required area is, the larger the power consumption is.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a parallel redundancy correction circuit, which is used for solving the problems of time consuming correction, complex circuit structure, large layout occupation area and large power consumption caused by the conventional serial redundancy correction mode in the prior art.
To achieve the above and other related objects, the present invention provides a parallel redundancy correction circuit including at least:
the redundancy correction identification generation module is used for comparing an input word address with a word address where a preset redundancy correction bit is located and judging whether the input word address and the word address are matched;
the correction array module is formed by combining a correction bit control array and a correction value array in a one-to-one correspondence manner; the correction bit control array is controlled by the redundancy correction mark, decodes the correction bit address and generates the correction bit address according to the decoding sequence of the correction bit address in one-to-one parallel connection; the correction value array is generated by the correction value stored in each redundancy correction word and is parallel to the correction bit control array;
and the correction module is used for inputting each read-in word data into the correction bit control array according to the bit synchronization and replacing the actual value of the read-in data on each correction bit by the correction value on the correction bit.
Preferably, the redundancy correction identifier generating module is configured to compare an input word address with a word address where a preset redundancy correction bit is located, and if the input word address and the word address are matched, the redundancy correction identifier generating module outputs a redundancy correction identifier "1" to indicate that data stored in the input address needs to be corrected; if the two are not matched, the redundancy correction flag is set to '0', and the data representing the input address does not need to be corrected.
Preferably, the redundancy correction identifier generating module outputs a plurality of redundancy correction identifiers according to the comparison between the input word address and the word address where the preset redundancy correction bit is located.
Preferably, the redundancy correction flag generation module is composed of an exclusive-or gate and an and gate.
Preferably, the redundancy correction word stores information that is the correct data value at a particular address in the efuse array.
Preferably, the first bit of the redundancy correction word is defined as a correction value, and the remaining bits are used to define the address of the correction value in the efuse array.
Preferably, the correction module is used for each word data to be read in.
Preferably, the correction array module is formed by connecting bit lines corresponding to the correction bit address decoding modules controlled by the redundancy correction marks in parallel, and each bit line is accompanied by a corresponding correction value line.
Preferably, the correction module comprises a correction bit control and a 2-to-1 multiplexing circuit.
As described above, the parallel redundancy correction circuit of the present invention has the following advantageous effects: the invention adopts a parallel processing mode to replace the traditional serial correction mode of correcting one by one according to the redundant bits, thereby reducing the time required in the correction process and correspondingly reducing the power consumption required; the parallel processing mode is adopted to simplify the circuit and layout design, reduce the layout area, and have obvious effect on high-capacity OTP application with more data bits needing redundancy correction.
Drawings
FIG. 1 is a schematic diagram of a parallel redundancy correction circuit of the present invention;
FIG. 2 is a schematic diagram of a redundancy correction flag generation module according to the present invention;
FIG. 3 is a schematic diagram of a modified array module according to the present invention;
FIG. 4 is a schematic diagram of a correction module according to the present invention;
FIG. 5 is a schematic diagram of a redundancy correction word according to the present invention;
fig. 6 shows a flow chart of a serial redundancy correction mode in the prior art.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The invention provides a parallel redundancy correction circuit, as shown in fig. 1, fig. 1 is a schematic diagram of the parallel redundancy correction circuit of the invention. The parallel redundancy correction circuit includes at least: a redundancy correction flag generation module (i.e. "redundancy correction flag generation module" in fig. 1), which is configured to compare an input word address with a word address where a preset redundancy correction bit is located, and determine whether the two match; the invention further provides a redundancy correction identification generation module which outputs a plurality of redundancy correction identifications according to the comparison between the input word address and the word address where the preset redundancy correction bit is located. The invention further provides a redundancy correction identification generation module, which is used for comparing an input word address with a word address where a preset redundancy correction bit is located, and if the input word address and the word address are matched, the redundancy correction identification generation module outputs a redundancy correction identification device '1', which indicates that data stored in the input address need to be corrected; if the two are not matched, the redundancy correction flag is set to '0', and the data representing the input address does not need to be corrected.
FIG. 2 is a schematic diagram of a redundancy correction flag generating module according to the present invention; the invention further provides a redundancy correction identification generation module which consists of an exclusive OR (not) gate and an AND gate.
The parallel redundancy correction circuit of the present invention further includes: the correction array module is formed by combining a correction bit control array and a correction value array in a one-to-one correspondence manner; as shown in fig. 3, fig. 3 is a schematic diagram of a modified array module according to the present invention, where the modified bit control array is controlled by the redundancy modified identifier, and the modified bit addresses are decoded and then are generated in parallel one by one according to the decoding order of the modified bit addresses; the correction value array is generated by the correction value stored in each redundancy correction word and is parallel to the correction bit control array; further, the correction array module is formed by connecting bit lines corresponding to the correction bit address decoding modules controlled by the redundancy correction marks in parallel, and each bit line is accompanied by a corresponding correction value line.
The invention further provides that the redundancy correction word stores information that is the correct data value at a particular address in the efuse array. In a further aspect of the present invention, the first bit of the redundancy correction word is defined as a correction value, and the remaining bits are used to define an address of the correction value in the efuse array. As shown in fig. 5, fig. 5 is a schematic diagram of a redundancy correction word according to the present invention, and further, the first bit of the redundancy correction word is defined as a correction value, and the remaining bits are used to define an address where the correction value is located in the efuse array.
The parallel redundancy correction circuit of the present invention further includes: and the correction module is used for inputting each read-in word data into the correction bit control array according to the bit synchronization and replacing the actual value of the read-in data on each correction bit by the correction value on the correction bit. The invention further provides that the correction module is used for each word data to be read in. As shown in fig. 4, fig. 4 is a schematic diagram of a correction module according to the present invention, and further, the correction module includes a correction bit control and a 2-to-1 multiplexing circuit.
The specific operation flow of the present invention is divided into three steps (taking the modification of 1 bit of the efuse array as an example), as shown in fig. 1:
step one, judging: it is confirmed whether the contents stored in the input address need to be corrected. The input address is divided into two parts: the word address and the bit address are compared with the word address where the preset redundancy correction bit is located. As shown in fig. 2, if the two match, a redundancy correction flag "1" is output, indicating that the data stored in the input address needs to be corrected; if there is no match, the word redundancy correction flag is set to "0", i.e., the data for the input address need not be corrected. Thus, in the redundancy correction operation, each time an input address is subjected to a redundancy correction operation, 1 redundancy correction flag is generated for a redundancy correction bit (which may not be corrected, and thus may be more than 1) that has been already preset, the correction flag having a value of "1" or "0" depending on whether or not the word addresses of both the input address and the redundancy correction address match.
Step two, preparation: and respectively carrying out merging operation on the addresses and the data of all the correction bits. The structure of a redundancy correction word is shown in fig. 5. The first bit defines the correction value and the other bits describe the address of the correction value in the efuse array, i.e. the redundant correction word stores information that is the correct data value at a particular address in the efuse array. In order to realize parallel correction of all bits in an input word address, decoding each prestored correction address under the control of each redundancy correction mark obtained in the first step, and connecting the obtained correction bits in parallel one by one according to the decoding sequence to generate a correction bit control array; simultaneously, correction values stored in each redundancy correction word are synchronously generated into a correction value array parallel to the correction control array, and the correction value arrays are correspondingly combined together one by one to form a correction array. As shown in fig. 3.
Step three, correction: and carrying out parallel correction operation on the data content of the input word address according to the bits. And inputting each read word data into the correction control array according to the bit synchronization, and replacing the actual value of the read data on each correction bit by the correction value on each correction bit to complete the redundancy correction process of the read data.
The bit structure of the redundancy correction word of the present invention is shown in fig. 5. In conventional redundancy correction operations, the address bits of an input word are compared with the address bits of a redundancy correction word one by one, and if they match, the correction operation is performed again. The invention does not adopt the mode of comparing all address bits at the same time, but separates the respective word address and bit address in the addresses of the input word and the redundancy correction word, compares the word addresses of the input word and the redundancy correction word, and outputs an identification for judging whether the input address needs correction (namely, the bit address of the input word does not participate in comparison). If the address bit of the input word is the same as the word address in the address of the redundant correction word, setting the correction mark to be '1', and controlling the subsequent correction operation according to the correction mark; if the two word addresses are different, a correction flag "0" is output, and in the subsequent correction operation, bit address comparison is not performed any more, and the input word is directly output. In the correction operation, as more than 1 data bits need to be corrected, the invention adopts a single-stage parallel processing mode, and the correction bits and the correction values in all redundancy correction words are processed in parallel to form a correction array. I.e. using the obtained read digital address and the correction identity of the redundant correction word address, for each input data the control generates a correction array comprising all correction bits and correction values. And simultaneously, reading the data from the input address, namely, the data values on all bits, performing parallel mux operation with all bits in the correction array, and replacing the data values on the corresponding data bits with the correction bits and the correction values to complete the correction of all the data bits of the input word.
Taking an efuse with a preset redundancy modifier as an example, each modifier structure is shown in fig. 5. If the serial redundancy correction method shown in fig. 6 is adopted, that is, the word address of each input data is compared and matched with the word address where the N redundancy correction bits are located, N correction flags are generated. If the comparison results are the same, the data on the corresponding data bit is required to be corrected; if not, this indicates that the input data does not need to be modified. After the N correction matching operations are completed, N corresponding correction identifications are generated; and then, performing N serial correction operations controlled by the correction identifications to complete redundancy correction of the data stored in the 1 input addresses. Therefore, time is required to complete the correction operation: t (T) delay ＝T compare (matching week)Phase) +n×t repair (correction period).
If the redundancy correction operation of the parallel connection mode is adopted, comparing and matching the word address of each input data with the word address where n redundancy correction bits are positioned, and generating n correction marks; all redundant correction bits and correction values are connected in parallel under control of these correction flags to produce a correction array. Then, the input data bits are directly input into the correction array, and the data bit correction operation corresponding to the n redundant bits is completed in parallel. Therefore, time is required to complete the correction operation: t (T) delay ＝T compare (matching period) +1*T repair (correction period).
As can be seen from the comparison of the two correction modes, the parallel correction circuit can reduce the redundant correction operation time, reduce the power consumption required by work, has a simple circuit structure, can simplify the layout design and reduce the layout area.
In summary, the present invention employs a parallel processing mode to complete the correction operation of the data value read from the input address. The basic idea is to perform parallel merging operation on all preset redundancy correction bits (including correction address and correction value information) to generate a correction array including all correction bits and correction values, and then let the actual data (including data bits and input data values) read from the input address pass through the correction array; the actual data value is replaced with the correction value in the array on the corresponding data bit on the array. Therefore, the invention adopts a parallel processing mode to replace the traditional serial correction mode of correcting one by one according to the redundant bits, thereby reducing the time required in the correction process and correspondingly reducing the power consumption required; the parallel processing mode is adopted to simplify the circuit and layout design, reduce the layout area, and have obvious effect on high-capacity OTP application with more data bits needing redundancy correction. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (5)
1. A parallel redundancy correction circuit, comprising:
the redundancy correction identification generation module is used for comparing an input word address with a word address where a preset redundancy correction bit is located and judging whether the input word address and the word address are matched; the redundancy correction identification generation module is used for comparing an input word address with a word address where a preset redundancy correction bit is located, and outputting a plurality of redundancy correction identifications;
the correction array module is formed by combining a correction bit control array and a correction value array in a one-to-one correspondence manner; the correction array module is formed by connecting bit lines corresponding to the correction bit address decoding modules controlled by the redundancy correction marks in parallel, and each bit line is accompanied by a corresponding correction value line;
the correction bit control array is controlled by the redundancy correction mark, decodes the correction bit address and generates the correction bit address according to the decoding sequence of the correction bit address in one-to-one parallel connection; the correction value array is generated by the correction value stored in each redundancy correction word and is parallel to the correction bit control array;
and the correction module is used for inputting each read-in word data into the correction bit control array according to the bit synchronization and replacing the actual value of the read-in data on each correction bit by the correction value on the correction bit.
2. The parallel redundancy correction circuit of claim 1, wherein: the redundancy correction mark generation module is used for comparing an input word address with a word address where a preset redundancy correction bit is located, and if the input word address and the word address are matched, the redundancy correction mark generation module outputs a redundancy correction mark setting '1', which indicates that data stored in the input word address need to be corrected; if the two are not matched, the redundancy correction flag is set to '0', and the data representing the input word address is not required to be corrected.
3. The parallel redundancy correction circuit of claim 1, wherein: the redundancy correction identification generation module consists of an exclusive OR (not) gate and an AND gate.
4. The parallel redundancy correction circuit of claim 1, wherein: the first bit of the redundancy correction word is defined as a correction value, and the remaining bits are used to define the address of the correction value in the efuse array.
5. The parallel redundancy correction circuit of claim 1, wherein: the correction module comprises a 2-selected 1 multiplexing circuit controlled by correction bits.
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| CN202010053416.5A CN111243652B (en) | 2020-01-17 | 2020-01-17 | Parallel redundancy correction circuit |
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| EP1383135A2 (en) * | 2002-07-19 | 2004-01-21 | Broadcom Corporation | System and method for providing one-time programmable memory with fault tolerance |
| CN101996689A (en) * | 2009-08-12 | 2011-03-30 | 台湾积体电路制造股份有限公司 | Memory errors processing method |
| CN109614275A (en) * | 2018-12-12 | 2019-04-12 | 上海华力集成电路制造有限公司 | Redundancy corrects circuit and the redundancy modification method using it |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8363502B2 (en) * | 2010-11-19 | 2013-01-29 | Analog Devices, Inc. | System and method for correcting programming failures in a programmable fuse array |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1383135A2 (en) * | 2002-07-19 | 2004-01-21 | Broadcom Corporation | System and method for providing one-time programmable memory with fault tolerance |
| CN101996689A (en) * | 2009-08-12 | 2011-03-30 | 台湾积体电路制造股份有限公司 | Memory errors processing method |
| CN109614275A (en) * | 2018-12-12 | 2019-04-12 | 上海华力集成电路制造有限公司 | Redundancy corrects circuit and the redundancy modification method using it |
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