CN109741781B

CN109741781B - Data writing and reading method of multi-substrate memory based on triple modular redundancy

Info

Publication number: CN109741781B
Application number: CN201811407648.5A
Authority: CN
Inventors: 赵磊; 伍攀峰; 刘庆民; 张毅; 韩德崇; 王勇
Original assignee: Shandong Institute of Space Electronic Technology
Current assignee: Shandong Institute of Space Electronic Technology
Priority date: 2018-11-23
Filing date: 2018-11-23
Publication date: 2020-07-28
Anticipated expiration: 2038-11-23
Also published as: CN109741781A

Abstract

The invention discloses a data writing and reading method of a multi-substrate memory based on triple modular redundancy, which combines the triple modular redundancy with the multi-substrate memory, and adds a shift operation in the write operation of the triple modular redundancy by utilizing the characteristics of the multi-substrate memory so as to store different segments of spliced data in a single substrate; then adding a shift operation in the triple modular redundancy read operation, wherein the shift direction is opposite to the write operation, so as to recover splicing data; when some substrates have errors, because different fragments of the spliced data are stored in a single substrate, the same data fragment cannot be mistaken, so that the problem of failure of the whole memory caused by the failure of a certain substrate in a multi-substrate memory can be solved through the triple modular redundancy technology, and the safety and the reliability of target data are effectively improved.

Description

Data writing and reading method of multi-substrate memory based on triple modular redundancy

Technical Field

The invention belongs to the technical field of memories, and particularly relates to a data writing and reading method of a multi-substrate memory based on triple modular redundancy.

Background

Triple Modular Redundancy (TMR) is the mainstream anti-SEU hardening design method at present, and the basic principle is to design three repeated circuit modules or units, compare their outputs to decide and select the correct output value, so that even if one module fails, the whole circuit can still work normally.

In order to meet different task requirements, a design method for splicing a plurality of memories (called substrates) with small bit widths (called data fragments, such as 8-bit data lines) into memories with large bit widths (called spliced data, such as 32-bit data lines) is commonly adopted in a computer; or a plurality of small bit wide industrial grade memories are used as substrates and packaged into 1 large bit wide memory, so as to achieve the purpose of saving the PCB space; in the aerospace field, after data line bit width splicing is carried out on a plurality of low-grade substrates, radiation-resistant packaging is carried out in a targeted manner.

Taking an integrated memory with 32-bit data line width formed by splicing 4 pieces of 8-bit data line width substrates as an example, in the current application, a processor or an FPGA adopting a triple modular redundancy technology writes target data into three different addresses in a multi-substrate memory respectively.

It can be seen that a single chip stores the same data segment (e.g. chip 1 stores the lower 7-bit data segment of three addresses), and if 1 chip fails, which results in the data segments of three addresses being all wrong, then the three pieces of concatenated data read from the three addresses are all wrong, and the result of the two-out-of-three decision is also wrong. Other multi-substrate memory and triple modular redundancy techniques may be used in combination similar to the example described above.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a data writing and reading method for a multi-substrate memory based on triple modular redundancy, which can solve the problem of access error caused by an abnormal substrate in the multi-substrate memory.

A data writing and reading method of a multi-substrate memory based on triple modular redundancy is disclosed, wherein a plurality of substrates are spliced into an integrated memory according to a set sequence, and each substrate is provided with 3 addresses; setting the bit width m of the target data to be K times of the bit width n of the substrate data, wherein the writing and reading method comprises the following steps:

firstly, shifting target data for the first time, wherein the shifted bit number is integral multiple L of the bit width of the substrate data, namely n ×L, wherein L < K;

secondly, shifting the target data for the second time, wherein the number of shifted bits is integral multiple M of the bit width of the substrate data, namely n × M, wherein M is not equal to L and M is less than K;

the third step, shifting the target data for the third time, wherein the number of the shifted bits is integral multiple N of the bit width of the substrate data, namely N × N, wherein N is not equal to M is not equal to L, and N is less than K;

fourthly, reading out the data stored in the first address in the integrated memory, and shifting the read data, wherein the number of the shifted bits is n ×L, and the shifting direction is opposite to that of the first step;

fifthly, reading out the data stored in the second address in the integrated memory, and shifting the read data, wherein the number of the shifted bits is n × M, and the shifting direction is opposite to that of the second step;

sixthly, reading out data stored in a third address in the integrated memory, and shifting the read data, wherein the number of shifted bits is N × N, and the shifting direction is opposite to that in the third step;

and seventhly, performing two-out-of-three judgment on the data obtained in the fourth step, the fifth step and the sixth step to obtain final target data.

Preferably, in the first step, the data shifting direction is left shift or right shift.

The invention has the following beneficial effects:

the invention combines the triple modular redundancy with the multi-substrate memory, and adds the shift operation in the write operation of the triple modular redundancy by utilizing the characteristics of the multi-substrate memory, so that different segments of the spliced data are stored in a single substrate; then adding a shift operation in the triple modular redundancy read operation, wherein the shift direction is opposite to the write operation, so as to recover splicing data; when some substrates have errors, because different fragments of the spliced data are stored in a single substrate, the same data fragment cannot be mistaken, so that the problem of failure of the whole memory caused by the failure of a certain substrate in a multi-substrate memory can be solved through the triple modular redundancy technology, and the safety and the reliability of target data are effectively improved.

Drawings

Fig. 1 is a flowchart of a data writing and reading method of a multi-chip memory based on triple modular redundancy according to the present invention.

Detailed Description

The invention is described in detail below by way of example with reference to the accompanying drawings.

As shown in fig. 1, in the data writing and reading method for a multi-substrate memory based on triple modular redundancy of the present invention, a plurality of substrates are spliced into an integrated memory according to a set sequence, and each substrate is provided with 3 addresses. And accessing the multi-substrate memory by adopting a triple modular redundancy technology, and respectively writing and reading target data (namely splicing data) into three addresses. The bit width m of the appointed target data is K times of the bit width n of the substrate data.

In the first step, the target data is shifted for the first time, the number of shifted bits is an integral multiple L (L < K), namely n ×L, of the bit width of the data fragment, the target data can be shifted to the left or right, and the shifted target data is written into the first address from the first substrate of the integrated memory according to the splicing sequence of the substrates.

And secondly, shifting the target data for the second time, wherein the number of shifted bits is integral multiple M (M is not equal to L and M < K) of the bit width of the data fragment, namely n × M.

And thirdly, shifting the target data for the third time, wherein the number of shifted bits is integral multiple N (N is not equal to M is not equal to L, and N is less than K) of the bit width of the data fragment, namely N × N.

And fourthly, reading out the data stored in the first address in the integrated memory, and shifting the read-out data by the number of n ×L, wherein the shifting direction is opposite to that of the first step.

And fifthly, reading the data stored in the second address in the integrated memory, and shifting the read data by n × M, wherein the shifting direction is opposite to that of the second step.

And sixthly, reading the data stored in the third address in the integrated memory, and shifting the read data, wherein the number of the shifted bits is N × N, and the shifting direction is opposite to that in the third step.

The invention fully utilizes the triple modular redundancy technology, solves the problem of failure of the whole memory caused by the fault of a certain substrate in the multi-substrate memory, and effectively improves the safety and reliability of target data.

Example (b):

the target data is illustrated as 0x44332211, where M is 32, N is 8, K is 4, L is 0, M is 1, and N is 2.

In a first step, target data is written to a first address. The target data 0x44332211 is distributed as follows: 0x44 into the substrate 4, 0x33 into the substrate 3, 0x22 into the substrate 2, 0x11 into the substrate 1.

And secondly, circularly right-shifting the target data by 8 bits, and writing the shifted target data into a second address. The target data is shifted to 0x11443322, and is distributed as follows: 0x44 into the substrate 3, 0x33 into the substrate 2, 0x22 into the substrate 1, 0x11 into the substrate 4.

And thirdly, circularly right shifting the target data by 16 bits, and writing the shifted target data into a third address. The target data is shifted to 0x22114433, and the distribution is as follows: 0x44 into the substrate 2, 0x33 into the substrate 1, 0x22 into the substrate 4, 0x11 into the substrate 3.

Assuming here that the substrate 1 is faulty, the data is constantly 0x 00. Then the data in the first address is 0x44332200, the data in the second address is 0x11443300, and the data in the third address is 0x 22114400.

And fourthly, directly reading out the data stored in the first address, wherein the data is 0x 44332200.

In the fifth step, the data stored in the second address is read out and shifted to the left by 8 bits, which is 0x11443300, and is cyclically shifted to the left by 0x 44330011.

In the sixth step, the data stored in the third address is read out and shifted to the left by 16 bits, which is 0x22114400, and is 0x 44002211.

And seventhly, performing third-second judgment on the data obtained in the fourth step, the fifth step and the sixth step, and correcting the error of the substrate 1 to obtain correct target data 0x 44332211.

The technology of combining triple modular redundancy and a multi-substrate memory is verified by reading and writing for more than 300 times, and the work is stable.

In summary, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A data writing and reading method of a multi-substrate memory based on triple modular redundancy is disclosed, wherein a plurality of substrates are spliced into an integrated memory according to a set sequence, and each substrate is provided with 3 addresses; setting the bit width m of original target data to be K times of the bit width n of the substrate data, wherein the writing and reading method comprises the following steps:

firstly, shifting original target data for the first time, wherein the shifted bit number is integral multiple L of the bit width of the substrate data, namely n ×L, wherein L < K;

secondly, shifting the original target data for the second time, wherein the number of the shifted bits is integral multiple M of the bit width of the substrate data, namely n × M, wherein M is not equal to L and M is less than K;

the third step, shifting the original target data for the third time, wherein the number of the shifted bits is integral multiple N of the bit width of the substrate data, namely N × N, wherein N is not equal to M is not equal to L, and N is less than K;

2. The method as claimed in claim 1, wherein the data shifting direction in the first step is left-shift or right-shift.