KR20140039980A - Error bit search circuit, error check and correction circuit therewith, and memory device therewith - Google Patents
Error bit search circuit, error check and correction circuit therewith, and memory device therewith Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/36—Data generation devices, e.g. data inverters
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Abstract
The error detecting and correcting circuit according to an embodiment of the present invention uses an element of the Galois field GF (2 n ) as an substitution value of an error location search equation, and determines that the Chien search unit determines whether there is an error for each bit of the data string. It may include. The Chien search unit calculates the first bit string by multiplying the plurality of elements by the (nk) bit value, and multiplies the plurality of elements by the k bit value to calculate the second bit string, and the first circuit calculated by the calculation circuit. A plurality of Chien search circuits may be included to connect the bit string and the second bit string to calculate an arbitrary element and substitute the error location search equation. The plurality of Chien search circuits may be arranged in a matrix shape along the row direction and the column direction. The first bit column may be provided in a row direction or a column direction, and the second bit column may be provided in a direction different from the first bit column in the row direction and the column direction. Relocation of used bits used as elements and unused bits not used as elements may be performed in a bit space composed of a matrix of the first bit string and the second bit string.
Description
BACKGROUND OF THE
As one of the electrically erasable and programmable nonvolatile semiconductor memory devices (EEPROM), there is a NAND flash memory. The NAND flash memory can store a large amount of information even with a small chip area by using a NAND cell unit in which a plurality of memory cells are connected in series.
In the case of a large memory such as NAND flash memory, the storage characteristics of the memory cell may be lost due to deterioration of the tunnel oxide layer during a plurality of program operations. That is, the stored data may be damaged due to various causes during the process of storing the data in the NAND flash memory. Accordingly, the occurrence rate (error rate) of the error bit may increase. In particular, the error rate tends to increase as the memory capacity is increased and the manufacturing process becomes smaller. Error check and correction (ECC) circuits are used to solve this problem and to improve the performance of flash memory. By mounting the ECC system on a chip, a memory having high reliability can be obtained. Furthermore, after redundant data of an error correcting code is added to the data to be stored, the data is programmed into a data string. In addition, in order to compensate for data in which an error bit has occurred when data is read, the data is corrected based on redundant data of an error correction code.
On the other hand, since the data cannot be output to the outside until the correction operation of the ECC system is completed, it is necessary to shorten the time for completion of the correction operation. To this end, a method of speeding up a BCH (Bose-Chaudhuri-Hocquenghem) code capable of using a hamming code having a high processing time and correcting a higher order has been studied. The BCH code is one of block codes using a Galois field operation. According to a block code such as a BCH code and a Reed-Solomon Code, an error location can be calculated by using an error location search equation. For example, an error location search is made by sequentially substituting each element of a non-zero Galois field into an error location search equation to search for the root of the equation. This root search process is called Chien Search. Techniques for speeding up the search for Chien are described in Japanese Patent Laid-Open No. 2001-044853 (hereinafter referred to as Patent Document 1) and Japanese Patent Laid-Open Publication No. 2001-203587 (hereinafter referred to as Patent Document 2). Japanese Patent Laid-Open Publication No. 2009-100369 (hereinafter referred to as Patent Document 3) discloses a NAND flash memory including an error detection correction circuit.
The technique described in
The error detection correction circuit of
According to the techniques described in
One embodiment of the present invention is to solve the problem that the circuit size of the Chien search unit increases. One embodiment of the present invention can provide an error detection correction circuit and a memory device having a small scale while determining errors in parallel for a plurality of bits.
According to the disclosure of
In order to output the corrected data to the outside at high speed, the data of the error bits included in all bits of the data string including the bit to be read must be corrected at high speed. In order to quickly correct the data of the error bit, a method of simultaneously assigning from the lowest address to the highest address to the Chien search unit may be used. To use this method, the Chien search portion of the error detection correction circuit must include an error position search circuit (SRC circuit) that substitutes a bit position into the error position search equation. In this case, an error location search circuit should be provided to correspond bit by bit.
Fig. 26 is a block diagram showing the configuration of the Chien
As will be described in detail later, a total of 353612 logic circuits are required in the case where correction for 511 bits is collectively performed through the Chien
The error detecting and correcting circuit according to an embodiment of the present invention uses an element of the Galois field GF (2 n ) as an substitution value of an error location search equation, and determines that the Chien search unit determines whether there is an error for each bit of the data string. It may include. According to an embodiment of the present invention, the Chien search unit calculates a first bit string by multiplying a plurality of predetermined elements by a predetermined value of (nk) bits, and multiplies the predetermined plurality of elements by a predetermined value of k bits. A calculating circuit for calculating a second bit string; And a plurality of Chien search circuits connecting the first bit stream and the second bit stream calculated by the calculation circuit to calculate an arbitrary element and substitute the error location search equation. In an embodiment of the present disclosure, the plurality of Chien search circuits may be arranged in a matrix shape along the row direction and the column direction. In an embodiment of the present disclosure, the first bit column may be provided in a row direction or a column direction, and the second bit column may be provided in a direction different from the first bit column in the row direction and the column direction, respectively. In an embodiment of the present invention, relocation of used bits used as elements and unused bits not used as elements may be performed in a bit space including a matrix of the first bit string and the second bit string.
According to another exemplary embodiment of the present invention, an error location search circuit substitutes (2 m -1) elements represented by an m-bit vector on a Galois field GF (2 m ) into an error location search equation, and corresponds to a bit corresponding to each element. An error detection signal may be generated that indicates whether there is an error in the data at the location. According to another embodiment of the present invention, a plurality of error location search circuits are provided with elements, substitute elements in each term of the error location search equation, and calculate an output value by calculating a product of the coefficients and the elements of the error location search equation. It may include a position search circuit of. In another embodiment of the present disclosure, an exclusive OR operation corresponding to each element may be performed on the plurality of output values calculated by the plurality of position search circuits. In another embodiment of the present disclosure, an error detection signal may be generated based on a result of performing an exclusive OR operation.
According to an embodiment of the present disclosure, a bit column may be commonly provided for each of the plurality of Chien search circuits arranged in a matrix shape along the column direction and the row direction. Thus, a line for supplying a signal representing the bit position may not be connected to each of the Chien search circuits. As a result, the number of lines for supplying the signal indicating the bit position to the Chien search circuit can be reduced, and the circuit scale of the Chien search section can be reduced. In addition, since the plurality of Chien search circuits for performing the error determination can be appropriately intensively arranged, the overall circuit scale can be reduced more efficiently.
According to another embodiment of the present invention, the remaining elements are represented by using an element having only a logical value of one bit among the elements of the Galois field. According to another embodiment of the present invention, the number of logic circuits included in the error location search circuit is significantly reduced. Accordingly, according to another embodiment of the present invention, the size of the error location search circuit is reduced, and an error detection correction circuit and a memory device including the reduced size error location search circuit are obtained.
1 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention.
2 is a conceptual diagram illustrating a configuration of code data according to an embodiment of the present invention.
3 is a block diagram illustrating a configuration example of an error detection correction circuit of FIG. 1.
4 is a block diagram illustrating a configuration example of the Chien search unit of FIG. 3.
5 is a block diagram illustrating a configuration example of the Chien search circuit of FIG. 4.
FIG. 6 is a block diagram illustrating an example of a configuration of an error position search equation calculator of FIG. 5.
7 is a diagram showing a part of the elements of the
FIG. 8 is a diagram for explaining contents of an output signal of the S calculator, an output signal of the P calculator, and an output signal of the Q calculator.
FIG. 9 is a diagram for describing processing contents of the Chien search unit of FIG. 4.
10 to 12 are diagrams for explaining the concept of error search bit rearrangement according to an embodiment of the present invention.
FIG. 13 is a diagram for describing an example of a calculation process of the syndrome calculation circuit of FIG. 3.
14 to 15 are conceptual views illustrating an example of the layout of the Chien search circuit of FIG. 4.
FIG. 16 is another diagram for describing an example of a calculation process of the syndrome calculation circuit of FIG. 3.
17 to 18 are other conceptual diagrams for describing an example of the layout of the Chien search circuit of FIG. 4.
19 is a diagram for explaining a vector component of Z [8: 0].
20 is a diagram for explaining a process of outputting Z [8: 0], which is a result of multiplication of X [8: 0] and Y [8: 0].
FIG. 21 is a diagram for explaining a p generation circuit that performs a logic expression and a logic operation for obtaining values of p [0] to p [7] from a combination of y [0] to y [8].
Fig. 22 shows the coefficient vector e 1 of X [8: 0] = (1, 0, 1, 0, 1, 0, 1, 0, 1) using only one bit with an element having a logical 1 value. This figure explains the structure of the logical expression to find the product.
FIG. 23 is a block diagram illustrating another configuration example of the error detection correction circuit of FIG. 1.
24 is a block diagram illustrating an example of a configuration of the Chien search unit of FIG. 23.
25 is a block diagram illustrating an example of a configuration of an error position search circuit of FIG. 24.
26 is a block diagram illustrating a configuration of a Chien search unit according to the prior art.
The foregoing characteristics and the following detailed description are all illustrative for ease of explanation and understanding of the invention. That is, the present invention is not limited to this embodiment and may be embodied in other forms. The following embodiments are merely examples to fully disclose the present invention, and are descriptions for conveying the present invention to those skilled in the art to which the present invention pertains. Therefore, when there are several methods for implementing the components of the present invention, it is necessary to make clear that the implementation of the present invention can be implemented in any of these methods or in the same.
It is to be understood that, in the context of this specification, when reference is made to a configuration including certain elements, or when it is mentioned that a process includes certain steps, other elements or other steps may be included. That is, the terms used in the present specification are only for describing specific embodiments and are not intended to limit the concept of the present invention. Further, the illustrative examples set forth to facilitate understanding of the invention include its complementary embodiments.
The terms used in this specification are meant to be understood by those of ordinary skill in the art to which this invention belongs. Commonly used terms should be construed in a manner consistent with the context of this specification. Also, terms used herein should not be construed as overly ideal or formal meanings unless the meanings are clearly defined. Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
1 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention. The nonvolatile
The
The
Meanwhile, during the program operation of the nonvolatile
In an embodiment of the present invention, it is assumed that the extended information data string in which the error
Meanwhile, in the process of performing error detection and correction on 320-bit code data according to an embodiment of the present invention, the correction unit is not formed of a 256-bit information data string included in the 320-bit code data, but virtually. It is formed of extended information data extended to 448 bits. For a detailed description of the expansion of the data, the description of FIG. 2 is first mentioned.
2 is a conceptual diagram illustrating a configuration of code data according to an embodiment of the present invention. 2 (1) illustrates the configuration of the code data D1. The length of the sign data D1 stored in or read from the
On the other hand, Fig. 2 (2) explains the configuration of extension code data D2. The length of the extended code data D2 processed in the process of the syndrome is calculated by the error detection and
2 (3) explains the configuration of the extension information data D21. The extended information data D21 may include divided information data D23a, D23b, ..., in which the information data D11 is divided into predetermined bit units. In addition, the extended information data D21 may include, for example, additional data D24a, D24b, ... that includes one or more bits having a value fixed to a logical zero.
The division information data D23a, D23b, ... may be obtained by dividing the information data D11 in bit order. Alternatively, the division information data D23a, D23b, ... may be obtained by changing the order of the bits of the information data D11, that is, rearranging the bits and then dividing them. The additional data D24a, D24b, ... are 192 bits in total. The position of each bit of the information data D11 is any one of 0 to 255. On the other hand, the position of each bit of the division information data D23a, D23b, ... is any one of 0 to 447. In addition, the position of each bit of additional data D24a, D24b, ... is any one of 0th to 447th. However, the position of each bit of the division information data D23a, D23b, ... is different from the position of each bit of the additional data D24a, D24b, ....
The position of each bit (or the position after each bit is rearranged) of the extension information data D21 may be set in advance. In addition, the configuration of the logic structure, line connection, and the like of the error detection and
The word "virtual" here means that a circuit for processing bits not included in the information data D11 but added only to the extended information data D21 is not actually added to the processing portion of the extended information data D21. do. For example, the addition of the elements of the Galois field corresponds to an exclusive OR operation, and the process of adding the added bits to the predetermined data may be omitted when the added bits are always logical zeros. This is because even when bits are added, it is sometimes unnecessary to add a configuration or a line.
The nonvolatile
In addition, during program operation of the nonvolatile
The
The
The row /
In a read operation according to an embodiment of the present invention, the cell data (Cell Data, sign data D1) of the
In the program operation, the cell data of the
3 is a block diagram illustrating an example of a configuration of the error
The
The
The error
The
The
4 is a block diagram illustrating a configuration example of the
First, the configuration of each
The error location search
Next, the configuration of the error location search
In FIG. 4, the
Next, the contents of the signals S0, S1, S2, S3, S4, S5, S6, S7, and S8 output by the
For example, an element α 9 corresponding to
FIG. 8 is a diagram for explaining contents of the output signal of the
The
α 0 , α 1 , α 2 ,. The nine elements of, α 8 may be called basis values. In order to reduce unnecessary wiring, in the embodiment of FIG. 4, the base value is divided into two groups of signals (called P group and Q group). In addition, the signal group of the P group and the Q group is divided into 32 and 16 classifications, respectively, according to a value called a quasi-base value (that is, the signal group is divided into a total of 512 classifications). In addition, a signal corresponding to one classification of a group is provided to one
FIG. 9 is a diagram for describing processing contents of the Chien search unit of FIG. 4. Referring to FIGS. 9 (1) and 9 (2), the quasi-base value may include 5-bit values p0 to p31 of the P group and 4-bit values q0 to q15 of the Q group. p0 to p31 may have values obtained by using the base values α 4 , α 5 , α 6 , α 7 , α 8 of the upper 5 bits of x. Specifically, p0 to p31 are x = 9'b00000_0000, 9'b00001_0000, 9'b00010_0000,... , 9'b11111_0000. Meanwhile, q0 to q15 may have values obtained by using the base values α 0 , α 1 , α 2 , α 3 of the lower 4 bits of x. In an embodiment of the present invention, based on the combination of the bit string signals dpj and dqk generated according to the quasi-base values of the P group and the Q group, respectively, α 0 , α 1 , α 2 ,... , 9 elements of α 8 and the remaining elements α 9 ,..., α 510 can be generated. The bit string signals dpj and dqk of the P group and the Q group may be calculated by the
The
The signals dp0, dp1, dp2,..., Dp31 calculated by the
The
The signals dq0, dq1, dq2,..., Dq15 calculated by the
However, the configuration of the bit string signals dpj and dqk is not limited to the above embodiments. That is, the wiring directions of the bit column signal dpj and the bit column signal dqk may be reversed with respect to the rows and columns. Alternatively, the number of wirings of the bit string signal dpj or the bit string signal dqk may be changed. In an embodiment of the present invention, the plurality of
The bit
The circuit for correcting n errors by employing the Galois field GF (2 m ) is an error position search equation Λ (x) = e n x n +... Substituting each element (α i ) (i = 0, 1, 2,…, 2 m −2) of the Galois field GF (2 m ) into the variable x of + e 2 x 2 + e 1 x 1 + e 0 It is then determined whether or not Λ (x) = 0. The value of the error location search equation (Λ (x)) is the error of each element (α 0 , α 1 , α 2 ,…, α t-2 ) of the Galois field GF (2 m ) (where t = 2 m ). It is calculated by substituting in the position search equation Λ (x).
According to the prior art, each element α i (i = 0, 1, 2,..., 2 m ) of the Galois field GF (2 m ) in one circuit that yields the error position search equation Λ (x) -2) were assigned sequentially. Thus, in one period of the clock signal, only one error location search equation Λ (x) for one element was calculated. On the other hand, according to the configuration disclosed in
Furthermore, according to an embodiment of the present invention, each element α i (i = 0, 1, 2,..., 2 m −2) of the Galois field GF (2 m ) may include the plurality of
In one embodiment of the present invention, the plurality of
10 to 12 are diagrams for explaining the concept of error search bit rearrangement according to an embodiment of the present invention. 10 illustrates input and output during decoding during the parallel Chien search process. That is, FIG. 10 illustrates input / output data of an error correction system using parallel Chien search according to an embodiment of the present invention. An example of a simple 4-3 code is shown on the right side of FIG. 10, and the final error information Output is output as a 7-bit bit string. FIG. 11 illustrates an example of using the system of FIG. 10 and sets a fixed bit without using a part of 4-bit data.
In the example of Fig. 11, the first two bits of the 4-bit data are set to the fixed bits (the two previous bits are fixed to 00). Parity data is generated for 4-bit data including fixed bits during the encoding process. In the example of FIG. 11, parity data of 100 is generated as in the example of FIG. 9. It can be seen that the error correction apparatus works similarly in the decoding process and works without any problem even when a fixed bit is included. In the example of FIG. 11, although the preceding two bits are set to the fixed bits, there will be no problem in the operation of the error correcting device even if any of the bits are set to the fixed bits.
If a fixed bit is included, it is important that no error is detected in the fixed bit. In Fig. 12, blocks surrounded by squares represent the Chien search circuit. When the Chien search circuit is arranged as shown in FIG. 12 (1), if the fixed bit is set at
By way of example, it is known that for the inputs X1 to X7 of the encoder, the syndrome can be computed using an expression of exclusive OR, XOR, symbol ^, such as S1 = X1 ^ X3 ^ X4 ^ X7. However, when X4 is a fixed bit fixed to 0, the term X4 is deleted from the equation and the syndrome may be expressed as S1 = X1 ^ X3 ^ X7. Thus, if there is a fixed bit, the logic circuit in the syndrome calculation circuit can also be omitted. However, the parity data is generated based on the information data, and the bits forming the parity data cannot be set as fixed bits. Thus, parity data is excluded from the discussion.
According to the above description, if the bit not used in the matrix of 2 n units is appropriately selected and the selected bit is set to the fixed bit, the size of the Chien search circuit can be minimized.
FIG. 13 is a diagram for explaining an example of a calculation process of the
FIG. 13 illustrates a case where the error
FIG. 14 shows that the error
15 illustrates a case where the error
FIG. 16 is another diagram for describing an example of a calculation process of the syndrome calculation circuit of FIG. 3. 17 to 18 are other conceptual diagrams for describing an example of the arrangement of the Chien search circuit of FIG. 4. In particular, FIGS. 16 to 18 illustrate a case where the error
When the code data D1 is extended to the extended code data D2, 256-bit information data D11 is rearranged at a predetermined position on the 448-bit extended information data D21. At the same time, a bit with a fixed logical value is added to the empty 192 bits of the extended code data D2. In addition, the calculation formula for calculating the syndrome is changed to correspond to the relocated bits to maintain mathematical equivalence. For example, if the positions of
According to FIG. 18, the bits used are allocated in order from the cell at the upper left. However, the bit (
According to an embodiment of the present invention, relocation may be performed such that unused or used bits are constantly collected in data formed of bits of 2 n or more and less than 2 n + 1 −1. In addition, the logic structure of the parity generating unit or the syndrome generating unit may be rearranged together to maintain logic consistency. In particular, having the additional bits have a fixed value of logical zero does not increase the cost of relocation.
On the other hand, the configuration of an embodiment of the present invention is not limited to those described so far. The number of bits of the information data or parity data can be changed, each block of the configuration shown in the block diagram can be further divided, and a plurality of blocks can be integrated. In addition, the error detection correction circuit of the present invention is not limited to the semiconductor memory. The error detection correction circuit of the present invention can be used in a process in which information is recorded on another type of recording medium and information is read from the recording medium.
The following is a description of another embodiment of the present invention. First, the multiplication performed in the system employing the
X [8: 0] = (x8, x7, x6, x5, x4, x3, x2, x1, x0)
Y [8: 0] = (y8, y7, y6, y5, y4, y3, y2, y1, y0)
The two vectors can be expressed as follows according to the polynomial expression method.
X [8: 0] = x8 × X 8 + x7 × X 7 + x6 × X 6 + x5 × X 5 + x4 × X 4 + x3 × X 3 + x2 × X 2 + x1 × X 1 + x0
Y [8: 0] = y8 × X 8 + y7 × X 7 + y6 × X 6 + y5 × X 5 + y4 × X 4 + y3 × X 3 + y2 × X 2 + y1 × X 1 + y0
X, x0 to x8, and y0 to y8 each have a value of 0 or 1, respectively.
Z [8: 0], which is the result of multiplying X [8: 0] and Y [8: 0], can be expressed as follows. However, the multiplication sign is omitted in the following expression.
Z [8: 0] = (x8y8) × X 16
+ (x8y7 + x7y8) × X 15
+ (x8y6 + x7y7 + x7y8) × X 14
+ (x8y5 + x7y6 + x6y7 + x5y8) × X 13
+ (x8y4 + x7y5 + x6y6 + x5y7 + x4y8) × X 12
+ (x8y3 + x7y4 + x6y5 + x5y6 + x4y7 + x3y8) × X 11
+ (x8y2 + x7y3 + x6y4 + x5y5 + x4y6 + x3y7 + x2y8) × X 10
+ (x8y1 + x7y2 + x6y3 + x5y4 + x4y5 + x3y6 + x2y7 + x1y8) × X 9
+ (x8y0 + x7y1 + x6y2 + x5y3 + x4y4 + x3y5 + x2y6 + x1y7 + x0y8) × X 8
+ (x7y0 + x6y1 + x5y2 + x4y3 + x3y4 + x2y5 + x1y6 + x0y7) × X 7
+ (x6y0 + x5y1 + x4y2 + x3y3 + x2y4 + x1y5 + x0y6) × X 6
+ (x5y0 + x4y1 + x3y2 + x2y3 + x1y4 + x0y5) × X5
+ (x4y0 + x3y1 + x2y2 + x1y3 + x0y4) × X 4
+ (x3y0 + x2y1 + x1y2 + x0y3) × X 3
+ (x2y0 + x1y1 + x0y2) × X 2
+ (x1y0 + x0y1) × X 1
+ (x0y0)
19 is a diagram for explaining a vector component of Z [8: 0]. In particular, Fig. 19 (1) shows the product of the vector component of X [8: 0] and the vector component of Y [8: 0]. 10 (2) also shows a logical formula for calculating each bit of Z [8: 0] from a0 to a16 using an exclusive OR operation.
In Fig. 10 (1), the product of the vector component of X [8: 0] and the vector component of Y [8: 0] is added along the longitudinal direction to obtain coefficients of each term of the polynomial representation of Z [8: 0]. a0 to a16 mean coefficients corresponding to each of the X 0 to X 16 terms of the polynomial representation of Z [8: 0]. That is, each of the following equations is established.
a16 = x8y8,
a15 = x8y7 + x7y8,
a14 = x8y6 + x7y7 + x7y8,
a13 = x8y5 + x7y6 + x6y7 + x5y8,
a12 = x8y4 + x7y5 + x6y6 + x5y7 + x4y8,
a11 = x8y3 + x7y4 + x6y5 + x5y6 + x4y7 + x3y8,
a10 = x8y2 + x7y3 + x6y4 + x5y5 + x4y6 + x3y7 + x2y8,
a9 = x8y1 + x7y2 + x6y3 + x5y4 + x4y5 + x3y6 + x2y7 + x1y8,
a8 = x8y0 + x7y1 + x6y2 + x5y3 + x4y4 + x3y5 + x2y6 + x1y7 + x0y8,
a7 = x7y0 + x6y1 + x5y2 + x4y3 + x3y4 + x2y5 + x1y6 + x0y7,
a6 = x6y0 + x5y1 + x4y2 + x3y3 + x2y4 + x1y5 + x0y6,
a5 = x5y0 + x4y1 + x3y2 + x2y3 + x1y4 + x0y5,
a4 = x4y0 + x3y1 + x2y2 + x1y3 + x0y4,
a3 = x3y0 + x2y1 + x1y2 + x0y3,
a2 = x2y0 + x1y1 + x0y2,
a1 = x1y0 + x0y1,
a0 = x0y0
Therefore, Z [8: 0] can be expressed as a polynomial using a0 to a16 as follows.
Z [8: 0] = a16 × X 16 + a15 × X 15 + a14 × X 14 + a13 × X 13 + a12 × X 12 + a11 × X 11 + a10 × X 10
+ a9 × X 9 + a8 × X 8 + a7 × X 7 + a6 × X 6 + a5 × X 5 + a4 × X 4 + a3 × X 3 + a2 × X 2 + a1 × X 1 + a0
For example, the Galois field to the irreducible polynomial (primitive polynomial) in GF (2 9) X 9 +
X 9 = X 4 +1,
X 10 = X × X 9 = X 5 + X,
X 11 = X × X 10 = X 6 + X 2 ,
X 12 = X × X 11 = X 7 + X 3 ,
X 13 = X × X 12 = X 8 + X 4 ,
X 14 = X × X 13 = X 9 + X 5 = X 5 + X 4 +1,
X 15 = X × X 14 = X 6 + X 5 + X,
X 16 = X × X 15 = X 7 + X 6 + X 2
Substituting the higher-order terms into the polynomial for Z [8: 0] using a0 to a16 and solving the equation, the following polynomial is obtained.
Z [8: 0] = (a8 + a13) × X 8 + (a7 + a12 + a16) × X 7 + (a6 + a11 + a15 + a16) × X 6
+ (a5 + a10 + a14 + a15) × X 5 + (a4 + a9 + a13 + a14) × X 4 + (a3 + a12) × X 3
+ (a2 + a11 + a16) × X 2 + (a1 + a10 + a15) × X 1 + (a0 + a9 + a14)
On the other hand, Z [8: 0] may be expressed as Z [8: 0] = (z8, z7, z6, z5, z4, z3, z2, z1, z0) according to a vector expression method. Using the vector representation of Z [8: 0], Z [8: 0] is also represented by the following polynomial:
Z [8: 0] = z8 × X 8 + z7 × X 7 + z6 × X 6 + z5 × X 5 + z4 × X 4 + z3 × X 3 + z2 × X 2 + z1 × X 1 + z0
Therefore, each bit z [8] to z [0] of Z [8: 0] is represented as follows.
z8 = a8 + a13,
z7 = a7 + a12 + a16,
z6 = a6 + a11 + a15 + a16,
z5 = a5 + a10 + a14 + a15,
z4 = a4 + a9 + a13 + a14,
z3 = a3 + a12,
z2 = a2 + a11 + a16,
z1 = a1 + a10 + a15,
z0 = a0 + a9 + a14
That is, multiplication of two vectors may be performed as follows: (a) An exclusive OR operation is performed on elements of the upper bits other than the lower m bits (m = 8 in the example above) of the multiplication result. (b) convert the result of the exclusive OR operation to a vector representation of the lower m bits based on a given raw polynomial. (c) An exclusive OR operation is performed using each element of the lower m bits converted to the vector representation and each element of the result obtained by performing an exclusive OR on each of the lower m bits of the multiplication result.
When steps (a), (b), and (c) are performed, each bit z [0] to z [8] of Z [8: 0] is equal to each bit of X [8: 0] and Y [8: 0] is represented as the result of adding the combinations of the sum of the multiplication results of each bit (i.e., any of a0 to a16).
To multiply each bit of X [8: 0] by each bit of Y [8: 0], 81 (= 9 × 9) logical AND circuits are required. An exclusive OR circuit can be used to find the sum of the multiplication result of each bit of X [8: 0] and each bit of Y [8: 0] (that is, any one of a0 to a16). In order to find all a0 to a16, 64 exclusive logical OR circuits are required.
In addition, an exclusive OR circuit can be used to obtain each bit of Z [8: 0] from a0 to a16. Fig. 19 (2) shows a logical expression for obtaining each bit of Z [8: 0] by performing an exclusive OR operation on a0 to a16. In Fig. 19 (2), the symbol ^ means an exclusive OR operation. In Fig. 19 (2), each bit of Z [8: 0] is z [0] to z [8], and a0 to a16 corresponding to the coefficient of the polynomial representation of Z [8: 0] are a [0. ] To a [16]. Nineteen exclusive OR circuits are needed to compute the equation shown in FIG. 19 (2).
According to the above description, each bit of Z [8: 0] is the sum of 81 multiplication circuits for multiplying each bit of X [8: 0] and each bit of Y [8: 0], i.e. , a0 to a16) to obtain 64 exclusive OR circuits and 19 exclusive OR circuits for performing the operation according to the logical expression of FIG. 19 (2). That is, each bit of Z [8: 0] can be obtained by a total of 164 logic circuits (= 81 + 64 + 19).
On the other hand, when collective correction is performed for 511 bits in order to speed up data correction, each of the position search circuits 339_1 to 339_510 in FIG. 26 has coefficients e 4 , e 3 , e 2 , and e of the error position search equation. Multiply 1 ) by the power of the bit position (x) and find the sum of the multiplication results. As mentioned earlier, each bit of Z [8: 0] can be obtained by a total of 164 logic circuits. Also, as an example, the position search circuit 339_0 for
Another embodiment of the present invention includes a plurality of error location search circuits that substitute elements of
Here is the Galois field GF (2 9) and the element of the Galois field GF (2 9) of the case where the use BCH code capable of correcting an error of four bits: a description of (the X mentioned above [80]) . For explanation, reference is again made to the diagram of FIG. 7. FIG. 7 can show the elements of Galois field GF (2 9 ) when X 9 + X 4 +1 is employed as the primitive polynomial. As mentioned above, in FIG. 7, the GF (2 9 ) elements of the Galois field are represented by a polynomial expression method and a vector expression method.
In FIG. 7, nine elements of α 0 to α 8 are elements in which only one bit has a value of logical one. Nine elements of α 0 to α 8 are expressed as follows according to a vector representation and a binary representation.
α 0 = (0, 0, 0, 0, 0, 0, 0, 0, 1) = 9'b000000001,
α 1 = (0, 0, 0, 0, 0, 0, 0, 1, 0) = 9'b000000010,
α 2 = (0, 0, 0, 0, 0, 0, 1, 0, 0) = 9'b000000100,
α 3 = (0, 0, 0, 0, 0, 1, 0, 0, 0) = 9'b000001000,
α 4 = (0, 0, 0, 0, 1, 0, 0, 0, 0) = 9'b000010000,
α 5 = (0, 0, 0, 1, 0, 0, 0, 0, 0) = 9'b000100000,
α 6 = (0, 0, 1, 0, 0, 0, 0, 0, 0) = 9'b001000000,
α 7 = (0, 1, 0, 0, 0, 0, 0, 0, 0) = 9'b010000000,
α 8 = (1, 0, 0, 0, 0, 0, 0, 0, 0) = 9'b100000000
α 0 to α 8 are linearly independent elements that cannot be represented using other elements.
Further, by using the original polynomial α 9 = α 4 +1 to express the remaining 502 elements α 9 to α 510 other than α 0 to α 8 as polynomials, the following equations are obtained.
α 9 = α 4 +1,
α 10 = α 9 α 1 = (α 4 +1) α = α 5 + α,
α 11 = α 10 α 1 = (α 5 + α) α = α 6 + α 2 ,
α 12 = α 11 α 1 = (α 6 + α 2 ) α = α 7 + α 3 ,
α 13 = α 12 α 1 = (α 7 + α 3 ) α = α 8 + α 4 ,
α 14 = α 13 α 1 = (α 8 + α 4 ) α = α 9 + α 5 = α 5 + α 4 +1,
α 15 = α 14 α 1 = (α 5 + α 4 +1) α = α 6 + α 5 + α,
α 16 = α 15 α 1 = (α 6 + α 5 + α) α = α 7 + α 6 + α 2 ,
α 17 = α 16 α 1 = (α 7 + α 6 + α 2 ) α = α 8 + α 7 + α 3 ,
α 18 = α 17 α 1 = (α 8 + α 7 + α 3 ) α = α 9 + α 8 + α 4 = α 4 + 1 + α 8 + α 4 = α 8 +1
α 19 = α 18 α 1 = (α 8 +1) α = α 9 + α = α 4 + α + 1
...
α 510 = α 509 α 1 = (α 7 + α 2 ) α = α 8 + α 3
That is, the elements of α 9 to α 510 can be obtained by adding two or more of nine elements of α 0 to α 8 , respectively.
The following is a description of a method of generating an element in which only one bit has a logical value of 1. This method can be used to calculate Z [8: 0] by the product of X [8: 0] and Y [8: 0], for example, the product of coefficients and elements. For example, X [8: 0] may correspond to elements α 0 to α 510 of gallua field GF (2 9 ). In addition, Y [8: 0] may correspond to a coefficient (any one of e 1 , e 2 , e 3 , and e 4 depending on the order) of the error location search equation. In addition, Z [8: 0] may correspond to the product of the coefficient and the element (e 1 x, e 2 x 2 , e 3 x 3 , e 4 x 4 depending on the order).
As an example, the process of finding e 1 x out of the product of coefficients and elements is described. As mentioned above, z [0] among Z [8: 0] may be represented by z [0] = a0 + a9 + a14. Using elements of X [8: 0] and Y [8: 0], z [0] is expressed as
z [0] = y0x0 + y8x1 + y7x2 + y6x3 + y5x4 + y4x5 + (y3 + y8) x6 + (y2 + y7) x7 + (y1 + y6) x8
If y3 + y8 is replaced by p0, y2 + y7 is replaced by p1, and y1 + y6 is replaced by p2, z [0] is expressed as follows.
z [0] = y0x0 + y8x1 + y7x2 + y6x3 + y5x4 + y4x5 + p0x6 + p1x7 + p2x8
And, z [1] among Z [8: 0] may be expressed as z [1] = a1 + a10 + a15. Using elements of X [8: 0] and Y [8: 0], z [1] is expressed as
z [1] = y1x0 + y0x1 + y8x2 + y7x3 + y6x4 + y5x5 + y4x6 + (y3 + y8) x7 + (y2 + y7) x8
If y3 + y8 is replaced by p0 and y2 + y7 is replaced by p1, z [1] is expressed as follows.
z [1] = y1x0 + y0x1 + y8x2 + y7x3 + y6x4 + y5x5 + y4x6 + p0x7 + p1x8
In addition, z [2] among Z [8: 0] may be expressed as z [2] = a2 + a11 + a16. Using elements of X [8: 0] and Y [8: 0], z [2] is expressed as
z [2] = y2x0 + y1x1 + y0x2 + y8x3 + y7x4 + y6x5 + y5x6 + y4x7 + (y3 + y8) x8
If y3 + y8 is replaced with p0, z [2] is expressed as follows.
z [2] = y2x0 + y1x1 + y0x2 + y8x3 + y7x4 + y6x5 + y5x6 + y4x7 + p0x8
Z [3] among Z [8: 0] may be expressed as z [3] = a3 + a12. Using elements of X [8: 0] and Y [8: 0], z [3] is expressed as
z [3] = y3x0 + y2x1 + y1x2 + y0x3 + y8x4 + y7x5 + y6x6 + y5x7 + y4x8
Z [4] among Z [8: 0] may be expressed as z [4] = a4 + a9 + a13 + a14. Using elements of X [8: 0] and Y [8: 0], z [4] is expressed as
z [4] = y4x0 + (y3 + y8) x1 + (y2 + y7) x2 + (y1 + y6) x3 + (y0 + y5) x4
+ (y4 + y8) x5 + (y3 + y7 + y8) x6 + (y2 + y6 + y7) x7 + (y1 + y5 + y6) x8
Replace y3 + y8 with p0, y2 + y7 with p1, y1 + y6 with p2, y0 + y5 with p3, y4 + y8 with p4, y3 + y7 + y8 with p5, y2 Substituting + y6 + y7 with p6 and y1 + y5 + y6 with p7 z [4] is expressed as:
z [4] = y4x0 + p0x1 + p1x2 + p2x3 + p3x4 + p4x5 + p5x6 + p6x7 + p7x8
Z [5] among Z [8: 0] may be expressed as z [5] = a5 + a10 + a14 + a15. Using elements of X [8: 0] and Y [8: 0], z [5] is expressed as
z [5] = y5x0 + y4x1 + (y3 + y8) x2 + (y2 + y7) x3 + (y1 + y6) x4
+ (y0 + y5) x5 + (y4 + y8) x6 + (y3 + y7 + y8) x7 + (y2 + y6 + y7) x8
Y3 + y8 to p0, y2 + y7 to p1, y1 + y6 to p2, y0 + y5 to p3, y4 + y8 to p4, y3 + y7 + y8 to p5, y2 + y6 Substituting + y7 with p6, z [5] is expressed as
z [5] = y5x0 + y4x1 + p0x2 + p1x3 + p2x4 + p3x5 + p4x6 + p5x7 + p6x8
Z [6] among Z [8: 0] may be expressed as z [6] = a6 + a11 + a15 + a16. Using elements of X [8: 0] and Y [8: 0], z [6] is expressed as
z [6] = y6x0 + y5x1 + y4x2 + (y3 + y8) x3 + (y2 + y7) x4
+ (y1 + y6) x5 + (y0 + y5) x6 + (y4 + y8) x7 + (y3 + y7 + y8) x8
In the above formula, replace y3 + y8 with p0, y2 + y7 with p1, y1 + y6 with p2, y0 + y5 with p3, y4 + y8 with p4, y3 + y7 + y8 with p5 and z [ 6] is expressed as follows.
z [6] = y6x0 + y5x1 + y4x2 + p0x3 + p1x4 + p2x5 + p3x6 + p4x7 + p5x8
Z [7] among Z [8: 0] may be expressed as z [7] = a7 + a12 + a16. Using elements of X [8: 0] and Y [8: 0], z [7] is expressed as
z [7] = y7x0 + y6x1 + y5x2 + y4x3 + (y3 + y8) x4]
+ (y2 + y7) x5 + (y1 + y6) x6 + (y0 + y5) x7 + (y4 + y8) x8
If y3 + y8 is replaced by p0, y2 + y7 is replaced by p1, y1 + y6 is replaced by p2, y0 + y5 is replaced by p3, and y4 + y8 is replaced by p4, z [7] is expressed as follows.
z [7] = y7x0 + y6x1 + y5x2 + y4x3 + p0x4 + p1x5 + p2x6 + p3x7 + p4x8
Z [8] among Z [8: 0] is represented by z [8] = a8 + a13. Using elements of X [8: 0] and Y [8: 0], z [8] is expressed as
z [8] = y8x0 + y7x1 + y6x2 + y5x3 + y4x4 + (y3 + y8) x5 + (y2 + y7) x6 + (y1 + y6) x7 + (y0 + y5) x8
If y3 + y8 is replaced by p0, y2 + y7 is replaced by p1, y1 + y6 is replaced by p2, and y0 + y5 is replaced by p3, z [8] is expressed as follows.
z [8] = y8x0 + y7x1 + y6x2 + y5x3 + y4x4 + p0x5 + p1x6 + p2x7 + p3x8
In order to perform the above operation, an exclusive OR operation on y [8] to y [0] may be performed and a combination of each bit of Y [8: 0] may be obtained. Each bit z [0] to z [8] of Z [8: 0] performs an AND operation on each bit of X [8: 0] and each bit or combination of each bit of Y [8: 0]. Can be obtained by performing an exclusive OR operation on the result of the AND operation. The calculation process for obtaining z [0] to z [8] is summarized in FIGS. 20 to 21. 20 is a diagram for explaining a process of outputting Z [8: 0], which is a result of multiplication of X [8: 0] and Y [8: 0]. 21 is a diagram illustrating a p generation circuit that performs a logic expression and a logic operation for obtaining values of p [0] to p [7] from a combination of y [0] to y [8].
The
The exclusive OR circuit 20_5 may be provided with p0 generated by the exclusive OR circuit 20_0 through a first input, and may receive y [7] among Y [8: 0] through a second input. The exclusive OR circuit 20_5 may perform an exclusive OR operation on the two signals provided and generate y3 + y7 + y8, that is, p5. The exclusive OR circuit 20_6 may receive p1 generated by the exclusive OR circuit 20_1 through a first input, and may receive y [6] among Y [8: 0] through a second input. The exclusive OR circuit 20_6 may perform an exclusive OR operation on the two signals provided and generate y2 + y6 + y7, that is, p6. The exclusive OR circuit 20_7 may receive p2 generated by the exclusive OR circuit 20_2 through the first input, and may receive y [5] of Y [8: 0] through the second input. The exclusive OR circuit 20_7 may perform an exclusive OR operation on the two received signals and generate y1 + y5 + y6, that is, p7. That is, the
Thus, each bit of Z [8: 0] is each bit x [0] through x [8] of X [8: 0], and each bit y [0] through y [8] of Y [8: 0] Or p [0] to p [8], which is a combination of y [0] to y [8]. In this embodiment, the vector X [8: 0] is a 9 bit vector. The vector Y [8: 0] is composed of a 9-bit vector in which a plurality of bits in 9 bits of Y [8: 0] are combined with a plurality of bits in which some of the 9 bits are combined.
As an example, assume that X [8: 0] corresponds to nine elements of α 0 to α 8 , with only one bit having a value of logic one. Y [8: 0] is equal to the coefficient vector e 1 = (e 18 , e 17 , e 16 , e 15 , e 14 , e 13 , e 12 , e 11 , e 10 ) among the coefficients of the error location search equation. Assume that they correspond. At this time, the product of any of nine elements of α 0 to α 8 and the coefficient vector e 1 is expressed as follows.
e 1 α 0 = (e 18 , e 17 , e 16 , e 15 , e 14 , e 13 , e 12 , e 11 , e 10 )
e 1 α 1 = (e 17 , e 16 , e 15 , e 14 , (e 13 + e 18 ), e 12 , e 11 , e 10 , e 18 )
e 1 α 2 = (e 16 , e 15 , e 14 , (e 13 + e 18 ), (e 12 + e 17 ), e 11 , e 10 , e 18 , e 17 )
e 1 α 3 = (e 15 , e 14 , (e 13 + e 18 ), (e 12 + e 17 ), (e 11 + e 16 ), e 10 , e 18 , e 17 , e 16 )
e 1 α 4 = (e 14 , (e 13 + e 18 ), (e 12 + e 17 ), (e 11 + e 16 ), (e 10 + e 15 ), e 18 , e 17 , e 16 , e 15 )
e 1 α 5 = ((e 13 + e 18 ), (e 12 + e 17 ), (e 11 + e 16 ), (e 10 + e 15 ), (e 14 + e 18 ), e 17 , e 16 , e 15 , e 14 )
e 1 α 6 = ((e 12 + e 17 ), (e 11 + e 16 ), (e 10 + e 15 ), (e 14 + e 18 ), (e 13 + e 17 + e 18 ),
e 16 , e 15 , e 14 , (e 13 + e 18 ))
e 1 α 7 = ((e 11 + e 16 ), (e 10 + e 15 ), (e 14 + e 18 ), (e 13 + e 17 + e 18 ), (e 12 + e 16 + e 17 ),
e 15 , e 14 , (e 13 + e 18 ), (e 12 + e 17 ))
e 1 α 8 = ((e 10 + e 15 ), (e 14 + e 18 ), (e 13 + e 17 + e 18 ), (e 12 + e 16 + e 17 ), (e 11 + e 15 + e 16 ),
e 14 , (e 13 + e 18 ), (e 12 + e 17 ), (e 11 + e 16 ))
That is, the product of the element vector having only one bit and the value of
Fig. 22 shows the coefficient vector e 1 of X [8: 0] = (1, 0, 1, 0, 1, 0, 1, 0, 1) using only one bit with an element having a logical 1 value. This figure explains the structure of the logical expression to find the product.
X [8: 0] = (1, 0, 1, 0, 1, 0, 1, 0, 1) may be represented by α 8 + α 6 + α 4 + α 2 + α 0 . Thus, the product of X [8: 0] = (1, 0, 1, 0, 1, 0, 1, 0, 1) and the coefficient vector e 1 is the element and coefficient vector whose only one bit has the value of logical 1 Based on e 1 can be expressed by the following logical expression.
X [8: 0] × e 1 = (1, 0, 1, 0, 1, 0, 1, 0, 1) × e 1 = e 1 α 0 + e 1 α 2 + e 1 α 4 + e 1 α 6 + e 1 α 8
= (e 18 + e 16 + e 14 + (e 12 + e 17 ) + (e 10 + e 15 ),
e 17 + e 15 + (e 13 + e 18 ) + (e 11 + e 16 ) + (e 14 + e 18 ),
e 16 + e 14 + (e 12 + e 17 ) + (e 10 + e 15 ) + (e 13 + e 17 + e 18 ),
e 15 + (e 13 + e 18 ) + (e 11 + e 16 ) + (e 14 + e 18 ) + (e 12 + e 16 + e 17 ),
e 14 + (e 12 + e 17 ) + (e 10 + e 15 ) + (e 13 + e 17 + e 18 ) + (e 11 + e 15 + e 16 ),
e 13 + e 11 + e 18 + e 16 + e 14 ,
e 12 + e 10 + e 17 + e 15 + (e 13 + e 18 ),
e 11 + e 18 + e 16 + e 14 + (e 12 + e 17 ),
e 10 + e 17 + e 15 + (e 13 + e 18 ) + (e 11 + e 16 ))
That is, each of the 502 elements of α 9 to α 510 can be represented using an element having only a value of
The form of the equation appears to be four exclusive OR circuits needed to compute X [8: 0] × e 1 . However, the operation of adding any one element whose three bits of α 9 to α 510 have a value of 1 and the two bits having a value of 1, or only one bit having a value of 1 An operation may be required to add an element and any one of four elements of α 9 to α 510 having a value of 1. Thus, the error location search circuit must include nine exclusive OR circuits.
For example, the product of elements α 14 , α 15 , α 16, each of which three bits have a value of
e 1 α 14 = e 1 (α 5 + α 4 +1) = e 1 (α 5 + α 9 )
e 1 α 15 = e 1 (α 6 + α 5 + α) = e 1 (α 6 + α 10 )
e 1 α 16 = e 1 (α 7 + α 6 + α 2 ) = e 1 (α 7 + α 11 )
The above operation may be performed by adding any one of 511 elements of α 0 to α 510 times the coefficient vector e 1 . The product of each of elements other than α 14 , α 15 , and α 16 and e 1 may also be calculated by adding any of 511 elements of α 0 to α 510 and the product of the coefficient vector e 1 . Thus, nine exclusive OR circuits may be needed to sum the nine bits.
As mentioned above, the product of the coefficient element e 1 and the nine elements with only one bit having the value of
The Chien search unit may perform an operation of adding the outputs (9 bits x 511) of each of the four error location search circuits. Thus, 18396 (= 4x9x511) exclusive OR circuits may be required to generate the error detection signal. Therefore, the Chien search unit requires 36824 logic circuits (= 18428 + 18396). Compared with the conventional Chien search unit requiring 353612 logic circuits, it can be seen that the Chien search unit according to another embodiment of the present invention requires only a logic circuit reduced to about 1/10.
In the above, a multiplication operation performed according to another embodiment of the present invention employing the
Reference is again made to FIG. 1 to describe another embodiment of the present invention. The nonvolatile
The
The
Meanwhile, during the program operation of the nonvolatile
The sign data may include parity data generated by the error
In another embodiment of the present invention, typical data stored in the memory may be accessed by an external device according to the input of the column address Y [13: 0]. However, the parity data is internal data added for correction of normal data and thus may not be directly accessed by an external device.
The error
In addition, during program operation of the nonvolatile
The
The
The row /
In a read operation according to an embodiment of the present disclosure, cell data of the
In the program operation, the cell data of the
FIG. 23 is a block diagram illustrating another configuration example of the error
The error
The
The error
The configuration and operation of the
Each of the position search circuits 33_1 to 33_4 may calculate e 1 x, e 2 x 2 , e 3 x 3 , and e 4 x 4 . X in the formulas e 1 x, e 2 x 2 , e 3 x 3 , and e 4 x 4 are values representing the positions of bits forming the sign data (that is, the cell data stored in the page buffer 12). x may have a value of any one of 511 9-bit elements α 0 to α 510 . Incidentally, the coefficients e 1 , e 2 , e 3 , and e 4 are 9-bit vectors provided from the error
Location detection circuit (33_1) has been provided with a factor e 1, e 1 is multiplied by the coefficient α and the element α 0 ~ 510, respectively can be calculated from i0 to the i510. Location detection circuit (33_2) may been provided with a coefficient e 2, calculated by multiplying the coefficient e j510 j0 to 2 and an element α 0 to α 510, respectively. Location detection circuit (33_3) may receive service coefficient e 3, calculated by multiplying the coefficient k0 to k510 e 3 and the element α 0 to α 510, respectively. Location detection circuit (33_4) may been provided with a coefficient e 4, calculates a l0 to l510 multiplied by a coefficient α 0 to α e 4 and element 510, respectively.
The exclusive OR calculation unit 33_11 may perform an exclusive OR operation on the calculation result of the coefficient e 0 and the four position search circuits 33_1, 33_2, 33_3, and 33_4. Exclusive OR operations may be performed on each of elements α 0 to α 510 . As an example, (i0 + j0 + k0 + l0) may be calculated for element α 0 . The exclusive OR operation 33_11 generates the error detection signal bch [510: 0] based on the calculation result, and provides the generated error detection signal bch [510: 0] to the
According to another embodiment of the present disclosure, the
On the other hand, when the error detection signal bch [s] has a value of logical zero, the exclusive OR circuit 34_s can be stored in the
FIG. 25 is a block diagram illustrating a configuration example of the position search circuits 33_1 to 33_4 of FIG. 24. Each of the position search circuits 33_1 to 33_4 calculates the product of the coefficients of the error position search equation and each of the nine elements of α 0 to α 8 , in which only one bit has a value of
Each of the selection circuits 80_0 to 80_8 has binary values 9'b000000001, 9'b000000010, 9'b000000100, 9'b000001000, 9'b000010000, 9'b000100000, which are preset so that only one bit has a value of
Each of the selection circuits 80_0 to 80_8 is provided from the e i0 to e i8 and
Each of 9 bits e i α 0 to e i α 8 may be provided as an exclusive OR circuit of the exclusive OR circuit 33_11 and an exclusive OR circuit of the second
The second
For example, the product of the coefficient e 2 of the error location search equation and each of the 511 elements α 0 to α 510 may be expressed as follows.
e 2 (α 0 ) 2 = e 2 (α 0 ),
e 2 (α 1 ) 2 = e 2 (α 2 ),
e 2 (α 2 ) 2 = e 2 (α 4 ),
e 2 (α 3 ) 2 = e 2 (α 6 ),
e 2 (α 4 ) 2 = e 2 (α 8 ),
e 2 (α 5 ) 2 = e 2 (α 10 ) = e 2 (α 5 + α),
e 2 (α 6 ) 2 = e 2 (α 12 ) = e 2 (α 7 + α 3 ),
e 2 (α 7 ) 2 = e 2 (α 14 ) = e 2 (α 5 + α 4 +1) = e 2 (α 5 + α 9 ),
e 2 (α 8 ) 2 = e 2 (α 16 ) = e 2 (α 7 + α 6 + α 2 ) = e 2 (α 7 + α 11 ),
...
The operation of multiplying the coefficient e 2 of the error location search equation by each of the 511 elements α 0 to α 510 may be performed by the first
The second
The second
Another embodiment of the present invention may substitute (2 m −1) elements represented by an m-bit vector on the Galois field GF (2 m ) into an error location search equation. The
Each of the position searching circuits 33_1 to 33_4 may include a first
The second
According to another embodiment of the present invention, the product of nine elements having only one bit of
In addition, the exclusive AND operation unit 33_11 included in the
Compared with the conventional
The present invention has been described above with reference to the embodiments of the present invention. However, in view of the nature of the technical field to which the present invention belongs, the object of the present invention may be achieved in a form different from the above embodiments while including the gist of the present invention. Therefore, the above embodiments are to be understood in terms of description rather than limitation. That is, the technical idea which can achieve the same objective as this invention, including the summary of this invention, should be interpreted as being included in the technical idea of this invention.
Therefore, modifications or variations of the technical spirit within the scope not departing from the essential characteristics of the present invention are included in the protection scope claimed by the present invention. In addition, the protection scope of the present invention is not limited to the above embodiments.
10 nonvolatile
12: page buffer 13: error detection correction circuit
14: Buffer 15: I / O Pad
16: control circuit 17: address decoder
18: row / block decoder 20: p generation circuit
20_0, 20_1, 20_2, 20_3, 20_4, 20_5, 20_6, 20_7: exclusive OR circuit
21: decoder section 22: encoder section
31: syndrome output circuit
31_1, 31_2, 31_3, 31_4: syndrome generator
32: error coefficient calculation circuit 33: Chien search unit
33_1, 33_2, 33_3, 33_4: location search circuit
33_11: exclusive OR operation unit
33_a: first vector generation circuit 33_b: second vector generation circuit
34: error correction circuit 34_s: exclusive OR circuit
41: parity generation circuit
51: S calculator 52: P calculator
53: P latch 54: Q calculator
55: Q latch 56: Chien search circuit group
57: Chien search circuit 58: bit position conversion circuit
71: substitution value calculation unit 72: error position search equation calculation unit
80_0, 80_1, 80_2, 80_3, 80_4, 80_5, 80_6, 80_7, 80_8: selection circuit
81: e 1 (α i ) + e 0 calculator 82: e 2 (α i ) 2 calculator
83: e 3 (α i ) 3 calculator 84: e 4 (α i ) 4 calculator
85: L [i] calculation unit 339: Chien search unit
339_0 to 339_510: position search circuit
Claims (10)
The chien search unit:
A calculation circuit for calculating a first bit string by multiplying the predetermined plurality of elements by a predetermined value of (nk) bits, and calculating a second bit string by multiplying the predetermined plurality of elements by a predetermined value of k bits ; And
And a plurality of Chien search circuits that connect the first bit stream and the second bit stream calculated by the calculation circuit to calculate any element and substitute the error location search equation.
The plurality of Chien search circuits are arranged in a matrix shape along the row direction and the column direction,
The first bit column is provided in the row direction or the column direction, and the second bit column is provided in a direction different from the first bit column in the row direction and the column direction, respectively.
And an unused bit used as an element and an unused bit not used as an element in a bit space consisting of the matrix of the first bit string and the second bit string.
And the number of the plurality of Chien search circuits is equal to or greater than the number of bits in the data string.
An error detection correction circuit comprising a Chien search unit that uses any element of the Galois field GF (2 n ) as an substitution value of an error location search equation, and determines whether there is an error for each bit of the data string read from the memory cell; And
A data storage unit for temporarily storing the data string and providing the data string to the error detection correction circuit;
The chien search unit:
A calculation circuit for calculating a first bit string by multiplying the predetermined plurality of elements by a predetermined value of (nk) bits, and calculating a second bit string by multiplying the predetermined plurality of elements by a predetermined value of k bits ; And
And a plurality of Chien search circuits that connect the first bit stream and the second bit stream calculated by the calculation circuit to calculate any element and substitute the error location search equation.
The plurality of Chien search circuits are arranged in a matrix shape along the row direction and the column direction,
The first bit column is provided in the row direction or the column direction, and the second bit column is provided in a direction different from the first bit column in the row direction and the column direction, respectively.
And rearrangement of used bits used as elements and unused bits not used as elements in a bit space consisting of the matrix of the first bit string and the second bit string.
And the number of the plurality of Chien search circuits is equal to or greater than the number of bits of the data string.
A plurality of position searching circuits, each of which is provided with the elements, substitutes the elements in each term of the error positioning search equation, and calculates an output value by calculating a product of the coefficients of the error positioning searching equation and the element,
An exclusive OR operation corresponding to each of the elements is performed on the plurality of output values calculated by the plurality of position searching circuits,
And the error detection signal is generated based on a result of performing the exclusive OR operation.
Each of the plurality of location search circuits is:
A first vector for generating m first vectors based on a coefficient vector of m bits, which is a coefficient of the error location search equation, and a fixed vector of m bits corresponding to an element having only a value of logic 1, only one bit. Generating circuit; And
A second vector generation circuit for generating (2 m- 1-m) second vectors obtained by the sum of two or more vectors among the vectors corresponding to the first vector,
The first vector generation circuit is:
M bit determination units for generating the first vector in parallel from each bit or a combination of each bit of the coefficient vector according to a position of a bit having a logic 1 value among the fixed vectors;
The second vector generation circuit is:
And an exclusive OR circuit for generating the second vector by the sum of two vectors, the vector corresponding to the first vector and the vector corresponding to the second vector.
A syndrome calculation unit calculating a syndrome based on the data string;
An error coefficient calculator for calculating a coefficient of an error location search equation using the syndrome;
(2 m -1) elements represented by m bit vectors on Galois field GF (2 m ) are substituted into the error position search equation, and an error indicating whether or not there is an error in the data at the bit position corresponding to each of the elements. An error location search circuit for generating a detection signal; And
An error correction unit for correcting a value of an error bit of the data string according to the error detection signal and outputting a corrected data string;
The fault location search circuit is:
A plurality of position searching circuits, each of which is provided with the element, substitutes the element in each term of the error position search equation, and calculates an output value by calculating a product of the coefficient of the error position search equation and the element; And
An exclusive OR operation unit configured to perform an exclusive OR operation corresponding to each of the elements with respect to the plurality of output values calculated by the plurality of position search circuits,
And the error detection signal is generated based on a result of performing the exclusive OR operation.
Each of the plurality of location search circuits is:
A first vector for generating m first vectors based on a coefficient vector of m bits, which is a coefficient of the error location search equation, and a fixed vector of m bits corresponding to an element having only a value of logic 1, only one bit. Generating circuit; And
A second vector generation circuit for generating (2 m- 1-m) second vectors obtained by the sum of two or more vectors among the vectors corresponding to the first vector,
The first vector generation circuit is:
M bit determination units for generating the first vector in parallel from each bit or a combination of each bit of the coefficient vector according to a position of a bit having a logic 1 value among the fixed vectors;
The second vector generation circuit is:
And an exclusive-OR circuit for generating the second vector by the sum of two vectors of the vector corresponding to the first vector and the vector corresponding to the second vector.
A syndrome calculation unit calculating a syndrome based on the data string;
An error coefficient calculator for calculating a coefficient of an error location search equation using the syndrome;
(2 m -1) elements represented by m bit vectors on Galois field GF (2 m ) are substituted into the error position search equation, and an error indicating whether or not there is an error in the data at the bit position corresponding to each of the elements. An error location search circuit for generating a detection signal; And
An error correction unit for correcting a value of an error bit of the data string according to the error detection signal and outputting a corrected data string;
The fault location search circuit is:
A plurality of position searching circuits, each of which is provided with the element, substitutes the element in each term of the error position search equation, and calculates an output value by calculating a product of the coefficient of the error position search equation and the element; And
An exclusive OR operation unit configured to perform an exclusive OR operation corresponding to each of the elements with respect to the plurality of output values calculated by the plurality of position search circuits,
The error detection signal is generated based on a result of performing the exclusive OR operation;
The data storage unit is a circuit for storing the data string read from the storage element,
And the element corresponds to a column address indicating a location of a memory column of the storage element.
Each of the plurality of location search circuits is:
A first vector for generating m first vectors based on a coefficient vector of m bits, which is a coefficient of the error location search equation, and a fixed vector of m bits corresponding to an element having only a value of logic 1, only one bit. Generating circuit; And
A second vector generation circuit for generating (2 m- 1-m) second vectors obtained by the sum of two or more vectors among the vectors corresponding to the first vector,
The first vector generation circuit is:
M bit determination units for generating the first vector in parallel from each bit or a combination of each bit of the coefficient vector according to a position of a bit having a logic 1 value among the fixed vectors;
The second vector generation circuit is:
And an exclusive OR circuit configured to generate the second vector by the sum of two vectors, the vector corresponding to the first vector and the vector corresponding to the second vector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/034,803 US9384083B2 (en) | 2012-09-24 | 2013-09-24 | Error location search circuit, and error check and correction circuit and memory device including the same |
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| Application Number | Priority Date | Filing Date | Title |
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| JPJP-P-2012-209772 | 2012-09-24 | ||
| JP2012209772A JP2014068058A (en) | 2012-09-24 | 2012-09-24 | Error location search circuit, error detection and correction circuit and memory device |
| JPJP-P-2012-209529 | 2012-09-24 | ||
| JP2012209529A JP2014064242A (en) | 2012-09-24 | 2012-09-24 | Error detection and correction circuit and semiconductor memory |
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| KR20140039980A true KR20140039980A (en) | 2014-04-02 |
| KR102021560B1 KR102021560B1 (en) | 2019-09-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20180022014A (en) * | 2016-08-23 | 2018-03-06 | 에스케이하이닉스 주식회사 | Memory device thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999016175A1 (en) * | 1997-09-24 | 1999-04-01 | Hitachi, Ltd. | Semiconductor integrated circuit and data processing system |
| JPH11265276A (en) * | 1998-03-18 | 1999-09-28 | Fujitsu Ltd | Phase shift coefficient calculation system for m sequence |
| JP2000315955A (en) * | 1999-04-30 | 2000-11-14 | Mitsubishi Electric Corp | Encoding method, syndrome calculating method, number of erroneous bits estimating method, erroneous bit position estimating method, decoding method and decoder |
| KR20100113143A (en) * | 2008-03-01 | 2010-10-20 | 가부시끼가이샤 도시바 | Chien search device and chien search method |
-
2013
- 2013-08-13 KR KR1020130096080A patent/KR102021560B1/en active IP Right Grant
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999016175A1 (en) * | 1997-09-24 | 1999-04-01 | Hitachi, Ltd. | Semiconductor integrated circuit and data processing system |
| JPH11265276A (en) * | 1998-03-18 | 1999-09-28 | Fujitsu Ltd | Phase shift coefficient calculation system for m sequence |
| JP2000315955A (en) * | 1999-04-30 | 2000-11-14 | Mitsubishi Electric Corp | Encoding method, syndrome calculating method, number of erroneous bits estimating method, erroneous bit position estimating method, decoding method and decoder |
| KR20100113143A (en) * | 2008-03-01 | 2010-10-20 | 가부시끼가이샤 도시바 | Chien search device and chien search method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180022014A (en) * | 2016-08-23 | 2018-03-06 | 에스케이하이닉스 주식회사 | Memory device thereof |
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