KR102064857B1 - Galois field calculating circuit and memory device - Google Patents

Abstract

The present invention relates to a galloise arithmetic circuit for substituting (2 ^m -1) circles, vector represented by m bits on a galloise, into an error position detection polynomial. Galois field operation circuit of the present invention, (2 ^m -1) from the base computing unit, and (2 ^m -1) of the circles for calculating linearly independent of the m source from the two circles other than the m source (2 ^m - 1-m) consists of linear developments that compute each circle as a combination of m circles.

Description

GALOIS FIELD CALCULATING CIRCUIT AND MEMORY DEVICE}

The present invention relates to a galloche calculation circuit and a memory device used as an error detection and correction circuit.

NAND flash memory is known as one of the electrically rewritable nonvolatile semiconductor memories (EEPROM), Electrically Erasable and Programmable Read Only On Memory. The NAND flash memory uses a NAND cell unit (NAND string) in which a plurality of memory cells are connected in series, so that large capacity can be stored with a small chip area.

In NAND flash memory, the stored contents are damaged due to various reasons during data holding. For example, due to deterioration of the tunnel oxide film due to rewriting many times, the holding characteristic of the memory element (memory cell) is lowered during data holding, so that the occurrence rate (error rate) of error bits tends to increase. In particular, in NAND flash memories, the error rate tends to increase as the size of the memory and the size of the manufacturing process become smaller. In order to cope with this, error detection and correction circuits (ECC circuits) are used to improve the performance of NAND flash memories. By mounting the error detection correction circuit on-chip, it is possible to provide a high reliability memory.

In addition, there is a circuit using a gallosome arithmetic circuit formed by a finite body (galloise) (GF (2 ^ m)) as an error correction circuit (see Patent Document 1). The galloache arithmetic circuit described in Patent Literature 1 is a component of an upper bit other than the lower m bit in the multiplication process when multiplying two circles represented by a vector of m bits on a galloise (GF (2 ^ m)). For each exclusive OR, converting its output into a vector representation of m bits by the given source polynomial (f (X)), and performing an exclusive OR with the components of the lower m bits. To get the multiplied vector output. Accordingly, the galloche calculation circuit simplifies the multiplication circuit configuration on the galloche.

Japanese Patent Application Laid-Open No. 06-314979j

By the way, in the error correction process using the linear block code represented by the BCH code or the RS code, it takes the most time to determine the zero point of the error position detection polynomial (error position search equation) P (X) (error or not). Detecting) process. In general, the process of finding this zero is, for example, in the galloise arithmetic circuit (the galloise arithmetic circuit of the fourth-order polynomial) shown in Fig. 12, the coefficients p0, of the error position detection polynomial P (X). After p1, p2, p3 and p4) are determined, 1, alpha, alpha 2, alpha 3, ..., alpha t-2 (where t = 2 ^ m) are sequentially input as gallosome element (circle) (X). The zero of P (X) is obtained. The time taken for this process can be greatly shortened by calculating all of the values that the variable X of the polynomial can take at once. For example, as shown in FIG. 13, each parallel operation circuit of elements 1, alpha, alpha 2, alpha 3, ..., alpha t-2 is provided, and P (1), P (alpha 1) and P are provided. By simultaneously calculating (? 2), ..., P (? t-2) (where t = 2 ^ m), the calculation time of the error position detection polynomial can be greatly shortened. However, in the method shown in Fig. 13, the circuit scale for calculating the error position detection polynomial becomes very large, and it becomes very difficult to mount the error detection correction circuit on-chip in the memory device.

An object of the present invention is to provide a galloche arithmetic circuit and a memory device for reducing the scale of a circuit for calculating an error position detection polynomial.

Galoache operation according to an embodiment of the present invention by substituting (2 ^m- 1) circles represented by a vector by m bits of GF (2 ^ m) into an error position detection polynomial The circuit comprises: a base calculation unit for calculating m independent circles from the (2 ^m -1) circles; And (2 ^m -1-m) circles except for the m circles from the (2 ^m -1) circles, each of which includes a linear development part for calculating a combination of the m circles.

In an embodiment, the terms constituting the same linear space for the error position detection polynomial are integrated as a linear function, and the calculation is performed using the basis calculation unit and the linear expansion unit for the integrated linear function.

A memory device having an error correction circuit for performing an error detection of an input data string, the memory device comprising: a syndrome calculation unit calculating a syndrome from the input data string; An error coefficient calculation unit for calculating a coefficient of the error position detection polynomial with the syndrome; A galloche arithmetic circuit for calculating a value indicating a position of a bit of data of said data string and said coefficient by substituting said error position detection polynomial; A Chien search unit for outputting an error detection signal indicating whether or not there is an error for each bit of the data string in response to the substitution result of the error position detection polynomial; And an error correcting unit for correcting and outputting an error of data of a bit of the data string in response to the error detection signal, wherein the galloche calculation unit is a vector representation by m bits on a galloche GF (2 ^ m). Substituting the (2 ^m -1) circles into the error position detection polynomial, and the Galoache calculation unit calculates the linearly independent m circles from the (2 ^m -1) circles (m is an integer). Basis calculation unit; And (2 ^m -1-m) circles except for the m circles from the (2 ^m -1) circles, each of which includes a linear development part for calculating a combination of the m circles.

The galloache arithmetic circuit according to the embodiments of the present invention, a basis calculation unit for calculating m independent linear circles from (2 ^m -1) circles on the galloise (GF (2 ^ m), (2 ^m A linear development part is obtained which obtains the circle | round | yen except 2 ^m circles which are linear independent from -1) circles by the combination of m circles which are each linear independent. Accordingly, in the galloise calculation circuit, the scale of the circuit for calculating the error position detection polynomial can be reduced.

1 illustrates a memory device according to an embodiment of the present invention.
2 shows an example of an error detection correction circuit.
3 is a table showing the elements of Galoache (FG (2 ^ 4)).
4 is a table showing the elements of Galoache.
5A and 5B show a configuration example of a galloche calculation circuit.
6A and 6B show examples of linear structures of polynomials.
FIG. 7 is a diagram for describing an operation of the galloche calculation circuit illustrated in FIG. 5A.
8 shows an example of a circuit that calculates a linear term for X.
9 shows an example of winning a circle shown in the table of FIG.
10 shows an example of a circuit for calculating the linear term for X ^ 3.
11A and 11B are views for explaining the reduction effect of the circuit element.
12 shows an example of a Galoache calculation circuit for finding the zero of a conventional Galoache polynomial.
13 shows an example of a galloche calculation circuit using a parallel calculation circuit.
14 shows an example of a matrix operation.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

In the conventional Galoache arithmetic circuit, for example, the circuit shown in Fig. 12 (the circuit of the quadratic polynomial) has the coefficients p0, p1, p2, p3, p4 of the error position detection polynomial P (X). After this is confirmed, 1 (= α ^ 0), α (= α ^ 1), α ^ 2, α ^ 3, ... as the tracheal element (circle) (X) are sequentially input and error position is detected. Find the zero of the polynomial (P (X)).

More specifically, the Galoache calculation circuit for finding the zero of the conventional Galoache polynomial calculates the coefficient pi (i (i = 0, 2, 3, 4) in the first order, and calculates the term as the second order. (piXi) is calculated and each term corresponding to i = 0, 1, 3, 4 is added to each other as a third order. Then, the error position detection polynomial is performed for all elements X (1, α, α ^ 2, α ^ 3, ...), or parts thereof, which can take the first, second and third orders. Find the zero of (P (X)).

In this method, however, the zero of the error position detection polynomial (P (X)) is obtained by sequentially inputting the elements (1, α, α ^ 2, α ^ 3, ...) of galloise. It takes a very long time.

In order to solve this problem, a circuit (example of the fourth order polynomial) for finding the zero point of the error position detection polynomial P (X) at once can be used. For example, as shown in the galloace calculation circuit shown in FIG. 13, each element 1 (α ^ 0), α, α ^ 2, α ^ 3, ..., α ^ (t-2) (but t P (1), P (α ^ 1), P (α ^ 2), P (α ^ 3), P (α ^ (t) By simultaneously calculating -2)), the computation time of the error position detection polynomial can be greatly shortened. However, in the method shown in Fig. 13, since the error position detection polynomial P (X) for all Xs that can be taken is collectively obtained, it takes no time to zero each bit, but the circuit scale is increased.

Very large.

In the circuit configuration as shown in Fig. 13, the portion corresponding to each term of each unit is indicated by matrix operation since the operation of multiplying integer sources is a linear operation (for example, the matrix operation shown in Fig. 14). See). Here, the matrix used for the calculation is a matrix which converts this into another vector when the galloise element X is regarded as a vector. In the case of adopting the galloace (GF (2 ^ m)) (m is the data length when the galloise element (X) is regarded as binary data), the circuit corresponding to the matrix operation part is about m ( m-1) / 2 EXOR elements. In the case of the order n of the polynomial, since m bits of the matrix operation are added to each other by (n + 1) terms, m x n EXOR elements are required. If the range of values that the Galloache element (X) can take is made into the whole Galloache, the number of units in FIG. 13 is 2 ^m- 1, and the total is (n + 1) * ( ^2m- 1) * m (m It becomes -1) / 2 + n * ( ^2m- 1) * m.

For example, when m = 8 and n = 4, about 43800 EXOR elements in total are required. In this way, even if the operation of each term is converted from multiplication of two inputs to matrix operation, the circuit scale becomes very large.

According to an embodiment of the present invention, the Galoache calculation circuit reduces circuit size by using the linearity of each term of the Galoache and the error position detection polynomial. Each term of the error position detection polynomial is represented by the parts "X, X ^ 2, X ^ 4, X ^ 8, ..." which are linear with respect to the Galoache element (X), and the Galoache element (X ^ 3). For linearity "X ^ 3, X ^ 6, X ^ 12, ...", the linearity for gallosome elements (X ^ 5) "X ^ 5, X ^ 10, X ^ 20, ... "into several parts, each of which is integrated as the same linear function. In addition, the integrated linear function calculates a circle circle by a base calculation unit and a linear development unit which calculate using a base value.

The basis calculation unit calculates the error position retrieval polynomial for m circles that are linearly independent on Galoache (GF (2 ^ m)). In addition, in the calculation of the error position search polynomial corresponding to the remaining (2 ^m -1-m) circles except m circles that are linearly independent, the linear expansion unit adds the calculation result of the base calculation unit to perform the calculation.

Accordingly, the circuit scale of the Galois calculation circuit can be reduced compared to the Galois calculation circuit that calculates the error position detection polynomial per circle. In addition, a galloche calculation circuit for finding the zero point of the error position detection polynomial in a short time can be realized on a circuit scale that can be mounted in a semiconductor memory.

Memory device configuration

1 illustrates a memory device according to an embodiment of the present invention. As a memory device, a nonvolatile semiconductor memory device 10, which is a NAND flash memory, is shown in FIG.

The nonvolatile semiconductor memory device 10 includes a memory cell array 11, a page buffer 12, an error detection correction circuit (ECC circuit) 13, a buffer 14, an I / O pad 15, and a control circuit. (16), address decoder 17, and row and block decoder 18.

The nonvolatile semiconductor memory device 10 has the same configuration as a general NAND flash memory, but is characterized by a galloche arithmetic circuit (an arithmetic circuit of an error position detection polynomial) installed in the error detection correction circuit 13 (Fig. 2). .

In the following, the overall configuration of the nonvolatile semiconductor memory device 10 will be described. In the nonvolatile semiconductor memory device 10, the memory cell array 11 includes a plurality of stacked gate structure transistors, that is, electrically rewritable nonvolatile memory cells (memory elements) in a column direction (column direction). A plurality of NAND cell strings connected in series and provided for each bit line are arranged in a row direction (bit line arrangement direction). A plurality of blocks are arranged in the wiring direction of the bit line. Blocks are set in units of erasing data of a memory cell. In each block, a word line orthogonal to the bit line is connected to the gate of each of the nonvolatile memory cells arranged in the same row. The range of a nonvolatile memory cell selected by one word line is a page which is a unit of program and read.

The page buffer 12 includes a page buffer circuit provided for each bit line in order to program and read data in page units. Each page buffer circuit of the page buffer 12 includes a latch circuit connected to each bit line and used as a sense amplifier circuit for amplifying and determining the potential of the connected bit line.

The page buffer 12 (data storage unit) is a cell that is data (data string) stored in memory cells of one page of the memory cell array 11 during a data read operation of the nonvolatile semiconductor memory device 10. The data Cell # Data is received, and the received data is amplified and output to the error detection correction circuit 13. On the other hand, the page buffer 12 stores the data supplied from the error detection and correction circuit 13 in the internal latch circuit during the data write (program) operation of the nonvolatile semiconductor memory device 10, and verifies the operation. While executing, all data is written into the memory cells of one page as code data Code # Data.

The code data Code_Data includes parity data Parity generated by the error detection correction circuit 13. For example, in an error correction system that performs 4 bit (bit) correction using a BCH code for data having an information length of 512 bytes, one page is 2 K (= 2048) bytes, that is, 16 k ( 16384) memory cells each storing bits of normal data and memory cells each storing 208 bits of parity data. That is, the cell data Cell # Data and the code data Code # Data are composed of (16k + 208) bits. In addition, for example, one page is divided into four sectors as a unit of correction by the error detection and correction circuit 13. That is, the data corresponding to one sector is composed of 512 bytes (= 4096 bits) of normal data and 52 bits of parity data.

In the data read operation of the nonvolatile semiconductor memory device 10, the error detection correction circuit 13 processes data read from the page buffer 12 for each sector to calculate coefficients of the error position detection polynomial, and calculates the result. Latch and keep it inside. In addition, the error detection correction circuit 13 corrects an error of data of bits whose position is indicated by a column address during a read operation, and externally corrects the data as corrected data through the I / O pad 15. Will output

In addition, the error detection correction circuit 13 receives the information data (Information_Data) input from the I / O pad 15 through the buffer 14 during the data write operation of the nonvolatile semiconductor memory device 10. do. The error detection correction circuit 13 generates parity data from the received information data, and sends the received information data and the parity data to the page buffer 12. Output The page buffer 12 writes the received data as code data to memory cells connected to the selected page.

The control circuit 16 inputs various control signals to perform operations such as programming, reading, erasing data, and verifying operations of the nonvolatile memory cells. For example, the control signal may include an external clock signal, a chip enable signal (/ CE), a read enable signal (/ RE), a program enable signal (WE), a command latch enable signal (CLE), and an address latch enable. Signal ALE, write prevention signal / WP, and the like.

The control circuit 16 outputs an internal control signal to each circuit in response to the operation mode indicated by the control signal and the command data input from the I / O pad 15. For example, the control circuit 16 responds to the command latch enable signal CLE from the low (L) level to the high (H) level at the first start of the program enable signal (/ WE), The command data is read from the I / O pad 15 and stored in an internal register.

The address decoder 17 holds an address (row address, block address, column address) input from the I / O pad 15 based on an internal control signal from the control circuit 16. In addition, the address decoder 17 transfers the held address to the row and block decoder 18, the page buffer 12, and the error detection correction circuit 13 based on an internal control signal from the control circuit 16. Output

For example, the control circuit 16 responds to the address latch enable signal ALE from the low (L) level to the high (H) level at the first start of the program enable signal (/ WE). The address is read from the / O pad 15 and held in an internal register of the address decoder 17.

The row and block decoder 18 selects the block and the word line of the memory cell array 11 in response to the row address and the block address held and output by the address decoder 17 to select one page of memory cells. Choose. In addition, the address decoder 17 selects the bit line and the page buffer 12 of the memory cell array 11 in response to the column address held therein.

In the data read operation of the nonvolatile semiconductor memory device 10, the error detection correction circuit 13 processes data read from the page buffer 12 sector by sector and calculates the coefficient of the error position detection polynomial. In addition, the error detection correction circuit 13 corrects an error of data for each bit whose position is indicated by a column address during a read operation, and externally corrects the data as corrected data through the I / O pad 15. Will output

In addition, the error detection and correction circuit 13 receives information data (Information Data) input from the I / O pad 15 through the buffer 14 during the data write operation of the nonvolatile semiconductor memory device 10. do. The error detection correction circuit 13 generates parity data from the received information data, and outputs the received information data and parity data to the page buffer 12. do. The page buffer 12 writes the received data as code data to memory cells connected to the selected page.

In the NAND flash memory of the above configuration, FIG. 2 shows an example of the configuration of the error detection correction circuit 13.

In the embodiment of the present invention, an error detection correction circuit (ECC circuit) using a BCH code (Bose-Chaudhuri Hocquenghem code) is described as the error detection correction circuit 13. The error detection correction circuit uses a block code using a galloche operation represented by a BCH code. In addition, it is also possible to use a modified example of the BCH code, for example, a Hamming code (Haming code) and a Reed-Solomon code.

The error detection correction circuit 13 includes a decoder unit 30 for decoding data and an encoder unit 40 for generating correction parity data Parity and adding correction parity data Parity to data written in a cell. Include.

Among these, the encoder unit 40 includes a parity generation circuit 41. The parity generating circuit 41 generates parity data generated by dividing (for example, dividing) the information data written in the buffer 14 by a generation polynomial. The parity generating circuit 41 adds the parity data Parity generated to the information data and outputs the parity data to the page buffer 12. The data to be output is code data (Code Data) written in one page selected at the time of writing data of the nonvolatile semiconductor memory device 10. Further, in the embodiment of the present invention, when the data is read from the nonvolatile semiconductor memory device 10, the error detection and correction circuit 13 performs data correction processing at high speed, and at the same time, the error detection and correction circuit 13 The circuit scale of the galloache arithmetic circuit 34 is reduced, and the decoder unit 30 will be described in detail below.

The decoder unit 30 includes a syndrome calculator 31, an error coefficient calculator 32, a Chien search unit 33, and an error corrector 35. The Chien search unit 33 includes a galloche calculation circuit 34.

When reading data from the nonvolatile semiconductor memory device 10, the syndrome calculation unit 31 receives the cell data (Cell # Data) read into the page buffer 12 as code data, and receives the received code data as an independent minimum. Compute the syndrome by calculating it in a polynomial. There are four independent minimum polynomials used in the BCH code capable of error correction of four bits of data. The syndrome calculation unit 31 includes four syndrome calculation circuits 31_1 to 31_4 corresponding to four minimum polynomials. The syndrome calculation circuits 31_1 to 31_4 calculate syndromes S1, S3, S5, and S7, respectively.

The error coefficient calculation unit 32 calculates the coefficients of the error position detection polynomial using the syndromes S1, S3, S5, and S7. For example, when the error position detection polynomial is the fourth order polynomial (P (X) = p4X ⁴ + p3X ³ + p2X ² + p1X + p0), the error coefficient calculation unit 32 calculates the coefficients p4, p3, p2, p1, p0. Calculate The Chien search unit 33 calculates the error position detection polynomial P (X) by using the galloche calculation circuit 34. In the error position detection polynomial P (X), the variable X has a value indicating a bit position (for example, the position of the bit line) of the sign data, that is, the cell data stored in the page buffer. ) Is entered. That is, the error position detection polynomial P (X) is used by the Chien search unit 33 when searching whether or not there is an error in the bit read from the page buffer 12.

For example, the Chien search unit 33 calculates the error position detection polynomial (P (X) = p4X ⁴ + p3X ³ + p2X ² + p1X + p0) by the galloche calculation circuit 34, and calculates the error position detection polynomial (P (X). If the value of)) is 0, an error detection signal (Error) is output at the H level. On the other hand, when the value of the error position detection polynomial P (X) is not 0, the Chien search unit 33 outputs an error detection signal Error at an L level.

If the error detection signal Error is at the H level, the error correction unit 35 inverts the logical value (0 or 1) of the data of the bit at the corresponding position, and outputs one bit of the corrected data. On the other hand, if the error detection signal (Error) is at L level, the error correction unit 35 outputs the logical value of the data of the bit at the corresponding position as it is, that is, without correcting it as one bit of corrected data. .

That is, in the Chien search unit 33, the error position detection polynomial (P (X) = p4X ⁴ + p3X ³ + p2X ² + p1X + p0) by the galloche calculation circuit 34, x = α ^ i (element of the galloche: i is When the value of the error position detection polynomial P (X) is 0 when the bit line positions) are substituted, the error detection signal Error <i> becomes H level. On the other hand, when the value of the error position detection polynomial P (X) is not 0, the error detection signal Error <i> becomes L level.

The exclusive OR operation circuit 35_i of the error correction unit 35 stores the (i) th bit of the cell data (Cell Data) stored in the error detection signal Error <i> and the page buffer 12 by a read operation. The bits of the position of the line are input. That is, when the error detection signal Error <i> is at the H level, the exclusive OR calculation circuit 35_i inverts the logical value of the data of the bit at the position of the (i) th bit line, thereby correcting the corrected data. Output as 1 bit of. On the other hand, if the error detection signal Error <i> is L level, the exclusive OR operation circuit 35_i does not correct the logical value of the data of the bit at the position of the (i) th bit line without correcting the correction data (Corrected Data). Output as 1 bit of).

Linearity of Polynomials and Linear Structure of Galoache

In the nonvolatile semiconductor memory device 10 according to an embodiment of the present invention, the error detection and correction circuit 13 performs a galloche and a polynomial when the error position detection polynomial is calculated using the galloche calculation circuit 34. The circuit scale is reduced by using the linear structure of the circuit. Here, for the first time, the linearity of galoache and polynomial is supplemented and explained.

In the following description, for the sake of brevity, it is assumed that m = 3 (or m = 4) for the galloace GF (2 ^ m), and the order of the error position detection polynomial is fourth order (n = 4). Is assumed to be an example. However, the orders (m, n) are not limited. The orders (m, n) are arbitrary values set according to the bit length of the data to be subjected to error detection and the number of error correction bits.

When a function F (X) satisfies two conditions of moving, the function F (X) is linear with respect to X.

(Condition 1) F (X1 + X2) = F (X1) + F (X2)

(Condition 2) F (aX1) = aF (X1)

For example, if X is an element of Galoache, then "F (X) = X ^ 2" is a linear function of X. Because X1 and X2 are elements of galloace, and a = 1 and 0, F (X1 + X2) satisfies Equation 1, so that condition 1 is satisfied.

The addition on Galoache is the exclusive OR and 1 + 1 = 2 = 0, so 2 × 1 × 2 is zero.

Since a is 0 and 1, it is clear that the condition 2 is satisfied. Similarly, the function of multiplying X ^ 4, X ^ 8, X ^ 16, ..., etc. by the power of 2 squared from "1 + 1 = 0" on galloise is a linear function on galloise.

Here, attention is paid to the terms of the first, second, and fourth order of the Galoache polynomial, and this combination is defined as Q (X) as in Equation (2).

At this time, if X and Y are substituted into Equation 2 as an element of Galoache, it is summarized as in Equation 3.

The addition on Galoache is the exclusive OR and 1 + 1 = 2 = 0, so 2 × 1 × 2 is zero.

According to equation (3), since condition 1 and condition 2 are satisfied, Q (X) is a linear function of X.

On the other hand, for other terms (terms other than X4, X2, X), for example, X3, X5, etc. can be regarded as a linear function. For example, paying attention to terms of the third, sixth, and twelfth order, a combination thereof may be defined as a function (R (X)) as shown in Equation (4).

R (X) is a linear function.

Next, the linear structure which galoache has is demonstrated.

Fig. 3 shows elements 1 (= α ^ 0), α ^ 1, α ^ 2, ... of Galoache GF (2 ^ 4) when the primitive polynomial (F (X)) is F (X) = X4 + X + 1. , α ^ 14 is shown in Table 1. Here, attention is paid to four elements (parts enclosed by dashed lines) of 1, α, α ^ 2, and α ^ 3, and they are linear independence in which they themselves are never expressed by a combination of elements other than themselves. Assuming these are basis vectors, the other elements appear as linear combinations of the basis vectors. That is, by using the relationship of α ⁴ + α ¹ + α ⁰ = 0, each element 0, α ^ 0 (= 1), α ^ 1, α ^ 2, ..., α ^ 14 are α ^ 0, α, It can be represented by a four-dimensional vector (0, 0, 0, 0) through (1, 1, 1, 1) having α ^ 2 and α ^ 3 as elements.

For example, the elements of Galoache can be expressed as shown in Equation 5.

Here, assuming that βi = 0, 1 (i = 0, 1, 2, 3), any gallosome element is represented by equation (6).

Here, β3, β2, β1, and β0 are vector expressions corresponding to αj.

Q (X) in Equation 2 is defined as Qj = Q (α ^ j) (j = 0, 1, 2, ...). Substituting equation (6) into Q (X) results in equation (7).

In the conventional case, it was necessary to add the result of performing the matrix operation on each term as Qj = p4α ⁴ + p2α ² + p1α based on the formula (a), but in the embodiment of the present invention, the basis 1 is obtained by using the equation (b). Q0, Q1, Q2, and Q3 corresponding to (= α ^ 0), α ^ 1, α ^ 2, and α ^ 3 can be obtained by matrix operation in advance, and another Qj can be obtained by simple addition.

Fig. 4 shows elements (1 (= α ^ 0) and α ^ 1 of galloache (GF (2 ^ 3)) when the primitive polynomial F (X) is " F (X) = X3 + X + 1 &quot;). , α ^ 2, ..., α ^ 6) is shown in Table 2. Here, attention is paid to the three elements (parts surrounded by the dashed lines) of 1, α, and α ^ 2, which are linear independence in which they are never expressed by a combination of elements other than themselves. Assuming these are basis vectors, the other elements are represented by a linear combination of these basis vectors. That is, using the relationship of "α ³ + α ¹ + α ⁰ = 0", each element 0, α ^ 0 (= 1), α ^ 1, α ^ 2, ..., α ^ 6 are α ^ 0, It can be represented by three-dimensional vectors (0, 0, 0) to (1, 1, 1) having α, α ^ 2 as elements.

Configuration of Galoache Arithmetic Circuit 34

Hereinafter, the configuration of the galloace calculation circuit 34 for obtaining the zero point of the galloche polynomial (error position detection polynomial) will be described. The galloche arithmetic circuit 34 is configured to reduce the circuit size by using the linearity of the error position detection polynomial (error position search polynomial) described above and the linear structure of the galloise. That is, when calculating the error position detection polynomial (P (X)), the galloise calculation circuit 34 performs a basis calculation unit and a linear expansion unit which will be described later with respect to a linear function incorporating terms constituting the same linear space. By performing the calculation, the circuit scale is reduced.

5A shows an example of the configuration of the galloche arithmetic circuit 34, and particularly shows an example in the case of m = 3. The galloche calculation circuit 34 includes a base calculation unit 330 and a linear development unit 340. The base calculation unit 330 includes three calculation units R0, R1, and R2, and the linear development unit 340 includes four EXOR elements. In the galloche arithmetic circuit 34 shown in FIG. 5A, the base calculation unit 330 calculates a linear function y corresponding to the base element of the elements x (m−1: 0) by matrix operation, The linear development unit 340 develops (adds) the calculation result of the base calculation unit 330 to obtain an output of the linear function y corresponding to other elements except for the base. The operation of the galloche calculation circuit 34 shown in FIG. 5A will be described later.

As described above, the Galoache calculation circuit 34 according to the embodiment of the present invention calculates the basis by the base calculation unit 330 for the linear function included in the error position detection polynomial, and the linear development unit 340 , A simple addition of the basis calculation results, outputs all the values that the linear function X can take at once. That is, the galloise calculation circuit 34 has a matrix computation unit (2 ^m- 1-m) for the number (2 ^m -1-m) of which the number (2 ^m -1) of the base is reduced from the number (2 ^m -1) of the values that X can take. The circuit scale can be reduced by converting about m (m-1) / 2 of EXOR elements into simple additions (using m-1 EXOR elements).

On the other hand, Fig. 5B shows the configuration of a conventional galloche calculation circuit 34 '. In the conventional galloche arithmetic circuit 34 ', seven parallel arithmetic circuits R0 to R6 for each of the elements X are provided, and these seven parallel arithmetic circuits R0 to R6 provide a signal y0. , y1, y2, ..., y6) are computed simultaneously.

That is, in the case of the fourth-order error position detection polynomial "P (X) = p4X ⁴ + p3X ³ + p2X ² + p1X ¹ + p0", the conventional Galoache calculation circuit 34 'is shown in Fig. 6A. , Each operation (piX ^ i) is performed. On the other hand, the Galoache calculation circuit 34 according to the embodiment of the present invention, as shown in Figure 6b, polynomial (linear function "Q (X) = p4X ⁴ ) with terms having the same linear structure with respect to X + P2X ² + p1X ").

Then, for the linear function "Q (X) = p4X ⁴ + p2X ² + p1X", the calculation is performed by the base calculation unit 330 and the linear development unit 340 in the Galoache calculation circuit 34 shown in Fig. 5A. By doing so, in the calculation of the error position detection polynomial P (X), the number of units for calculating each term is reduced, and the number of elements in the circuit for adding the output between the units is also reduced. In addition, the terms "p3X ^ 3" and "P0" other than Q (X) are separately calculated by a circuit not shown in the galloche calculation circuit 34, and then "Q (X) = p4X ⁴ + p2X. ² + p1X "and the calculation result are added.

FIG. 7 is a diagram for explaining the operation of the galloace calculation circuit 34 shown in FIG. 5A, and is a diagram showing the variable X in a Becky expression of α. The galoache arithmetic circuit 34 shown in FIG. 7 sets elements (circles) X inputted to the base calculation unit 330 as 1, α, and α ^ 2, and is linear to X by the base calculation unit 330. The functions Q (1), Q (α), and Q (α ^ 2) are calculated, and Q (α ^ 3), Q (α ^ 4), Q (α ^ 5), Q by the linear expansion unit 340. (α ^ 6) is calculated.

As shown in FIG. 7, the Galoache calculation circuit 34 includes a base calculation unit 330 and a linear development unit 340, and the base calculation unit 330 includes three calculation units R0, R1, and R2. In addition, the linear development part 340 has four EXOR elements 341, 342, 343, and 344.

The calculating unit R0 in the base calculating unit 330 is a linear function Q (1) = p4 1 ⁴ + p2 1 ² + p1 1 ^{1 in} the error position detection polynomial corresponding to the element X (1 = α ^ 0). Is calculated by matrix operation. The calculation unit R1 calculates a linear function Q (α) = p4α ⁴ + p2α ² + p1α ¹ for the element X (= α ^ 1 = α) by matrix operation. R2 is operating section, the element X (= α2) of the linear function (= Q (α ^ 2) p4 (α 2) 4 + p2 (α 2) 2 + p1α 2) is calculated by a matrix operation.

The linear development unit 340 expands the calculation results Q (1), Q (α), and Q (α ^ 2) calculated by the base calculation unit 330 by simple addition to obtain different outputs. For example, as shown in Table 2 of the gallosome (GF (2 ^ 3)) of FIG. 4 at Q (α ^ 3), since "α ^ 3 = α + 1", "Q" by the linearity mentioned above is used. (α ^ 3) = Q (α) + Q (1) ". Therefore, Q (α ^ 3) can be obtained by adding the output Q (1) and Q (α) of the base calculation unit 330 by the EXOR element (adder) 341.

Further, in Q (α ^ 4), as shown in Table 2 of the gallosome (GF (2 ^ 3)) of FIG. 4, since "α ^ 4 = α ² + α", the linearity described above is " Q (α ^ 4) = Q (α ^ 2) + Q (α) ". Therefore, Q (α ^ 4) can be obtained by adding the output Q (α) and Q (α ^ 2) of the base calculation unit 330 by the EXOR element 342.

In Q (α ^ 5), "α ⁵ = α ² + α + 1" and "α ⁴ = α ² + α", and therefore "α ⁵ = α ⁴ +1". Therefore, Q (α ^ 5) can be obtained by adding the output Q (1) of the base calculation unit 330 and the output Q (α ^ 4) of the EXOR element 342 by the EXOR element 343. . Similarly, since Q (α ^ 6) is "α ⁶ = α ² +1", Q (α ^ 6) is the output Q (1) and Q (α) of the base calculation unit 330 by the EXOR element 344. Can be obtained by adding ^ 2).

As such, in the case of gallosome GF (2 ^ 3), the basis calculation unit 330 is configured to generate three linearly independent circles (1, α ^ 1, α ^ 2) corresponding to these circles. Calculate the linear functions Q (1), Q (α ^ 1) and Q (α ^ 2). In addition, the linear development unit 340 uses the linear functions Q (α ^ 3), Q (α ^ 4), Q (α ^ 5), and Q (α ^ 6) to Q (1) of the base calculation unit 330, Based on the calculation result of Q (α ^ 1) and Q (α ^ 2), it can be calculated by adding to an EXOR element. As such, in the galloise calculation circuit 34, four error position detection polynomials (more specifically, the error position detection polynomial) is obtained by subtracting the number of bases 3 from the total number 7 of values that the galloise element X can take. Linear function), the circuit scale is reduced by converting the matrix operation to simple addition.

In addition, in the example shown in FIG. 7, the bases of the vector representations 001, 010, 100 shown in Table 2 of FIG. 4 are used as three linear independent bases. However, it is not necessary to select a vector having only one bit as the basis. Any vectors can be selected as basis if the condition of the linear independent vector is satisfied.

As described above, the Galoache calculation circuit 34 according to an embodiment of the present invention integrates terms constituting the same linear space with respect to the error position detection polynomial as a linear function, and the basis calculation unit 330 for the integrated linear function. And linear development unit 340. As a result, the galloise calculation circuit 34 can greatly reduce the scale of the calculation element required when calculating the error position detection polynomial. In addition, the number of units that calculate each term of the error position detection polynomial is reduced, so that the number of elements in the circuit that adds the output between each unit is reduced.

Error Position Detection Polynomial Contains Linear Functions of X2 and X3

In the above-described embodiment, a galloise calculation circuit 34 for calculating a linear function for X (Q (X) = p1X ⁴ + p2x ² + p1X) has been described. In the following, an example is described where the error position detection polynomial Λ (X) includes a linear function for X and a linear function for X ^ 3.

For example, the error position detection polynomial (Λ (X)) is expressed by "P (X) = σ1X + σ2X ² + σ4X ⁴ + ... + σ3X ³ + σ6X ⁶ + σ12X ¹² + ... In this case, the linear function (M (X) = σ1X + σ2X ² + σ4X ⁴ + ...) in X and the linear function (N (X) = σ3X ³ + σ6X ⁶ + σ12X ¹² + ¹² ) in X3 By dividing and integrating each, we can perform the calculation separately for each linear function.

For example, FIG. 8 shows an example of a circuit that calculates a linear term for X. In the example shown in FIG. 8, similar to the circuit shown in FIG. 5, the base calculation unit 400 has three calculation units 401, 402, and 403, and the linear deployment unit 410 has four EXOR elements ( 411, 412, 413, 414.

The basis calculation unit 400 calculates M (α ^ 0) using the calculation unit 401, calculates M (α ^ 1) using the calculation unit 402, and uses M ( α ^ 2) is calculated. That is, the calculation unit 401 calculates the error position detection polynomial M (X) = sigma 1 1 + sigma 2 1 ² + sigma ⁴ 1 ⁴ + ... for the element X (1 = α ^ 0) by matrix operation. . The calculation unit 402 calculates the error position detection polynomial M (X) = sigma 1α + sigma 2α ² + sigma 4α ⁴ + ... for element X (= alpha ^ 1 = alpha) by matrix operation. In addition, the calculation unit 403 determines the error position detection polynomial (M (X) = sigma 1 (α ² ) + sigma 2 (α ² ) ² + sigma ⁴ (α ² ) ⁴ + ... for element X (= α ^ 2). ) Is calculated by matrix operation.

Then, the linear development unit 410 expands the calculation result calculated by the base calculation unit 400 by simple addition using the EXOR elements 411, 412, 413, and 414, M (α ^ 3), M (α ^ 4), M (α ^ 5) and M (α ^ 6) are calculated.

For example, in M (α ^ 3), as shown in Table 2 of the gallosome (GF (2 ^ 3)) of FIG. 4, since "α ^ 3 = α + 1", the linearity described above gives " M (α ^ 3) = M (α) + M (α ^ 0 = 1) ". Therefore, M (α ^ 3) can be obtained by adding the output M (α ^ 0 = 1) and M (α) of the base calculation unit 400 using the EXOR element (adder) 411. have.

In M (α ^ 4), as shown in Table 2 of the gallosome (GF (2 ^ 3)) of FIG. ⁴ , since "α ⁴ = α ² + α", the linearity described above is "M (α ^). 4) = M (α ^ 2) + M (α) ". Therefore, M (α ^ 4) can be obtained by adding the output M (α) and M (α2) of the base calculation unit 400 using the EXOR element 412.

Because ^{"α 5 = α 2 + α} + 1" , ^{and, "α 4 = α 2 +} α" in the M (α ^ 5), is the ^{"α 5 = α 4 +1"} . Therefore, M (α ^ 5) adds the output M (α ^ 0 = 1) of the base calculation unit 400 and the output M (α ^ 4) of the EXOR element 342 by using the EXOR element 413. Can be obtained.

Similarly, in M (α ^ 6), since "α ⁶ = α ² +1", M (α ^ 6) uses the EXOR element 414 to output M (α ^ 0 =) of the base calculation unit 400. Can be obtained by adding 1) and M (α ^ 2).

Therefore, in the galloise arithmetic circuit 34, the circuit scale of the arithmetic circuit with respect to the linear function (sigma 1X + sigma 2X ² + sigma 4X ⁴ + ...) can be reduced.

Next, the operation of the function (N (X) = sigma 3X ³ + sigma 6X ⁶ + sigma 12X ¹² + ...) for X ^ 3 will be described. FIG. 9 shows in Table 3 the trigonometry of the circle (circle shown in Table 2) of galloache (GF (2 ^ 3)) when the primitive polynomial shown in FIG. 4 is " X ³ + X + 1 " . In this case, the portion 1, α ^ 3, α ^ 6 enclosed by the dotted line in Fig. 9 is the basis, and the other circles α ^ 9, α ^ 12, α ^ 15, α ^ 18 are combinations of the basis. It may be indicated by.

Therefore, in the embodiment of the present invention, the linear function (N (X) = σ 3X ³ + sigma 6X ⁶ + sigma 12X ¹² + ...) that summarizes the terms X ^ 3, X ^ 6, X ^ 12, ... As shown in FIG. 10, the calculation is performed by dividing the basis calculation unit 500 and the linear development unit 510. However, the circuit pattern which expands a base with respect to the linear development part 510 is different from FIG. This is a linear function of "N (Y) = σ3Y + sigma 6Y ² + sigma 12Y ⁴ + ..." with respect to N (X) when Y = X ^ 3. This is because the sum of the bases shown in Fig. 3 can be expressed. In this example, since N (X) is not a nonlinear function of X but a linear function whose X ^ 3 is a variable, calculation is performed by the expansion of the bases, so that a circuit reduction effect equivalent to the circuit shown in FIG. Obtained.

In the example shown in Fig. 10, for the polynomial (N (X) = sigma 1X ³ + sigma 6X ⁶ + sigma 12X ¹² + ...), N (α ^ 0) is calculated using the calculation unit 501 in the base calculation unit 500. It is computed by matrix operation, N ((alpha) ^ 3) is calculated by matrix operation using the calculating part 502, and N ((alpha) ^ 6) is calculated by matrix operation using the calculating part 503. FIG. And, the linear development unit 510 is based on the calculation results N (α ^ 0), N (α ^ 3), N (α ^ 6) of the basis calculated by the base calculation unit 500, EXOR The elements 511, 512, 513, and 514 are used to calculate N (α ^ 9), N (α ^ 12), N (α ^ 15), N (α ^ 18),...

For example, in N (α ^ 9), as shown in Table 3 of FIG. 9, since "α ⁹ = α ⁶ +1", according to the linearity described above, "N (α ^ 9) = N (α) ^ 6) + N (α ^ 0 = 1) ". Therefore, N (α ^ 9) can be obtained by adding the outputs N (α ^ 0 = 1) and N (α6) of the base calculation unit 500 using the EXOR element (adder) 511. have.

In N (α ^ 12), as shown in Table 3 of FIG. 9, since "α ¹² = α ⁶ + α ³ + 1" and "α ⁹ = α ⁶ + 1", "α ¹² = α ⁹ + Α ³ ". Thus, according to the linearity described above, it can be developed as "N (α ^ 12) = N (α ^ 9) + N (α ^ 3)". N (α ^ 12) is obtained by adding the output N (α ^ 3) of the base calculation unit 500 and the output N (α ^ 9) of the EXOR element 512 using the EXOR element 512. Can be.

In N (α ^ 15), "α ¹⁵ = α ³ +1". Therefore, according to the linearity described above, N (α ^ 15) adds the outputs N (α ^ 0 = 1) and N (α ^ 3) of the base calculator 500 using the EXOR element 513. Can be obtained.

Similarly, in M (α ^ 18), since "α ¹⁸ = α ⁶ + α ³ ", N (α ^ 18) is the output N (α ^ 6) of the base calculation unit 500 using the EXOR element 514. ) And N (α ^ 3) can be obtained.

For this reason, the circuit scale can be reduced when in the Galois field operation circuit 34 performs an operation on a linear function (N (X) = ³ + σ3X σ6X σ12X ⁶ + ¹² + ···).

As described above, in the error detection correcting circuit 13 according to the embodiment of the present invention, the Galoache calculation circuit 34 is a circuit of a base calculation unit that calculates a basis and a circuit of a linear development unit that expands the base by simple addition. It has two things.

In the galloche arithmetic circuit 34, after the coefficient (pi (i = 0, 1, 2, ...)) of the galloche polynomial P (X) is determined, the error position detection polynomial P (X) For each linear function included in the), the base calculation unit 330 calculates the bases, and the linear development unit 340 outputs all the values that X of P (X) can take at a time by simple addition of these bases. You can do it. Thus, the circuit scale of the truncated arithmetic circuit 34 is reduced.

As shown in Figs. 8 and 10, integrating and calculating terms having the same linear structure reduces the number of units that calculate the terms of the polynomial, and also reduces the number of elements in the circuit that adds the output between each unit.

Concrete example of reduction effect of the number of elements by this embodiment

Next, the coefficient (pi (i = 0, 1, 2, ...)) and the m-th order polynomial (P (X)) whose variable (X) is the element of galloche (GF (2 ^ m)) By counting the number of elements used in the zero-determining circuit, the case of the prior art (in the case of the galloche arithmetic circuit 34 'of FIG. Are compared.

In the prior art, 2 m-1 matrix arithmetic circuits requiring about m (m-1) / 2 of EXOR elements are required, and n + 1 corresponding to the number of terms of the polynomial. Moreover, the EXOR element for adding each term requires 2 ^m -1 circuits which require m pieces, and this requires n pieces. Therefore, the total number of elements required for the circuit is (n + 1) × (2 ^m −1) × m (m −1) / 2 + n × (2 ^m −1) × m.

In the Galoache calculation circuit 34 according to the embodiment of the present invention, only m matrix calculation circuits requiring about m (m-1) / 2 EXOR elements are needed. The part which determines a value requires "2 ^m -1-m" ^m EXOR elements. The function of multiplying X by two Becky times, such as "X ^ 2, X ^ 4, X ^ 8, X ^ 16, ··", is a linear function on Galoache, and the linear combination of linear functions However, these terms can be integrated. Similarly, "X ^ 3, X ^ 6, X ^ 12, ...", "X ^ 5, X ^ 10, X ^ 20, ...", etc. can also be integrated.

Accordingly, the number of linear functions after integration is equal to the number of odd numbers less than or equal to the order n of the polynomial. Considering the integer term (p0), the number of units required after consolidation is 10 (0) when n = 0, 2 (0, 1) when n = 1, and 2 (0, 1) when n = 2. If n = 3, 3 (0, 1, 3), n = 4, 3 (0, 1, 3), n = 5, 4 (0, 1, 3, 5).

The number of units is n / 2 + 1 when n is even and n + 1 when n is odd (n + 1) / 2 + 1. Considering that the basis calculation part is not integrated, the number of elements required for the circuit is represented by Equation 8 when n is even and by Equation 9 when n is odd.

In Fig. 11A, when the order n = 4 of the polynomial, an example is shown in which the total number of elements of the prior art (Galoche arithmetic circuit 34 'shown in Fig. 5B) is compared with the embodiment of the present invention.

In Fig. 11B, when n = 8, an example is shown in which the total number of elements of the prior art (Galoche arithmetic circuit 34 'shown in Fig. 5B) is compared with the embodiment of the present invention. In accordance with an increase in the parameter m, which characterizes the crossharrow, embodiments of the present invention suppress an increase in circuit scale than in the prior art.

Next, the effectiveness other than the reduction of the circuit scale will be described. The circuit structure of the linear development portion 340 shown in FIG. 5A is independent of each bit of data to be handled. That is, the linear development unit 340 may be implemented with m circuits corresponding to 1 bit. This facilitates the reduction of the layout area of the circuit.

In addition, the linear expansion part corresponding to 1 bit is a circuit of "m input / 2m-1 output." The portion corresponding to the m bits is a circuit of " m ² input / 2 2 ^m −1 power output &quot;, and it is difficult to verify all the input / output patterns in a realistic time. On the other hand, since the unit of one bit is a circuit of "m input / 2m-1 output", all input / output patterns can be verified in a realistic time. By verifying all the input / output patterns with this unit and verifying the connection of the upper layer, more accurate verification can be performed. In addition, since the linear deployment unit 340 can be divided into m units, it is possible to maintain the output from one unit and obtain a final result with m clocks. In this case, m clocks are required until zero is obtained, but it is possible to reduce the circuit scale to about 1 / m in the embodiment of the present invention.

While the embodiments of the present invention have been described, the following will further explain the correspondence between the present invention and the above-described embodiments. That is, in the above embodiments, the galloache arithmetic circuit of the present invention corresponds to the galloache arithmetic circuit 34 in the Chien search unit 33 shown in FIG. 2, and the memory device of the present invention is shown in FIG. It corresponds to a volatile semiconductor memory device (NAND flash memory EEPROM) 10. The base calculation unit of the present invention corresponds to the base calculation unit 330 shown in FIG. 5, for example, and the linear development unit of the present invention corresponds to, for example, the linear development unit 340.

The error detection correction circuit of the present invention corresponds to the error detection correction circuit 13 shown in FIG. 2, and the syndrome calculation unit of the present invention corresponds to the syndrome calculation unit 31 in the decoder unit 30 shown in FIG. 2. The error coefficient calculation unit of the present invention corresponds to the error coefficient calculation unit 32, the Chien search unit of the present invention corresponds to the Chien search unit 33, and the error correction unit of the present invention corresponds to the error correction unit 35. do.

In the above-described embodiments, the galloache arithmetic circuit 34 is a vector of (2 ^m -1) circles represented by m bits on the galloise (GF (2 ^ m)) where m is an integer. Galoache arithmetic circuit substituted in the detection polynomial, and m circles are calculated from (2 ^m -1) circles from a base calculation unit 330 or ^m (2 ^m -1) circles. The linear development part 340 which obtains the excluded ( ^2m -1m) circle | round | yen by the combination of said m circles, respectively.

The galloche calculation circuit 34 is composed of a basis calculation unit 330 and a linear development unit 340. The basis calculation unit 330 calculates an error position detection polynomial for m circles that are linearly independent on galloise GF (2 ^ m). In addition, the calculation result of the linear expansion part 340 and the base calculation part 330 is computed at the time of the calculation of the error position detection polynomial corresponding to the remaining (2 ^m -1-m) circle except m linearly independent circles. Addition calculation is performed. For example, in the case of gallosomes (GF (2 ^ 3)), the linear function of X of the error position detection polynomial (P (X) = p4X ⁴ + p3X ³ + p2X ² + p1X ¹ + p0), for example For "Q (X) = p4X ⁴ + p2X ² + p1X", the basis calculation unit 330 is Q (1), Q (α) in three linearly independent circles (1, alpha ^ 1, alpha ^ 2). ^ 1), Q (α ^ 2) is calculated. In addition, the linear expansion unit 340 includes the linear functions Q (α ^ 3), Q (α ^ 4), and Q (α ^ 5) for the circles α ^ 3, α ^ 4, α ^ 5, α ^ 6. ), For Q (α ^ 6), based on the calculation result of Q (1), Q (α ^ 1), Q (α ^ 2), the calculation result Q (1), Q (α ^ 1), Q (α ^ 2) is added and calculated using the EXOR elements 341, 342, and 343.

Thus, the galloise arithmetic circuit 34 can reduce the circuit scale by transforming a conventional matrix operation into a simple addition.

In the above-described embodiments, the galloche arithmetic circuit 34 integrates the terms constituting the same linear space in the error position detection polynomial as a linear function, and integrates the integrated linear function into the base calculation unit 330 and the linear expansion unit 340. Calculate using Galoache calculation circuit 34 calculates by integrating terms having the same linear structure in the error position detection polynomial. Thus, by integrating the terms having the same linear structure, the number of units for calculating the terms of the polynomial is reduced, and the number of elements of the circuit for calculating the output between the units is also reduced.

In the above-described embodiments, the memory device (nonvolatile semiconductor memory device 10) uses an galloise calculation circuit 34 to calculate an error position detection polynomial and perform an error correction circuit for performing error detection of an input data string. Memory device (nonvolatile semiconductor memory device 10). The error detection correction circuit 13 includes a syndrome calculation unit 31 for calculating a syndrome from an input data string, an error coefficient calculation unit 32 for calculating a coefficient of an error position detection polynomial with the syndrome, and a bit position of data in the data string. Galois arithmetic circuit 34 for calculating by substituting the values and coefficients indicated by the error position detection polynomial, and Chien search outputting an error detection signal indicating whether or not there is an error for each bit of the data string in response to the substitution result of the error position detection polynomial. A unit 33 is provided with an error correction unit 35 for correcting and outputting an error of data of bits in a data string by an error detection signal.

When the memory device (nonvolatile semiconductor memory device 10) calculates the error position detection polynomial in the galloche arithmetic circuit 34, it uses the basis calculation unit 330 to set the galloche (GF (2 ^ m)). Compute the error position detection polynomial for m circles that are linearly independent on. The linear development unit 340 calculates an error position detection polynomial for the remaining (2 ^m -1-m) circles except for m independent circles, based on the calculation result of the base calculation unit 330. Generate by addition of result. Therefore, the circuit scale of the galloche calculation circuit 34 mounted in the memory device (nonvolatile semiconductor memory device 10) can be reduced. The memory device (nonvolatile semiconductor memory device 10) can mount on-chip an error detection and correction circuit capable of high speed operation.

In the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

10; Nonvolatile semiconductor memory 11; Memory cell array
12; Page buffer 13; Error detection correction circuit
14; Buffer 15; I / O pad
16; Control circuit 17; Address decoder
18; Low and Block Decoder
30; Decoder section 31; Syndrome calculator
32; An error coefficient calculator 33; Chien Seeker
34; Galloche calculation circuit 35; Error correction part
40; An encoder section 41; Parity generation circuit
330; Basis calculation unit 340; Linear development
400; Basis calculation unit 410; Linear development
500; Basis calculation unit 510; Linear development

Claims (8)

In a Galoache computation circuit that assigns (2 ^m -1) circles to the error-position detection polynomial vector represented by m bits on galoache (GF (2 ^ m)) (m is an integer):
A basis calculation unit for calculating linearly independent m circles from the (2 ^m -1) circles; And
And a linear development unit for calculating (2 ^m -1-m) circles except for the m circles from the (2 ^m -1) circles as a combination of the m circles, respectively. The method of claim 1,
Galoiche arithmetic circuit for integrating terms constituting the same linear space with respect to the error position detection polynomial as a linear function, and performing operations using the basis calculation unit and the linear expansion unit on the integrated linear function. A memory device having an error correction circuit for performing error detection of an input data string:
The error correction circuit,
A syndrome calculation unit for calculating a syndrome from the input data string;
An error coefficient calculation unit for calculating a coefficient of an error position detection polynomial with the syndrome;
A galloche arithmetic circuit for calculating a value indicating a position of a bit of data of said data string and said coefficient by substituting said error position detection polynomial;
A Chien search unit for outputting an error detection signal indicating whether or not there is an error for each bit of the data string in response to the substitution result of the error position detection polynomial; And
An error correction unit configured to correct and output an error of data of bits of the data string in response to the error detection signal,
The galloise calculation circuit is configured to substitute (2 ^m −1) circles, which are vector represented by m bits on galloise GF (2 ^ m), into an error position detection polynomial,
The galloche calculation circuit,
A basis calculation unit for calculating m independent circles from (2 ^m -1) circles (m is an integer); And
And (2 ^m -1-m) circles except for the m circles from the (2 ^m -1) circles, each of which includes a linear development unit for calculating a combination of the m circles. A plurality of computing devices, each of the plurality of computing devices calculating a linear function corresponding to a particular element of the polynomial, wherein the number of elements of the polynomial is greater than the number of the plurality of computing devices; And
Adding the output of the first computing device of the plurality of computing devices to the output of the second computing device of the plurality of computing devices, and separately outputting the output of the first computing device to the third computing device of the plurality of computing devices Galoache calculation circuit comprising a linear expansion to add. The method of claim 4, wherein
The output of the first computing device is Q (1), the output of the second computing device is Q (α), and the output of the third computing device is Q (α ² ). The method of claim 5,
The linear development is:
A first exclusive logical OR device for adding Q (1) and Q (α) to output Q (α ³ ); And
And a second exclusive logical sum device that adds the Q (α) and the Q (α ² ) to output Q (α ⁴ ). The method of claim 6,
The linear development is:
A third exclusive OR device that adds an output of the second exclusive OR device to the Q (1); And
And a fourth exclusive logical OR device for adding the Q (1) to the Q (α ² ). The method of claim 6,
The first computing device is a first matrix operation, where 'Q (1) = (p4) (1 ⁴ ) + (p2) (1 ² ) + in the error position detection polynomial corresponding to the element of X (1 = a ⁰ ). compute the linear function of (p1) (1 ¹ ) ',
The second computing device is a second matrix operation that corresponds to X (= α ¹ = α) where 'Q (α) = (p4) (α ⁴ ) + (p2) (α ² ) + (p1) (α ¹ ). Compute the linear function of
The third computing device is a third matrix operation that corresponds to an element of X (= α ² ) such that 'Q (α ² ) = (p4) ((α ² ) ⁴ ) + (p2) ((α ² ) ² ) Galoache arithmetic circuit for calculating a linear function of + (p1) (α ² ) '.

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