JP2019028952A - Storage device - Google Patents

Abstract

To provide a storage device which can detect an error of data in a data path.SOLUTION: A storage device includes a nonvolatile storage medium storing data, and a controller. The controller generates a first error detection code for detecting error in first data, generates a first flag indicating whether an error has been detected from at least one piece of first data of multiple pieces of first data included in second data, on the basis of the first error detection code, for the second data, generates a first error correction code for correcting an error in data including the second data and the first flag, and causes the nonvolatile storage medium to store the second data, the first flag, and the first error correction code.SELECTED DRAWING: Figure 12

Description

  Embodiments described herein relate generally to a storage device.

A semiconductor integrated circuit such as a SoC (System on a Chip) is often used as a controller for controlling a storage device. In recent years, a semiconductor process for manufacturing a semiconductor integrated circuit has been miniaturized and is easily affected by an external environment (for example, radiation such as α rays in the environment). For this reason, there is an increased possibility of data errors in the data path in the semiconductor integrated circuit.

JP 2013-137708 A JP 2011-187039 A Special table 2011-508349 gazette Special table 2010-515176 gazette

An object of the present invention is to provide a storage device that can detect an error in data in a data path.

In order to achieve the above object, a storage device according to an embodiment includes a nonvolatile storage medium that stores data and a controller. The controller generates a first error detection code capable of detecting an error for the first data, and at least one of the plurality of first data included in the second data for the second data including the plurality of first data. A first flag that indicates whether or not an error has been detected based on the first error detection code from the first data, and that can correct the error of the data including the second data and the first flag A correction code is generated, and the second data, the first flag, and the first error correction code are stored in the nonvolatile storage medium.

It is a block diagram explaining the structure of the memory | storage device of 1st Embodiment. It is a figure explaining the various function parts implement | achieved by execution of the firmware which concerns on 1st Embodiment. It is a figure explaining the write data path which concerns on 1st Embodiment. It is a figure explaining the data format in the write data path which concerns on 1st Embodiment. It is a figure explaining the structure of the E2E production | generation circuit which concerns on 1st Embodiment. It is a figure explaining the structure of the E2E test | inspection circuit and compressed parity generation circuit which concern on 1st Embodiment. It is a figure explaining the structure of the ECC generation circuit which concerns on 1st Embodiment. It is a figure explaining the read data path concerning a 1st embodiment. It is a figure explaining the data format in the read data path which concerns on 1st Embodiment. It is a figure explaining the structure of the compression parity fixed circuit which concerns on 1st Embodiment. It is a figure explaining the structure of the ECC correction circuit which concerns on 1st Embodiment. It is a figure explaining the error detection of the data which concerns on 1st Embodiment. It is a figure explaining the structure of the E2E production | generation circuit which concerns on 1st Embodiment. It is a figure explaining the structure of the E2E test | inspection circuit which concerns on 1st Embodiment. It is a figure explaining the modification which concerns on 1st Embodiment. It is a figure explaining the data format in the write data path which concerns on 2nd Embodiment. It is a figure explaining the structure of the E2E production | generation circuit which concerns on 2nd Embodiment. It is a figure explaining the structure of the E2E test | inspection circuit and compressed parity generation circuit which concern on 2nd Embodiment. It is a figure explaining the data format in the read data path which concerns on 2nd Embodiment. It is a figure explaining the structure of the E2E production | generation circuit which concerns on 2nd Embodiment. It is a figure explaining the structure of the E2E test | inspection circuit which concerns on 2nd Embodiment.

Hereinafter, a storage device according to an embodiment will be described with reference to the drawings. In the following explanation,
Components having the same function and configuration are denoted by common reference numerals.

[First embodiment]
FIG. 1 is a block diagram illustrating the configuration of the storage device according to the first embodiment.

The storage device 1 can communicate with the host 2. The storage device 1 includes a controller 10, a nonvolatile storage medium 20, and a buffer 30.

The controller 10 communicates with the host 2 and controls the operation of the entire storage device 1. The controller 10 is a semiconductor integrated circuit configured as, for example, a SoC (System on a Chip).

In the description of the present embodiment, the host 2 is a computer that supports an interface of the SATA (Serial ATA) standard, but other standards such as SAS (Seria).
It may be a computer that supports an interface of l Attached SCSI) standard or NVMe (NVM Express) (registered trademark) standard.

The nonvolatile storage medium 20 stores data in a nonvolatile manner (permanently). The nonvolatile storage medium 20 of the present embodiment is a NAND flash memory, but is not limited to this. For example, 3D structure flash memory, NOR type flash memory, MRAM (M
It may be a semiconductor memory such as an anisotropic random access memory) or a disk medium such as a magnetic disk or an optical disk. In the following description, the nonvolatile storage medium 20 may be referred to as a NAND memory 20.

The buffer 30 stores data volatilely (temporarily). The data stored in the buffer 30 includes (1) user data received from the host 2, (2) user data read from the NAND memory 20, and (3) information necessary for the controller 10 to control the storage device 1. and so on. The buffer 30 of this embodiment is a DRAM (Dynamic Ran
dom Access Memory), but SRAM (Static Rando)
Other types of volatile semiconductor memories, such as m Access Memory). The buffer 30 may be built in the controller 10.

The controller 10 includes a CPU (Central Processing Unit) 4
0, a host interface (IF) control unit 50, a buffer control unit 60, and a memory interface (IF) control unit 70.

The CPU 40 controls the entire storage device 1 based on FW (Firmware). FIG.
These are figures which show the various function parts implement | achieved when CPU40 performs FW. CP
The U 40 functions as a processing unit 42 that controls the entire storage device 1. The processing unit 42 includes a host processing unit 44, a buffer processing unit 46, and a memory processing unit 48. Host processing unit 44
Mainly controls the host IF controller 50. The buffer processing unit 46 includes a buffer control unit 60.
The main control. The memory processing unit 48 mainly controls the memory IF control unit 70. CPU4
0 may not be built in the controller 10 and may be a separate semiconductor integrated circuit. In addition, in the following description, a part or all of the functions executed by the FW is a dedicated HW (Hardwa
re), and a part or all of the functions executed by the HW can be executed by the FW
It is also possible to execute by.

  Returning to FIG.

  The host IF control unit 50 interprets and executes commands received from the host 2.

The buffer control unit 60 controls the writing and reading of data to the buffer 30, and
Management of free space in the buffer 30 is performed.

The memory IF control unit 70 includes a NAND control unit 80. The NAND control unit 80 is connected to the NAN
It controls operations such as writing, reading, and erasing data in the D memory 20.

The NAND control unit 80 includes an ECC control unit 100. The ECC control unit 100 is a NAND
An error correction code is added to the data written to the memory 20. In addition, the ECC control unit 100 performs error correction processing on the data read from the NAND memory 20 based on the error correction code. As the error correction code, any code can be adopted as long as the error position in the data can be specified at the time of error correction. For example, RS (Reed
Solomon) code, BCH (Bose Chaudhuri Hocquenge)
m) A code can be used. LDPC (Low Density Parity C
In the case of using a (hex) code, the ECC control unit 1 can identify the error position in the data by comparing the data before error correction and the data after error correction.
If 00 is configured, this embodiment can be adopted.

[Write data path]
Hereinafter, the write data path in this embodiment will be described with reference to FIGS.

  FIG. 3 is a diagram for explaining a write data path in the controller 10.

  The host IF control unit 50 includes a CRC check circuit 52 and an E2E generation circuit 54.

An error detection code is added to user data received from the host 2 for each predetermined data amount (for example, 4 kB) based on the interface standard. The error detection code is, for example, CRC
(Cyclic Redundancy Check). The CRC inspection circuit 52
Check the error detection code and verify the validity of the user data. The output of the CRC check circuit 52 has a data width of, for example, 64 bits (that is, 8B). The CRC check circuit 52 outputs 8B of user data (data D1 shown in FIG. 4A) per cycle.

The data D1 is input to the E2E generation circuit 54 as shown in FIG. The E2E generation circuit 54 applies an end-to-end data protection parity (hereinafter referred to as E2E_) to the data D1.
P)). The E2E generation circuit 54 adds E2E_P to the data D1, and generates data D2 as shown in FIG. 4B. As shown in FIG. 5, the E2E generation circuit 54 performs, for example, an exclusive OR (XOR) operation on the data D1, thereby obtaining E2E_P.
Is generated. As shown in FIG. 3, the E2E generation circuit 54 outputs data D2. E2E
The output of the generation circuit 54 has a data width of 65 bits, for example. The E2E generation circuit outputs 1 bit + 8B of data D2 per cycle.

The buffer control unit 60 stores the data D2 in the buffer 30. The buffer control unit 60 reads the data D2 from the buffer 30 and inputs it to the NAND control unit 80. The buffer control unit 60 may add a stronger error detection code (for example, CRC) when storing the data D2 in the buffer 30.

The NAND control unit 80 includes an E2E check circuit 81 and a compressed parity generation circuit 82.

The E2E inspection circuit 81 applies E2 to the data D2 input from the buffer control unit 60.
The validity of the data D2 is verified by checking E_P. E2E_P test result,
The user data in the data D2 is input to the compressed parity generation circuit 82.

FIG. 6 shows the E2E_P check by the E2E check circuit 81 and the compressed parity generation circuit 8.
2 is a diagram for explaining generation of compressed parity by 2. FIG. The E2E inspection circuit 81 generates data D2 (
For example, an XOR operation (hereinafter referred to as E2E check) is performed on 1 bit + 8B) to check the validity of the data D2. If there is no error in the data D2, the result of the E2E inspection (hereinafter referred to as the E2E inspection result) is zero. If there is an error in data D2, E2E
The inspection result is 1.

The compressed parity generation circuit 82 includes a data latch 83, a data latch 84, and an OR circuit 85. Each of the data latch 83 and the data latch 84 is plural (for example, 64).
The E2E inspection result for the data D2 and the corresponding user data are held. The E2E test results held by the data latch 83 are input to the OR circuit 85 every 64 pieces, and ORed (ORed). The result of the OR operation is the compressed parity CMP_P. As described above, the E2E inspection result is 0 if there is no error in the data D2. Therefore, if there is no error in all 64 pieces of data D2, CMP_P is also 0. On the other hand, if any one of the 64 pieces of data D2 has an error, CMP_P becomes 1. The compressed parity generation circuit 82 outputs user data corresponding to 64 pieces of data D2 held by CMP_P and the data latch 84 as data D3. As shown in FIG. 4C, the data D3 is 1
It has a size of bit + 512B.

As shown in FIG. 3, the data D3 output from the compressed parity generation circuit 82 is input to the ECC control unit 100.

The ECC control unit 100 includes an ECC generation circuit 101. The ECC generation circuit 101 is similar to that shown in FIG.
As shown in FIG. 2, the data latch 102 and the code generation circuit 103 are included. Data latch 1
02 holds a plurality (for example, 8) of data D3. 8 held by the data latch 102
The pieces of data D3 are input to the code generation circuit 103. The code generation circuit 103 is, for example, 3
A 12B error correction code ECC is generated. The ECC generation circuit 101 outputs the eight data D3 held by the ECC and data latch 102 as data D4. Data D4 is
As shown in FIG. 4D, for example, it has a size of 312B + 8 bits + 4 kB.

  The data D4 is stored in the NAND memory 20 as shown in FIG.

[Read data path]
Hereinafter, the read data path in the present embodiment will be described with reference to FIGS.

  FIG. 8 is a diagram for explaining a read data path in the controller 10.

The NAND control unit 80 includes a compressed parity fixing circuit 86 and an E2E generation circuit 87.

The NAND control unit 80 reads the data D5 from the NAND memory 20. The data D5 is input to the compressed parity fixing circuit 86. As shown in FIG. 9A, the data D5 has a size of 312B + 8 bits + 4 kB, for example. Data D5 is equivalent to data D4 in the write data path, but may contain errors.

As shown in FIG. 10, the compressed parity fixing circuit 86 is connected to the compressed parity CM in the data D5.
P_P is converted to fixed parity FIX_P. FIX_P is a value fixed to 0, for example. The compressed parity fixing circuit 86 combines the ECC in the data D5, FIX_P, and the user data in the data D5, and outputs it as data D6. As shown in FIG. 9B, the data D6 has a size of 312B + 8 bits + 4 kB, for example. Data D6 is shown in FIG.
As shown in FIG.

The ECC control unit 100 includes an ECC correction circuit 104. The ECC correction circuit 104 is shown in FIG.
As shown in FIG. 1, an error correction circuit 105 and a data latch 106 are included. The error correction circuit 105 performs error correction on the data D6 based on the error correction code ECC in the data D6. As described above, the error correction circuit 105 can specify the error position in the data D6. In particular, the error correction circuit 105 can specify the location of the error in the FIX_P in the data D6.

As shown in FIG. 12, the compressed parity CMP_P in the data D3 is 0 when there is no error for all the data D2 corresponding to the data D3. The compressed parity CMP_P in the data D3 is 1 when there is an error for at least one data D2 corresponding to the data D3.

On the other hand, FIX_P in the data D6 is fixed to 0 as described above. Therefore, when the compressed parity CMP_P in the data D4 is 0, the error correction circuit 105 does not detect an error in the FIX_P of the data D6 corresponding thereto. Further, when the compressed parity CMP_P in the data D4 is 1, the error correction circuit 105 fixes the FIX of the data D6 corresponding thereto.
An error is always detected in _P.

Accordingly, an error is detected from FIX_P of data D6 corresponding to data D3 including at least one data D2 in which an error is detected in the E2E inspection. F of data D6 corresponding to data D3 not including any data D2 in which an error is detected in the E2E inspection
No error is detected from IX_P.

As shown in FIG. 11, the data latch 106 stores 51 user data that has been subjected to error correction.
Hold 2B at a time. Further, the data latch 106 holds a flag (hereinafter referred to as an error flag) indicating whether or not an error is detected in the FIX_P corresponding to the 512B user data. The error flag is 1 when an error is detected in FIX_P. The error flag is
It is 0 when no error is detected in FIX_P.

The ECC correction circuit 104 outputs the user data subjected to error correction held by the data latch 106 as data D7 together with an error flag corresponding to the user data every 512B. The data D7 has a size of 1 bit + 512B as shown in FIG. 9C.

  As shown in FIG. 8, the data D <b> 7 is input to the E2E generation circuit 87.

As shown in FIG. 13, the E2E generation circuit 87 includes a data latch 88, an exclusive OR circuit 89, a logic inversion circuit 90, and a selection circuit 91.

The data latch 88 holds the input data D7. The exclusive OR circuit 89 performs exclusive OR (XO) on user data in the data D7 held by the data latch 88 by 8B.
R) Calculate. The logic inversion circuit 90 performs a logic inversion operation on the output of the exclusive OR circuit 89.

The selection circuit 91 selects and outputs the output of the exclusive OR circuit 89 and the output of the logic inversion circuit 90 based on the error flag in the data D7 held by the data latch 88. Specifically, when the error flag is 0, the output of the exclusive OR circuit 89 is selected. Error flag is 1
In this case, the output of the logic inversion circuit 90 is selected. The output of the selection circuit 91 is data D described later.
8 becomes an end-to-end data protection parity (E2E_P).

The E2E generation circuit 87 outputs the output of the selection circuit 91 (that is, E2E_P) and the user data held by the data latch 88 as data D8 by 8B. The output of the E2E generation circuit 87 has a data width of 65 bits, for example. The E2E generation circuit 87 outputs 64 pieces of data D8 corresponding to one piece of data D7 over 64 cycles. Data D8
Has a size of 1 bit + 8B, as shown in FIG. 9D.

The buffer control unit 60 stores the data D8 in the buffer 30 as shown in FIG. The buffer control unit 60 reads the data D8 from the buffer 30 and inputs it to the host IF control unit 50. The buffer control unit 60 may add a stronger error detection code (for example, CRC) when storing the data D8 in the buffer 30.

  The host IF control unit 50 includes an E2E inspection circuit 56 and a CRC generation circuit 58.

As shown in FIG. 14, the E2E check circuit 56 checks the validity of the data D8 by performing, for example, an XOR operation (hereinafter referred to as E2E check) on the data D8 (1 bit + 8B). If there is no error in the data D8, the result of the E2E inspection (hereinafter referred to as the E2E inspection result) is zero. If the data D8 has an error, the E2E inspection result is 1.

As described above, when the error flag in the data D7 is 0, E2 added to the data D8
E_P is an output of the exclusive OR circuit 89. Therefore, the error flag in the data D7 is 0.
In this case, no error is detected from the E2E inspection on the data D8 corresponding to all the user data included in the data D7.

When the error flag in the data D7 is 1, E2E_P added to the data D8 is
This is the output of the logic inversion circuit 90. Therefore, when the error flag in the data D7 is 1, an error is detected from the E2E inspection for the data D8 corresponding to all the user data included in the data D7. Note that when the error flag in the data D7 is 1, the selection circuit 91 may be configured so that an error is detected from the E2E inspection for at least one data D8 corresponding to the user data included in the data D7. .

When the E2E inspection result is 1 (that is, when an error is detected), the host IF control circuit 50 discards the data D8 without transmitting it to the host 2. This can prevent user data in which an error has occurred in either the write data path or the read data path from being transmitted to the host 2.

When the E2E test result is 0 (that is, when no error is detected), the host IF control circuit 50 removes E2E_P from the data D8 and generates data D9.

The data D9 is input to the CRC generation circuit 58 as shown in FIG. The CRC generation circuit 58 performs a predetermined data amount (for example, 4 k) on the data D9 based on the interface standard.
An error detection code (for example, CRC) is added every B) and transmitted to the host 2.

When the E2E inspection result is 1, instead of discarding the data D8, an error detection code is generated so that an error is detected when an error detection code is generated from the data D9 corresponding to the data D8. Also good.

Although the protection of user data has been described above, the data that can be protected by the storage device 1 of this embodiment is not limited to this. For example, system data such as management data can be protected in the same manner as user data protection described above.

In the above description, as shown in FIG. 15A, when no error is detected in the E2E inspection for the data D2, CMP_P in the corresponding data D3 is set to 0, and an error is detected in the E2E inspection for the data D2. When it was detected, CMP_P in the data D3 corresponding to this was set to 1. In addition, FIX_P in the data D6 is fixed to 0. The storage device 1 of the present embodiment may be configured as described below.

[First Modification]
In the storage device 1 of the first modified example, as shown in FIG. 15B, when no error is detected in the E2E inspection for the data D2, CMP_P in the corresponding data D3 is set to 0, and E2E for the data D2 is set. When an error is detected in the inspection, CMP_P in data D3 corresponding to the error is set to 1. Further, FIX_P in the data D6 is fixed to 1. In this case, the error flag in the data D7 corresponding to the user data for which no error was detected in the E2E inspection for the data D2 is 1. Further, the error flag in the data D7 corresponding to the user data in which an error is detected in the E2E inspection for the data D2 is 0.

The selection circuit 91 in the memory device 1 of the first modification selects the output of the exclusive OR circuit 89 when the error flag is 1, and outputs the output of the logic inversion circuit 90 when the error flag is 0. select.

[Second Modification]
In the storage device 1 of the second modification, as shown in FIG. 15C, when no error is detected in the E2E inspection for the data D2, CMP_P in the data D3 corresponding thereto is set to 1, and E2E for the data D2 is set. When an error is detected in the inspection, CMP_P in data D3 corresponding to the error is set to zero. This is realized by, for example, setting CMP_P as a result of logical inversion operation of the output of the OR circuit 85. Further, FIX_P in the data D6 is fixed to 0. In this case, the error flag in the data D7 corresponding to the user data for which no error was detected in the E2E inspection for the data D2 is 1. Further, the error flag in the data D7 corresponding to the user data in which an error is detected in the E2E inspection for the data D2 is 0.

The selection circuit 91 in the storage device 1 of the second modification selects the output of the exclusive OR circuit 89 when the error flag is 1, and outputs the output of the logic inversion circuit 90 when the error flag is 0. select.

[Third Modification]
In the storage device 1 of the third modified example, as shown in FIG. 15D, when no error is detected in the E2E inspection for the data D2, CMP_P in the corresponding data D3 is set to 1, and E2E for the data D2 is set. When an error is detected in the inspection, CMP_P in data D3 corresponding to the error is set to zero. This is realized by, for example, setting CMP_P as a result of logical inversion operation of the output of the OR circuit 85. Further, FIX_P in the data D6 is fixed to 1. In this case, the error flag in the data D7 corresponding to the user data for which no error was detected in the E2E inspection for the data D2 is 0. Further, the error flag in the data D7 corresponding to the user data in which an error is detected in the E2E inspection for the data D2 is 1.

The selection circuit 91 in the storage device 1 of the third modification selects the output of the exclusive OR circuit 89 when the error flag is 0, and outputs the output of the logic inversion circuit 90 when the error flag is 1. select.

According to the first embodiment described above, the storage device generates a compressed parity from the end-to-end data protection parity, and stores it in the nonvolatile storage medium together with the user data and the error correction code. The storage device can detect whether there is an error in the compressed parity by performing error correction after setting the compressed parity portion read from the nonvolatile storage medium to a fixed value. As a result, the storage device can detect an error in the data in the data path.

[Second Embodiment]
In the storage device of the first embodiment, the end-to-end data protection parity (E2E_
As P), 1-bit parity capable of detecting an error of 1 bit per 8B was used. On the other hand, in the storage device of this embodiment, for example, an error detection code (for example, an 8-bit Hamming code) capable of correcting a 1-bit error and detecting a 2-bit error per 8B is used as E2E_P. In the following description, only different points from the first embodiment will be described.

[Write data path]
Hereinafter, the write data path in the present embodiment will be described with reference to FIGS.

16A to 16D are diagrams illustrating the format of each data in the write data path. 16A to 16D correspond to FIGS. 4A to 4D of the first embodiment, respectively. Only data D2 shown in FIG. 16B is different from data D2 shown in FIG. 4B. That is, E2E_P included in the data D2 is an 8-bit Hamming code (HM code), and the data D2 has a size of 8 bits + 8B.

FIG. 17 is a diagram illustrating the configuration of the E2E generation circuit 54A of the present embodiment. FIG.
This corresponds to FIG. 5 of the first embodiment. The E2E generation circuit 54A of the present embodiment includes an HM code generation circuit 55. Since the configuration of the HM code generation circuit 55 is well known to those skilled in the art, a detailed description thereof will be omitted. The HM code generation circuit 55 generates an 8-bit HM code capable of correcting a 1-bit error and detecting a 2-bit error with respect to the 8B data D1. The HM code generation circuit 55 adds the HM code as E2E_P to the data D1, and outputs the data D2.

FIG. 18 is a diagram illustrating the configuration of the E2E inspection circuit 81A of the present embodiment. FIG.
This corresponds to FIG. 6 of the first embodiment. The E2E inspection circuit 81A of this embodiment includes an HM code inspection circuit 92. Since the configuration of the HM code inspection circuit 92 is well known to those skilled in the art, a detailed description thereof will be omitted. The HM code check circuit 92 verifies the validity of the data D2 by checking the E2E_P, that is, the 8-bit HM code, with respect to the data D2. When a 2-bit error is detected from the data D2, the E2E inspection circuit 81A outputs 1 as the E2E inspection result. When no error is detected from the data D2, or when a 1-bit error is corrected, the E2E inspection circuit 81A outputs 0 as the E2E inspection result. Similar to the first embodiment, the E2E check results are collected into 1-bit compressed parity CMP_P. The user data in the data D2 is held by the data latch 84 after the error is corrected by the HM code check circuit 92.

[Read data path]
Next, the read data path in the present embodiment will be described with reference to FIGS.

19A to 19D are diagrams for explaining the format of each data in the read data path. 19A to 19D correspond to FIGS. 9A to 9D of the first embodiment, respectively. Only data D8 shown in FIG. 19D is different from data D8 shown in FIG. 9D. That is, E2E_P included in the data D8 is an 8-bit Hamming code (HM code), and the data D8 has a size of 8 bits + 8B.

FIG. 20 is a diagram illustrating the configuration of the E2E generation circuit 87A of the present embodiment. FIG.
This corresponds to FIG. 13 of the first embodiment. The E2E generation circuit 87A of this embodiment includes an HM code generation circuit 93. Since the configuration of the HM code generation circuit 93 is well known to those skilled in the art, a detailed description thereof will be omitted. The HM code generation circuit 93 can correct a 1-bit error and detect a 2-bit error with respect to 8B user data in the data D7 held by the data latch 88.
An 8-bit HM code is generated. The logic inversion circuit 90 performs a logic inversion operation on at least two bits of the output of the HM code generation circuit 93, that is, the number of bits exceeding the error detection capability by the HM code.

FIG. 21 is a diagram illustrating the configuration of the E2E inspection circuit 56A of the present embodiment. FIG.
This corresponds to FIG. 14 of the first embodiment. The E2E inspection circuit 56A of this embodiment includes an HM code inspection circuit 57. Since the configuration of the HM code inspection circuit 57 is well known to those skilled in the art, a detailed description thereof will be omitted. The HM code checking circuit 57 verifies the validity of the data D8 by checking the E2E_P, that is, the 8-bit HM code with respect to the data D8. When a 2-bit error is detected from the data D8, the E2E check circuit 56A discards the data D8.
When no error is detected from the data D8 or when a 1-bit error is corrected, the E2E check circuit 56A removes E2E_P of the data D8 and generates data D9. The user data in the data D8 is output as data D9 after the error is corrected by the HM code inspection circuit 57.

According to the storage device of the second embodiment described above, an error detection code capable of detecting a multi-bit error is used as the end-to-end data protection parity, so that data protection can be further strengthened. it can.

According to at least one embodiment described above, the storage device generates a compressed parity from the end-to-end data protection parity and stores it in the nonvolatile storage medium together with the user data and the error correction code. The storage device can detect whether there is an error in the compressed parity by performing error correction after setting the compressed parity portion read from the nonvolatile storage medium to a fixed value. As a result, the storage device can detect an error in the data in the data path.

Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Memory | storage device, 2 ... Host, 10 ... Controller, 20 ... Nonvolatile storage medium, 30 ... Buffer, 40 ... CPU, 42 ... Processing part, 44 ... Host processing part, 46 ... Buffer processing part, 4
8 ... Memory processing unit, 50 ... Host interface control unit, 52 ... CRC check circuit, 54 ...
E2E generation circuit, 55... HM code generation circuit, 56... E2E check circuit, 57... HM code check circuit, 58... CRC generation circuit, 60 ... Buffer control unit, 70 ... Memory interface control unit, 80 ... NAND control unit, 81 ... E2E check circuit, 82 ... compressed parity generation circuit, 83
... Data latch, 84 ... Data latch, 85 ... OR circuit, 86 ... Compressed parity fixing circuit, 87 ... E2E generation circuit, 88 ... Data latch, 89 ... Exclusive OR circuit, 90 ... Logic inversion circuit, 91 ... Selection Circuit, 92... HM code inspection circuit, 93... HM code generation circuit, 100.
ECC control unit 101 ... ECC generation circuit 102 ... data latch 103 ... code generation circuit 104 ... ECC correction circuit 105 ... error correction circuit 106 ... data latch

Claims (6)

A non-volatile storage medium for storing data;
Generating a first error detection code capable of error detection for the first data;
For second data including a plurality of the first data,
Generating a first flag indicating whether an error has been detected based on the first error detection code from at least one of the plurality of first data included in the second data;
Generating a first error correction code capable of error correction for data including the second data and the first flag;
A controller for storing the second data, the first flag, and the first error correction code in the nonvolatile storage medium;
A storage device comprising: The controller is
Including a first error correction circuit capable of specifying a position of an error included in the data based on the error correction code;
The controller is
Third data corresponding to the second data read from the nonvolatile storage medium;
A fixed flag corresponding to the first flag and having a fixed value;
A second error correction code corresponding to the first error correction code read from the nonvolatile storage medium;
The storage device according to claim 1, wherein the first error correction circuit is input to the first error correction circuit. The controller is
Dividing the third data into a plurality of fourth data;
When the first error correction circuit detects an error in the fixed flag corresponding to the third data,
Generating at least one fourth data corresponding to the third data a second error detection code indicating that the fourth data is incorrect;
The storage device according to claim 2. The controller is
Read data from the non-volatile storage medium based on a request from the host,
When an error is detected for the fourth data based on the second error detection code,
The storage device according to claim 3, wherein the fourth data is not transmitted to the host. The controller is
5. The storage device according to claim 1, wherein the first error detection code is generated by performing an exclusive OR operation on each bit constituting the first data. 6. The controller is
The storage device according to claim 1, wherein a Hamming code for the first data is generated as the first error detection code.

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