JP2010079856A - Storage device and memory control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve the efficient mirroring of data processing by using a non-volatile semiconductor memory. <P>SOLUTION: In a storage device 6, when receiving the write-in instruction of data from a host device 3, a memory control part 1 writes the data in both two non-volatile semiconductor memories 2, and when receiving the readout instruction of the data from the host device 3, the memory control part 1 reads the corresponding data from one of the two semiconductor memories 2, and checks whether or not there exists an error in the read data, and when deciding that there exists the error in the read data, the memory control part 1 reads the corresponding data from the other semiconductor memory 2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique of mirroring (storing and using the same data in a plurality of storage devices) using a nonvolatile semiconductor memory.

  In recent years, as an auxiliary storage device for information equipment, in addition to a magnetic disk storage device, a storage device using a semiconductor memory excellent in vibration resistance and access speed as a storage medium has been used. Among them, in particular, those using an electrically erasable and rewritable nonvolatile semiconductor memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory) such as a flash memory is an auxiliary storage device of information equipment. It has become mainstream.

  In general, the reliability of data stored in a nonvolatile semiconductor memory cannot be said to be sufficiently high due to the characteristics of the element. That is, in a storage device using a nonvolatile semiconductor memory, data is damaged due to bit corruption (“0” → “1” or “1” → “0”) at an initial stage or with an increase in the number of rewrites. May occur.

  Therefore, mirroring is one of the effective means to make up for the drawbacks of such a nonvolatile semiconductor memory. For example, if the same data is stored in two places by mirroring, even if one data is damaged, if the other data is not damaged, there is no problem by using the non-damaged data. It is.

For example, in Patent Document 1, mirroring is performed using two flash memories, and when data is read, the corresponding data is read from both flash memories and compared, and if they match, normal (no data corruption), A technique is disclosed that increases the reliability of data by determining an abnormality (with data corruption) if they do not match.
JP 2007-257547 A

  However, in the technique of Patent Document 1, when data is read out, it is necessary to read out the corresponding data from both flash memories and compare whether the two read out data match. There was a problem that it was not good.

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to realize efficient data processing mirroring using a nonvolatile semiconductor memory.

In order to solve the above-mentioned problem, the present invention provides two nonvolatile semiconductors that perform data writing to a storage area in a predetermined unit and erase data in units of physical blocks having a larger data amount than the predetermined unit. A storage device includes a memory and a memory control unit that controls writing and reading of data to and from two nonvolatile semiconductor memories in accordance with instructions from an external host device.
When receiving a data write instruction from the host device, the memory control unit writes the data to both of the two nonvolatile semiconductor memories, and when receiving a data read instruction from the host device, the two nonvolatile semiconductors Read the corresponding data from one of the memories, check if there is an error in the read data, and read the corresponding data from the other of the two nonvolatile semiconductor memories when it is determined that there is an error in the read data It is characterized by that. Other means will be described later.

  According to the present invention, efficient mirroring of data processing can be realized using a nonvolatile semiconductor memory.

  Hereinafter, the best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described with reference to the drawings (refer to drawings other than the referenced drawings as appropriate). FIG. 1 is an explanatory diagram including the hardware configuration of the storage device of this embodiment.

  As shown in FIG. 1, the storage device 6 is a device that stores data based on an instruction from the host device 3, and is connected to the host device 3 via the data bus 4 so as to be accessible. As the data bus 4, for example, a small computer system interface (SCSI) or an advanced technology attachment (ATA) is used, but another data bus such as a USB (Universal Serial Bus) may be used.

  The storage device 6 includes a memory control unit 1 and two nonvolatile semiconductor memories 2 (2a, 2b) that form a pair for mirroring. Hereinafter, when the two semiconductor memories 2 are distinguished from each other, they are expressed as “semiconductor memory (A system) 2a” and “semiconductor memory (B system) 2b” without distinguishing the two semiconductor memories 2 ( When expressed in terms of (common or both), it is expressed as “semiconductor memory 2”.

  Data exchange between the semiconductor memory 2 and the memory control unit 1 is performed via the data bus 5. The semiconductor memory 2 is, for example, a flash memory. In this case, data writing and reading are performed in units of pages (predetermined units), and data is erased in units of blocks composed of a plurality of pages. The blocks include, for example, a data block in which data has already been stored, a replacement block in which data is not stored and is waiting, and an erasure waiting block in a state waiting for data erasure. In some cases, the detailed description that has been distinguished is omitted.

  The memory control unit 1 includes a microprocessor 11, a memory I / F (interface) control unit 12, a host I / F control unit 13, and a memory 14.

  The microprocessor 11 controls writing and reading of data to and from the two semiconductor memories 2 in accordance with instructions from the host device 3.

  The memory I / F control unit 12 performs access control with the semiconductor memory 2 according to an instruction from the microprocessor 11. Note that the memory I / F control unit 12 is not necessarily required if the microprocessor 11 can directly control the semiconductor memory 2.

  The host I / F control unit 13 controls data transmission / reception with the host device 3 in accordance with data write / read requests (instructions) from the host device 3. Note that data write and read requests from the host device 3 are made to a logical storage area constructed with respect to the semiconductor memory 2 (details will be described later).

  The memory 14 has a logical / physical conversion table 141. The logical / physical conversion table 141 is a table for associating a logical address indicated at the time of access from the host device 3 with a physical address on the two semiconductor memories 2 (details will be described later in FIG. 3).

  The memory 14 also manages a table for managing the next write page for each block, a table for storing a list of replacement blocks, a table for managing the number of times of erasure for each block, and a block waiting for erasure. However, since they are not directly related to the features of the present invention, illustrations and detailed descriptions are omitted. The contents of tables such as the logical / physical conversion table 141 are set by the microprocessor 11 when the storage device 6 itself is initialized.

  As the memory 14, for example, a memory element such as an SRAM (Static Random Access Memory), a DRAM (Dynamic RAM), or an MRAM (Magneto-resistive RAM) other than the flash memory can be used.

  FIG. 2 is a diagram showing an internal configuration of the semiconductor memory according to the present embodiment. FIG. 2 shows a logical storage area related to the semiconductor memory 2. The host device 3 shown in FIG. 1 recognizes this logical storage area with respect to the storage device 6.

  The block 21 is a minimum unit for erasing data. The page 211 is a unit for reading and writing data. In FIG. 2, the logical storage area of the semiconductor memory 2 is composed of a plurality of blocks 21, and the block 21 is composed of a plurality of pages 211. That is, the logical storage area of the semiconductor memory 2 has m blocks 21 from block 1 to block m (integer), and each block includes n blocks from page 1 to page n (integer). Has a page.

  FIG. 3 is a diagram showing a configuration example of the logical / physical conversion table. The logical / physical conversion table 141 includes a logical address indicated at the time of access from the host device 3, a physical block of the semiconductor memory (A system) 2a, a physical block of the semiconductor memory (B system) 2b, and the two physical blocks. And a common page number. In the present embodiment, “block” and “physical block” are synonymous.

  Among these, the value of the logical address remains unchanged from the initial setting in principle, but the physical block of the semiconductor memory (A system) 2a, the physical block of the semiconductor memory (B system) 2b, and the page number values are: Rewriting is performed according to a write operation to the semiconductor memory 2 by the memory control unit 1. That is, the correspondence relationship between the logical address and the physical address (block number and page number) changes at any time, and the correspondence relationship is managed by the logical / physical conversion table 141.

  As can be seen from the logical / physical conversion table 141 of FIG. 3, by making the page number common to the physical block of the semiconductor memory (A system) 2a and the physical block of the semiconductor memory (B system) 2b, The data size of the physical conversion table 141 can be reduced, and thereby the speed of rewriting and referring to the logical / physical conversion table 141 by the microprocessor 11 can be increased.

  Next, with reference to FIG. 4, an outline of the operation of the microprocessor 11 on the semiconductor memory 2 to make the page number common to two physical blocks in the logical / physical conversion table 141 will be described. FIG. 4 is an explanatory diagram of the outline of the operation.

  Here, it is assumed that page 5 is defective in a physical block having the semiconductor memory (A system) 2a, and all pages are not defective in a physical block having the semiconductor memory (B system) 2b. When data (1) to (6) is written to these two physical blocks, the page number is shared between the two physical blocks, so page 5 of both physical blocks is not used and both physical blocks are used. Data (1) to (4) are written to pages 1 to 4 of the block, and data (5) and (6) are written to pages 6 and 7. In this way, the page number can be made common to the two physical blocks.

  Subsequently, a writing process to the semiconductor memory 2 will be described with reference to FIG. FIG. 5 is a flowchart showing a writing process to the semiconductor memory. Note that description of the operations of the memory I / F control unit 12 and the host I / F control unit 13 is omitted.

First, the microprocessor 11 receives a write instruction (logical address, data, data size) from the host device 3 (step S501).
Next, the microprocessor 11 adds a CRC (Cyclic Redundancy Check) code to the data received in step S501 (step S502). The CRC code is a code for error (error) detection, and a remainder obtained by dividing data by a predetermined generator polynomial is used as a numerical value for error detection. If this CRC code is used, error detection of data can be performed, but data cannot be recovered when an error is detected.

  Subsequently, the microprocessor 11 adds a Reed-Solomon code to the data to which the CRC code is added in step S502 (step S503). The Reed-Solomon code is one of error (error) correction codes using the Galois field concept. If this Reed-Solomon code is used, error detection can be performed, and data can be recovered with high probability when an error is detected.

  Next, the microprocessor 11 refers to the logical / physical conversion table 141 in order to specify the physical address of the semiconductor memory 2 to be written, and the predetermined block of the semiconductor memory (A system) 2a and the semiconductor memory (B system). The data to which the Reed-Solomon code is added in step S503 is written to the same page of each block for the predetermined block 2b (step S504). In step S504, the microprocessor 11 confirms whether the free space of the page in each specified block is sufficient, and if the free space is insufficient, the microprocessor 11 performs a block replacement process in which the writing target is another block. The block replacement process associated with the write error is performed, but detailed description thereof is omitted.

  Subsequently, the microprocessor 11 updates the contents of the logical / physical conversion table 141 in accordance with the processing contents in step S504 (step S505), notifies the host device 3 of the end of writing (step S506), and ends the processing. To do.

  Next, read processing for the semiconductor memory 2 will be described with reference to FIGS. 6A and 6B. 6A and 6B are flowcharts showing a read process for the semiconductor memory. Note that description of the operations of the memory I / F control unit 12 and the host I / F control unit 13 is omitted.

First, the microprocessor 11 receives a read instruction (logical address) from the host device 3 (step S601).
Next, the microprocessor 11 refers to the logical / physical conversion table 141 and reads out the corresponding data from one semiconductor memory 2, for example, the semiconductor memory (A system) 2a (step S602). The semiconductor memory 2 to be read in step S602 may be, for example, alternating between the semiconductor memory (A system) 2a and the semiconductor memory (B system) 2b, or may be determined according to other criteria.

  Subsequently, the microprocessor 11 performs Reed-Solomon decoding on the data read in step S602 (step S603), and determines whether there is an error (step S604).

  If it is determined that there is no error (No in step S604), the process proceeds to step S607. If it is determined that there is an error (Yes in step S604), the microprocessor 11 determines whether or not the error can be corrected (step S605).

  If it is determined that error correction is not possible (No in step S605), the process proceeds to step S609 (the process in step S609 will be described later). If it is determined that error correction is possible (Yes in step S605), the microprocessor 11 performs error correction by Reed-Solomon (step S606), and proceeds to step S607. In step S606, in order to avoid performance degradation of the semiconductor memory 2, it is preferable to perform block replacement processing in which error-corrected data is written to another block and the read data is erased.

In step S607, the microprocessor 11 performs CRC decoding and error check based on the CRC decoding.
Next, the microprocessor 11 determines whether or not there is an error due to the CRC check (step S608). When it is determined that there is no error (No), the microprocessor 11 proceeds to step S618 and when it is determined that there is the error ( Yes) Since valid data could not be read from the block, the block is registered as abnormal (not used) in the logical / physical conversion table 141 (step S609).

  After step S609, the microprocessor 11 refers to the logical / physical conversion table 141, and reads the corresponding data from the other semiconductor memory 2, for example, the semiconductor memory (B system) 2b (step S610). Since the processing of steps S611 to S617 is similar to the processing of steps S603 to S609, the description thereof is omitted.

  In step S618, the microprocessor 11 transmits data to the host device 3 (step S618), and mirroring is restored in the background (free time) as necessary (data of the error occurrence portion is moved to another location). (Step S619), and the process ends.

  After step S617, necessary data could not be read from both the semiconductor memories 2 here, so the microprocessor 11 sends a read error notification to the host device 3 (step S620) and ends the process.

  As described above, according to the storage device 6 of the present embodiment, when data is read, the data is first read from only one of the two semiconductor memories 2, and the read data is checked for errors, and the read data is read out. When it is determined that there is an error, reading the corresponding data from the other semiconductor memory 2 makes it possible to realize mirroring with efficient data processing.

  Further, by making the page number common to a predetermined block of the two semiconductor memories 2 in the logical / physical conversion table 141, the data size of the logical / physical conversion table 141 can be reduced. The rewrite and reference operations of the logical / physical conversion table 141 by the microprocessor 11 can be speeded up.

  Furthermore, by using a CRC code for error checking of read data, for example, there is an advantage that it has a higher error detection capability compared to the redundancy check compared to the error check of the parity check method, and burst errors (errors are concentrated). It is possible to have advantages such as being strong against In addition, a high error correction function can be realized by using Reed-Solomon codes for error checking of read data.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to this, It can implement in the range which does not change the meaning. For example, efficient mirroring of data processing according to the present invention can be realized without adopting a method in which page numbers are common to predetermined blocks of two semiconductor memories 2. In addition, specific configurations of hardware and software can be appropriately changed without departing from the gist of the present invention.

It is explanatory drawing containing the hardware constitutions of the memory | storage device of this embodiment. It is the figure which showed the internal structure of the semiconductor memory of this embodiment. It is the figure which showed the structural example of the logical / physical conversion table. It is explanatory drawing of the outline | summary of operation | movement with respect to two semiconductor memories. 5 is a flowchart showing a writing process to a semiconductor memory. It is the flowchart which showed the read-out process with respect to a semiconductor memory. It is the flowchart which showed the read-out process with respect to a semiconductor memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory control part 2 Semiconductor memory 2a Semiconductor memory (A system)
2b Semiconductor memory (B system)
3 Host device 4 Data bus 5 Data bus 6 Storage device 11 Microprocessor 12 Memory I / F control unit 13 Host I / F control unit 14 Memory 21 block 141 Logical / physical conversion table 211 pages

Claims (6)

Two nonvolatile semiconductor memories that perform writing of data to the storage area in a predetermined unit and erase data in units of physical blocks having a data amount larger than the predetermined unit;
A memory control unit that controls writing and reading of data to and from the two nonvolatile semiconductor memories in accordance with instructions from an external host device;
A storage device comprising:
The memory control unit
When receiving a data write instruction from the host device, the data is written to both of the two nonvolatile semiconductor memories,
When receiving a data read instruction from the host device, the corresponding data is read from one of the two nonvolatile semiconductor memories, the read data is checked for errors, and the read data has errors. When it is determined, the corresponding data is read from the other of the two nonvolatile semiconductor memories. The memory control unit
When receiving the data write instruction from the host device and writing the data to both of the two nonvolatile semiconductor memories, the predetermined physical block of one of the nonvolatile semiconductor memories and the other nonvolatile semiconductor The storage device according to claim 1, wherein the same data is written to the same address in the predetermined unit with respect to the predetermined physical block of the memory. The memory control unit
3. The storage device according to claim 1, wherein when checking whether there is an error in the read data, at least one of a CRC (Cyclic Redundancy Check) code and a Reed-Solomon code is used. Two nonvolatile semiconductor memories that perform writing of data to the storage area in a predetermined unit and erase data in units of physical blocks having a data amount larger than the predetermined unit;
A memory control unit that controls writing and reading of data to and from the two nonvolatile semiconductor memories in accordance with instructions from an external host device;
A memory control method using a storage device comprising:
The memory control unit
When receiving a data write instruction from the host device, the data is written to both of the two nonvolatile semiconductor memories,
When receiving a data read instruction from the host device, the corresponding data is read from one of the two nonvolatile semiconductor memories, the read data is checked for errors, and the read data has errors. When it is determined that the corresponding data is read out from the other of the two non-volatile semiconductor memories, a memory control method. The memory control unit
When receiving the data write instruction from the host device and writing the data to both of the two nonvolatile semiconductor memories, the predetermined physical block of one of the nonvolatile semiconductor memories and the other nonvolatile semiconductor 5. The memory control method according to claim 4, wherein control is performed so that the same data is written to the same address in the predetermined unit with respect to the predetermined physical block of the memory. The memory control unit
6. The memory control method according to claim 4, wherein when checking whether there is an error in the read data, at least one of a CRC (Cyclic Redundancy Check) code and a Reed-Solomon code is used.

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