JP2010128697A - Memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve data reliability of a specific area storing management information. <P>SOLUTION: A memory system 1 includes a nonvolatile memory having a first storage area 22 and a second storage area 21, and a controller 12 for raising error correction capability higher than the first storage area 22 when writing into the second storage area 21. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory system, for example, a memory system including a nonvolatile memory such as a NAND flash memory.

  In recent years, nonvolatile memories such as flash memories have been used as storage devices for electronic devices such as PCs (personal computers), mobile phones, digital cameras, and PDAs (personal digital assistants). In particular, a memory card in which a flash memory is detachable from an electronic device is used.

  A memory cell constituting a flash memory has a stacked gate structure in which a floating gate electrode, an inter-gate insulating film, and a control gate electrode are stacked in this order on a semiconductor substrate via a tunnel insulating film. Yes. In a flash memory having such a configuration, excessive electrons are injected into the floating gate electrode at the time of writing, and the threshold voltage of the memory cell becomes abnormally high. Electron injected into the floating gate electrode leaks to the substrate, etc., or leakage electron from the substrate etc. injects into the floating gate electrode, resulting in a retention failure that inverts the original data to reverse data There is.

  On the other hand, a file system is used for recording data in the flash memory. The flash memory is provided with a management area to store management information such as a file system, and performs writing, reading, erasing, and the like of data based on the management information. For this reason, if the data in the management area is corrupted, it becomes impossible to access the data recorded in the flash memory.

In addition, as a related technique of this type, a method is disclosed in which a pair of blocks is used when storing updated management information, thereby increasing resistance to a management information write error (see Patent Document 1).
Japanese Patent Laid-Open No. 2004-280752

  The present invention provides a memory system capable of improving the data reliability of a specific area for storing management information and the like.

  A memory system according to one embodiment of the present invention includes a non-volatile memory having a first storage area and a second storage area, and a more error than the first storage area when writing to the second storage area. And a controller for increasing the correction capability.

  ADVANTAGE OF THE INVENTION According to this invention, the memory system which can improve the data reliability of the specific area | region which stores management information etc. can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

[First Embodiment]
Various types of memory systems including a non-volatile memory (for example, a NAND flash memory) can be considered. Among the various memory systems, in this embodiment, a memory card will be described as an example. The memory card is configured to be detachable from a slot provided in the host device 2 and operates in a state where it is mounted on the host device. However, the present invention is not limited to the memory card, and the memory system and the host device may be configured as one LSI (Large-Scale Integrated Circuit). That is, a controller and a nonvolatile semiconductor memory that constitute a memory system may be mounted on a printed board on which a host device is mounted.

[1. Configuration of Memory System 1]
FIG. 1 is a block diagram showing a configuration of a memory system (memory card) 1 according to the first embodiment of the present invention. The memory card 1 operates upon receiving power supply when connected to the host device 2, and performs processing in response to an access request from the host device 2. The host device 2 includes hardware and software for accessing the memory card 1 connected via the bus interface. The host device 2 includes a power supply circuit for supplying power to the memory card 1.

  The memory card 1 exchanges data with the host device 2 via the bus interface. The memory card 1 includes a NAND flash memory 11 that is a kind of nonvolatile memory, and a memory controller 12 that controls the NAND flash memory 11. Note that the nonvolatile memory is not limited to the NAND flash memory 11, and various types of nonvolatile memories can be used.

  The memory controller 12 has a physical state inside the NAND flash memory 11 (for example, which physical block address includes data of which logical sector address or which block is in an erased state). Manage. The memory controller 12 includes a host interface (host I / F) 13, a CPU (Central Processing Unit) 14, a ROM (Read-only memory) 15, a RAM (Random access memory) 16, a buffer 17, a memory interface (memory I / F). ) 18, a first ECC (Error Check and Correct) circuit 19, and a second ECC circuit 20.

  The host interface 13 performs interface processing between the memory controller 12 and the host device 2 according to a predetermined protocol. The memory interface 18 performs an interface process between the memory controller 12 and the NAND flash memory 11 according to a predetermined protocol.

  The ROM 15 stores a control program and the like used by the CPU 14. The RAM 16 is used as a work area for the CPU 14 and stores a control program read from the ROM 15 and various tables. The buffer 17 temporarily stores a certain amount of data based on the host interface or writes data read from the NAND flash memory 11 when writing data sent from the host device 2 to the NAND flash memory 11. When sending to the host device 2, a certain amount of data is temporarily stored.

  The CPU 14 controls the operation of the entire memory card 1. When the memory card 1 receives power supply from the host device 2, the CPU 14 reads out a control program stored in the ROM 15 or the NAND flash memory 11 and executes predetermined processing, or from the ROM 15 or the NAND flash memory 11. Various tables are created on the RAM 16 using the read data, and predetermined processing is executed using the tables. In addition, the CPU 14 receives a write command, a read command, an erase command, and the like from the host device 2, and executes a write process, a read process, an erase process, and the like on the NAND flash memory 11 based on these commands.

  Each of the first ECC circuit 19 and the second ECC circuit 20 generates an error correction code for each data portion having a predetermined number of bits (or the number of bytes) for write data sent from the host device 2. To do. Each error correction code is stored in the NAND flash memory 11 together with a data portion corresponding thereto. In addition, each of the first ECC circuit 19 and the second ECC circuit 20 uses an error correction code that is simultaneously read for read data sent from the NAND flash memory 11, and generates an error for each data portion. Perform detection and correction. After correcting the error, the ECC circuit sends the data to the buffer 17 with the error correction code removed. Therefore, read data that does not include an error correction code is sent from the memory card 1 to the host device 2.

  FIG. 2 is a schematic diagram showing a logical configuration of the NAND flash memory 11. The NAND flash memory 11 includes a file system management area 21 and a user area 22. The file system management area 21 is from the start address “0” to the address “X−1”, and the user area 22 is after the address “X”. The address shown in FIG. 2 represents a logical address.

  The user area 22 is used for storing user data (data such as documents, still images, and moving images) that can be freely read and written by the user.

  On the other hand, the file system management area 21 includes management information on data stored in the user area 22 and various management information on the NAND flash memory 11 (basically, the user cannot freely read and write, This is used to store information used by the host device 2 and the memory controller 12 when the NAND flash memory 11 is activated. The file system management area 21 stores a file system that is a method for managing data stored in the NAND flash memory 11. In the file system, a method of creating a file or a folder (directory) in the NAND flash memory 11, moving or deleting the file, a method of recording data, a location of a management area, a usage method, and the like are determined. ing.

  FIG. 3 is a schematic diagram showing the structure of the NAND flash memory 11. Each page has, for example, 4224 bytes. Among these, for example, 4096 bytes are used as a data area and the remaining 128 bytes are used as a redundant area. A page is a unit for writing or reading data. The block is composed of a plurality of pages and is a data erasing unit. In addition to the storage area, the NAND flash memory 11 includes a page buffer that holds data in units of pages. In the present embodiment, the storage capacity of the page buffer is 4224 bytes, which is the same as the capacity of one page. Data is exchanged between the NAND flash memory 11 and the memory interface 18 via the page buffer.

  FIG. 4 is an equivalent circuit diagram showing a configuration of one block included in the NAND flash memory 11.

  The block includes (m + 1) NAND strings arranged in order along the X direction (m is a natural number of 1 or more). Each NAND string includes two select transistors ST1 and ST2 and (n + 1) memory cell transistors MT (n is a natural number of 1 or more). The select transistors ST1 included in each of (m + 1) NAND strings have drains connected to the bit lines BL0 to BLm and gates commonly connected to the select gate line SGD. In addition, the selection transistor ST2 has a source commonly connected to the source line SL and a gate commonly connected to the selection gate line SGS.

  Each memory cell transistor MT is a MOSFET (metal oxide semiconductor field effect transistor) having a stacked gate structure formed on a semiconductor substrate with a gate insulating film (tunnel insulating film) interposed therebetween. The stacked gate structure includes a charge storage layer (floating gate electrode) formed on the gate insulating film and a control gate electrode formed on the charge storage layer with an inter-gate insulating film interposed. The memory cell transistor MT changes its threshold voltage according to the number of electrons injected into the floating gate electrode, and stores data according to the difference in threshold voltage.

  In each NAND string, (n + 1) memory cell transistors MT are arranged such that their current paths are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. That is, the plurality of memory cell transistors MT are connected in series in the Y direction so that adjacent ones share a diffusion region (source region or drain region).

  The control gate electrodes are connected to the word lines WL0 to WLn in order from the memory cell transistor MT located closest to the drain side. Therefore, the drain of the memory cell transistor MT connected to the word line WL0 is connected to the source of the selection transistor ST1, and the source of the memory cell transistor MT connected to the word line WLn is connected to the drain of the selection transistor ST2.

  The word lines WL0 to WLn connect the control gate electrodes of the memory cell transistors MT in common between the NAND strings in the block. That is, the control gate electrodes of the memory cell transistors MT in the same row in the block are connected to the same word line WL. The (m + 1) memory cell transistors MT connected to the same word line WL are handled as one page, and data writing and data reading are performed for each page.

  The bit lines BL0 to BLm connect the drains of the selection transistors ST1 in common between the blocks. That is, NAND strings in the same column in a plurality of blocks are connected to the same bit line BL.

  The memory cell transistor MT included in the NAND flash memory 11 according to the present embodiment may be configured to store a binary value (1 bit), or store a multi-value (2 bits or more). It may be configured.

[2. Operation of memory card 1]
Next, the operation of the memory card 1 configured as described above will be described. FIG. 5 is a flowchart showing the data writing operation of the memory card 1. At the time of data writing, the host device 2 sends a write command, an address, and write data to the memory card 1. The memory controller 12 receives these write command, address, and write data (step S100). The address here means a logical address.

  Subsequently, the memory controller 12 determines whether the address indicates the file system management area 21 or the user area 22, that is, whether the address is smaller than “X” (step S101). In the present embodiment, the write processing method is changed for each of the file system management area 21 and the user area 22. If the address is smaller than “X”, the memory controller 12 executes a write process to the file system management area 21 (step S102). On the other hand, if the address is “X” or more, the memory controller 12 executes a write process to the user area 22 (step S103).

[2-1. Write operation to user area 22]
First, the writing process to the user area 22 in step S103 will be described. FIG. 6 is a flowchart showing a writing process to the user area 22. FIG. 7 is a schematic diagram specifically explaining the writing process to the user area 22. For example, it is assumed that a 512-byte write access to address “Y” has occurred. The address “Y” is equal to or higher than the address “X”. Therefore, the address “Y” indicates the user area 22.

  First, the memory controller 12 divides the write data, for example, in units of 256 bytes (step S200). Assuming that the minimum data size handled between the host device 2 and the memory card 1 is 512 bytes, 8 data each of 512 bytes are stored in the data area in one page. It corresponds to these 8 data and includes 8 redundant areas each of 16 bytes. In this embodiment, the 512-byte write data is divided into two data portions each having 256 bytes, so that the entire 4096-byte data area included in one page is divided into 16 data areas each having 256 bytes. Will be divided. Also, a 128-byte all redundant area included in one page is divided into 16 redundant areas each of 8 bytes.

  Subsequently, the first ECC circuit 19 generates an error correction code for each 256-byte data portion (step S201). In this case, the size of the error correction code is, for example, 3 bytes. The first ECC circuit 19 has a correction capability of 1 bit and a detection capability of 2 bits, and can correct random errors. Therefore, the first ECC circuit 19 can correct an error of 1 bit per 256 bytes.

  Subsequently, the memory controller 12 writes the write data in the data area in the user area 22 in units of 256 bytes. Further, the memory controller 12 writes the error correction code corresponding to the data portion of 256 bytes in the 8-byte redundant area provided corresponding to the error correction code (step S202).

  Specifically, as shown in FIG. 7, when 512 bytes of write data is written to the page “A” in the user area 22, the write data is divided into two data portions each having 256 bytes. Are stored in the data area 1 and the data area 2, respectively. Further, the first ECC circuit 19 generates an error correction code ECC1 for the first data portion, and an error correction code ECC2 for the second data portion. The error correction code ECC1 is The 8-byte redundant area corresponding to the data area 1 is stored, and the error correction code ECC2 is stored in the 8-byte redundant area corresponding to the data area 2. Thus, the writing process to the user area 22 is performed.

[2-2. Write Operation to File System Management Area 21]
Next, the writing process to the file system management area 21 in step S102 will be described. FIG. 8 is a flowchart showing a writing process to the file system management area 21. FIG. 9 is a schematic diagram specifically explaining the writing process to the file system management area 21. For example, it is assumed that a 512-byte write access has occurred for the address “Z”. The address “Z” is smaller than the address “X”. Therefore, the address “Z” indicates the file system management area 21.

  First, the memory controller 12 divides write data, for example, in units of 32 bytes (step S300). Assuming that the minimum data size handled between the host device 2 and the memory card 1 is 512 bytes, 8 data each of 512 bytes are stored in the data area in one page. It corresponds to these 8 data and includes 8 redundant areas each of 16 bytes. In this embodiment, since 512-byte write data is divided in units of 32 bytes, the 512-byte data area is divided into 16 data areas each having 32 bytes. Therefore, the entire 4096-byte data area included in one page is divided into 128 data areas each having 32 bytes. An 8-byte redundant area is provided corresponding to 8 data areas each having 32 bytes.

  Subsequently, the second ECC circuit 20 generates an error correction code for each 32-byte data portion (step S301). In this case, the size of the error correction code is, for example, 2 bytes. The second ECC circuit 20 has a correction capability of 1 bit and a detection capability of 2 bits, and can correct random errors. Therefore, the second ECC circuit 20 can correct an error of 1 bit per 32 bytes.

  Subsequently, the memory controller 12 writes the write data in the data area in the file system management area 21 in units of 32 bytes. That is, the data size at the time of writing to the file system management area 21 is set to 1/8 or less of the data size at the time of writing to the user area 22. Further, the memory controller 12 writes all error correction codes generated for the write data in the data area in the file system management area 21 (step S302).

  Specifically, as shown in FIG. 9, when 512 bytes of write data is written to page “B” in the file system management area 21, this write data is divided into 16 data portions each of 32 bytes. These are stored in the data area 1 to the data area 16, respectively. Also, 16 ECCs (ECC 1 to ECC 16) are generated for the 16 data parts by the second ECC circuit 20, and these ECC 1 to ECC 16 are stored in the data area 113, for example. In this way, the writing process to the file system management area 21 is performed.

[2-3. Data read operation]
Next, the data read operation of the memory card 1 will be described. When reading data, the host device 2 sends a read command and an address to the memory card 1. When receiving a read access, the memory controller 12 changes the data read method according to the address.

  When the address is “X” or more, the memory controller 12 determines that it is a read access to the user area 22. In this case, since the read data and the error correction code are written in the data area and the redundant area shown in FIG. 7, the memory controller 12 reads the read data and the error correction code from the data area and the redundant area. The storage location of the data and error correction code can be determined by, for example, storing the management information in advance in the redundant area in the user area 22 and confirming the management information.

  Subsequently, the first ECC circuit 19 executes error correction for each data portion of 256 bytes using the error correction code. Then, the memory controller 12 sends the read data whose error has been corrected to the host device 2.

  On the other hand, if the address is smaller than “X”, the memory controller 12 determines that the access is a read access to the file system management area 21. In this case, since the read data and the error correction code are written in the data area shown in FIG. 9, the memory controller 12 reads the read data and the error correction code from these data areas. The storage location of the data and the error correction code can be determined by, for example, storing the management information in advance in the redundant area in the file system management area 21 and confirming the management information.

  Subsequently, the second ECC circuit 20 executes error correction for each 32-byte data portion using the error correction code. Then, the memory controller 12 sends the read data whose error has been corrected to the host device 2.

  As described above in detail, in the first embodiment, the NAND flash memory 11 includes the file system management area 21 and the user area 22, and the memory controller 12 corresponds to the file system management area 21 and the user area 22. However, the method for writing and reading data is changed. That is, for the user area 22, error correction code generation and error correction processing are executed in units of a first data size (for example, 256 bytes), and for the file system management area 21, the first data size is set. Error correction code generation and error correction processing are executed in units of a smaller second data size (for example, 32 bytes).

  Therefore, according to the first embodiment, it is possible to increase the error correction capability with respect to the specific area (file system management area 21), and important data such as the file system and management information stored in the specific area can be stored. Reliability can be improved. As a result, the reliability of the entire memory system can be improved. In addition, it is possible to increase the error correction capability for the file system management area 21 while suppressing the storage capacity of the file system management area 21 from decreasing.

[Second Embodiment]
In the second embodiment, the method of writing the error correction code to the file system management area 21 is changed, and this error correction code is stored in the redundant area of the file system management area 21.

  FIG. 10 is a schematic diagram showing the configuration of one page in the file system management area 21 according to the second embodiment of the present invention.

  In the NAND flash memory 11 of the present embodiment, each page has, for example, 4480 bytes, of which 4096 bytes are used as a data area and the remaining 384 bytes are used as a redundant area.

  When writing data to the file system management area 21, the memory controller 12 divides the write data in units of 32 bytes. Assuming that the minimum data size handled between the host device 2 and the memory card 1 is 512 bytes, 8 data each of 512 bytes are stored in the data area in one page. It corresponds to these 8 data and includes 8 redundant areas of 48 bytes each. Also in this embodiment, since 512-byte write data is divided in units of 32 bytes, the 512-byte data area is divided into 16 data areas each having 32 bytes. Therefore, the entire 4096-byte data area included in one page is divided into 128 data areas each having 32 bytes. Further, the entire 384-byte redundant area included in one page corresponds to 128 data areas and is divided into 128 redundant areas of 3 bytes each.

  Here, as shown in FIG. 10, the memory controller 12 converts the 16 ECCs (ECC1 to ECC16) generated for the 512-byte write data by the second ECC circuit 20 into the data areas 1 to data, respectively. The data is stored in 16 redundant areas corresponding to the area 16.

  At the time of data reading, the memory controller 12 reads the read data and the error correction code from the data area and the redundant area. The storage location of the data and the error correction code can be determined by, for example, storing the management information in advance in the data area or the redundant area in the file system management area 21 and confirming the management information. Then, the second ECC circuit 20 performs error correction for each 32-byte data portion using the error correction code. Then, the memory controller 12 sends the read data subjected to error correction to the host device 2. Note that the writing method to the user area 22 and the reading method from the user area 22 are the same as those in the first embodiment.

  As described above in detail, according to the second embodiment, as in the first embodiment, it is possible to increase the error correction capability for the specific area (file system management area 21) and store it in the specific area. It is possible to improve the reliability of important data such as file systems and management information. Further, in this embodiment, it is not necessary to store the error correction code in the data area, so that it is possible to prevent the storage capacity of the data area of the file system management area 21 from being reduced.

  In each of the above embodiments, the NAND type nonvolatile semiconductor memory has been described as an example. However, the present invention is also applicable to a NOR type, AND type, and DINOR (Divided bit-line NOR) type nonvolatile semiconductor memory. Is possible.

  The present invention is not limited to the above-described embodiment, and can be embodied by modifying the components without departing from the scope of the invention. In addition, various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the embodiments, or constituent elements of different embodiments may be appropriately combined.

1 is a block diagram showing a configuration of a memory card 1 according to a first embodiment of the present invention. 1 is a schematic diagram showing a logical configuration of a NAND flash memory 11. FIG. 1 is a schematic diagram showing the structure of a NAND flash memory 11. FIG. FIG. 2 is an equivalent circuit diagram showing a configuration of one block included in the NAND flash memory 11. 4 is a flowchart showing a data writing operation of the memory card 1. 5 is a flowchart showing a writing process to a user area 22. FIG. 5 is a schematic diagram specifically explaining a writing process to a user area. 10 is a flowchart showing a write process to the file system management area 21. FIG. 3 is a schematic diagram specifically explaining a writing process to a file system management area 21. Schematic which shows the structure of 1 page in the file system management area | region 21 which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

  MT ... memory cell transistor, ST1, ST2 ... selection transistor, SGD, SGS ... selection gate line, SL ... source line, WL ... word line, BL ... bit line, 1 ... memory system, 2 ... host device, 11 ... NAND type Flash memory, 12 ... Memory controller, 13 ... Host interface, 14 ... CPU, 15 ... ROM, 16 ... RAM, 17 ... Buffer, 18 ... Memory interface, 19 ... First ECC circuit, 20 ... Second ECC circuit, 21 ... File system management area, 22 ... User area.

Claims (5)

A non-volatile memory having a first storage area and a second storage area;
A controller that has an error correction capability higher than that of the first storage area when writing to the second storage area;
A memory system comprising: A first ECC (Error Check and Correct) circuit that generates a first error correction code in units of a first data size when writing to the first storage area;
A second ECC circuit that generates a second error correction code in a second data size unit smaller than the first data size when writing to the second storage area;
The memory system according to claim 1, further comprising: The controller divides write data into the first data size when writing to the first storage area, and divides the write data into the second data size when writing to the second storage area. Then write,
The memory system according to claim 2, wherein the second data size is 1/8 or less of the first data size.   The controller writes the first error correction code in a redundant area of the first storage area, and writes the second error correction code in a redundant area of the second storage area. 4. The memory system according to 2 or 3.   5. The memory system according to claim 1, wherein the controller selects a writing method to the first storage area and the second storage area based on an address at the time of writing.

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