TWI674767B - Turbo product codes for nand flash - Google Patents

Abstract

A method for encoding data in a data block includes: XOR of all data bits in the data block and XOR of parity check bits of all rows in the data block except the last Generate the first XOR parity check bit, store the first XOR parity check bit in the last row, and XOR the parity check bit from all the columns of all columns in the data block and the parity check bit for the last row XOR of the elements to generate a second XOR parity check bit.

Description

Turbo product code for NAND flash memory

This application claims priority from US Provisional Application No. 62 / 089,109, filed on December 8, 2014, entitled "Turbo Product Code for NAND Flash Memory" ("TURBO PRODUCT CODES FOR NAND FLASH"), which The entire contents are incorporated herein by reference.

Exemplary embodiments of the present disclosure relate to a signal processing and encoding technique.

Magnetic storage technology is most commonly used to store data, but for current electronic devices, the smaller weight and faster read / write operation requirements make magnetic storage technology less than ideal. NAND-based technology can meet the requirements for high-density data storage devices, but this technology is expensive. There is a need to reduce the cost of NAND-based technologies while maintaining performance levels.

Aspects of the invention include a method of encoding data in a data block. The method may include: generating a first XOR parity check bit from an XOR of all data bits in the data block and an XOR of all row parity check bits of all rows except the last row in the data block; Storing the first XOR parity bit in the last row; and generating a second XOR parity from the XOR of all the columns parity check bits of all the columns in the data block and the XOR of the parity bits of the last row Check the bits.

Furthermore, aspects of the invention include a device for encoding data in a data block. The device may include an encoder configured to: from all pairs in the data block The XOR of the data bit and the XOR of all the parity check bits of all rows except the last row in the data block to generate the first XOR parity check bit; the first XOR parity check bit is stored in the last row And generating a second XOR parity bit from the XOR of all the parity check bits of all the columns in the data block and the XOR of the parity check bits of the last row.

100‧‧‧Memory System

102‧‧‧Host

110‧‧‧Memory System

130‧‧‧controller

132‧‧‧Host Interface Unit

134‧‧‧Processor

138‧‧‧Error Correction Code (ECC) Unit

140‧‧‧Power Management Unit (PMU)

142‧‧‧Memory Controller

144‧‧‧Memory

150‧‧‧Memory device

152‧‧‧Memory Block

154‧‧‧Memory Block

156‧‧‧Memory Block

200‧‧‧Memory System

210‧‧‧Storage

220‧‧‧write controller

222‧‧‧TPC encoder

230‧‧‧Read controller

232‧‧‧TPC decoder

300‧‧‧ Information

302‧‧‧Parity check bit

310‧‧‧XOR parity check bit 2

312‧‧‧XOR parity check bit 2

470‧‧‧XOR parity check bit 2

480‧‧‧XOR parity check bit 2

500‧‧‧type

600‧‧‧type

700‧‧‧type

800‧‧‧type

900,902‧‧‧ Blocked error pattern

910,912,914,916‧‧‧row / column intersection

1000, 1002 ‧‧‧ blocked error pattern

1100‧‧‧Picture

1102, 1104‧‧‧‧ Performance

[Fig. 1] A data processing system including a memory system to which an embodiment of the present invention is applied is illustrated.

[FIG. 2] A block diagram of a memory system including an encoder and a decoder according to an embodiment of the present invention.

3A and 3B are diagrams illustrating an encoding process according to an aspect of the present invention.

[Fig. 4] A diagram showing an encoding process according to an aspect of the present invention.

5 is a diagram illustrating a blocked error pattern according to an aspect of the present invention.

6 is a diagram illustrating a blocked error pattern according to an aspect of the present invention.

[FIG. 7] A diagram illustrating a blocked error pattern according to an aspect of the present invention.

[FIG. 8] A diagram illustrating a blocked error pattern according to an aspect of the present invention.

[FIG. 9A] is a diagram illustrating a blocked error pattern according to an aspect of the present invention.

[FIG. 9B] is a diagram illustrating a blocked error pattern according to an aspect of the present invention.

[FIG. 10] A diagram illustrating a blocked error pattern according to an aspect of the present invention.

[FIG. 11] A diagram illustrating the performance of an encoding and decoding scheme according to an aspect of the present invention.

Various embodiments will be described in more detail below with reference to the drawings. However, this disclosure may Implemented in different forms and should not be construed as limited to the embodiments set forth. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art to which this invention belongs. Throughout this disclosure, the same reference numerals refer to the same parts in the various drawings and embodiments of the present invention.

The invention can be implemented in many ways, including as a process; a device; a system; a combination of things; a computer program product implemented on a computer-readable storage medium; and / or a processor (such as Instructions connected to the processor's memory and / or instructions provided by the memory coupled to the processor). In this description, these embodiments or any other form that the invention may take may be referred to as technology. Generally, the order of the steps in the disclosed processes may be changed within the scope of the invention. Unless stated otherwise, an element (such as a processor or memory) described as being configured to perform a task may be implemented as a conventional element temporarily configured to perform the task at a given time or manufactured to perform the task Task-specific components. As used herein, the term "processor" refers to one or more devices, circuits, and / or processing cores configured to process data, such as computer program instructions.

One way to reduce the cost of NAND-based technology involves reducing the process, but reducing the process reduces efficiency. This performance loss can be compensated by using advanced signal processing and coding techniques. Bose-Chaudhuri-Hocquenghem (BCH) codes and low-density parity check (LDPC) codes have been used to ensure data integrity. For BCH codes, the main disadvantage is that they cannot be used for soft-decision decoding, which makes these codes not ideal. LDPC codes provide good hard decision decoding performance and soft decision decoding performance. However, the complexity of the LDPC decoder is quite high, which makes this solution too expensive for hardware implementation. The following discloses and describes advanced coding techniques that can take advantage of lower hardware complexity to provide high performance benefits.

Turbo product code (TPC) is considered an advanced coding technique that can provide significant benefits with much lower hardware complexity than LDPC codes. In hard-decision decoding, TPC gives significant performance gains compared to BCH codes and LDPC codes. In soft decision decoding, TPC achieves performance gains close to LDPC codes.

TPC is considered an advanced coding technology that provides significant benefits with much lower hardware complexity than LDPC codes. In hard-decision decoding, TPC gives significant performance gains compared to BCH codes and LDPC codes. In soft decision decoding, TPC achieves performance gains close to LDPC codes.

Therefore, in systems using turbo product codes, advanced coding techniques are needed to provide benefits in terms of performance and throughput.

In some embodiments, the present invention will be applied to the data processing system shown in FIG. 1.

FIG. 1 illustrates a data processing system 100 including a memory system to which an embodiment of the present invention is applied. The data processing system 100 shown in FIG. 1 is for illustration only. Other structures of the data processing system 100 may be used without departing from the scope of the present disclosure. Although FIG. 1 illustrates one example of the data processing system 100, various changes can be made to FIG. 1. For example, in any suitable arrangement, the data processing system 100 may include any elements, or may not include any elements.

Referring to FIG. 1, the data processing system 100 may include a host 102 and a memory system 110.

The host 102 may include, for example, a portable electronic device such as a mobile phone, an MP3 player, and a notebook computer or an electronic device such as a desktop computer, a game console, a TV, and a projector.

The memory system 110 may operate in response to a request from the host 102, and specifically, stores data to be accessed by the host 102. In other words, the memory system 110 can be used as the host 102 Main memory system or auxiliary memory system. The memory system 110 may be implemented with any one of various types of storage devices according to a host interface protocol to be electrically coupled with the host 102. The memory system 110 can use various types of storage devices such as solid state drives (SSD), multimedia cards (MMC), embedded MMC (eMMC), reduced size MMC (RS-MMC) and micro MMC, secure digital (SD) cards , Mini SD and micro SD, universal serial bus (USB) storage devices, universal flash storage (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, and memory sticks) Either way.

The storage device for the memory system 110 may use volatile memory devices such as dynamic random access memory (DRAM) and static random access memory (SRAM) or non-volatile memory devices such as read-only memory ROM (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM ), Phase change RAM (PRAM), magnetoresistive RAM (MRAM), and resistive RAM (RRAM)).

The memory system 110 may include a memory device 150 and a controller 130. The memory device 150 stores data to be accessed by the host 102, and the controller 130 controls the data to be stored in the memory device 150.

The controller 130 and the memory device 150 may be integrated into one semiconductor device. For example, the controller 130 and the memory device 150 may be integrated into one semiconductor device and configured with a solid state drive (SSD). When the memory system 110 is used as an SSD, the operation speed of the host 102 electrically coupled with the memory system 110 can be significantly increased.

The controller 130 and the memory device 150 may be integrated into one semiconductor device and configured with a memory card. The controller 130 and the memory device 150 may be integrated into one semiconductor device. And configures such as the International Personal Computer Memory Card Association (PCMCIA) card, compact flash memory (CF) card, smart media (SM) card (SMC), memory stick, multimedia card (MMC), RS-MMC and micro MMC , Secure digital (SD) cards, mini SD, micro SD and SDHC, and memory cards for universal flash storage (UFS) devices.

As another example, the memory system 110 may be configured with a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless phone, a mobile phone, and a smart phone. , E-books, portable multimedia players (PMP), portable game consoles, navigators, black boxes, digital cameras, digital multimedia broadcast (DMB) players, three-dimensional (3D) TVs, smart TVs, digital answering machines , Digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, storage equipped with data center, equipment capable of sending and receiving information in a wireless environment, and various electronic devices equipped with home network One of various electronic devices that configure a computer network, one of various electronic devices that configure remote information processing, one of RFID devices, or one of various constituent elements of a computing system.

The memory device 150 of the memory system 110 can maintain the stored data when the power is interrupted, specifically, stores the data provided from the host 102 during a write operation, and provides the stored data to the host 102 during a read operation . The memory device 150 may include a plurality of memory blocks 152, 154, and 156. Each of the memory blocks 152, 154, and 156 may include multiple pages. Each of the pages may include a plurality of memory cells electrically coupled to a plurality of word lines (WL). The memory device 150 may be a non-volatile memory device, such as a flash memory. The flash memory may have a three-dimensional (3D) stacked structure.

The controller 130 of the memory system 110 may control the memory device 150 in response to a request from the host 102. The controller 130 may provide data read from the memory device 150 to The host 102 and the data provided from the host 102 are stored in the memory device 150. To this end, the controller 130 may control overall operations of the memory device 150, such as a read operation, a write operation, a program operation, and an erase operation.

In detail, the controller 130 may include a host interface unit 132, a processor 134, an error correction code (ECC) unit 138, a power management unit (PMU) 140, a memory controller (MC) 142, and a memory 144.

The host interface unit 132 can process commands and data provided from the host 102, and can communicate with the host 102 through at least one of the following various interface protocols: such as a universal serial bus (USB), a multimedia card (MMC), and peripheral components Connectivity-Express (PCI-E), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI) And integrated drive circuit (IDE).

The ECC unit 138 may detect and correct errors in the data read from the memory device 150 during a read operation. When the number of error bits is greater than or equal to the threshold number of correctable error bits, the ECC unit 138 cannot correct the error bits, and can output an error correction failure signal indicating that the error bit has failed to be corrected.

The ECC unit 138 may perform an error correction operation based on the following code modulation: such as a low-density parity check (LDPC) code, a Bosch-Chaudhuri-Hocquenghem code, a turbo code , Turbo product code (TPC), Reed-Solomon (RS, Reed-Solomon) code, convolutional code, recursive system code (RSC), trellis code modulation (TCM), and block code modulation (BCM). The ECC unit 138 may include all circuits, systems, or devices for error correction operations.

The PMU 140 may provide and manage power for the controller 130, i.e., for controlling the The power source of the constituent elements included in the controller 130.

The MC 142 may be used as a memory interface between the controller 130 and the memory device 150 to allow the controller 130 to control the memory device 150 in response to a request from the host 102. The MC 142 can generate control signals for the memory device 150 and process data under the control of the processor 134. When the memory device 150 is a flash memory such as a NAND flash memory, the MC 142 may generate a control signal for the NAND flash memory 150 and process data under the control of the processor 134.

The memory 144 can be used as a working memory of the memory system 110 and the controller 130 and stores data used to drive the memory system 110 and the controller 130. The controller 130 may control the memory device 150 in response to a request from the host 102. For example, the controller 130 may provide data read from the memory device 150 to the host 102 and store data provided from the host 102 in the memory device 150. When the controller 130 controls the operation of the memory device 150, the memory 144 may store data used by the controller 130 and the memory device 150 for operations such as a read operation, a write operation, a program operation, and an erase operation. .

The memory 144 may be implemented by a volatile memory. The memory 144 may be implemented by a static random access memory (SRAM) or a dynamic random access memory (DRAM). As described above, the memory 144 may store data used by the host 102 and the memory device 150 for read operations and write operations. To store the data, the memory 144 may include program memory, data memory, a write buffer, a read buffer, a mapping buffer, and the like.

The processor 134 may control a general operation of the memory system 110 and control a write operation or a read operation to the memory device 150 in response to a write request or a read request from the host 102. The processor 134 may drive a firmware called a flash memory translation layer (FTL) to control the general operation of the memory system 110. The processor 134 may be a microprocessor or a central processing unit (CPU) To implement.

A management unit (not shown) may be included in the processor 134 and may perform bad block management on the memory device 150. The management unit may find the bad memory blocks (which do not satisfy the conditions for further use) included in the memory device 150 and perform bad block management on the bad memory blocks. When the memory device 150 is a flash memory (for example, a NAND flash memory), a programming failure may occur during a write operation (for example, during a program operation) due to characteristics of a NAND logic function. During bad block management, data in failed memory blocks or bad memory blocks can be programmed into new memory blocks. In addition, the bad blocks caused by the programming failure severely reduce the utilization efficiency of the memory device 150 with the 3D layered structure and the reliability of the memory system 110, thereby requiring reliable bad block management.

FIG. 2 is a block diagram of a memory system 200 including an encoder and a decoder according to an embodiment of the present invention. For example, the memory system 200 corresponds to the memory system 110 shown in FIG. 1. For clarity, the components in FIG. 1 which are directly related to the embodiment of the present invention are not shown in the figure.

Referring to FIG. 2, the memory system 200 includes a storage 210, a write controller 220, and a read controller 230. For example, the storage 210 corresponds to the memory device 150 shown in FIG. 1, and the write controller 220 and the read controller 230 correspond to the ECC unit 138 shown in FIG. 1.

The memory 210 may include a solid state memory such as a NAND flash memory. The write controller 220 receives data from the host 102 in FIG. 1 and processes the data on the storage 210. The reading controller 230 reads the data on the storage 210 and processes the data. The write controller 220 includes a TPC encoder 222 and the read controller 230 includes a TPC decoder 232 as elements for a TPC scheme, respectively.

As described herein, the TPC code includes Nr row codes and Nc column codes. All of them Is a BCH code with the following parameters: row code: (nr, kr, Tr, mr); column code: (nc, kc, Tc, mc); XOR code: (nx, kx, Tx, mx); where n Represents the length of the encoding, k represents the dimension of the encoding, T represents the error correction capacity of the encoding, and m represents the finite field-size of the encoding. The number of columns that are combined to generate the column parity bit is specified through C #, where C # is the number of columns that are combined.

3A and 3B are flowcharts illustrating a TPC encoding scheme according to an embodiment of the present invention.

FIG. 4 is a diagram showing an example of a rectangular data block.

The encoding scheme is described below with reference to FIGS. 3 and 4.

Can be arranged in a rectangular block (see Figure 4). The data 300 includes row data and column data. The first line (line 1 to line R-1) may be encoded with a component code. In one embodiment, the first line may be encoded using BCH as the component code, although those having ordinary knowledge in the technical field to which the present invention pertains will appreciate that the present invention is not limited to this choice of component code.

Generates parity check bits 302 for rows 1 to R-1, and parity check bits for all data bits and all rows (ie, for this purpose, all parity check bits for rows include rows 1 to (R-1) parity check bit) are mutually exclusive or (XOR). The number of XOR bits is given in C #. Since the row parity check bits will contain Tr * mr, and Tr * mr will not be an integer multiple of C #, zero padding of the row parity check bits can be made such that they are integer multiples of C #. For example, if the row parity check bit length is 42 and C # is given as 24, zero padding can be performed on 6 bits so that the row parity check bit is 48 bits long, and the length can be constructed from the row parity check bit as 24 of two Blocks.

XOR the data 300 and the parity check bit 302, and the XOR will be included in the last line 406 of the data. This XOR can be considered as XOR parity bit 1 (306,450). XOR parity bit 1 (306,450) will have length C #.

The XOR parity bit 1 (306,450) is included in the last line 406 (ie, line R) of the data, and the last line parity bit (308,460) is generated. It is worth noting that the parity bit (308,460) of the last row including the XOR parity bit 1 (306,450) is generated.

The column parity check bit 304 is generated by combining the columns. For a given number of columns C (for example, C #), the column parity check bit may include column parity check bit 1 440, column parity check bit 2 442, column parity check bit (C-1) 444, and column parity Check bit C 446. In the example of this scheme, a column parity check bit (C-1) 444 is generated if the XOR parity check bit 1 (450) is included, and a row parity check bit is each included to be generated Column parity check bit C 446 (which includes row R parity check bit 460, and as described above, row R parity check bit is generated including XOR parity check bit 1 450). It is assumed that the correction capacity (T) and the Galois field (m) are the same for the row parity check bit and the column parity check bit.

XOR parity bit 2 (310,470) can be generated by XORing all column parity bits and the last row parity bit. The length of XOR parity bit 2 (310,470) is given as Tr * mr (= Tc * mc). For simplicity, assume Tr * mr = Tc * mc. If Tr * mr ≠ Tc * mc, zero padding can be used to generate XOR parity bit 2 (310,470).

You can apply another component code to XOR parity bit 2 (310,470) (for example, parity bit to XOR parity bit 2 (312,480)), XOR parity bit The encoding parameters of 2 (310,470) are given as (nx, kx, Tx, mx). Overall, the Galois field of this BCH code for XOR parity bit 2 is quite small, so the complexity of the encoding / decoding of this encoding is minimal. It should be noted that this parity bit for the XOR parity bit 2 is only written to the NAND. In this method, parity check bits can be saved by not writing XOR parity check bit 2. The parity bit overhead of this scheme is given as: the total parity bit of the proposed scheme = Tr * mr + Tc * mc + C # + Tx * mx

Compared with the previously implemented scheme, the XOR parity check bit burden (C # + Tx * mx) other than the row parity check bit and the column parity check bit is relatively small. Therefore, this scheme has significant performance benefits compared to other schemes.

5 to 10, various decoding processes for the encoding schemes disclosed above are described. The decoding program is similar to regular TPC decoding. In regular TPC decoding, column decoding is repeated in loops followed by row decoding until the data is successfully decoded or the number of iterations exceeds the maximum number of iterations. There is a specific error pattern, and even if the weight of the error pattern is small, the error pattern will be blocked in decoding.

In FIGS. 5 to 8, a (1,1) stuck error pattern is shown. The (1,1) blocked error pattern is a blocked error pattern in which exactly one row and one column of faults exist. In Figures 9A and 9B, a (2,2) blocked error pattern is shown, where there are two rows and two columns of faults. In Fig. 10, a (0,2) blocked error pattern is shown.

In FIG. 5, an error pattern 500 in the data that may be blocked in decoding is shown. In this example, it is assumed that the error correction capacity of the row encoding and the column encoding is equal to two. Although the weight of error pattern 500 is 4, it will be blocked in decoding. The XOR parity bit 1 450 can be used to correct the error pattern 500. Because the faulty rows and columns are known, the row / column intersection is known. first First, XOR all the data except row / column intersection part, row parity check bit and XOR parity check bit 1. The resulting XOR parity check bit can replace the faulty row / column intersection, which will correct all erroneous bits in the row / column intersection.

Similarly, in Figure 6, a blocked error pattern is shown. A blocked error pattern 600 exists in the parity check bit portion. Using the decoding process described above with reference to FIG. 5, the blocked error pattern 600 can also be corrected.

In FIG. 7, a blocked error pattern 700 existing in the parity bit of the R-th row is shown. In order to correct this pattern 700, XOR parity check bit 2 may be generated at the decoding end, and XOR parity check bit 2 is obtained by XORing the Rth row parity check bit and all column parity check bits. BCH decoding is run on this XOR parity bit 2. This BCH decoding will correct all errors because the BCH for XOR parity bit 2 has a large correction capacity. Once the correct XOR parity bit 2 is obtained, this parity bit can be used to correct the hindered pattern 700.

In FIG. 8, a blocked error pattern 800 in a column parity portion is shown, and the blocked pattern 800 can be corrected by the process described above with reference to FIG. 7. In this way, all (1,1) blocked error patterns present in the decoding program can be decoded.

9A, a (2,2) blocked error pattern is shown. That is, the data includes an error pattern 900 and an error pattern 902. XOR parity check bit 1 and XOR parity check bit 2 cannot be used to correct this blocked error pattern 900, 902. In FIG. 9A, an example where C # is equal to 6 is shown for simplicity. The goal is to correct this blocked error pattern 900, 902 by identifying the most likely error locations. Once the location of the error is known, a simple flip algorithm can be used to correct this blocked error pattern 900, 902. In FIG. 9A, the blocked error pattern has 6 errors appearing at different positions in the intersection portion of the row and column.

Since the correct XOR parity bit 1 is known, the XOR for all data and row parity bits (line 1 to line (R-1)) can be found and compared to XOR parity bit 1 . The XOR parity bit 1 is different from these calculated XOR parity bits at a maximum of 6 positions. The location of the error is now known, but the exact location of the error in the row / column intersection is unknown.

As shown in FIG. 9B, in the (2,2) blocked error pattern, there are 4 row / column intersections (910,912,914,916) that may have errors. A bit flip process (eg, Chase decoding) may be used, in which the bits at the wrong bit position determined by the XOR parity check bit 1 are flipped. In Chase decoding, all 2 ^ flip_bits will be tried, where flip_bits is the number of flipped bits detected by xor calculated from stored xor or data.

In another example of the present invention, one bit will be selected from the flip bit (eg, nchoosek (1)), and this bit flip will be attempted at n * m obstructed error intersections of all faults And then try to decode. Next, nchoosek (rollover bits, 2) will be tried for n * m faulty blocked error patterns, and this process will be repeated for all n * m faulty blocked error patterns (for example, nchoosek (rollover bit Yuan, flip bits)). All corrections must be made inside the intersecting part of the fault to avoid introducing more errors outside the wrong intersecting part.

In the first run, a single bit among the 6 error position bits of all 4 row / column fault intersections (910,912,914,916) can be flipped. After a bit is flipped, regular decoding can be applied to the failed row / column decoding. When decoding, the bits that are guaranteed to be decoded during BCH decoding must be in the row / column fault intersection section. In this way, no false correction is introduced in the TPC structure.

In the error pattern shown in FIG. 9A, one bit flip in the first row / column intersection portion is not enough. A bit flip is then used to process the second row / column intersection, which will decode the row encoding and satisfy the column encoding. Once the errors in a row / column intersection are corrected, the blocked error pattern becomes a (1,1) error pattern, which can be easily corrected by using XOR parity bit 1. .

If the pattern is not decoded by trying all the single bit flips in all the failed row / column intersections, this pattern is usually decoded by a single bit flip. Two or more bit flips can be attempted on the row / column intersection of the failure.

In FIGS. 9A and 9B, the value of C # is equal to 6. However, in the regular TPC code design, the value of C # is larger. In those types of cases, the advantages from the disclosed bit flip algorithm will be substantial compared to the random bit flip process. Different from random bit flipping, through the description of XOR parity check bit 1 and XOR parity check bit 2, the most likely error position is known, which significantly reduces the complexity of the proposed scheme for integration. The solution disclosed above can be easily generalized as a (n, n) blocked error pattern. In the (n, n) blocked error pattern, n rows and n columns are faulty. However, if the value of n is large, the complexity will increase. Therefore, patterns within hardware complexity are corrected using this proposed scheme.

Referring next to Fig. 10, an alternative error pattern of (0, 2) is shown. To simplify the decoding, an alternative method of decoding the (0, k) blocked error pattern can also be performed. In the (0, k) blocked error pattern (eg, 1000, 1002), all rows are correct, and k columns are faulty. This pattern can be corrected using the correct data. The correctness of the data is verified by XOR parity check bit 1 and row parity check bit. The data can be used to generate (k-1) row parity check bits, and the XOR parity check bit 2 can be used to generate the last faulty parity check bit. Corrected k-th The parity check bit can be verified from the k-th data. If the parity bit of the k-th column of data matches the corrected k-th parity bit, then the TPC is declared to be successfully decoded. The correction capacity of XOR parity bit 2 is not very large, so this program can be applied to decode the (0, k) blocked error pattern. The blocked error patterns 1000 and 1002 shown in FIG. 10 can be corrected through the above scheme. In general, the probability of (0, k) appearing is quite low, so the proposed scheme is rarely used in decoding.

Although decoding of (n, n) and (0, k) error code patterns is disclosed, the process described herein can also be used to (n, m), (m, n), etc. error codes Patterns are decoded.

As a further description, decoding of a (n, m) failure pattern (where n rows and m columns are defective) can be performed as follows. First, an XOR is calculated for all data and row parity bits and compared to the stored parity bits (eg, XOR_data). Once XOR_data is received, it is compared to XOR_stored to find the error bit position. The error bit locations are now known, but it is necessary to determine where these errors are located in the intersection of n * m faults. In this way, the erroneous bits found from the above comparison are taken, and these bits are flipped at specific positions among all the n * m faulty intersections. If the component codeword is decoded and all corrections are made within the failed component codeword, the correction is applied. If any row of codewords is corrected by attempting to correct the corresponding column codeword by inverting the bits, then further checks can be performed and all corrections made in the intersecting portion of the fault. These bit flips can be performed on 1 error bit, 2 error bits, 3 error bits, etc. at the same time according to the number of mismatched bits from XOR_data and XOR_stored.

In addition, for a (0, k) error pattern, the decoding process can be performed as follows. If all rows are qualified, and XOR_stored matches the XOR calculated on the data and row parity check bits, the k faulty column codewords are encoded to obtain the corresponding k column parity check bits. under these circumstances, All errors are in the parity check bit, and the correctness of the parity check bit generated in this way can be determined through the XOR parity check bit 2.

The effectiveness of the scheme disclosed above is tested and compared with the 2K BCH code. The value of the TPC code constructed based on the scheme disclosed above was tested as: data length = 32864.

Allowed parity check bits = 308 bytes.

Line encoding: (nr, kr, Tr, mr) = (1310,1266,4,11).

Column encoding: (nc, kc, Tc, mc) = (1318,1274,4,11).

Nr = 26, Nc = 27, and C # = 49.

XOR parity check encoding on bit 2: (nx, kx, Tx, mx) = (121,44,11,7).

This performance is shown in FIG. 11. Diagram 1100 in FIG. 11 shows the efficiency 1102 of 2k BCH and the efficiency 1104 of the scheme described above. Findings in coding design: Codes with Galois Field (m) and a correction capacity (T) equal to (11,4) are already suitable through significantly shortened bits. The larger correction capacity reduces the error correction capacity, and the shortened bits can be used for error correction detection. If there are flipped bits in the shortened bits during BCH decoding, it is known that the BCH decoder has erroneously corrected the codeword, and this erroneous correction can be avoided in TPC decoding.

Although the invention has been particularly shown and described with reference to exemplary embodiments thereof, those having ordinary knowledge in the technical field to which the invention pertains will appreciate without departing from the scope defined by the appended application patents Various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Therefore, the foregoing is merely an example, and is not intended to be limiting. For example, any number of elements shown and described herein are by way of example only. The present invention is limited only by the scope of the attached patents and their equivalents.

Claims (14)

A method for encoding / decoding data in a data block, including: from a mutex or (XOR) of all data bits in the data block and all of all rows except the last row in the data block XOR of row parity check bits to generate a first XOR parity check bit; storing the first XOR parity check bit in the last row; and XOR from all column parity check bits of all columns in the data block And an XOR of the parity bit of the last row to generate a second XOR parity bit. The method of claim 1, further comprising: applying a component code to the second XOR parity bit to generate parity of the second XOR parity bit. The method according to claim 1, further comprising: zero-padding the row parity check bit, so that the length of the row parity check bit is an integer multiple of the number of columns in the data block. The method according to claim 1, further comprising a decoding step: decoding a blocked error pattern in the data. The method according to claim 4, wherein the decoding step includes: generating a third XOR parity check from data other than the faulty row / column intersection portion, a row parity check bit, and a first XOR parity check bit. Bit, the faulty row / column intersection portion includes a blocked error pattern; and corrects the blocked error pattern by inverting a bit in the blocked error pattern based on the generated third XOR parity check bit. The method according to claim 4, wherein the decoding step further comprises: determining a row / column intersection portion of the data block having a blocked error pattern by comparing the first XOR parity check bit with the following, The content includes all information in the data block. The XOR of the material bit and the XOR of the parity check bit for all the rows in the data block except the last row; and the bit error by determining the bit in the determined row / column intersection The position of the element in the blocked error pattern. The method according to claim 4, wherein the blocked error pattern is at least one of a (n, m) blocked error pattern or a (0, k) blocked error pattern. A device for encoding / decoding data in a data block includes an encoder configured to: from an XOR of all data bits in the data block and to the data block except the last row XOR of all rows parity check bits of all rows to generate the first XOR parity check bit; store the first XOR parity check bit in the last row; and parity check from all columns of all columns in the data block The XOR of the bit and the XOR of the parity bit of the last row generate a second XOR parity bit, wherein the data is encoded based on the first XOR parity bit and the second XOR parity bit. The apparatus of claim 8, wherein the encoder is further configured to apply a component code to the second XOR parity bit to generate a parity bit of the second XOR parity bit. The device according to claim 8, wherein the encoder is further configured to: zero-fill the row parity check bits, so that the length of the row parity check bits is an integer multiple of the number of columns in the data block. The apparatus according to claim 8, further comprising a decoder configured to decode a blocked error pattern in the data. The apparatus according to claim 11, wherein the decoder is configured to decode the blocked error pattern through the following steps: from data other than the failed row / column intersection portion, row parity check bit, and An XOR parity check bit to generate a third XOR parity check bit, the row / column intersection portion of the failure includes a blocked error pattern; and based on the generated third XOR parity bit, the The bits are flipped to correct the blocked error pattern. The apparatus according to claim 11, wherein the decoder is configured to decode the blocked error pattern through the following steps: determining that the data block has the following by comparing the first XOR parity check bit with the following: A row / column intersection of a blocked error pattern, which includes XOR of all data bits in the data block and XOR of all parity check bits of all rows in the data block except the last row; And determining the position of the error bit in the blocked error pattern by bit flipping the bits in the determined row / column intersection. The device according to claim 11, wherein the blocked error pattern is at least one of a (n, m) blocked error pattern or a (0, k) blocked error pattern.