JP2014057203A - Galois field arithmetic circuit and memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a Galois field arithmetic circuit that has a reduced circuit scale for operation on an error location detection polynomial.SOLUTION: A Galois field arithmetic circuit 34 for substituting (2-1) elements (m is an integer) vector-represented by m bits on a Galois field GF(2) into an error location detection polynomial includes a base calculation section 330 for calculating m linear independent ones of the (2-1) elements, and a linear expansion section 340 for determining (2-1-m) of the (2-1) elements other than the m elements as combinations of the m elements, respectively.

Description

  The present invention relates to a Galois field arithmetic circuit used in an error detection and correction circuit, and a memory device.

  A NAND flash memory is known as one of electrically rewritable nonvolatile semiconductor memory devices (EEPROM) that are electrically erasable and programmable read only memory (EEPROM). The NAND flash memory uses a NAND cell unit (NAND string) in which a plurality of memory cells are connected in series, thereby enabling large-capacity storage with a small chip area.

In the NAND type flash memory, the stored contents are destroyed due to various reasons while holding data. For example, the retention characteristics of the memory element (memory cell) are lost during data retention due to deterioration of the tunnel oxide film due to many rewrites, and the error bit generation rate (error rate) tends to increase. is there. In particular, in the NAND flash memory, the error rate tends to increase as the memory capacity increases and the manufacturing process becomes finer.
In order to cope with this, an error detection and correction circuit (ECC circuit) has been used for improving the performance of the NAND flash memory. By mounting this error detection and correction circuit on-chip, it is possible to provide a highly reliable memory.

As an error correction circuit, there is a circuit using a Galois field arithmetic circuit based on a finite field (Galois field) GF (2 ^m ) (see Patent Document 1). In the Galois field arithmetic circuit described in Patent Document 1, when performing two original multiplications represented by m bits on a Galois field GF (2 ^m ), higher-order bits other than the lower-order m bits in the multiplication process are used. Each component is obtained by performing an EXOR operation, and its output is converted into an m-bit vector representation by a given primitive polynomial f (X), and an EXOR operation is performed on the lower m-bit component to obtain a multiplied vector output. obtain. This simplifies the multiplication circuit configuration on the Galois field.

JP-A-6-314979

By the way, in an error correction process using a linear block code represented by a BCH code or an RS code, the most time consuming process is to obtain a zero point of an error position detection polynomial (error position search equation) P (X). Detection process). In general, the processing for obtaining the zero is performed by, for example, the coefficients p ₀ , p ₁ , and p ₂ of the error position detection polynomial P (X) in the Galois field arithmetic circuit (fourth-order polynomial Galois field arithmetic circuit) shown in FIG. , P ₃ , p ₄ are determined, 1, α, α ² , α ³ ,..., Α ^t−2 (where t = 2 ^m ) are sequentially input as Galois field elements (elements) X Thus, the zero point of P (X) is obtained. The time required for this process can be greatly reduced by calculating all the possible values of the polynomial variable X at once. For example, as shown in FIG. 13, a parallel operation circuit is provided for each of the elements 1, α, α ² , α ³ ,..., Α ^t−2 , and P (1), P (α ¹ ), By simultaneously calculating P (α ² ),..., P (α ^t−2 ) (where t = 2 ^m ), the calculation time in the error position detection polynomial can be greatly reduced. However, in the method shown in FIG. 13, the circuit scale for calculating the error position detection polynomial becomes very large, and it becomes very difficult to mount the error detection and correction circuit on-chip in the memory device.

  Therefore, an object of the present invention is to provide a Galois field arithmetic circuit and a memory device that can reduce the scale of a circuit for calculating an error position detection polynomial.

The Galois field arithmetic circuit of the present invention substitutes (2 ^m −1) elements represented by m bits on the Galois field GF (2 ^m ) (m is an integer, the same shall apply hereinafter) into the error position detection polynomial. a Galois field operation circuit, said from (2 m ^-1) number of elements of the base calculation unit for calculating a linearly independent m-number of the original, from the (2 m ^-1) number of elements of A linear expansion unit that obtains (2 ^m −1−m) elements excluding m linearly independent elements as a combination of the m elements.

  Also, the Galois field arithmetic circuit of the present invention integrates the terms constituting the same linear space in the error position detection polynomial as a linear function, and for the integrated linear function, the basis calculation unit and the The calculation is performed by a linear expansion unit.

  The memory device of the present invention is a memory device including an error correction circuit that performs error position detection polynomial calculation using the Galois field calculation circuit and detects an error of an input data string, The detection correction circuit indicates a syndrome calculation unit that calculates a syndrome from the input data sequence, an error coefficient calculation unit that calculates a coefficient of the error position detection polynomial from the syndrome, and indicates a bit position of data in the data sequence Whether or not there is an error for each bit of the data string according to the substitution result to the error position detection polynomial, and the Galois field arithmetic circuit that substitutes the value and the coefficient into the error position detection polynomial. A chain search unit that outputs an error detection signal indicating whether or not an error in the bit data in the data string is corrected by the error detection signal and output. Ri and correction unit, characterized in that it comprises a.

The Galois field arithmetic circuit of the present invention includes a basis calculation unit that calculates linearly independent m elements from (2 ^m −1) elements on the Galois field GF (2 ^m ), and the above (2 ^m -1) a linear expansion unit that obtains (2 ^m -1-m) elements obtained by removing the above linearly independent m elements from the elements, as a combination of m linearly independent elements, Is provided.
Thereby, in the Galois field arithmetic circuit, the scale of the circuit for calculating the error position detection polynomial can be reduced.

1 is a diagram illustrating an overall configuration of a memory device according to an embodiment of the present invention. It is a figure which shows the structural example of an error detection correction circuit. It is the figure which showed the element of the Galois field GF (2 < ⁴ >) by the table | surface. It is the figure which showed the element of the Galois field GF (2 ³ ) by the table | surface. 3 is a diagram illustrating a configuration example of a Galois field arithmetic circuit 34. FIG. It is a figure which shows the example of the linear structure of a polynomial. It is a figure for demonstrating the calculation operation | movement of the Galois field arithmetic circuit 34 shown in FIG. 2 is a diagram illustrating an example of a circuit that calculates a linear term for X. FIG. It is a figure which shows the example which cubed the element shown in Table 2 of FIG. Is a diagram illustrating an example of a circuit for calculating a linear term for X ^3. It is a figure for demonstrating the reduction effect of a circuit element. It is a figure which shows the example of the Galois field arithmetic circuit which calculates | requires the zero of the conventional Galois field polynomial. It is a figure which shows the example of the Galois field arithmetic circuit using a parallel arithmetic circuit. It is a figure which shows the example of a matrix calculation.

Embodiments of the present invention will be described below with reference to the accompanying drawings.
[Overview]
In the conventional Galois field arithmetic circuit, for example, the coefficients p ₀ , p ₁ , p ₂ , p ₃ , and p ₄ of the error position detection polynomial P (X) are determined in the circuit shown in FIG. 12 (fourth order polynomial circuit). Then, as the Galois field element (element) X, 1 (= α ⁰ ), α (= α ¹ ), α ² , α ³ ,... Are sequentially input to find the zero of P (X) ing.
More specifically, in the conventional Galois field arithmetic circuit for obtaining the zero of the Galois field polynomial, the coefficient p _i (i = 0, 2, 3, 4) is calculated as the first procedure, and the second procedure is performed as the second procedure. , Term p _i X ⁱ is calculated, and the terms corresponding to i = 0, 1, 3, 4 are added together as a third procedure. Then, the first, second, and third procedures are performed on all possible elements X (1, α, α ² , α ³ ,...) Or a part thereof, and the polynomial P (X ). However, in this method, Galois field elements 1, α, α ² , α ³ ,... Are sequentially input to obtain the zero of P (X), and thus it takes a very long time to obtain the zero. .

In order to cope with this, a circuit (an example of a fourth-order polynomial) that obtains zeros of the polynomial P (X) at a time can be used. For example, as shown in the Galois field arithmetic circuit shown in FIG. 13, each element 1 (α ⁰ ), α, α ² , α ³ ,..., Α ^t−2 (where t = 2 ^m ) Error position detection by providing a parallel arithmetic circuit and calculating P (1), P (α ¹ ), P (α ² ), P (α ³ ),..., P (α ^t−2 ) simultaneously The calculation time in the polynomial can be greatly reduced. However, in the method shown in FIG. 13, since P (X) for all possible Xs is obtained at once, it takes no time to obtain the zero of each bit, but the circuit scale becomes very large.

In the circuit configuration as shown in FIG. 13, the portion corresponding to each term of each unit is represented by a matrix operation because the operation of multiplying the constant element is a linear operation (for example, an example of the matrix operation shown in FIG. 14). reference). Here, the matrix used for the calculation is a matrix for converting the Galois field element X into another vector when the Galois field element X is regarded as a vector. When the Galois field GF (2 ^m ) is adopted (m corresponds to the data length when the Galois field element is regarded as binary data), the circuit corresponding to the matrix operation part is about m (m−1) / 2. It is composed of one EXOR element. When the degree of the polynomial is n, m bits of the matrix operation result are added by n + 1 terms, and this requires m × n EXOR elements. If the range of possible values of X is the entire Galois field, the number of units in FIG. 13 is 2 ^m −1, and the total is
(N + 1) × (2 ^m −1) × m (m−1) / 2 + n × (2 ^m −1) × m
It becomes.

  For example, when m = 8 and n = 4, a total of about 43800 EXOR elements are required. As described above, even if the calculation of each term is replaced from the multiplication of two inputs to the matrix calculation, the circuit scale becomes very large.

Therefore, in the Galois field arithmetic circuit of this embodiment, as will be described later, the circuit scale is reduced by utilizing the linearity of each term in the Galois field and the error position detection polynomial. That is, each term of the error locator polynomial, linearity of certain portions for X ^{"X, X 2,} X ^{4, X} 8, · · ·," part ^"X 3 having the linearity of the ^{X 3, X 6} , X ¹² ,..., X ⁵ are divided into linear parts “X ⁵ , X ¹⁰ , X ²⁰ ,...”, And these are integrated as the same linear function. For the integrated linear function, the element is calculated by dividing it into a basis calculation unit that calculates using a basis value and a linear expansion unit.
The basis calculation unit calculates an error position detection polynomial for linearly independent ^m elements on the Galois field GF (2 ^m ). For the calculation of the error position detection polynomial for the remaining (2 ^m −1−m) elements excluding the linearly independent m elements, the calculation result in the base calculation part is added by the linear expansion part. Perform the calculation.
Thereby, the circuit scale of the Galois field arithmetic circuit can be reduced as compared with the Galois field arithmetic circuit that calculates the error position detection polynomial for each element. As a result, a Galois field arithmetic circuit for obtaining the zero point of the error position detection polynomial in a short time can be realized with a circuit scale that can be mounted on a semiconductor memory.

[Configuration of memory device]
FIG. 1 is a diagram showing an overall configuration of a memory device according to an embodiment of the present invention, and is a diagram showing an overall configuration of a NAND flash memory that is a nonvolatile semiconductor memory device 10 as a memory device.
The nonvolatile semiconductor memory device 10 includes a memory cell array 11, a page buffer 12, an error detection and correction circuit (ECC circuit) 13, a buffer 14, an I / O pad 15, a control circuit 16, an address decoder 17, and a row and block decoder 18. It is comprised including.
The configuration of the nonvolatile semiconductor memory device 10 is the same as that of a NAND flash memory having a general configuration, but in this embodiment, a Galois field arithmetic circuit (error error correction circuit provided in the error detection / correction circuit 13). The position detection polynomial calculation circuit (FIG. 2) is characterized.

Hereinafter, the overall configuration of the nonvolatile semiconductor memory device 10 will be described. In the nonvolatile semiconductor memory device 10, the memory cell array 11 includes a plurality of stacked gate structure transistors, that is, electrically rewritable nonvolatile memory cells (storage elements) connected in series in the column direction (column direction) to form bit lines. Each NAND cell string provided for each block is composed of blocks arranged in the row direction (bit line arrangement direction). A plurality of blocks are arranged in the wiring direction of the bit lines. Further, this block is provided in units of erasing data of memory cells. In each block, a word line orthogonal to the bit line is connected to the gate of each nonvolatile memory arranged in the same row.
A range of nonvolatile memory cells selected by one word line is one page as a unit for programming and reading.

  The page buffer 12 includes a page buffer circuit provided for each bit line in order to program and read data in units of pages. Each page buffer circuit in the page buffer 12 has a latch circuit that is connected to each bit line and that is used as a sense amplifier circuit that amplifies and determines the potential of the connected bit line.

  The page buffer 12 (data storage unit) receives cell data Cell Data consisting of data (data string) stored in one page of memory cells in the memory cell array 11 in the data read operation of the nonvolatile semiconductor memory device 10. This data is amplified and output to the error detection and correction circuit 13. On the other hand, the page buffer 12 stores the data supplied from the error detection / correction circuit 13 in the internal latch circuit in the data write (program) operation of the nonvolatile semiconductor memory device 10, and performs all the data while performing the verify operation. Is written as code data Code Data in a memory cell in one page.

The code data Code Data includes parity data Parity generated by the error detection and correction circuit 13.
For example, when an error correction system that performs 4-bit (bit) correction using a BCH code for an information length of 512 bytes (bytes) is taken as an example, one page is 2K (= 2048) bytes, that is, 16k (= 16384) bits. The memory cells each store normal data and the memory cells each store 208-bit parity data. That is, cell data Cell Data and code data Code Data are composed of (16k + 208) bits. For example, one page is divided into, for example, four sectors as a correction unit of the error detection and correction circuit 13. That is, the data corresponding to one sector is composed of normal data of 512 bytes (= 4096 bits) and parity data of 52 bits.

  The error detection and correction circuit 13 processes the data read from the page buffer 12 for each sector in the data read operation of the nonvolatile semiconductor memory device 10, calculates the coefficient of the error position detection polynomial, and latches it internally. And hold. Further, the error detection / correction circuit 13 corrects an error in the data of the bit whose position is indicated by the column address in the read operation, and outputs the corrected data to the outside through the I / O pad 15 as corrected data.

  Further, the error detection and correction circuit 13 receives information data Information Data input from the I / O pad 15 through the buffer 14 in the data write operation of the nonvolatile semiconductor memory device 10. The error detection / correction circuit 13 generates parity data parity from the received information data information data, and outputs the received information data information data and parity data parity to the page buffer 12. The page buffer 12 writes these data as code data Code Data in a memory cell connected to the selected page.

The control circuit 16 receives various control signals and controls operations such as data programming, reading, and erasing of the nonvolatile memory cell, and verification operation.
For example, the control signals are an external clock signal, a chip enable signal / CE, a read enable signal / RE, a program enable signal / WE, a command latch enable signal CLE, an address latch enable signal ALE, a write protect signal / WP, and the like. The control circuit 16 outputs an internal control signal to each circuit in accordance with the operation mode indicated by these control signals and command data input from the I / O pad 15.
For example, when the command latch enable signal CLE changes from the low (L) level to the high (H) level when the program enable signal / WE rises, the control circuit 16 takes in the command data from the I / O pad 15 and Hold in register.

  The address decoder 17 holds an address (row address, block address, column address) input from the I / O pad 15 based on an internal control signal from the control circuit 16. The address decoder 17 outputs the held address to the row and block decoder 18, the page buffer 12, and the error detection and correction circuit 13 based on the internal control signal from the control circuit 16.

  For example, the control circuit 16 fetches an address from the I / O pad 15 when the address latch enable signal ALE changes from the low (L) level to the high (H) level when the program enable signal / WE rises, and the address decoder 17 In the internal register.

  The row and block decoder 18 selects a memory cell on one page by selecting a block and a word line of the memory cell array 11 according to a row address and a block address held and output by the address decoder 17. The address decoder 17 selects a bit line of the memory cell array 11 and the page buffer 12 according to a column address held therein.

  In the data read operation of the nonvolatile semiconductor memory device 10, the error detection / correction circuit 13 processes the data read from the page buffer 12 for each sector, and calculates the coefficient of the error position detection polynomial. Further, the error detection / correction circuit 13 corrects an error in the data for each bit whose position is indicated by the column address in the read operation, and outputs the corrected data to the outside through the I / O pad 15 as corrected data Corrected Data.

  Further, the error detection and correction circuit 13 receives information data Information Data input from the I / O pad 15 through the buffer 14 in the data write operation of the nonvolatile semiconductor memory device 10. The error detection / correction circuit 13 generates parity data parity from the received information data information data, and outputs the received information data information data and parity data parity to the page buffer 12. The page buffer 12 writes these data as code data Code Data in a memory cell connected to the selected page.

  FIG. 2 is a diagram showing a configuration example of the error detection / correction circuit 13 in the NAND flash memory having the above configuration.

  In the present embodiment, an error detection / correction circuit (ECC circuit) using a BCH code (Bose-Chudhuri Hocquechem code) will be described as an example of the error detection / correction circuit 13. The error detection and correction circuit is a block code using Galois field arithmetic represented by a BCH code. Instead of the BCH code, for example, a Hamming code (Hamming code) or a Reed-Solomon code (Reed-Solomon code) can be used.

The error detection and correction circuit 13 includes a decoder unit 30 that controls decoding of data, and an encoder unit 40 that generates correction parity data parity and adds the correction parity data parity to data to be written to the cell. .
Among these, the encoder unit 40 includes a parity generation circuit 41. The parity generation circuit 41 generates parity data Parity obtained by dividing the information data Information Data written in the buffer 14 by a generator polynomial. Further, the parity generation circuit 41 adds the generated parity data Parity to the information data Information Data, and outputs the information data Information Data to the page buffer 12. These data become code data Code Data written to one selected page when the nonvolatile semiconductor memory device 10 writes data. In this embodiment, when data is read from the nonvolatile semiconductor memory device 10, the error detection / correction circuit 13 performs data correction processing at a high speed and the circuit of the Galois field arithmetic circuit 34 in the error detection / correction circuit 13. The decoder is characterized by reducing the scale, and the decoder unit 30 will be described in detail below.

The decoder unit 30 includes a syndrome calculation unit 31, an error coefficient calculation unit 32, a chain search unit 33, and an error correction unit 35. The chain search unit 33 includes a Galois field arithmetic circuit 34.
The syndrome calculation unit 31 receives the cell data Cell Data read to the page buffer 12 as code data when reading data from the nonvolatile semiconductor memory device 10, and divides the code data by an independent minimum polynomial. Calculate the syndrome. There are four independent minimum polynomials used in a BCH code capable of correcting an error of 4-bit data. The syndrome calculation unit 31 includes four syndrome calculation circuits 31_1 to 31_4 corresponding to these four minimum polynomials. These syndrome calculation circuits 31_1 to 31_4 calculate syndromes S1, S3, S5, and S7, respectively.

The error coefficient calculation unit 32 uses these syndromes S1, S3, S5, and S7 to calculate the coefficient of the error position detection polynomial. For example, when the error position detection polynomial is a fourth-order polynomial P (X) = p ₄ X ⁴ + p ₃ X ³ + p ₂ X ² + p ₁ X + p ₀ , the error coefficient calculator 32 calculates the coefficients p ₄ and p _3. , P ₂ , p ₁ , and p ₀ . In the chain search unit 33, the Galois field arithmetic circuit 34 calculates an error position detection polynomial P (X). In this error position detection polynomial P (X), the variable X has a value (a Galois field) indicating the bit position (for example, the position of the bit line) of the code data, that is, the cell data Cell Data stored in the page buffer. Element) is input. That is, this error position detection polynomial P (X) is used in the chain search unit 33 when searching for an error in the bits read from the page buffer 12.

For example, the chain search unit 33 calculates the error position detection polynomial P (X) = p ₄ X ⁴ + p ₃ X ³ + p ₂ X ² + p ₁ X + p ₀ in the Galois field arithmetic circuit 34, and the value of P (X) Is 0, the error detection signal Error is output as an H level. On the other hand, when the value of P (X) is not 0, the chain search unit 33 outputs the error detection signal Error as the L level.

  If the error detection signal Error is at the H level, the error correction unit 35 inverts the logic (0 or 1) of the bit data at the corresponding position, and outputs the inverted data as 1 bit of the corrected data Corrected Data. On the other hand, if the error detection signal Error is L level, the error correction unit 35 outputs the data logic of the bit at the corresponding position as it is, that is, without correction, as 1 bit of the corrected data Corrected Data.

In other words, the chain search unit 33 uses the Galois field arithmetic circuit 34 to set the error position detection polynomial P (X) = p ₄ X ⁴ + p ₃ X ³ + p ₂ X ² + p ₁ X + p ₀ to x = α ⁱ (element of Galois field: If i is the position of the bit line) and the value of P (X) is 0, the error detection signal Error <i> is at the H level. On the other hand, when the value of P (X) is not 0, the error detection signal Error <i> becomes L level.

  The exclusive OR operation circuit 35_i in the error correction unit 35 is configured to display the error detection signal Error <i> and the cell data Cell Data stored in the page buffer 12 in the read operation at the position of the (i) th bit line. Bits are input. That is, each of the exclusive OR operation circuits 35_i inverts the logic of the data of the bit data at the position of the (i) th bit line if the error detection signal Error <i> is at the H level, and the corrected data Output as 1 bit of Corrected Data. On the other hand, if the error detection signal Error <i> is L level, the exclusive OR operation circuit 35_0 corrects the logic of the data of the bit data at the position of the (i) th bit line as it is without correcting it. Output as 1 bit of Data.

[Linearity of polynomials and linear structures of Galois fields]
In the nonvolatile semiconductor memory device 10 of the present embodiment, the error detection / correction circuit 13 uses the linear structure of the Galois field and the polynomial when the error position detection polynomial is calculated in the Galois field calculation circuit 34. Is being reduced. Here, first, the linearity of the Galois field and the polynomial will be supplementarily described.
In the following description, in order to make the drawings easy to see and understand, it is assumed that m = 3 (or m = 4) in the Galois field GF (2 ^m ), and the order of the error position detection polynomial is The case of the fourth order (n = 4) will be described as an example. Of course, the orders m and n are arbitrary values set according to the bit length of the data subject to error detection and the number of error correction bits. Of value.

When a function F (X) satisfies the following two conditions, F (X) is said to be linear with respect to X.
(Condition 1) F (X ₁ + X ₂ ) = F (X ₁ ) + F (X ₂ )
(Condition 2) F (aX ₁ ) = aF (X ₁ )

For example, if X is a Galois field element, F (X) = X ² is a linear function of X. Because, when X ₁ and X ₂ are Galois field elements, and a = 0, 1,
F (X ₁ + X ₂ ) = (X ₁ + X ₂ ) ²
= X ₁ ² + 2X ₁ · X ₂ + X ₂ ²
= X ₁ ² + X ₂ ² (The addition on the ∵ Galois field is an exclusive OR, and 1 + 1 = 2 = 0, so 2X ₁ · X ₂ is 0)
= F (X ₁ ) + F (X ₂ )
And satisfies (Condition 1). Since a is 0 and 1, it is clear that (Condition 2) is satisfied. Similarly, since “1 + 1 = 0” on the Galois field, functions such as X ⁴ , X ⁸ , X ¹⁶ ,... That multiply X by a power of 2 are linear functions on the Galois field. I understand.

Here, paying attention to the first-order, second-order, and fourth-order terms of the Galois field polynomial,
Put “Q (X) = p ₄ X ⁴ + p ₂ X ² + p ₁ X”.
At this time, X and Y are elements of Galois field,
Q (X + Y) = p ₄ (X + Y) ⁴ + p ₂ (X + Y) ² + p ₁ (X + Y)
= P ₄ (X ⁴ + Y ⁴ ) + p ₂ (X ² + Y ² ) + p ₁ (X + Y)
(Addition on the ∵ Galois field is an exclusive OR, and 1 + 1 = 2 = 0, so 2 = 4 = 0)
= P ₄ X ⁴ + p ₄ Y ⁴ + p ₂ X ² + p ₂ Y ² + p ₁ X + p ₁ Y
= (P ₄ X ⁴ + p ₂ X ² + p ₁ X) + (p ₄ Y ⁴ + p ₂ Y ² + p ₁ Y)
= Q (X) + Q (Y)
Thus, the above (condition 1) is satisfied. Since it is clear that (Condition 2) is satisfied, Q (X) is a linear function of X.

Thus, it can be seen that “Q (X) = p ₄ X ⁴ + p ₂ X ² + p ₁ X” is a linear function with respect to X.

On the other hand, other terms (terms other than X ⁴ , X ² , and X) can be regarded as a linear function by regarding X ³ and X ⁵ as variables, for example. For example, paying attention to the third, sixth, and twelfth terms,
If you put the _{^{R (X) = p 12 X}} 12 + p 6 X 6 + p 3 X 3, R (X) is a linear function of ^{X 3.}

Next, the linear structure of the Galois field will be described.
FIG. 3 shows elements 1 (= α ⁰ ), α ¹ , α ² ,... Of Galois field GF (2 ⁴ ) when the primitive polynomial F (X) is “F (X) = X ⁴ + X + 1”. , Α ¹⁴ is shown in the table (Table 1). Here, paying attention to the four elements 1, α, α ² , and α ³ (portions surrounded by dotted lines), it can be seen that these are linearly independent sets in which oneself is never expressed by the sum of other elements. . If these are considered to be basis vectors, other elements are expressed by linear combinations of the basis vectors. That is, by using the relationship of “α ⁴ + α ¹ + α ⁰ = 0”, each element 0, α ⁰ (= 1), α ¹ , α ² ,..., Α ¹⁴ is α ⁰ , α, α ^2. , Α ³ can be represented by four-dimensional vectors (0, 0, 0, 0) to (1, 1, 1, 1).

For example, α ⁴ = 1 + α ¹ and
Further, α ¹² = α (α ¹ + α ² + α ³ ) = α ² + α ³ + α ⁴ = 1 + α ¹ + α ² + α ³ .

Here, assuming that βi = 0, 1 (i = 0, 1, 2, 3), an arbitrary Galois field element is α ^j = β ₃ α ³ + β ₂ α ² + β ₁ α ¹ + β ₀ α ⁰ (j = 0, 1, 2,...). Here, (β ₃ , β ₂ , β ₁ , β ₀ ) is a vector expression corresponding to α ^j .

For Q (X), Q _j = Q (α ^j ) (j = 0, 1, 2,...) Is written. Substituting α ^j = β ₃ α ³ + β ₂ α ² + β ₁ α ¹ + β ₀ α ⁰ into Q (X),
Q _j = Q (α ^j ) (a)
= Q (β ₃ α ³ + β ₂ α ² + β ₁ α ¹ + β ₀ α ⁰ )
= Β ₃ Q (α ³ ) + β ₂ Q (α ² ) + β ₁ Q (α ¹ ) + β ₀ Q (α ⁰ )
(From the linearity of ∵Q (X))
= Β ₃ Q ₃ + β ₂ Q ₂ + β ₁ Q ₁ + β ₀ Q ₀ (b)
Get. Conventionally, from the above formula (a), it was necessary to further add the result of matrix calculation of each term as “Q _j = p ₄ α ⁴ + p ₂ α ² + p ₁ α”. b) Using equations, Q ₀ , Q ₁ , Q ₂ , Q ₃ corresponding to the base 1 (= α ⁰ ), α ¹ , α ² , α ³ are obtained in advance by matrix operation, and these simple additions are performed. Other Q _j can be determined.

FIG. 4 shows elements 1 (= α ⁰ ), α ¹ , α ² ,... Of the Galois field GF (2 ³ ) when the primitive polynomial F (X) is “F (X) = X ³ + X + 1”. ... Α ⁶ is shown in the table (Table 2). Here, paying attention to three elements 1, α and α ² (portions surrounded by dotted lines), it can be seen that these are linearly independent sets in which oneself is never expressed by the sum of elements other than oneself. If these are considered to be basis vectors, other elements are expressed by linear combinations of the basis vectors. That is, using the relationship of “α ³ + α ¹ + α ⁰ = 0”, each element 0, α ⁰ (= 1), α ¹ , α ² ,..., Α ⁶ is expressed as α ⁰ , α, α ^2. Can be represented by three-dimensional vectors (0, 0, 0) to (1, 1, 1).

[Configuration of Galois Field Arithmetic Circuit 34]
Next, the configuration of the Galois field arithmetic circuit 34 for obtaining the zero point of the Galois field polynomial (error position detection polynomial) will be described. The Galois field arithmetic circuit 34 is configured to reduce the circuit scale using the linearity of the error position detection polynomial (error position detection polynomial) described above and the linear structure of the Galois field. That is, when the Galois field arithmetic circuit 34 calculates the error position detection polynomial P (X), a linear function that integrates terms constituting the same linear space is used by using a basis calculation unit and a linear expansion unit described later. By performing the operation, the circuit scale can be reduced.

FIG. 5A is a diagram illustrating a configuration example of the Galois field arithmetic circuit 34, and is an example in the case of “m = 3”. The Galois field arithmetic circuit 34 includes a base calculation unit 330 and a linear expansion unit 340. The basis calculation unit 330 includes three sets of calculation units R ₀ , R ₁ , and R ₂ , and the linear expansion unit 340 includes four EXOR elements.
In the Galois field arithmetic circuit 34 shown in FIG. 5A, the base calculation unit 330 calculates a linear function y for the element serving as a base among the elements x “m−1: 0” by matrix operation, and performs linear expansion. The unit 340 expands (adds) the calculation result of the basis calculation unit 330 to obtain the output of the linear function y for the other elements excluding the basis (about the operation of the Galois field arithmetic circuit 34 shown in FIG. 5A). Will be described later).

As described above, in the Galois field arithmetic circuit 34 of the present embodiment, the basis calculation unit 330 calculates the basis for the linear function included in the error position detection polynomial, and the linear expansion unit 340 calculates the calculation results of these bases. All the possible values of X of the linear function are output at once by simple addition of. That is, in this Galois field arithmetic circuit 34, a matrix arithmetic unit (EXOR element is set to about m for 2 ^m −1−m subtracting the number m of bases from all combinations 2 ^m −1 of possible values of X. The circuit scale can be reduced by replacing (m−1) / 2) with simple addition (using m−1 EXOR elements).

On the other hand, FIG. 5 (B) is a diagram showing a configuration of a conventional Galois field arithmetic circuit 34 ′. In this Galois field arithmetic circuit 34 ′, seven parallel arithmetic circuits R ₀ to R for each element X are shown. R ₆ is provided, and signals y ₀ , y ₁ , y ₂ ,..., Y ₆ are calculated simultaneously by the seven parallel arithmetic circuits R _{0 to} R ₆ .

That is, as shown in FIG. 6, in the case of the fourth-order error position detection polynomial “P (X) = p ₄ X ⁴ + p ₃ X ³ + p ₂ X ² + p ₁ X ¹ + p ₀ ”, the conventional Galois field arithmetic In the circuit 34 ′, as shown in FIG. 6A, the calculation is performed for each term p _i X ⁱ . On the other hand, in the Galois field arithmetic circuit 34 of the present embodiment, as shown in FIG. 6B, a term having the same linear structure for X is expressed by a polynomial (linear function Q (X) = p ₄ X ⁴ + P ₂ X ² + p ₁ X).

Then, for this linear function “Q (X) = p ₄ X ⁴ + p ₂ X ² + p ₁ X”, the Galois field arithmetic circuit 34 shown in FIG. By performing the calculation using 340, the number of units for calculating each term is reduced in the calculation of the error position detection polynomial P (X), and further, the number of elements of the circuit for adding outputs between the units is also reduced.
The terms “p ₃ X ³ ” and “P ₀ ” other than Q (X) are separately calculated by a circuit (not shown) in the Galois field arithmetic circuit 34, and later “Q (X) = p ₄ X ⁴ + P ₂ X ² + p ₁ X ”is added to the calculation result.

FIG. 7 is a diagram for explaining the operation of the Galois field arithmetic circuit 34 shown in FIG. 5A, in which the variable X is represented by a power of α. In the Galois field arithmetic circuit 34 shown in FIG. 7, the element (element) X input to the basis calculation unit 330 is set to 1, α, α ² , and the basis calculation unit 330 uses the linear function Q (1) for X. , Q (α), Q (α ² ), and Q (α ³ ), Q (α ⁴ ), Q (α ⁵ ), Q (α ⁶ ) are calculated by the linear expansion unit 340. .

As shown in FIG. 7, the Galois field arithmetic circuit 34 includes a base calculation unit 330 and a linear expansion unit 340. The base calculation unit 330 includes three calculation units R ₀ , R ₁ , R ₂ and the linear expansion unit 340 includes four EXOR elements 341, 342, 343, and 344.

The calculation unit R ₀ in the basis calculation unit 330 is a matrix of the linear function “Q (1) = p ₄ 1 ⁴ + p ₂ 1 ² + p ₁ 1 ¹ ” in the error position detection polynomial for the element X (1 = α ⁰ ). Calculate by calculation. The calculation unit R ₁ calculates a linear function “Q (α) = p ₄ α ⁴ + p ₂ α ² + p ₁ α ¹ ” for the element X (= α ¹ = α) by matrix calculation. The calculation unit R ₂ calculates a linear function “Q (α ² ) = p ₄ (α ² ) ⁴ + p ₂ (α ² ) ² + p ₁ α ² ” for the element X (= α ² ) by matrix calculation.

Then, the linear expansion unit 340 expands the calculation results Q (1), Q (α), and Q (α ² ) calculated by the base calculation unit 330 by simple addition to obtain another output.
For example, since Q (α ³ ) is “α ³ = α + 1” as shown in Table 2 of the Galois field GF (2 ³ ) in FIG. 4, “Q (α ³ ) = Q (α) + Q (1) ”. Therefore, Q (α ³ ) is obtained by adding the outputs Q (1) and Q (α) of the base calculation unit 330 by the EXOR element (adder) 341.

Further, since Q (α ⁴ ) is “α ⁴ = α ² + α” as shown in Table 2 of the Galois field GF (2 ³ ) in FIG. 4, “Q (α ⁴⁾ ) = Q (α ² ) + Q (α) ”. Therefore, Q (α ⁴ ) is obtained by adding the outputs Q (α) and Q (α ² ) of the basis calculation unit 330 by the EXOR element 342.

Further, since Q (α ⁵ ) is “α ⁵ = α ² + α + 1” and “α ⁴ = α ² + α”, “α ⁵ = α ⁴ +1”. For this reason, Q (α ⁵ ) is obtained by adding the output Q (1) of the base calculation unit 330 and the output Q (α ⁴ ) of the EXOR element 342 by the EXOR element 343.
Similarly, since Q (α ⁶ ) is “α ⁶ = α ² +1”, Q (α ⁶ ) is output by the EXOR element 344 from the outputs Q (1) and Q (α ² ) of the base calculation unit 330. ) Are added to each other.

As described above, in the case of the Galois field GF (2 ³ ), the basis calculation unit 330 performs three linear sets corresponding to the three linearly independent elements (1, α ¹ , α ² ). Functions Q (1), Q (α ¹ ), and Q (α ² ) are calculated. Then, the linear expansion unit 340 converts the linear functions Q (α ³ ), Q (α ⁴ ), Q (α ⁵ ), and Q (α ⁶ ) into Q (1) and Q (α ¹ ) in the basis calculation unit 330. , Q (α ² ), and can be calculated by addition using an EXOR element. As described above, the Galois field arithmetic circuit 34 has “4” error position detection polynomials (more precisely, in the error position detection polynomial, which is obtained by subtracting the number of bases 3 from the total number of combinations of possible values of the element X. The circuit scale can be reduced by replacing the matrix operation with simple addition.

  In the circuit example shown in FIG. 7, the bases of vector expressions (001), (010), and (100) are used as a set of three linearly independent bases as shown in Table 2 of FIG. However, it is not always necessary to select such a vector in which only one bit is 1 as a basis, and any combination may be used as long as it is a set of linearly independent vectors.

  As described above, in the Galois field arithmetic circuit 34 of the present embodiment, the terms constituting the same linear space are integrated as a linear function in the error position detection polynomial, and the basis calculation unit 330 and the integrated linear function are combined. Calculation is performed by the linear expansion unit 340. As a result, the Galois field arithmetic circuit 34 can greatly reduce the scale of arithmetic elements required when calculating the error position detection polynomial. Further, the number of units for calculating each term of the error position detection polynomial is reduced, and further, the number of elements of the circuit for adding outputs between the units is also reduced.

[When the error position detection polynomial includes a linear function of X ² and X ³ ]
In the above-described embodiment, the example of the Galois field arithmetic circuit 34 that calculates the linear function “Q (X) = p ₁ X ⁴ + p ₂ x ² + p ₁ X” for X has been described. Here, error position detection is performed. An example in which the polynomial Λ (X) includes a linear function for X and a linear function for X ³ will be described.
For example, if the error position detection polynomial Λ (X) is P (X) = “σ ₁ X + σ ₂ X ² + σ ₄ X ⁴ +...” + “Σ ₃ X ³ + σ ₆ X ⁶ + σ ₁₂ X ¹² +. “”, The linear function “M (X) = σ ₁ X + σ ₂ X ² + σ ₄ X ⁴ +...” For X and the linear function “N (X) = σ for X ^3. ₃ integrated separately in each of the _{^{X 3 + σ 6 X 6 +}} σ 12 X 12 + ··· ", can be individually computed for each of the linear function.

  For example, FIG. 8 is a diagram illustrating an example of a circuit that calculates a linear term for X. In the example shown in FIG. 8, the base calculation unit 400 is configured to include three calculation units 401, 402, and 403, and the linear expansion unit 410 includes four EXOR elements in the same manner as the circuit shown in FIG. 411, 412, 413, 414.

The basis calculation unit 400 calculates M (α ⁰ ) by the calculation unit 401, calculates M (α ¹ ) by the calculation unit 402, and calculates M (α ² ) by the calculation unit 403. That is, the calculation unit 401 calculates an error position detection polynomial “M (X) = σ ₁ 1 + σ ₂ 1 ² + σ ₄ 1 ⁴ +...” For the element X (1 = α ⁰ ) by matrix calculation. Further, the calculation unit 402 calculates an error position detection polynomial “M (X) = σ ₁ α + σ ₂ α ² + σ ₄ α ⁴ +...” For the element X (= α ¹ = α) by matrix calculation. Further, the calculation unit 403 calculates an error position detection polynomial “M (X) = σ ₁ (α ² ) + σ ₂ (α ² ) ² + σ ₄ (α ² ) ⁴ +...” For the element X (= α ² ). Is calculated by matrix operation.

The linear expansion unit 410 expands the calculation result calculated by the base calculation unit 400 by simple addition using the EXOR elements 411, 412, 413, and 414, and M (α ³ ), M (α ⁴ ), M ( α ⁵ ) and M (α ⁶ ) are calculated.
For example, M (α ³ ) is “α ³ = α + 1” as shown in Table 2 of the Galois field GF (2 ³ ) of FIG. 4, and therefore, “M (α ³ ) = M (α) + M (α ⁰ = 1) ”. Therefore, M (α ³ ) is obtained by adding the outputs M (α ⁰ = 1) and M (α) of the base calculation unit 400 by the EXOR element (adder) 411.

Further, since M (α ⁴ ) is “α ⁴ = α ² + α” as shown in Table 2 of the Galois field GF (2 ³ ) in FIG. 4, “M (α ⁴⁾ ) = M (α ² ) + M (α) ”. Therefore, M (α ⁴ ) is obtained by adding the outputs M (α) and M (α ² ) of the basis calculation unit 400 by the EXOR element 412.

In addition, M (α ⁵ ) is “α ⁵ = α ² + α + 1” and “α ⁴ = α ² + α”, and thus “α ⁵ = α ⁴ +1”. Therefore, M (alpha ⁵⁾ and the output M of the base calculation unit 400 by the EXOR element 413 (α ⁰ = 1), obtained by adding the output M of the EXOR elements 342 (α ^4).
Similarly, since M (α ⁶ ) is “α ⁶ = α ² +1”, M (α ⁶ ) is output from the output M (α ⁰ = 1) and M of the base calculation unit 400 by the EXOR element 414. It is obtained by adding (α ² ).
Thereby, in the Galois field arithmetic circuit 34, the circuit scale of the arithmetic circuit with respect to the linear function “σ ₁ X + σ ₂ X ² + σ ₄ X ⁴ +...” Can be reduced.

It will be described operation of the function _{"N (X) = σ 3 X} 3 + σ 6 X 6 + σ 12 X 12 + ··· " for ^{X 3.}
FIG. 9 is a table (Table 3) showing the elements (elements shown in Table 2) of the Galois field GF (2 ³ ) with the primitive polynomial X ³ + X + 1 shown in FIG. It is. In this case, the portion (1, α ³ , α ⁶ ) surrounded by the dotted line in FIG. 9 is used as a base, and the other elements (α ⁹ , α ¹² , α ¹⁵ , α ¹⁸ ) are expressed as the sum of the bases. it can.

For this reason, in the present embodiment, a part that summarizes the terms X ³ , X ⁶ , X ¹² ,... “Linear function N (X) = σ ₃ X ³ + σ ₆ X ⁶ + σ ₁₂ X ¹² +. As shown in FIG. 10, the calculation can be performed separately for the base calculation unit 500 and the linear expansion unit 510. However, the circuit pattern for expanding the base in the linear expansion unit 510 is different from that in FIG. This is a linear function of N (Y) = σ ₃ Y + σ ₆ Y ² + σ ₁₂ Y ⁴ +... When Y = X ³ with respect to N (X). This is because it can be expressed by base addition as shown in Table 3 of FIG. In this example, rather than the non-linear function of N and (X) X, regarded as a linear function of the X ³ and variables, for performing calculations using a basis expansion, circuit reduction equivalent to the circuit shown in FIG. 8 is obtained.

In the example shown in FIG. 10, the polynomial “N (X) = σ ₁ X ³ + σ ₆ X ⁶ + σ ₁₂ X ¹² +...” N (α ⁰ ) is calculated by the calculation unit 501 in the basis calculation unit 500. Is calculated by matrix calculation, N (α ³ ) is calculated by matrix calculation by the calculation unit 502, and N (α ⁶ ) is calculated by matrix calculation by the calculation unit 503. The linear expansion unit 510 uses the EXOR elements 511, 512, 513, and 514 based on the base calculation results N (α ⁰ ), N (α ³ ), and N (α ⁶ ) calculated by the base calculation unit 500. , N (α ⁹ ), N (α ¹² ), N (α ¹⁵ ), N (α ¹⁸ ),.

For example, since N (α ⁹ ) is “α ⁹ = α ⁶ +1” as shown in Table 3 of FIG. 9, “N (α ⁹ ) = N (α ⁶ ) + N due to the linearity described above. (Α ⁰ = 1) ”. Therefore, N (α ⁹ ) is obtained by adding the outputs N (α ⁰ = 1) and N (α ⁶ ) of the base calculation unit 500 by the EXOR element (adder) 511.

Further, N (alpha ^12), as shown in Table 3 of FIG. 9, an ^{"α 12 = α 6 + α 3} +1 ", also because of the "α ⁹ = α ⁶ +1", "alpha ¹² = α ⁹ + α ³ ”. For this reason, it can represent with "N ((alpha) ¹² ) = N ((alpha) ⁹ ) + N ((alpha) ³ )" by the linearity mentioned above. Thus, N (alpha ^12), due EXOR element 512, the output N of the base calculation unit 500 (alpha ^3), obtained by adding the output N of the EXOR elements 512 (alpha ^9).

N (α ¹⁵ ) is “α ¹⁵ = α ³ +1”. Therefore, N (α ¹⁵ ) is obtained by adding the outputs N (α ⁰ = 1) and N (α ³ ) of the base calculation unit 500 by the EXOR element 513 due to the linearity described above.
Similarly, since M (α ¹⁸ ) is “α ¹⁸ = α ⁶ + α ³ ”, N (α ¹⁸ ) is output by the EXOR element 514 using the outputs N (α ⁶ ) and N (α It is obtained by adding (α ³ ).

As a result, the Galois field arithmetic circuit 34 reduces the circuit scale when performing arithmetic on the linear function “N (X) = σ ₃ X ³ + σ ₆ X ⁶ + σ ₁₂ X ¹² +. Can do.

As described above, in the error detection and correction circuit 13 of the present embodiment, the Galois field operation circuit 34 includes two circuits, a base calculation unit circuit that calculates a base and a linear expansion unit circuit that expands the base by simple addition. have.
In the Galois field arithmetic circuit 34, after the coefficients p _i (i = 0, 1, 2,...) Of the Galois field polynomial P (X) are determined, each linear included in the error position detection polynomial P (X). For the function, the basis calculation unit 330 calculates the basis, and the linear expansion unit 340 can output all the possible values of X of P (X) at a time by simple addition of these bases. For this reason, the circuit scale of the Galois field arithmetic circuit 34 is reduced.
Further, as shown in FIG. 8 and FIG. 10, by integrating and calculating terms having the same linear structure, the number of units for calculating polynomial terms is reduced, and furthermore, a circuit for adding outputs between units. The number of elements is also reduced.

[Specific example of effect of reducing the number of elements according to this embodiment]
Next, a circuit for obtaining a zero of an m-th order polynomial P (X) having coefficients p _i (i = 0, 1, 2,...) And a variable X as elements of a Galois field GF (2 ^m ) is used. The number of elements to be calculated is calculated, and the case of the conventional technique (in the case of the Galois field arithmetic circuit 34 ′ in FIG. 5B) is compared with the case of the Galois field arithmetic circuit 34 of the present embodiment.
In the case of the prior art, 2 ^m −1 sets of matrix operation circuits that require about m (m−1) / 2 EXOR elements are required, and this requires n + 1 sets corresponding to the number of polynomial terms. In addition, the EXOR element for adding each term requires 2 ^m -1 sets of ^m sets and n sets of these. Therefore, the total number of elements required for the circuit is
(N + 1) × (2 ^m −1) × m (m−1) / 2 + n × (2 ^m −1) × m,
It becomes.

In the Galois field arithmetic circuit 34 of the present embodiment, only m sets of matrix arithmetic circuits that require about m (m−1) / 2 EXOR elements are necessary. The part that determines the value needs “2 ^m −1−m” sets of m EXOR elements. Functions such as “X ² , X ⁴ , X ⁸ , X ¹⁶ ,...” That multiply X by a power of 2 are linear functions on a Galois field, and linear combinations of linear functions are also linear functions. From these terms, these terms can be integrated. Similarly, “X ³ , X ⁶ , X ¹² ,...” And “X ⁵ , X ¹⁰ , X ²⁰ ,.

From this, it can be seen that the number of linear functions after integration is equal to an odd number that is less than or equal to the order n of the polynomial. Considering the constant term p ₀ together, the number of units required after integration is
When n = 0, 1 (0),
When n = 1, 2 (0, 1),
When n = 2, 2 (0, 1),
When n = 3, 3 (0, 1, 3),
When n = 4, 3 (0, 1, 3),
When n = 5, 4 (0, 1, 3, 5),
... and you can see that it increases.

The number of units is n / 2 + 1 when n is an even number and (n + 1) / 2 + 1 when n is an odd number. Considering that the basis calculation part is not integrated, the number of elements required for the circuit is as follows:
(N + 1) × m × m (m−1) / 2 + m × m × n + (n / 2 + 1) (2 ^m −1−m) × m + (2 ^m −1−m) n / 2.
When n is an odd number,
(N + 1) × m × m (m−1) / 2 + m × m × n + {(n + 1) / 2 + 1} (2 ^m −1−m) × m + (2 ^m −1−m) (n + 1) / 2
It is.

  FIG. 11A compares the total number of elements in the case of the conventional technique (the Galois field arithmetic circuit 34 ′ shown in FIG. 5B) and the case of the present embodiment in the case of the degree n = 4 of the polynomial. An example is shown. FIG. 11B shows an example in which the total number of elements is compared between the case of the conventional technique (the Galois field arithmetic circuit 34 ′ shown in FIG. 5B) and the case of this embodiment when n = 8. Indicates. From this, it can be seen that, with respect to the increase in the parameter m that characterizes the Galois field, this embodiment can suppress the increase in the circuit scale as compared with the conventional case.

  Next, the effectiveness other than the reduction of the circuit scale will be described. The circuit structure of the linear expansion unit 340 shown in FIG. 5A takes an independent form for each bit of data to be handled. That is, it is possible to realize this by preparing m circuits for 1 bit. This facilitates the reduction of the circuit layout area.

The linear expansion corresponding to one bit is a circuit of “m input / 2 ^m −1 output”. When m bits are described flat, it is a circuit of “m ² inputs / 2 2 ^m −1 power” and it is difficult to verify all input / output patterns in a realistic time. On the other hand, since the unit of 1 bit is a circuit of “m input / 2 ^m −1 output”, all input / output patterns can be verified in a realistic time. By verifying all input / output patterns with this unit and verifying connections at higher levels, more accurate verification can be performed.
In addition, since the linear expansion unit 340 can be divided into m units, it is possible to hold the output from one unit and obtain the final result with m clocks. In this case, m clocks are required until the zero point is obtained, but the circuit scale can be reduced to about 1 / m of the present embodiment.

Although the embodiment of the present invention has been described above, the correspondence relationship between the present invention and the above-described embodiment will be supplementarily described. That is, in the above embodiment, the Galois field arithmetic circuit in the present invention corresponds to the Galois field arithmetic circuit 34 in the chain search unit 33 shown in FIG. 2, and the memory device in the present invention is the nonvolatile semiconductor memory shown in FIG. The device (NAND flash memory EEPROM) 10 corresponds. The basis calculation unit in the present invention corresponds to, for example, the basis calculation unit 330 shown in FIG. 5, and the linear expansion unit in the present invention corresponds to, for example, the linear expansion unit 340.
The error detection and correction circuit in the present invention corresponds to the error detection and correction circuit 13 shown in FIG. 2, and the syndrome calculation unit in the present invention corresponds to the syndrome calculation unit 31 in the decoder unit 30 shown in FIG. The error coefficient calculation unit in the invention corresponds to the error coefficient calculation unit 32, the chain search unit in the present invention corresponds to the chain search unit 33, and the error correction unit in the present invention corresponds to the error correction unit 35.

In the above-described embodiment, the Galois field arithmetic circuit 34 performs error representation of (2 ^m −1) elements represented by m bits on the Galois field GF (2 ^m ) (m is an integer, the same applies hereinafter). a Galois field operation circuit for substituting the detected polynomial, from among the (2 m ^-1) number of elements, the basis computation unit 330 for calculating a linearly independent m-number of source, (2 m ^-1) pieces of A linear expansion unit 340 that obtains (2 ^m -1-m) elements obtained by removing the ^m elements from the elements as a combination of the m elements.
The Galois field arithmetic circuit 34 having such a configuration includes a base calculation unit 330 and a linear expansion unit 340. The basis calculation unit 330 calculates an error position detection polynomial for linearly independent ^m elements on the Galois field GF (2 ^m ). In addition, regarding the calculation of the error position detection polynomial for the remaining (2 ^m −1−m) elements excluding the linearly independent m elements, the calculation result in the basis calculation unit 330 is added by the linear expansion unit 340. And calculate.
For example, in the case of the Galois field GF (2 ³ ), the linear function of X in the error position detection polynomial “P (X) = p ₄ X ⁴ + p ₃ X ³ + p ₂ X ² + p ₁ X1 + p ₀ ” X) = p ₄ X ⁴ + p ₂ X ² + p ₁ X ”, the basis calculation unit 330 calculates Q (1), Q (α for three linearly independent elements (1, α ¹ , α ² ). ¹ ), Q (α ² ) is calculated. The linear expansion unit 340 then performs linear functions Q (α ³ ), Q (α ⁴ ), Q (α ⁵ ), and Q (α ⁶ ) on the element (α ³ , α ⁴ , α ⁵ , α ⁶ ). Q (1), Q (α 1), based on the calculation result of Q (α ^2), the calculation result Q (1), Q (α 1), EXOR elements Q (α ²⁾ 341,342,343 Calculate by adding.
Thus, in the Galois field arithmetic circuit 34, the conventional matrix operation can be replaced with simple addition, so that the circuit scale can be reduced.

Further, in the above embodiment, the Galois field arithmetic circuit 34 integrates the terms constituting the same linear space in the error position detection polynomial as a linear function, and the basis calculation unit 330 for the integrated linear function. In the Galois field arithmetic circuit 34 having such a configuration, terms having the same linear structure are integrated and calculated in the error position detection polynomial. Thus, by integrating and calculating terms having the same linear structure, the number of units for calculating polynomial terms is reduced, and further, the number of elements in a circuit for adding outputs between units is also reduced.

In the above embodiment, the memory device (nonvolatile semiconductor memory device 10) performs error position detection polynomial calculation using the Galois field arithmetic circuit 34, and error correction for detecting an error in the input data string. The error detection / correction circuit 13 is a memory device (nonvolatile semiconductor memory device 10) including a circuit, and a syndrome calculation unit 31 that calculates a syndrome from an input data string, and calculates a coefficient of an error position detection polynomial from the syndrome The error coefficient calculation unit 32, the value indicating the bit position of the data in the data string, the Galois field arithmetic circuit 34 for calculating by substituting the coefficient into the error position detection polynomial, and the result of the substitution into the error position detection polynomial In response, the chain search unit 33 for outputting an error detection signal indicating whether or not there is an error for each bit of the data string, and the error detection signal Provided Ri and error correction unit 35 to output the correcting an error bit of the data in the data row, the.
In the memory device (nonvolatile semiconductor memory device 10) having such a configuration, when the Galois field calculation circuit 34 calculates an error position detection polynomial, the basis calculation unit 330 performs linearity on the Galois field GF (2 ^m ). An error position detection polynomial is calculated for independent m elements. The linear expansion unit 340 then calculates error position detection polynomials for the remaining (2 ^m −1−m) elements excluding the linearly independent m elements based on the calculation result in the basis calculation unit 330. It is generated by adding the operation results of.
Thereby, the circuit scale of the Galois field arithmetic circuit 34 mounted in the memory device (nonvolatile semiconductor memory device 10) can be reduced. For this reason, the memory device (nonvolatile semiconductor memory device 10) can be equipped with an error detection and correction circuit capable of high-speed computation on-chip.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes a design and the like within the scope not departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 10 ... Nonvolatile semiconductor memory device, 11 ... Memory cell array, 12 ... Page buffer, 13 ... Error detection correction circuit, 14 ... Buffer, 15 ... I / O pad, 16 ... Control circuit, 17 ... Address decoder, 18 ... Row and Block decoder, 30 ... Decoder unit, 31 ... Syndrome calculation unit, 32 ... Error coefficient calculation unit, 33 ... Chain search unit, 34 ... Galois field arithmetic circuit, 35 ... Error correction unit, 40 ... Encoder unit, 41 ... Parity generation circuit , 330 ... basis calculation section, 340 ... linear expansion section, 400 ... basis calculation section, 410 ... linear expansion section, 500 ... base calculation section, 510 ... linear expansion section

Claims (3)

A Galois field arithmetic circuit for substituting (2 ^m −1) elements represented by m bits on a Galois field GF (2 ^m ) (m is an integer, the same applies hereinafter) into an error position detection polynomial,
A basis calculation unit for calculating linearly independent m elements from the (2 ^m -1) elements;
Wherein the (2 m ^-1) pieces of the original one except for the m source (2 m ^-1-m) pieces of the original, and the linear expansion unit for determining a combination of each of the m pieces of the original,
A Galois field arithmetic circuit comprising: Terms that constitute the same linear space in the error position detection polynomial are integrated as a linear function, and the integrated linear function is operated by the base calculation unit and the linear expansion unit. The Galois field arithmetic circuit according to claim 1. A memory device comprising an error correction circuit that performs an error position detection polynomial calculation using the Galois field arithmetic circuit according to claim 1 or 2 and detects an error in an input data string,
The error detection and correction circuit includes:
A syndrome calculation unit for calculating a syndrome from the input data sequence;
An error coefficient calculator that calculates a coefficient of the error position detection polynomial from the syndrome;
The Galois field arithmetic circuit which calculates by substituting the value indicating the bit position of data in the data string and the coefficient into the error position detection polynomial;
A chain search unit that outputs an error detection signal indicating whether or not there is an error for each bit of the data string, according to the substitution result to the error position detection polynomial,
An error correction unit that corrects and outputs an error in the bit data in the data string by the error detection signal; and
A memory device comprising:

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