JP2014033364A - Error detection and correction circuit and memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error detection and correction circuit and a memory device that can error-correct and output arbitrary addressed bits of a data string at high speed.SOLUTION: The error detection and correction circuit includes: a data storage section (page buffer 12) for storing a data string; a syndrome calculation section 31 for calculating syndromes from the data string; an error coefficient calculation section 32 for calculating coefficients of an error location search equation from the syndromes; a latch section 35 for storing the coefficients; a substitute value calculation section 36 for calculating a substitute value to be substituted into the error location search equation from an address indicating the location of the data string and the coefficients stored in the latch section 35; a Chien search section 33 for outputting error detection signals indicating whether or not there are any errors in respective bits of the data string in response to the result of substitution of the substitute value into the error location search equation when the data string is output; and an error correction section 34 for correcting errors in bit data of the data string to be output according to the error detection signals.

Description

  The present invention relates to an error detection / correction circuit and a memory device.

  A NAND flash memory is known as one of electrically rewritable nonvolatile semiconductor memory devices (EEPROM) that are electrically erasable and programmable read only memory (EEPROM). The NAND flash memory uses a NAND cell unit (NAND string) in which a plurality of memory cells are connected in series, thereby enabling large-capacity storage with a small chip area.

  In the NAND flash memory, the retention characteristics of the memory element (memory cell) are lost during data retention due to deterioration of the tunnel oxide film caused by many rewrites, and the error bit rate (error rate) is increased. There is a tendency to grow. In particular, in the NAND flash memory, the error rate tends to increase as the capacity of the memory cell increases, that is, the miniaturization in the manufacturing process proceeds. Therefore, error correction code (Error Correcting Code) redundant data is added to the data to be stored and written to the flash memory as a data string, and at the time of reading, the data is corrected based on the error correction code redundant data. Thus, data compensation is performed when an error bit occurs.

  For example, Patent Document 1 discloses a NAND flash memory including an error detection / correction circuit (ECC circuit). In the error detection and correction circuit described in Patent Document 1, the chain search unit substitutes the position of a bit in received information (data string) into an error position search equation, and detects whether or not the bit has an error. When the data string is output, all addresses from the lowest to the highest are assigned to the chain search unit. The error correction circuit (error correction unit) corrects the bit data when each bit has an error and outputs the corrected data, and outputs the bit data as it is without correction when there is no error. .

Japanese Patent Application Laid-Open No. 2009-100369

  However, in the configuration described in Patent Document 1 described above, when a bit at an arbitrary address in a data string is to be read, the bit output from the error correction circuit is once stored in a buffer memory or the like and then read out. The address of the bit to be supplied must be supplied to the buffer memory. That is, conventionally, the error detection / correction circuit performs error correction on the data of the bit at an arbitrary address until the error bit data correction processing for all the bits of the data string including the bit to be read is completed. There was a problem that data after error correction could not be read out at high speed.

  Therefore, the problem to be solved by the present invention is an error detection and correction circuit capable of performing error correction of data of a bit at an arbitrary address in a data string and outputting the error-corrected data to the outside at high speed, and It is to provide a memory device.

  The error detection and correction circuit of the present invention includes a data storage unit that stores a data string, a syndrome calculation unit that calculates a syndrome from the data string, an error coefficient calculation unit that calculates a coefficient of an error position search equation from the syndrome, A latch unit that stores the coefficient; an address that indicates a position of the data string; and a substitution value calculation unit that calculates a substitution value to be substituted into the error position search equation using the coefficient stored in the latch unit; A chain search unit that outputs an error detection signal indicating whether or not there is an error for each bit of the data string, according to a result of substitution of the substitution value into the error position search equation when the data string is output, And an error correction unit that corrects and outputs an error of bit data in the data string by an error detection signal.

  In the error detection / correction circuit of the present invention, the data string is composed of a plurality of data strings, and the latch unit is provided corresponding to each of the plurality of data strings.

  According to another aspect of the present invention, there is provided a memory device including the error detection and correction circuit, wherein the data storage unit stores a data string read from a storage element, and the address is a memory of the storage element. It is a column address indicating the position of the column in.

  The error detection and correction circuit according to the present invention includes a latch unit that stores a coefficient of an error position search equation, and a substitution value calculation unit that calculates a substitution value to the error position search equation from the coefficient and the bit position. Therefore, when an address of a bit to be read is input to the substitution value calculation unit at the time of reading data, the chain search unit detects whether or not there is an error in the data of the bit. The error correction unit corrects the bit data if there is an error in the bit data and outputs the corrected bit data, and outputs the bit data as it is if there is no error. Therefore, it is possible to provide an error detection and correction circuit and a memory device that can perform error correction on data of a bit at an arbitrary address in a data string and read the corrected data at high speed.

1 is a schematic block diagram illustrating a configuration example of a NAND flash memory that is a nonvolatile semiconductor memory device 10; 3 is a diagram illustrating a detailed configuration example of an error detection and correction circuit 13. FIG. It is a figure which shows an example of a detailed structure of the chain search part. 4 is a diagram illustrating an example of a detailed configuration of an assigned value calculation unit 36. FIG. It is a figure which shows the detailed structural example of the error detection correction circuit 13a. It is a figure for demonstrating the comparison with the error detection correction circuit 13 and the error detection correction circuit 13a.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing a configuration example of a NAND flash memory that is a nonvolatile semiconductor memory device 10.
The nonvolatile semiconductor memory device 10 includes a memory cell array 11, a page buffer 12, an error detection and correction circuit 13, a buffer 14, an I / O pad 15, a control circuit 16, an address decoder 17, and a row and block decoder 18. The

The memory cell array 11 is a NAND cell string provided for each bit line by connecting a plurality of stack gate transistors, that is, electrically rewritable nonvolatile memory cells (storage elements) in series in the column direction (column direction). Are made up of a plurality of blocks arranged in the row direction (bit line arrangement direction). A plurality of blocks are arranged in the wiring direction of the bit lines. Further, this block is provided in units of erasing data of memory cells. In each block, a word line perpendicular to the bit line is connected to the gate of each nonvolatile memory arranged in the same row.
A range of nonvolatile memory cells selected by one word line is one page as a unit for programming and reading.

The page buffer 12 includes a page buffer circuit provided for each bit line in order to program and read data in units of pages. Each page buffer circuit in the page buffer 12 has a latch circuit that is connected to each bit line and that is used as a sense amplifier circuit that amplifies and determines the potential of the connected bit line.
The page buffer 12 (data storage unit) receives cell data Cell Data composed of data (data string) stored in one page of memory cells in the memory cell array 11 in the data read operation of the nonvolatile semiconductor memory device 10. This data is amplified and output to the error detection and correction circuit 13. On the other hand, the page buffer 12 stores the data supplied from the error detection / correction circuit 13 in the internal latch circuit in the data write (program) operation of the nonvolatile semiconductor memory device 10, and performs all the data while performing the verify operation. Is written as code data Code Data in a memory cell in one page.
The code data Code Data includes parity data Parity generated by the error detection and correction circuit 13. In this embodiment, for example, when an error correction system that performs 4-bit (bit) correction using a BCH code for an information length of 512 bytes (bytes) is taken as an example, one page is 2K (= 2048) bytes, that is, The memory cells each store 16k (= 176384) bits of normal data and the memory cells each store 208 bits of parity data. That is, cell data Cell Data and code data Code Data are composed of (16k + 208) bits. One page is divided into, for example, four sectors as a correction unit of the error detection and correction circuit 13. That is, the data corresponding to one sector is composed of normal data of 512 bytes (= 4096 bits) and parity data of 52 bits.
In this embodiment, access from the outside of the memory is performed by inputting the corresponding column address Y [13: 0] to the normal memory. Parity data is internal data added for correction of normal data and is not directly accessed from the outside.

Although the details will be described later, the error detection / correction circuit 13 processes the data read from the page buffer 12 for each sector in the data read operation of the nonvolatile semiconductor memory device 10 to obtain the coefficient of the error position search equation. Is calculated and held in an internal latch. Further, the error detection / correction circuit 13 corrects an error in the data of the bit whose position is indicated by the column address in the read operation, and outputs the corrected data to the outside through the I / O pad 15 as corrected data. An input / output circuit may be provided between the I / O pad 15 and the error detection / correction circuit 13, and data may be output to the outside through the input / output circuit.
Further, the error detection and correction circuit 13 receives information data Information Data input from the I / O pad 15 through the buffer 14 in the data write operation of the nonvolatile semiconductor memory device 10. The error detection / correction circuit 13 generates parity data parity from the received information data information data, and outputs the received information data information data and parity data parity to the page buffer 12. The page buffer 12 writes these data as code data Code Data in a memory cell connected to the selected page.

The control circuit 16 receives various control signals and controls operations such as data programming, reading, and erasing of the nonvolatile memory cell, and verification operation.
For example, the control signals are an external clock signal, a chip enable signal / CE, a read enable signal / RE, a program enable signal / WE, a command latch enable signal CLE, an address latch enable signal ALE, a write protect signal / WP, and the like. The control circuit 16 outputs an internal control signal to each circuit in accordance with the operation mode indicated by these control signals and command data input from the I / O pad 15.
For example, when the command latch enable signal CLE changes from the low (L) level to the high (H) level when the program enable signal / WE rises, the control circuit 16 takes in the command data from the I / O pad 15 and Hold in register.

The address decoder 17 holds an address (row address, block address, column address) input from the I / O pad 15 based on an internal control signal from the control circuit 16. The address decoder 17 outputs the held address to the row and block decoder 18, the page buffer 12, and the error detection and correction circuit 13 based on the internal control signal from the control circuit 16.
For example, the control circuit 16 fetches an address from the I / O pad 15 when the address latch enable signal ALE changes from the low (L) level to the high (H) level when the program enable signal / WE rises, and the address decoder 17 In the internal register.

The row and block decoder 18 selects a memory cell on one page by selecting a block and a word line of the memory cell array 11 according to a row address and a block address held and output by the address decoder 17.
The address decoder 17 selects a bit line of the memory cell array 11 and the page buffer 12 according to a column address held therein.

  In the present embodiment, in the data read operation, the cell data Cell Data in the page buffer 12 is read to the error detection and correction circuit 13, and the coefficient of the error position search equation is calculated for each sector. Then, according to the coefficient calculated for each sector and the column address, it is detected whether or not there is an error in the bit data whose position is indicated by the column address, that is, the memory cell data (16 bits). If there is, it is corrected and output from the I / O pad 15 as corrected data Corrected Data (details will be described later).

Further, in the data write operation, the cell data Cell Data once stored in the page buffer 12 is read into the buffer 14. The buffer 14 is configured by, for example, SRAM (Static Random Access Memory).
In the buffer 14, the data corresponding to the input column address in the cell data Cell Data is rewritten to the data Information Data from the I / O pad 15. Further, the error detection and correction circuit 13 calculates parity data corresponding to data for one sector including the data after rewriting of the buffer 14. Then, data for four sectors including the parity data is written as code data Code Data on the page selected via the page buffer 12.

Next, FIG. 2 is a diagram illustrating a detailed configuration example of the error detection and correction circuit 13.
In this embodiment, an error detection correction circuit (hereinafter also referred to as an ECC circuit) 13 will be described as an example of an ECC circuit using a BCH code (Bose-Chudhuri Hocquenhem code). The ECC circuit is a block code using a Galois field operation represented by a BCH code. Instead of the BCH code, for example, a Hamming code (Hamming code) or a Reed-Solomon code (Reed-Solomon code) can be used. In the following description, an information data length of 512 bytes (= 4096 bits) is used as a correction unit, that is, data of a quarter cell of one page is used as a correction unit, and data of 4 bits of each correction unit. An ECC circuit using a BCH code that can be corrected will be described.

The error detection and correction circuit 13 includes a decoder unit 30 that controls decoding of data, and an encoder unit 40 that generates correction parity data parity and adds the correction parity data parity to data to be written to the cell. .
Among these, the encoder unit 40 includes a parity generation circuit 41. The parity generation circuit 41 generates parity data Parity obtained by dividing the information data Information Data written in the buffer 14 by a generator polynomial. Further, the parity generation circuit 41 adds the generated parity data Parity to the information data Information Data, and outputs the information data Information Data to the page buffer 12. These data become code data Code Data written to one selected page when the nonvolatile semiconductor memory device 10 writes data. The present embodiment is characterized in that the error detection / correction circuit 13 performs data correction processing at high speed when data is read from the nonvolatile semiconductor memory device 10, and the decoder section 30 will be described in detail below. explain.

The decoder unit 30 includes a syndrome calculation unit 31, an error coefficient calculation unit 32, a chain search unit 33, an error correction unit 34, a latch unit 35, and a substitution value calculation unit 36.
The syndrome calculation unit 31 receives the cell data Cell Data read to the page buffer 12 for each sector as code data when reading data from the nonvolatile semiconductor memory device 10, and divides the code data by an independent minimum polynomial. To calculate the syndrome. There are four independent minimum polynomials used in a BCH code capable of correcting an error of 4-bit data. The syndrome calculation unit 31 includes four syndrome calculation circuits 31_1 to 31_4 corresponding to these four minimum polynomials. These syndrome calculation circuits 31_1 to 31_4 calculate syndromes S1, S3, S5, and S7, respectively.

The error coefficient calculation unit 32 uses these syndromes S1, S3, S5, and S7 to calculate the coefficients e ₄ , e ₃ , e ₂ , e ₁ , and e ₀ of the error position search equation for each sector. The coefficients e ₄ , e ₃ , e ₂ , e ₁ , and e ₀ are calculated by the chain search unit 33 so that the error position search equation Λ (x) = e ₄ x ⁴ + e ₃ x ³ + e ₂ x ² + e ₁ x ¹ + e A coefficient of _zero . The error position search equation Λ (x) is used in the chain search unit 33 when searching for an error in the bits read from the page buffer 12 for each sector.

Here, in order to explain the error position search equation, the configuration and operation of the chain search unit 33 will be described.
FIG. 3 is a diagram illustrating an example of a detailed configuration of the chain search unit 33.
The chain search unit 33 includes four selectors, five flip-flops, 64 constant multiplication circuits, 16 exclusive OR operation circuits, and 16 logic inversion circuits.
As shown in FIG. 3, the four selectors are selectors 301, 302, 303, and 304, and the five flip-flops are flip-flops 310, 311, 312, 313, and 314. In addition, the 64 constant multiplication circuits include constant multiplication circuits 321_1, 321_2, ..., 321_16, constant multiplication circuits 322_1, 322_2, ..., 322_16, constant multiplication circuits 323_1, 323_2, ..., 323_16, constant Multiplier circuits 324_1, 324_2,..., 324_16. Further, the 16 exclusive OR operation circuits are exclusive OR operation circuits 330_1, 330_2,..., 330_15, 330_16, and the 16 logic inversion circuits are the logic inversion circuits 340_1, 340_2,. -340_15 and 340_16.

X in e ₁ x, e ₁ x ² , e ₁ x ³ , and e ₁ x ⁴ respectively input to the selectors 301 to 304 indicates code data, that is, the position of the cell data Cell Data stored in the page buffer. A value is entered. In this cell data Cell Data, a parity bit (52 bits) is added to the lowest column. Specifically, the following value is input as x. That is, since 16 kbit data (excluding parity data) is included in one page, the column address indicating the position of the bit line is the 14-bit column address Y [13: 0]. Of these, the upper 10 bits of the column address Y [13: 4] are represented by decimal numbers as Y = a ₁₃ × 2 ¹³ + a ₁₂ × 2 ¹² +... + A ₅ × 2 ⁵ + a ₄ × 2 ⁴ . In this embodiment, error correction of bit data is performed in units of 16 bits. Therefore, x is a ₁₃ × 2 ¹³ + a ₁₂ × 2 ¹² +... + A ₅ × 2 ⁵ + a shifted by a parity bit (52 bits). ₄ × 2 ⁴ +52 (= α ^j ) is input.

Here, when i = 0 to 15 (integer), α ^{i + j} is an element of the Galois finite field GF (2 ^m ), and the minimum value of the column address Y [13: 0], that is, the column address bits are all 0. This is a value indicating the position of the column address counting from the case of (i.e., the value of (j × 16 + i + 1) th bit line).
Since α ^{i + j} = α ⁱ × α ^j , the error location search equation Λ (x) = e ₄ x ⁴ + e ₃ x ³ + e ₂ x ² + e ₁ x ¹ + e ₀ is substituted by x = α ^{i + j} x)
Λ (α ^{i + j} )
= E ₄ (α ^{i + j} ) ⁴ + e ₃ (α ^{i + j} ) ³ + e ₂ (α ^{i + j} ) ² + e ₁ (α ^{i + j} ) ¹ + e ₀
= E ₄ (α ⁴ ) ⁱ · (α ⁴ ) ^j + e ₃ (α ³ ) ⁱ · (α ³ ) ^j + e ₂ (α ² ) ⁱ · (α ² ) ^j + e ₁ (α ¹ ) ⁱ · (α ¹ ) ^j + e ₀ (α ⁰ ) ⁱ · (α ⁰ ) ^j
It becomes.

Therefore, the selector 301 takes in e ₁ (α ^j ) and multiplies them by (α ¹ ) ⁱ times a constant within a range of i = 0 to 15 to obtain x ¹ of the error position search equation Λ (x). X = α ^{i + j} to be substituted, that is, x indicating the position of the (j × 16 + i) th bit line is obtained. Similarly, the selector 302 captures e ₂ (α ^j ), and if these are multiplied by a constant by (α ² ) ⁱ times within a range of i = 0 to 15, x ^{2 of the} error position search equation Λ (x). X = α ^{i + j} to be assigned to i.e., x indicating the position of the (j × 16 + i) th bit line is obtained. Similarly, if the selector 303 takes e ₃ (α ^j ) and multiplies them by a constant (α ³ ) ⁱ within a range of i = 0 to 15, the error position search equation Λ (x) x = α ^{i + j} to be substituted for x ³ , that is, x indicating the position of the (j × 16 + i) th bit line is obtained. Similarly, the selector 304 takes in e ₄ (α ^j ) and multiplies them by a constant (α ⁴ ) ⁱ within the range of i = 0 to 15 to obtain the error position search equation Λ (x). x = α ^{i + j} to be substituted for x ⁴ , that is, x indicating the position of the (j × 16 + i) th bit line is obtained.

Therefore, a control signal SEL for switching the selector input is input from the control circuit 16 to each of the selectors 301 to 304. This control signal SEL is a control signal that the control circuit 16 changes from L level to H level, for example, after the address decoder 17 latches the column address when reading data from the nonvolatile semiconductor memory device 10. In the selectors 301 to 304, when the control signal SEL becomes H level, e ₁ x, e ₁ x ² , e ₁ x ³ , e ₁ x ⁴ are fetched in the respective selectors, and the fetched values are the subsequent stages. Is stored in the flip-flops 311 to 314 connected to. The coefficient e ₀ is stored in the flip-flop 310.

In addition, 16 constant multiplication circuits are connected in series in the subsequent stages of the flip-flops 311 to 314, respectively. At the subsequent stage of the flip-flop 311, constant multiplier circuits 321 </ b> _ <b> 1 to 321 </ b> _ <b> 16 that multiply the input value by a constant α and output the result are connected in series. Further, in the subsequent flip-flop 312, a constant multiplier circuit 322_1～322_16 to output multiplied by a constant alpha ² are connected in series to the values entered. Further, in the subsequent flip-flop 313, a constant multiplier circuit 323_1～323_16 to output multiplied by a constant alpha ³ are connected in series to the values entered. Further, in the subsequent flip-flop 314, a constant multiplier circuit 324_1～324_16 to output multiplied by a constant alpha ⁴ are connected in series to the values entered.

The exclusive OR circuit 330_1 calculates an exclusive OR of the outputs of the flip-flops 310 to 314 and outputs the result to the subsequent logic inversion circuit 340_1. The logic inversion circuit 340_1 logically inverts the operation result of the exclusive OR circuit 330_1 and outputs an error detection signal Error <0> to the error correction unit 34. That is, in the exclusive OR circuit 330_1, x = α ^{i + j} (i = 0) is substituted into the error position search equation Λ (x) = e ₄ x ⁴ + e ₃ x ³ + e ₂ x ² + e ₁ x ¹ + e ₀ Sometimes, when the value of Λ (x) is 0, the error detection signal Error <0> becomes H level. On the other hand, when the value of Λ (x) is not 0, the error detection signal Error <0> is at the L level.
In this embodiment, the error correction unit 34 includes 16 exclusive OR operation circuits 34_i (see FIG. 2, i = 0 to 15). Of the exclusive OR operation circuit 34_i, the exclusive OR operation circuit 34_0 includes (j × 16 + 0) of the error detection signal Error <0> and the cell data Cell Data stored in the page buffer 12 in the read operation. The bit at the position of the th bit line is input. That is, the exclusive OR operation circuit 34_0 inverts the logic (0 or 1) of the bit data at the position of the (j × 16 + 0) th bit line if the error detection signal Error <0> is at the H level. And output as 1 bit of the corrected data Corrected Data. On the other hand, if the error detection signal Error <0> is at the L level, the exclusive OR operation circuit 34_0 corrects the logic of the data of the bit at the position of the (j × 16 + 0) th bit line as it is, that is, without correction. It is output as 1 bit of the completed data Corrected Data.

Similarly, assuming that i = 1 to 15, the exclusive OR circuit 330_i calculates the exclusive OR of the outputs of the constant multiplication circuit 321_i, the constant multiplication circuit 322_i, the constant multiplication circuit 323_i, and the constant multiplication circuit 323_i, and To the logic inversion circuit 340_i. The logic inversion circuit 340_i logically inverts the operation result of the exclusive OR circuit 330_i and outputs an error detection signal Error <i> to the error correction unit 34. That is, in the exclusive OR circuit 330_i, the error position search equation Λ (x) = e ₄ x ⁴ + e ₃ x ³ + e ₂ x ² + e ₁ x ¹ + e _{0 is set} to x = α ^{i + j} (i = 1 to 15). When each value is substituted and the value of Λ (x) is 0, the error detection signal Error <i> becomes H level. On the other hand, when the value of Λ (x) is not 0, the error detection signal Error <i> is at the L level.
The exclusive OR operation circuit 34_i in the error correction unit 34 has the error detection signal Error <i> and the cell data Cell Data stored in the page buffer 12 in the read operation, of the (j × 16 + i) th bit line. Position bit is input. In other words, each of the exclusive OR operation circuits 34_i (i = 1 to 15) determines the logic of the bit data at the position of the (j × 16 + i) th bit line if the error detection signal Error <i> is at the H level. Is inverted and output as one bit of the corrected data Corrected Data. On the other hand, if the error detection signal Error <i> is at the L level, the exclusive OR operation circuit 34_0 corrects the logic of the data of the bit at the position of the (j × 16 + i) th bit line without correction. Output as 1 bit of data Corrected Data.

  By the way, in a NAND flash memory that does not include an ECC circuit, data corresponding to one page is read from the memory cell to the page buffer 12 when a single read command, that is, a command for instructing data read is input. . Then, following the first column address, the data stored in the page buffer 12 can be continuously read in synchronization with the read enable signal / RE.

  Even in the nonvolatile semiconductor memory device 10 incorporating the ECC circuit, the following processing is required to enable the same reading. That is, the syndrome calculation unit 31 calculates the syndrome from the data read from the memory cell (data stored in the page buffer 12), and the coefficient calculation unit 32 obtains an error coefficient. Then, as described above, the column address of the selector input in the chain search unit 33 is changed from, for example, the lowest order to check whether the error position search equation Λ (X) becomes zero. According to this check result, if there is an error in the data read from the page buffer 12, the error may be corrected and the corrected data may be output.

However, in a NAND memory that does not incorporate an ECC circuit, there is a mode in which an arbitrary column address is input and accessed. Therefore, in the case where the nonvolatile semiconductor memory device 10 has a mode for accessing by inputting an arbitrary column address, error correction processing of data for one page is performed following data reading from the memory cell to the page buffer. It is necessary to complete the process and store the corrected data after the process.
Since the nonvolatile semiconductor memory device 10 includes a buffer 14 (for example, SRAM; Static Random Access Memory) in addition to the page buffer 12, all the corrected data is written in the buffer 14, and an arbitrary column address is written after the writing. And the corrected data can be output from the I / O pad 15. Alternatively, a method of reading data from the page buffer 12 after the corrected data is written back to the page buffer 12 instead of the buffer 14 by circuit contrivance is also conceivable.

  As described above, in the nonvolatile semiconductor memory device 10 incorporating the ECC circuit, when it is intended to have a mode for accessing by inputting an arbitrary column address, it is necessary to complete the error correction processing of data for one page. There is a long time (hereinafter referred to as “1st Access Overhead”) from when the arbitrary column address is input until the data of the memory cell at that position is read out.

Therefore, in the nonvolatile semiconductor memory device 10, in order to shorten this 1st Access Overhead and to enable random access equivalent to a NAND flash memory not incorporating an ECC circuit, a latch unit 35, an assigned value calculation unit 36, It has.
The latch unit 35 latches the coefficients e ₄ , e ₃ , e ₂ , e ₁ , and e ₀ of the error position search equation for each sector that is a unit of ECC processing for one page. The coefficient latch 35_0 is the coefficient e ₄ , e ₃ , e ₂ , e _{1 of the} error position search equation calculated from the data of sector <0> (512-byte data) and the parity data corresponding to this sector <0>. , and to latch the _{e 0.} Of the column address Y [13: 0] indicating the position of the memory cell holding the data of sector <0>, the upper 2-bit column address Y [13:12] is the column address Y [13:12]. = (0, 0).

The coefficient latch 35_1 also uses coefficients e ₄ , e ₃ , e _{2 of the} error position search equation calculated from the data of sector <1> (also 512-byte data) and the parity data corresponding to this sector <1>. , E ₁ , and e ₀ are latched. Of the column address Y [13: 0] indicating the position of the memory cell holding the data of sector <1>, the upper 2 bits of column address Y [13:12] are equal to column address Y [13:12] = (0, 1). In addition, the coefficient latch 35_2 has coefficients e ₄ , e ₃ , e _{2 of the} error position search equation calculated from the data of sector <2> (also 512-byte data) and the parity data corresponding to this sector <1>. , E ₁ , and e ₀ are latched. Of the column address Y [13: 0] indicating the position of the memory cell holding the data of sector <2>, the upper 2-bit column address Y [13:12] is equal to the column address Y [13:12] = It is represented by (1, 0). Further, the coefficient latch 35_3 has coefficients e ₄ , e ₃ , e _{2 of the} error position search equation calculated from the data of sector <3> (also 512-byte data) and the parity data corresponding to this sector <3>. , E ₁ , and e ₀ are latched. Of the column address Y [13: 0] indicating the position of the memory cell holding the data of sector <3>, the upper 2-bit column address Y [13:12] is equal to the column address Y [13:12] = (1, 1).

FIG. 4 is a diagram illustrating an example of a detailed configuration of the substitution value calculation unit 36.
The substitution value calculation unit 36 includes eight selectors, thirteen multiplication circuits, and two square operation circuits.
As shown in FIG. 4, the eight selectors are selectors 401, 402, 403, 404, 405, 406, 407, and 408. The 13 multiplication circuits are multiplication circuits 411, 412, 413, 414, 421, 422, 431, 441, 442, 461, 462, 463, 464. The two square calculation circuits are square calculation circuits 451 and 452.

Each selector, as j = 4 to 12, is input value and 1 2 ^j-th power of α is selected is one of the values of these by the column address signal Yj, to the subsequent multiplier circuit selected value Output.
2 ^j-th power value of this α is substituted into the above-described error location search equation lambda (x), representing the (2 j ⁺⁵²⁾ th position of the code data. The (2 ^j +52) -th value of the code data represents the position of the (2 ^j +52) -th bit line among the bit lines including the bit line corresponding to the parity bit. The column address signal Yj is 1 bit Y [j] of the column address Y [13: 0].
Each selector selects the value of α to the ^2jth power when the input column address signal Yj is at the H level, that is, when Y [j] = 1. On the other hand, each selector selects 1 when the input column address signal Yj is at L level, that is, when Y [j] = 0.
For example, the upper 10 bits of the column address: Of [13 4], in 1-bit Y [4] is 1, the remaining 9 bits of Y: when [13 5] are all 0, the selector 401 alpha ¹⁶ The other selectors 402 to 408 select “1”. Hereinafter, an example in which x = α ^{(16 + 52)} representing the (2 ⁴ +52) th position of the code data is input to the chain search unit 33 will be described while explaining the connection and operation of other circuits in the substitution value calculation unit 36. To do.

The multiplication circuit 411 is connected to the output terminal of the selector 401 and the output terminal of the selector 402, multiplies the output value of each selector, and outputs the multiplication result to the first input terminal of the subsequent multiplication circuit 421. In the example described above, the multiplication result is alpha ^16, the first input terminal of the multiplier circuit 421 alpha ¹⁶ is input.
The multiplication circuit 412 is connected to the output terminal of the selector 403 and the output terminal of the selector 404, multiplies the output value of each selector, and outputs the multiplication result to the second input terminal of the subsequent multiplication circuit 421. In the above example, the multiplication result is 1, and 1 is input to the second input terminal of the multiplication circuit 421.
The multiplier circuit 413 is connected to the output terminal of the selector 405 and the output terminal of the selector 406, multiplies the output value of each selector, and outputs the multiplication result to the first input terminal of the subsequent multiplier circuit 422. In the above example, the multiplication result is 1, and 1 is input to the first input terminal of the multiplication circuit 422.
The multiplication circuit 414 is connected to the output terminal of the selector 407 and the output terminal of the selector 408, multiplies the output value of each selector, and outputs the multiplication result to the second input terminal of the subsequent multiplication circuit 422. In the above example, the multiplication result is 1, and 1 is input to the second input terminal of the multiplication circuit 422.

The multiplication circuit 421 is connected to the output terminal of the multiplication circuit 411 and the output terminal of the multiplication circuit 412, multiplies the output value of each multiplication circuit, and the multiplication result is applied to the first input terminal of the subsequent multiplication circuit 431. Output. In the example described above, the multiplication result is alpha ^16, the first input terminal of the multiplier circuit 431 alpha ¹⁶ is input.
The multiplier circuit 422 is connected to the output terminal of the multiplier circuit 413 and the output terminal of the multiplier circuit 414, multiplies the output value of each multiplier circuit, and outputs the multiplication result to the second input terminal of the subsequent multiplier circuit 431. Output. In the above example, the multiplication result is 1, and 1 is input to the second input terminal of the multiplication circuit 431.
The multiplier circuit 431 is connected to the output terminal of the multiplier circuit 421 and the output terminal of the multiplier circuit 422, multiplies the output value of each multiplier circuit, and outputs the multiplication result to the first input terminal of the subsequent multiplier circuit 441. Output. In the above example, the multiplication result is α ¹⁶ , and α ¹⁶ is input to the first input terminal of the multiplication circuit 441.

In the multiplication circuit 441, the first input terminal is connected to the output terminal of the multiplication circuit 431, the output value of the multiplication circuit 431 is input, and the fixed value α ⁵² is input to the second input terminal. This α ⁵² is the position of the bit line from which the normal data located next to the parity bit 52 bits is read out of the code data, ie, the cell data Cell Data stored in the page buffer, that is, the column address Y [13: 0. ] = 0 is a value indicating the position of the bit line from which normal data is read.
The multiplication circuit 441 multiplies the output value of the multiplication circuit 431 and α ⁵² , and the multiplication result is input to the subsequent square operation circuit 451, the first input terminal of the multiplication circuit 442, and the first of the multiplication circuit 461. Output to the input terminal. In the above example, the multiplication result is α ^{(16 + 52)} , and the input terminal of the square operation circuit 451, the first input terminal of the multiplication circuit 442, and the first input terminal of the multiplication circuit 461 have α ^{( 16 + 52)} is input.
The square calculation circuit 451 is connected to the output terminal of the multiplication circuit 441, squares the output value of the multiplication circuit 441, and outputs the square result to the input terminal of the subsequent square calculation circuit 452, the second input terminal of the multiplication circuit 442, and The signal is output to the first input terminal of the multiplier circuit 462. In the above example, the square result is α ^{(16 + 52) × 2} , and the input terminal of the square calculation circuit 452, the second input terminal of the multiplication circuit 442, and the first input terminal of the multiplication circuit 462 are α ^{(16 + 52) × 2} is input.

The multiplication circuit 442 is connected to the output terminal of the multiplication circuit 441 and the output terminal of the square calculation circuit 451, multiplies the output values of the multiplication circuit 441 and the square calculation circuit 451, and multiplies the multiplication result by the multiplication circuit 463 in the subsequent stage. Output to the first input terminal. In the above example, the multiplication result is α ^{(16 + 52) × 3} , and α ^{(16 + 52) × 3} is input to the first input terminal of the multiplication circuit 463.
The square calculation circuit 452 is connected to the output terminal of the square calculation circuit 451, squares the output value of the square calculation circuit 451, and outputs the square result to the first input terminal of the subsequent multiplication circuit 464. In the above example, the squared result is α ^{(16 + 52) × 4} , and α ^{(16 + 52) × 4} is input to the first input terminal of the multiplication circuit 464.

The multiplication circuit 461 is connected to the output terminal of the coefficient latch in the latch unit 35 and the output terminal of the multiplication circuit 441. The multiplication circuit 461 multiplies each output value of the coefficient latch and the multiplication circuit 441, and uses the multiplication result as e ₁ x to perform a chain search. To the unit 33. In the example described above, the coefficient latch is a coefficient latch 35_0, the error coefficient ^{e 1} is input to the second input terminal of the multiplier circuit 461, the multiplication result of the multiplication circuit ^{_{461, e 1 (α (16 +}} 52) ). Thus, _{e 1} to the selector 301 of the Chien search section ^{33 (α (16 + 52)} ) , ie as ^{x (α (16 + 52)} ) is input.

The multiplication circuit 462 is connected to the output terminal of the coefficient latch in the latch unit 35 and the output terminal of the square calculation circuit 451, multiplies each output value of the coefficient latch and the square calculation circuit 451, and sets the multiplication result as e ₂ x. Output to the chain search unit 33. In the above example, the coefficient latch is the coefficient latch 35_0, the error coefficient e ₂ is input to the second input terminal of the multiplication circuit 462, and the multiplication result of the multiplication circuit 462 is e ² (α ^{(16 + 52) × 2} ). Thus, e ₂ (α ^{(16 + 52)} ) ² is input to the selector 302 of the chain search unit 33, that is, (α ^{(16 + 52)} ) is input as x.

The multiplication circuit 463 is connected to the output terminal of the coefficient latch in the latch unit 35 and the output terminal of the multiplication circuit 442, multiplies each output value of the coefficient latch and the multiplication circuit 442, and performs a chain search with the multiplication result as e ₃ x. To the unit 33. In the example described above, the coefficient latch a coefficient latch 35_0, the second input terminal of the multiplier circuit 463 is input the error coefficient ^{e 3,} the multiplication result of the multiplication circuit ^{_{463, e 3 (α (16 +}} 52) ^{× 3} ). Accordingly, e ₃ (α ^{(16 + 52)} ) ³ is input to the selector 303 of the chain search unit 33, that is, (α ^{(16 + 52)} ) is input as x.

The multiplication circuit 464 is connected to the output terminal of the coefficient latch in the latch unit 35 and the output terminal of the square calculation circuit 452, and multiplies each output value of the coefficient latch and the square calculation circuit 452, and sets the multiplication result as e ₄ x. Output to the chain search unit 33. In the example described above, the coefficient latch is a coefficient latch 35_0, the error coefficient _{e 4} is input to the second input terminal of the multiplier circuit 463, the multiplication result of the multiplication circuit ^{_{464, e 4 (α (16 +}} 52) ^{× 4} ). Accordingly, e ₄ (α ^{(16 + 52)} ) ⁴ is input to the selector 304 of the chain search unit 33, that is, (α ^{(16 + 52)} ) is input as x.

As described above, the substitution value calculation unit 36 uses the address indicating the position of the data string (column address Y) and the coefficient stored in the latch unit 35 (coefficients e _{1 to} e ₄ of the error position search equation). Then, a substitution value x (x = α ^{(16 + 52) in the} above example) to be substituted into the error position search equation Λ (x) is calculated.
Accordingly, if the error coefficient for each sector is latched in the latch unit 35 based on the data for one page stored in the page buffer 12 and the parity data when data is read from the memory cell, the coefficient and the column Based on the address Y [13: 4], the substitution value x to be substituted into the error position search equation Λ (x) can be obtained.
When the substitution value x is input to the chain search unit 33, as described above, 16 bits worth of the substitution value as an initial value (in the above example, x = α ^{(16 + 52)} , α ^{(17 + 52)} , α ^{(18 + 52 )} ,..., Α ^{(30 + 52)} , 16 bits of α ^{(31 + 52))} , it is checked whether or not the error position search equation Λ (x) becomes zero. Further, the chain search unit 33 outputs error detection signals ERR <0> to ERR (15> according to the check result. The address decoder 17 inputs the column address to the page buffer 12 in the error correction unit 34. Thus, the data of the memory cell at the position indicated by the column address is input, and the error correction unit receives the input data as error data according to the error detection signal output from the chain search unit 33. Is error-corrected, and the corrected data is output as it is if it is not error data.

Next, regarding the nonvolatile semiconductor memory device 10 including the error detection and correction circuit 13 including the latch unit 35 and the substitution value calculation unit 36 described above, the effect relating to the reduction of the delay time (1st Access Overhead) in the ECC processing will be described. This will be described with reference to the drawings. FIG. 5 is a diagram showing a detailed configuration example of the error detection and correction circuit 13a. FIG. 6 is a diagram for explaining a comparison between the error detection / correction circuit 13 and the error detection / correction circuit 13a.
In FIG. 5, the same parts as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted. Unlike the error detection and correction circuit 13 shown in FIG. 2, the error detection and correction circuit 13 a shown in FIG. 5 does not include the latch unit 35 and the substitution value calculation unit 36. The error detection / correction circuit 13a is configured such that the output result of the error correction unit 34 is output to the I / O pad 15 as corrected data Corrected Data via the buffer 14. Is different.

Hereinafter, the 1st Access Overhead in each of the error detection and correction circuit 13 and the error detection and correction circuit 13a will be described with reference to FIG.
In the error detection and correction circuit 13a, the number of bits of decoded data in one sector is a total of 4096 bits (= 512 kbytes) and 52 bits of parity bits (= column address 13 bits × 4). Since it is not realistic to calculate these data collectively because the circuit scale becomes large, the syndrome calculation unit 31 executes the calculation in units of 64 bits.
If the period of the clock signal used as a reference for calculation is 40 ns, the calculation time in each syndrome calculation circuit of the syndrome calculation unit 31 requires the clock number clk to be (4096 + 52) / 64≈65 clk, and 40 ns × 65 clk = 2. 6 μs (μ seconds). Further, in each of the syndrome calculation circuits in the syndrome calculation unit 31, in order to obtain a solution of the quaternary equation (coefficients e ₄ , e ₃ , e ₂ , e ₁ , and e _{0 of the} error position search equation), 40 ns × 20 clk = 0.8 μs. Further, the chain search unit 33 determines whether or not there is an error by batching 16 bits as described above. The calculation time required for this determination is that the number of clocks clk is (4096 + 52) / 16≈260 clk, and 40 ns × 260 clk = 10.4 μs. The error correction unit 34 corrects the input data simultaneously with the determination by the chain search unit 33, that is, using the error detection signal, so that calculation time is not required.

That is, the time required for the ECC processing is 2.6 μs + 0.8 μs + 10.4 μs = 13.8 μs per 512 bytes of one sector by adding the above calculation times.
FIG. 6A shows the ECC in order of sector 0 (Sector <0>), sector 1 (Sector <1>), sector 2 (Sector <2>), and sector 3 (Sector <3>) from time t0. It shows that the process proceeds. The syndrome calculation circuit 31_1 in the syndrome calculation unit 31 requires 2.6 μs for calculation of the syndrome S1 (Partial Syndrome). Then, the error coefficient calculation unit 32 in the next stage requires 0.8 μs to calculate the coefficients e ₄ , e ₃ , e ₂ , e ₁ , and e ₀ of the error position search equation. The chain search unit 33 in the next stage requires 10.4 μs to correct the input data. Note that the time required for writing to the buffer 14 (Data Out to SRAM) is short, and this 10.4 μs. Shall be included.
The above ECC processing is also executed for sector 2, sector 3, and sector 4, and takes 55.2 μs from the start of the ECC processing, and ends at time t1. That is, after inputting an arbitrary column address and reading out the bit data indicating the position of the column address to the outside, it is necessary to wait for a time until the corrected data of all the cells in one page is written in the buffer 14. Not possible. The time until the corrected data of all the cells in one page is written to the buffer 14 is 55.2 μs of 1st Access Overhead, and this time reaches almost twice that of the NAND flash memory not equipped with the ECC circuit. End up.

On the other hand, in the error detection and correction circuit 13, following the reading of the cell data Cell Data from the memory cell to the page buffer 12, each of the syndrome calculation circuits of the syndrome calculation unit 31 based on the data for one page, Sequentially for each sector. Further, the error coefficient calculation unit 32 sequentially performs a calculation for obtaining a solution of the quaternary equation (coefficients e ₄ , e ₃ , e ₂ , e ₁ , and e _{0 of the} error position search equation) for each sector. FIG. 6B shows the syndromes in order from the time t0 for the sector 0 (Sector <0>), the sector 1 (Sector <1>), the sector 2 (Sector <2>), and the sector 3 (Sector <3>). (Partial Syndrome) indicates that calculation processing of coefficients e ₄ , e ₃ , e ₂ , e ₁ , and e ₀ of the error position search equation proceeds. These calculation processes take time of 13.6 μs from the start of the ECC process and end at time t2. The processing time for each calculation is the same as that for the error detection and correction circuit 13a.

At time t2, the coefficients e ₄ , e ₃ , e ₂ , e ₁ , and e ₀ of the error position search equation in sectors 1 to 4 are latched in each of the coefficient latches of the latch unit 35. In other words, if an arbitrary column address is input to the substitution value calculation unit 36 after time t2, the chain search unit 33 can perform an error determination on the bit data indicating the position of the column address. Further, the error correction unit 34 can detect an error in the data of the cell whose position is indicated by the column address, correct it, and output it from the I / O pad 15 to the outside. That is, as compared with the error detection / correction circuit 13a, it is not necessary to write the corrected data of all the cells in one page in the buffer 14, and the 1st Access Overhead can be shortened to 13.6 μs. In FIG. 6B, reading of data to the outside is shown in the order of arrangement of the bit data in the page buffer 12 (column address order), that is, the order of sectors. However, after time t2, random access is possible, and a bit at any position in any sector can be error-corrected and output immediately. That is, as the calculation time required before data output, only the correction coefficient calculation time (the calculation time by the substitution value calculation unit 36 and the chain search unit 33, about 40 ns) is required, which is compared with the error detection and correction circuit 13a. As a result, the 1st Access Overhead can be significantly shortened.

  As described above, the error detection and correction circuit 13 of the present invention includes a data storage unit (page buffer 12) that stores a data string, a syndrome calculation unit 31 that calculates a syndrome from the data string, and a coefficient of an error position search equation from the syndrome. The error position search equation Λ (x (x) is calculated using the error coefficient calculation unit 32 for calculating the data, the latch unit 35 for storing the coefficient, the address (column address) indicating the position of the data string, and the coefficient stored in the latch unit 35 The substitution value calculation unit 36 that calculates the substitution value x to be substituted into () and an error for each bit of the data string according to the substitution result of the substitution value x into the error position search equation Λ (x) when the data string is output. A chain search unit 33 that outputs an error detection signal ERR <i> indicating whether or not there is a bit error, and the error detection signal ERR <i> An error correction unit 34 that corrects and outputs an error.

  The error detection and correction circuit 13 of the present invention includes a latch unit 35 that stores a coefficient of an error position search equation, and a substitution value calculation unit 36 that calculates a substitution value to the error position search equation from the coefficient and the bit position. Provided. For this reason, when an address of a bit to be read (column address) is input to the substitution value calculation unit 36 at the time of reading data, the chain search unit 33 detects whether or not there is an error in the data of the bit. If there is an error in the bit data, the error correction unit 34 corrects the bit data and outputs the corrected bit data. If there is no error, the error correction unit 34 outputs the bit data as it is. Therefore, it is possible to provide an error detection / correction circuit and a memory device that can perform error correction on data of a bit at an arbitrary address in a data string (cell data Cell Data) and read the corrected data at high speed. it can.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes a design and the like within the scope not departing from the gist of the present invention.

  DESCRIPTION OF SYMBOLS 10 ... Nonvolatile semiconductor memory device, 11 ... Memory cell array, 12 ... Page buffer, 13, 13a ... Error detection correction circuit, 14 ... Buffer, 15 ... I / O pad, 16 ... Control circuit, 17 ... Address decoder, 18 ... Row and block decoder, 30... Decoder unit, 31... Syndrome calculation unit, 31_1, 31_2, 31_3, 31_4... Syndrome calculation circuit, 32 .. error coefficient calculation unit, 33 ... chain search unit, 34. , 330_2, 330_15, 330_16 ... exclusive OR operation circuit, 35 ... latch unit, 35_1, 35_2, 35_3, 35_4 ... coefficient latch, 36 ... substitution value calculation unit, 40 ... encoder unit, 41 ... parity generation circuit, 301, 302, 303, 304, 401, 402, 403, 404, 40 , 406, 407, 408... Selector, 321_1, 321_2, 321_16, 322_1, 322_2, 322_16, 323_1, 323_2, 323_16, 324_1, 324_2, 324_16 ... constant multiplication circuit, 310, 311, 312, 313, 314. 340_1, 340_2, 340_15, 340_16 ... logic inversion circuit, 411, 412, 413, 414, 421, 422, 431, 441, 442, 461, 462, 463, 464 ... multiplication circuit, 451, 452 ... square operation circuit

Claims (3)

A data storage unit for storing data strings;
A syndrome calculation unit for calculating a syndrome from the data string;
An error coefficient calculation unit for calculating a coefficient of an error position search equation from the syndrome;
A latch unit for storing the coefficient;
An substitution value calculation unit that calculates an substitution value to be substituted into the error position search equation using an address indicating the position of the data string and a coefficient stored in the latch unit;
A chain search unit for outputting an error detection signal indicating whether or not there is an error for each bit of the data string, according to a result of substitution of the substitution value into the error position search equation when the data string is output;
An error correction unit comprising: an error correction unit that corrects and outputs an error of bit data in the data string by the error detection signal. The data string is composed of a plurality of data strings,
The error detection and correction circuit according to claim 1, wherein the latch unit is provided corresponding to each of the plurality of data strings. A memory device comprising the error detection and correction circuit according to claim 1,
The data storage unit is a circuit for storing a data string read from a storage element,
The memory device, wherein the address is a column address indicating a column position in the memory of the storage element.

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