WO1999016175A1 - Semiconductor integrated circuit and data processing system - Google Patents

Abstract

A semiconductor integrated circuit including a Galois multiplier which enables multiplication using a plurality of different primitive polynominals. The semiconductor integrated circuit (1) includes a Galois multiplier (2) which is used for Galois multiplication of the elements of a Galois field GF(2n). The coefficients (5, 4) of the elements of the Galois field GF(2n) which are the multiplier and the multiplicand and the coefficients (6) of the primitive polynominals are inputted to the Galois multiplier. The coefficients are arithmetically operated for different primitive polynominals with the same hardware to obtain Galois multiplication results. A coefficient setting means (3) which supplies the coefficients of the primitive polynominals of the Galois field GF(2n) is provided. With this constitution, the Galois multiplier can perform multiplication on the Galois field corresponding to the primitive polynominals supplied by the coefficient setting means. The semiconductor integrated circuit, therefore, can be versatilely applied to encoding or decoding of the error correction codes of the different Galois fields which are defined for the different primitive polynominals respectively.

Description

 Description: Semiconductor integrated circuit and data processing system

Technical field

 The present invention relates to a semiconductor integrated circuit including a Galois multiplier used for multiplication on a Galois field, for example, encoding or decoding for error correction using a Read-Solomon code defined using the number of Galois fields. Multiplier used for multiplexing, and recording of CD-R0M (Compact Disc-Read Only Memory), DVD (Digital Video Desc), M0 (Magnet Optics), etc. The present invention relates to a technology effective when applied to error correction processing in a data processing system such as a recorded information reproducing apparatus or information recording / reproducing apparatus for a medium, and a satellite communication terminal apparatus. Background art

 For example, a code word capable of correcting a reading error occurring in a recording medium is used in the recording information reproducing device or the information recording / reproducing device. A codeword can be defined by a special set of numbers called the Galois field and special operations defined with it. Code error correction is performed by data processing using the number of Galois fields and the above operation. The most frequently used codeword is a lead-Solomon code, which is particularly used for an error correction code in a data storage system (data recording system) or a communication system in which errors are easily concentrated in a part. Lead-Solomon codes are defined using the number of Galois fields, and encoding or decoding is performed by operations on the Galois field. For this encoding or decoding processing, addition and multiplication on Galois fields are frequently used.

Here, the set of numbers in the Galois field is defined by a primitive polynomial, and the set of numbers is defined. Multiple types of definitions are possible depending on the underlying polynomial to be defined. At the same time, operations on Galois fields are defined differently depending on the primitive polynomial. At present, different standards are defined for primitive polynomials that define Galois fields used in lead Solomon codes for each medium such as M0 and DVD. Further, in the storage system and communication system, codewords are continuously read or received, and there is a limit to the time allowed for reading or processing of received data including error correction. In other words, processing such as error correction must be performed at high speed without impairing the real-time performance.

 For this reason, conventionally, multipliers on Galois fields used for error correction and the like have been composed of hardware dedicated to primitive polynomials conforming to the standard of the system to which the multipliers are applied.

 However, a Galois multiplier dedicated to a particular primitive polynomial cannot be applied to systems using different primitive polynomials. Therefore, in an information recording / reproducing apparatus that can support both MO and DV with different primitive polynomial standards, Galois multipliers must be separately mounted for each of MO and DVD.

 As examples of documents describing error correction using a lead-Solomon code, see Japanese Patent Application Laid-Open No. 5-268011, IEICE Transactions on Electronics, Information and Communication Engineers A Vo1. J73-A No. 2 PP261- 268 (February 1990) "There is an error correction LSIj for optical disks.

 Here, in order to facilitate understanding of the following description according to the present specification, basic matters regarding the Gabor field and the Galois multiplication will be described in advance.

A Galois field is a Galois field in which a finite number of element sets are free to perform the four arithmetic operations and are in a closed configuration. The field means a set of elements that can freely perform the four arithmetic operations and its calculation rules. In the Galois field, a primitive polynomial is defined. The Galois number is defined. In other words, a set of numbers that satisfies that the primitive polynomial is zero is a Galois field.

 Error correction is performed by performing arithmetic operations on Galois numbers. As shown in Fig. 34 showing the model of the communication system and Fig. 35 showing the model of the storage system, the error correction process uses the error correction code on the transmitting side (recording side) and the receiving side (reproducing side; Error correction decoding. Error correction is achieved by combining code and decoding. The four basic arithmetic operations of the most basic Galois field GF (p) will be described. In the Galois field GF (p), mod p is used for the elements of 0, 1, 2,. Here, mod is an abbreviation for modulo (remainder), and p is a prime number.

 For example, addition and multiplication by the mod p algorithm are performed as usual, and if the result is greater than or equal to P, the remainder can be obtained by dividing by P.

 The subtraction is performed appropriately for elements a and b from 0 to p-1 such that a — b = a — b + p mod P (the remainder of p is 0 even if P is added.) , Calculate as usual, and divide by p to get the remainder.

Division is performed as follows. In the division of mod P, for any element other than 0, there is an element x such that a * x = 1 mod ρ. In this specification, the symbol * means a product. The X means X 2 1 / a: a- ¹ mod p. This X is called the multiplicative inverse of a, and is expressed as a- ¹ . Division by a is the multiplication of a by the multiplicative inverse a- ¹ .

 For example, in the case of addition in the Galois field GF (2) mod2, 1 + 0 = 1 mod2,

1 + 1 = 0 mod2, which can be calculated by exOR (Exclusive OR). In addition, when an example of the multiplication in the Galois field GF (2) mod 2 is shown, 1 · 0 = 0 mod 2 and 1 · 1 = 1 mod2, which can be calculated by AND (logical product).

The Galois field GF (p) is a further development of the Galois field GF (2 ^m ). In the Galois field GF (2), there are two types of elements, 0 and 1, between which the four arithmetic operations are performed. I did it. In the Galois field GF (2 ^m ), on the other hand, there are 2 ^m elements, and the four arithmetic operations can be performed freely between those elements. The 2 ^m elements can be represented by m-dimensional vectors on GF (2) or polynomials of degree m−1 or less on GF (2). The former is called vector display, and the latter is called polynomial display. Since the elements of the Galois field GF (2 ^m ) can be expressed by vectors and polynomials on the Galois field GF (2), GF (2 ^m ) is called an extension field of GF (2). For example, there are 2 ³ = 8 elements in the Galois field GF (2 ³ ) as shown in Fig. 36. The vector representation can be considered as a coefficient of each order in a polynomial.

Then, when mod x ³ + x + 1 is calculated for the elements 0 to xi (i = 0, 1, 2, 3,..) Of the Galois field GF (2 ^m ), the solution is repeated periodically. . The polynomial (x ³ + x + 1) of mod at this time is called a primitive polynomial. This means that any higher-order polynomial, if calculated with mod X ³ + X + 1, will return to the original set as shown in part A of Figure 36 or Figure 39 . For example, if the four arithmetic operations are performed under the conditions in Fig. 36, the operation results will be closed within the original set. For example, it is known that there are two primitive polynomials in the Galois field GF (2 ⁴ ) whose element is 4 bits. It is known that there are 16 primitive polynomials in the 8-bit Galois field GF (2 ⁸ ). The original set differs depending on the primitive polynomial.

The addition between the elements of the Galois field GF (2 ^m ) is defined by the addition of vectors (addition of polynomials). That is, the addition of the vector elements (coefficients of the same order of the polynomial). However, the elements or coefficients are elements of GF (2). The addition may be performed by mod 2 calculation. The same applies to subtraction.

The multiplication between the elements of the Galois field GF (2 ^m ) is usually performed by polynomial multiplication, and when the result is equal to or higher than the highest degree of the primitive polynomial, the result is divided by the primitive polynomial, and the remainder is the result. When a / b is performed on any element a or b other than 0, the division is X (= 1 / b) where b * x = 1. When X is found using the algorithm, the result can be obtained by multiplying by a * x.

Here, an example of addition and multiplication in the Galois field GF (2 ³ ) mod x ³ + x + 1 is shown. If an example of addition is shown in vector display, the addition of the element (0 1 0) and (0 1 1) of GF (2 ³ ) is (0 1 0) + (0 1 1) = (00 1) It is said. 1 + 1 2 0, 1 + 0 2 1 To show an example of addition in polynomial notation, the addition of the element X and x + 1 in GF (2 ³ ) is

x + x + 1 = x ( 1 + 1) are ^{+1 = 1 mod (x 3 +} x + 1).

By way of example of a multiplication by a polynomial, then the original ² and the multiplication of +1 GF (2 ^3), the

X ² * (χ + 1) = χ ³ + χ ² = ( _χ + 1) + χ ² (V χ ³ =-(χ + 1) = χ + 1)

2 χ ² + χ + 1 mod (χ ³ + χ + 1)

It is said. As is clear from the multiplication result, there is no multiplication result having a higher order than the primitive polynomial.

As can be understood from the above description, the addition between the elements of the Galois field GF (2 ^m ) is the addition of the coefficients of the same order of the polynomial, and the coefficients are elements of GF (2). For addition of coefficients of the same order, the calculation of mod 2 may be performed. In the multiplication between the elements of the Galois field GF (2 ^m ), after performing a polynomial multiplication as usual, if the result exceeds the highest order of the primitive polynomial, divide by the primitive polynomial, and the remainder is the result. I just need. The addition of coefficients of the same order in multiplication may be performed by the calculation of mod 2 as described above.

Here, the multiplication between elements will be described in detail by taking a 4-bit Galois field GF (2 ⁴ ) as an example.

As described above, error correction uses a numerical system called the Galois field, and frequently performs operations mainly on multiplication and addition. In this numerical system, four arithmetic operations are defined for a set of numbers, and the number of results of the four arithmetic operations is included in the original set of numbers. There is a feature that you can wear. Here, we describe moths lower number of defined operations 4 bits Bok Galois field GF (2 ^4). In the Galois field, a primitive polynomial is defined, and the Galois number is defined as the root of the primitive polynomial. 4 bits Bok moth lower body GF (2 ⁴⁾ In the following two primitive polynomials exist.

(Equation 1) primitive polynomial ^{1: x 4 + x 1 †} 1

(Equation 2) the primitive polynomial 2: x + x ³ + 1

A set of numbers that satisfies that the above primitive polynomial is a Zeguchi is a Gaguchi field.

The number of Galois fields can be represented by a polynomial as described above, and in the 4-bit Galois field GF (2 ⁴ )

(Equation 3) Xa = a ₃ x ³ + a ₂ x ² + a, x ¹ + a ₀ x °

Can be expressed as However, x ^Q = 1, a _n is expressed as 0 or 1. Addition is

(Equation 4) Xa = a ₃ x ³ + a ₂ x ² + axa ₀ x °

(Equation 5) Xb = b ₃ x ³ + b ₂ x ² + b, x, + b ₀ x °

As

The (Equation 6) Xa + Xb = (a 3 + b 3) x 3 + (a 2 + b 2) x 2 + (a, + b,) x '+ (a 0 ib.) X °. here,

(Equation 7) (a ₃ , a ₂ , a, a ₀ ) = (1, 0, 1, 0)

(Equation 8) (b ₃ , b ₂ , b ,, b ₀ ) 2 (0, 1, 1, 1)

Then, the definition of addition of Galois field to a „and b _n in the above equation is as shown below.

 0 + 0 = 0, 0 + 1 = 1,

 1 + 0 = 1, 1 + 1 = 0

Since it is e x OR of

(Equation 9) Xa + Xb = (1 + 0) x ³ + (0 + 1) x ² + (1 + 1) x ¹ + (0 + 1) x ° = x ³ + x ² + x °

2 x ³ + x ² + 1

Becomes

—On the other hand, multiplication differs from ordinary multiplication in that the result of multiplication differs depending on the primitive polynomial of the Galois field GF (2 ⁴ ).

 The above multiplication of Galois numbers Xa and Xb is

(Equation 10) Xa * Xb = (a ₃ b ₃ ) x ⁶ + (a ₃ b ₂ + a ₂ b ₃ )

x ⁴

+ (a ₃ b. + a ₂ b _l + a ₁ b ₂ + a.b ₃ ) x ³ + (a ₂ b ₀ + a ₁ b ₁ + a ₀ b ₂ ) x ² + (a ^ o + aobj x '+ (a.b.) x °

(See Fig. 29). here,

(a ₃₎ One aa. = (1, 0, 1, 0)

(b ₃ , b ₂ , bb ₀ ) = (0, 1, 1) 1)

Then

(Equation 11) Xa * Xb = (1 * 0) x ⁶ + (1 * 1 + 0 * 0) x ⁵ + (1 * 1 + 0 * 1 + 1 * 0) x ⁴

+ (1 * 1 + 0 * 1 + 1 * 1 + 0 * 0) x ³ + (0 * 1 + 1 * 1 + 0 * 1) x ²

+ (1 * 1 + 0 * 1) x ¹ + (0 * 1) x °

Becomes The definition of the Galois field multiplication of a _n and b _{n in the} above equation is as follows:

 0 * 0 = 0, 0 * 1 = 0,

 1 * 0 = 0, 1 * 1 = 1

Because of A N D

(Equation 12) Xa * Xb = χ ⁵ + χ4 + χ ² + χ ¹

(See Figure 30). Here, when primitive polynomial 1 is adopted, (Equation 13) x ⁴ + x ¹ i 1 = 0 or X ⁴ = x ¹ + 1

Because

(Formula M) Xa * Xb = x ⁴ x ¹ + x ⁴ + x ² + x ¹ Two (x '+ 1) x ¹ † (x ¹ + 1) + x ² + x ¹

= x ² + x '+ x ¹ + 1+ x ² + x ¹

Two x ¹ + 1

Becomes

 On the other hand, when primitive polynomial 2 is adopted,

(Equation 15) x + x ³ + 1 = 0 or X ⁴ = x ³ + 1

Because

(Equation 16) Xa * Xb = x ⁴ x ¹ + x ⁴ + x ² + x ¹

: (X ³ + 1) x ¹ + (x ³ + 1) + x ² + x ¹

= x ⁴ + x ¹ + x ³ + ¹ + x ² + x ¹

= (x ³ + 1) + x ¹ + x ³ + ¹ + x ² + x ¹

Two X ²

Becomes

As described above, the multiplication result differs depending on the primitive polynomial employed. Fig. 37 shows a Galois field for the primitive polynomial 1, and Fig. 38 shows a Galois field for the primitive polynomial 2. In FIGS. 37 and 38, the Galois field GF (2 ⁴ ) is expressed by showing the coefficients of x ³ , X ² , X ¹ , and x ° for each element.

In the 4-bit Galois field GF (2 ⁴ ), there are two types of primitive polynomials, and which primitive polynomial is adopted is arbitrary depending on the system. For this reason, the configuration of the conventional dedicated hard-wired Galois multiplier cannot use the same Galois multiplier in different systems. Conventionally, Galois multipliers had to be redesigned for each system (for each different primitive polynomial). _C Conventional hardwired multipliers replace (Equation 10) with (Equation 13) or (Equation 15). Can be directly transformed by the primitive polynomial of to form logic. When the primitive polynomial of (Equation 13) is used, (Equation 10) becomes as follows.

Xa * Xb two (a ₃ b ₃ ) x ⁶ + (a, b ₂ + a ₂ b ₃ )

x ⁴ + (a ₃ b ₀ + a ₂ b ₁ + a ₁ b ₂ + a ₀ b ₃ ) x ³ + (a ₂ b ₀ + a ₁ b _l + a ₀ b ₂ ) x ² + (a ^ o + aobj xHCaobo) x °

= (a ₃ b ₃ ) x ⁴ x ² + (a ₃ b ₂ + a ₂ b ₃ ) x ⁴ x ¹ + (a ₃ b _l + a ₂ b ₂ + a _l b ₃ ) x ⁴ + (a ₃ b ₀ + a ₂ b ₁ + a ₁ b ₂ + a ₀ b ₃ ) x ³ + (a ₂ b ₀ + a _l b ₁ + a ₀ b ₂ ) x ² + (a ^ o + aobj x ¹ + ( a.b.) x °

= (a ₃ b ₃ ) (x ^l + 1) x ² + (a ₃ b ₂ + a ₂ b ₃ ) (x ¹ + 1) x ¹

+ (a ₃ b _l + a ₂ b ₂ + a ₁ b ₃ ) (, x '+ 1)

+ (a ₃ b ₀ + a ₂ b ₁ + a ₁ b ₂ + a ₀ b ₃ ) x + (a ₂ b ₀ + a ₁ b ₁ + a ₀ b ₂ ) x ²

2 (a ₃ b3 + a ₃ b ₀ + a ₂ b ₁ + a ₁ b ₂ + a ₀ b ₃ ) x ³

+ (a ₃ b ₃ + a ₃ b ₂ + a ₂ b ₃ + a ₂ b. + a ₁ b ₁ + a.b ₂ ) x ²

+ (a ₃ b ₂ + a ₂ b ₃ + a ₃ b _l + a ₂ b ₂ + a _l b3 + a _l b ₀ + a ₀ b ₁ ) x ¹ + (a ₃ b ₁ + a ₂ b ₂ + a _l b ₃ + a ₀ b ₀ ) x °

 The conventional hardwired Galois multiplier employs, for example, a method in which the above equation is directly constituted by a logic circuit. In other words, the dedicated hardware multiplier forms the logic shown in FIG. 31 by the dedicated logic circuit shown in FIG. For this reason, in a system employing another primitive polynomial shown in (Equation 15), it was necessary to redesign a multiplier having another logic configuration. To avoid this, it is conceivable to mount multiple multipliers corresponding to each primitive polynomial on the same hardware, but in this case, the circuit scale increases.

The Galois multiplier can adopt a multiplication method based on a power expression, in addition to the above-described hardwired logical configuration based on the specific primitive polynomial. That is, the expression for the Galois field shown in FIG. 39 can be made the power expression shown in FIG. 40, and the root of the primitive polynomial x ³ + x + 1 is reduced by X = X ¹ ( i = 1~6 a), it can be expressed by the ratio ^1. Multiplication by a power expression is defined as the remainder when the original power number is added to an integer and this is divided by 7 (= 2 ³ _ 1).

For example, the multiplication of the element X ² of GF (2 ³ ) in the above polynomial expression and x + 1 is performed by a power expression.

x ² = HI ² , X +1 2 HI ³

X ² * (X +1) ^{2 2} * ^{3 3} 2 (2 +3) mod 2 1 = 5

Next, the search for polynomial corresponding to FIG. 40 Karahi ^5, X ² + X + 1

((1 1 1)) is obtained in the vector display.

Multiplication in power expression can be easily performed on a desk as described above, but when a circuit is built, it is performed using ROM. For example, FIG. 33 shows an example of a Galois multiplier, which is not publicly known, for performing multiplication in a power expression using a ROM. The vector representation data corresponding to the Galois numbers α ^η and ^m is decoded by the first and second Galois number decoding logic. In the first and second ROMs, exponents (power numbers) n and m of Galois numbers according to the decoding result by the first and second Galois number decoding logic are stored in advance. The exponent is read from the first and second R〇M according to the decoding result. The exponents n and m read from both ROMs are added, and the addition result is encoded by the encoder. The third R receiving the output of the encoder stores the Galois number according to the value of the exponent + n and the vector representation data of ^{m + n in} advance, and the Galois number according to the result of the encoding. The vector representation of am ^{+ n} is output.

The Galois multiplier shown in Fig. 33, which employs the power multiplication method, must have several types of ROMs, so the circuit size of the Galois multiplier becomes large. In addition, when the OM is used, if the primitive polynomial changes, the stored data of R0M may be rewritten accordingly, but as the number of bits N in the Galois field increases, the R〇M capacity becomes 2 ^N times increase, circuit rule There are more and more models. Moreover, when applied to different primitive polynomials,

Rewriting data in ROM requires a relatively long time.

 The present invention has been made in view of the above circumstances, and has a semiconductor integrated circuit including a Galois multiplier that has a smaller circuit size than that using a ROM and enables multiplication using a plurality of different primitive polynomials. To provide. Another object of the present invention is applied to an information recording system, an information communication system, and the like, which can reduce a circuit scale for performing error correction on a plurality of types of information using codewords related to a plurality of different primitive polynomials. To provide a data processing system.

 The above and other objects and novel features of the present invention will become apparent from the following description of the present specification. Disclosure of the invention

A semiconductor integrated circuit according to the present invention includes a Galois multiplier used for Galois multiplication between elements of a Galois field GF ( ²ⁿ ), wherein the Galois multiplier is a Galois field GF (2 ⁿ ), the original coefficient of the Galois field GF (2 ⁿ ), which is the multiplicand, and the coefficient of a primitive polynomial. The same hardware is used for primitive polynomials. The Galois multiplier is provided with coefficient setting means for giving a primitive polynomial coefficient of the Galois field GF ( ²ⁿ ).

 According to this, the Galois multiplier can perform multiplication on the Galois field in accordance with the primitive polynomial given from the coefficient setting means. Therefore, the semiconductor integrated circuit can be generally used for encoding or decoding of an error correction code or the like based on different Galois fields defined for each primitive polynomial.

The coefficient setting means stores the coefficients of the primitive polynomial in a rewritable manner, and It may be storage means such as a register for outputting the stored coefficients of the primitive polynomial to the Galois multiplier. Further, the coefficient setting unit may be a unit such as a ROM that stores a plurality of types of primitive polynomial coefficients and outputs a coefficient selected from the stored coefficients to the Galois multiplier. The Galois multiplier includes a partial product adder and a correction term adder, and the partial product adder performs partial product addition of a multiplier coefficient and a multiplicand coefficient for each partial product of the multiplier and the multiplicand. The correction term adding unit can be configured to perform an operation of correcting the coefficient of the partial product of order n + 1 or more obtained by the partial product adding unit to the coefficient of the partial product of order n or less. The coefficients of the primitive polynomial are set in advance by the coefficient setting means. The correction term addition unit has previously input the coefficients of the primitive polynomial set in advance in such a manner, and can immediately perform the correction operation by inputting the partial product addition result by the partial product addition unit.

 Specifically, the correction term addition unit calculates correction information for correcting the coefficient of the partial product of n + 1 or higher order obtained by the partial product addition unit to the coefficient of the partial product of nth or lower order by using a primitive polynomial. A first logical operation circuit that calculates in advance based on the coefficient; and a second logic operation circuit that obtains, for each coefficient of the n + 1 or higher order partial product obtained by the partial product addition unit, a product of the coefficient and the corresponding correction information. It can be composed of two logical operation circuits and a third logical operation circuit that adds the outputs of the respective second logical operation circuits. This is because, as a method of replacing the higher-order terms with lower-order terms, the calculation of the coefficients of the primitive polynomial is performed in advance independently of the calculation of the coefficients of the multiplier and the multiplicand. Thus, it can be positioned as one basic type of the correction term adder for speeding up the Galois multiplication.

The correction term adder uses a method to reduce the order of the higher-order terms, performing partial product operations of the coefficients of the primitive polynomial and the coefficients of the multiplier and the multiplicand. A configuration in which the order is reduced every time can be adopted. The correction term adder that realizes this is provided with an array of n unit circuits of n-1 columns, the order of the unit circuits in the column direction is from 1 to 2 n-2, and the array of the first column is n The order is 2 n-2, the n-th array in the second column is the order 2 n— 3, and the order is reduced sequentially. The n-th array in the n-th column is the n-th order. . The unit circuit of each column of the array receives, as a common input for each column, a first Galois sum of the output of the uppermost unit circuit of the array of the preceding column and the value of the partial product addition corresponding thereto, and A logical product is generated by receiving the input and a coefficient of a primitive polynomial commonly input to the unit circuits of each column, and a second logical product of the value of the logical product and the output of the unit circuit at the same order position in the preceding column is obtained. It has a function to generate Galois sums and output them. Each of the unit circuits in the first column is supplied with the value of the order 2 n−1, which is the highest order of partial product addition, as the common input, and generates an output without generating the second Galois sum. I do. The unit circuits of the second column and the lower array are used as the common input as the first Galois sum of the output of the uppermost unit circuit of the immediately preceding array and the corresponding partial product addition value. Receives and produces output. Then, the outputs of the n unit circuits in the n_1st column are output as the correction term additions. The Galois sum of the output of the correction term addition and the lower n bits of the partial product addition is used as the multiplication result.

Further, the correction term adder, which further speeds up the arithmetic processing by the correction term adder, includes an array of n unit circuits in n-1 columns, and the order of the unit circuits in the column direction is 1 to 2 n−2. In the array in the first column, the n-th array has the order 2 n—2, and in the array in the second column, the n-th array has the order 2 n— 3. The n-th array has the degree n. Unit circuits of order n + 1 or higher in each column of the array receive the value of the partial product addition at the corresponding bit position as a common input for each array, and are input to this common input and the unit circuit in each column. Generates a product by receiving the signal obtained by decoding the coefficients of the n-bit primitive polynomial And a function of generating and outputting the first Galois sum of the output from the unit circuit at the same order position in the front row and the product, and among the unit circuits of the order n + 1 or more in each column, the array The output of the unit circuit at the uppermost position generates a second Galois sum with the corresponding partial product addition value. A unit circuit of order n or less in each column of the array receives the second Galois sum as a common input, and calculates the common input and a corresponding coefficient of a primitive polynomial input to the unit circuit of each column. In addition to receiving and generating a product, a third Galois sum of the output from the unit circuit at the same order position in the front row and the product is output. The unit circuit in the first column receives the value of the highest order 2 n-1 1 of partial product addition as a common input for the order n + 1 or more and the order n or less and generates an output.The unit circuit in the second column or less In this case, the input common to the order n + 1 or more is the corresponding partial product addition value, and the input common to the order n or less is the corresponding value of the second Galois sum in the unit circuits in the second column and below. You. n — The output of the n unit circuits in the first column is the output of the correction term addition. The Galois sum of the output of the correction term addition and the lower n bits of the partial product addition is used as the multiplication result. Decoding logic that decodes the coefficients of n-bit primitive polynomials simplifies the logic of generating correction information based on partial product addition results of degree n + 1 or more and coefficients of primitive polynomials, and reduces the number of gate series stages. Less.

When handling a limited plurality of primitive polynomials, the correction term adder can be configured by omitting hardware relating to an order whose coefficient is commonly set to zero among a plurality of primitive polynomials. In other words, once the number of bits ^{n of the} Galois field GF (2 ⁿ ) is determined, the primitive polynomials corresponding to it are limited to several types.At this time, in the order where the coefficient is always zero in all primitive polynomials, Hardware can be omitted. This promotes faster arithmetic processing by reducing the number of gate series stages.

The partial product adder calculates the Galois sum of adjacent two bits of the multiplier as n−1 bits. , And further decodes every two consecutive bits of the multiplicand to generate four outputs for every two bits.The number of columns of the partial product is set to 1/2, and each column of the partial product is output. The input of the bit position has four inputs: a bit value of an adjacent multiplier, a Galois sum of two adjacent bits of the multiplier, and zero, and selects an input based on the four outputs decoded as described above. The Galois sum of the selected input and the partial product of the front row can be output to the back row as an output. Even with such a configuration in which partial product addition is performed by the selector method, the number of gate series stages in the signal path can be reduced, and high-speed arithmetic processing is realized.

The data processing system includes a Galois multiplier used for Galois multiplication between elements of a Galois field GF ( ²ⁿ ), and setting means for enabling a primitive polynomial of the Galois multiplier to be reset. In this case, the Galois multiplier, and the original coefficients of the Galois field GF (2 ⁿ⁾ which is the number of multiplication, and the original coefficients of the Galois field GF (2 ⁿ⁾ which is the multiplicand, and a coefficient of a primitive polynomial The input and the calculation of the coefficients for obtaining the Galois multiplication result are performed on the same hardware for a plurality of different primitive polynomials. The coefficients of the primitive polynomial may be provided from the setting means.

 The setting means may be configured to determine a primitive polynomial to be set in accordance with an operation state of a selection switch.

Another data processing system includes a recognizing unit that recognizes the type of the information recording medium, an access unit that can access a plurality of types of information recording media, and a recording unit that reads the recording information read from the information recording medium by the access unit. Error correction circuit used for error correction. In this case, the Galois multiplier is used for Galois multiplication between the original and the original Galois field GF (2 ^n), and the original coefficients of the Galois field GF (2 ⁿ⁾ which is a multiplier, is the multiplicand The original coefficients of the Galois field GF (2 ⁿ ) and the coefficients of the primitive polynomial are input, and the calculation of the coefficients for obtaining the result of the Galois multiplication is the same for a plurality of different primitive polynomials. This is done with one hardware. The primitive polynomial coefficient may be determined according to the result of recognition of the type of the information recording medium by the recognition means. According to this, in a system that handles both M0 and DVD recording media having different primitive polynomials used for defining an error correction code such as a Reed-Solomon code, either of the recording media is used for reproducing the recorded information and for recording the information. The Galois multiplier can also be used in common for the body, which contributes to the miniaturization of the system.

Still another data processing system includes control means for decoding a fetched instruction to generate a control signal, arithmetic means controlled by the control signal, and interface means for interfacing the arithmetic means with the outside. It has. At this time, the arithmetic means includes a Galois multiplier used for Galois multiplication between elements of the Galois field GF (2 ⁿ ), and the Galois multiplier is a Galois field GF (2 ⁿ ), The original coefficient of the Galois field GF (2 ⁿ ), which is the multiplicand, and the coefficient of the primitive polynomial, and the calculation of the coefficient to obtain the Galois multiplication result is performed by a plurality of different primitives. A Galois multiplier that performs the same hardware with respect to the polynomial may be included, and a coefficient of the primitive polynomial may be determined by control of the control unit. This data processing system can be configured as a microprocessor formed on a single semiconductor substrate. BRIEF DESCRIPTION OF THE FIGURES

 Fig. 1 is an explanatory diagram conceptually showing a Galois multiplier that enables multiplication of multiple types of primitive polynomials with the same hardware.

Fig. 2 is an explanatory diagram showing the first calculation example of partial product addition and correction term addition, and Fig. 3 is a Galois multiplier realized by dividing the logic shown in the calculation example of Fig. 2 into a partial product and a correction term. Example logic circuit diagram, Fig. 4 is an explanatory diagram showing a second calculation example of partial product addition and correction term addition, and Fig. 5 is a Galois multiplier that realizes the logic shown in the calculation example of Fig. 4 by dividing it into a partial product and a correction term. Example logic circuit diagram,

 Fig. 6 is an explanatory diagram showing a third calculation example of partial product addition and correction term addition, and Fig. 7 is a Galois multiplier that implements the logic shown in the calculation example of Fig. 6 by dividing it into a partial product and a correction term. Example logic circuit diagram,

FIG. 8 is an explanatory diagram showing a calculation example of a partial product adding a complement Seiko addition in the case of considering that the coefficients C ₂ both primitive polynomial in X ² is zero at the primitive polynomial of the two there quartic ,

 Fig. 9 is an example logic circuit diagram of a Galois multiplier realized by dividing the logic shown in the calculation example of Fig. 8 into partial products and correction terms,

 FIG. 10 is an example logic circuit diagram of a Galois multiplier when the logic of FIGS. 6 and 7 is applied to an 8-bit Galois field,

 FIG. 11 is a logic circuit diagram of an example of a Galois multiplier which is further speeded up from the configuration of FIG. 10,

 Fig. 12 is an explanatory diagram that functionally shows the configuration of a Galois multiplier that performs Galois multiplication by dividing into the partial product addition and the correction term addition specifically shown in Fig. 3, etc., and Fig. 13 is the correction term. Explanatory diagram functionally showing the configuration of a Galois multiplier that decodes the coefficients of a primitive polynomial in an adder in advance and supplies the decoded data to a correction term adder.

 FIG. 14 is an explanatory diagram specifically showing the configurations of the correction term adder and the decoder when the 4-bit circuit configuration of FIG. 7 is expanded to the decoding system of FIG.

 FIG. 15 is an explanatory diagram showing an example of expansion of a correction term using the decoder of FIG. 14,

Fig. 16 shows the case where the decoding method is applied to an 8-bit Galois multiplier. Explanatory diagram specifically showing the configuration of the correction term addition unit and the decoder of

 FIG. 17 is an explanatory diagram showing an example of expansion of a correction term using the decoder of FIG. 16,

 FIG. 18 is an explanatory diagram functionally showing a Galois multiplier in which a decoder is provided for both the input of the partial product addition unit and the input of the correction term addition unit to further speed up the processing;

 FIG. 19 is an explanatory diagram logically showing a configuration based on a selector system for further accelerating the arithmetic processing in the partial product addition unit.

 FIG. 20 is a logic circuit diagram of a partial product adder when the selector method shown in FIG. 19 is applied to a 4-bit Galois multiplier.

 FIG. 21 is a circuit diagram of an example of a first selector applied to the partial product adder of FIG. 20,

 FIG. 22 is a circuit diagram of an example of a second selector applied to the partial product adder of FIG. 20,

 FIG. 23 is a logic circuit diagram of the partial product adder when the selector system of FIGS. 19 and 20 is extended to an 8-bit Galois multiplier,

 FIG. 24 is a flow chart showing an example of the read'Solomon error correction decoding process, and FIG. 25 is a schematic diagram showing the internal configuration of each of the circuits for the sindom operation, the leak operation and the Chien search. Block diagram shown,

 FIG. 26 is a block diagram of a processor for performing the read 'Solomon error correction decoding process shown in FIG. 24,

 Fig. 27 is a block diagram of an example of a data processing system that records or reproduces information on storage media such as DVDs.

 Figure 28 is an example block diagram of a data processing system used for communication systems such as satellite broadcasting.

FIG. 29 is an explanatory diagram showing an example of multiplication calculation of a Galois number represented by a polynomial expression. FIG. 30 is an explanatory diagram showing a calculation example when a numerical value is inserted in the coefficient of each order of the multiplier and the multiplicand and the Galois number is multiplied,

FIG. 31 is an explanatory diagram showing an example of multiplication calculation when the primitive polynomial is X ⁴ = X ¹ +1.

3 Fig. 2 logic circuit diagram of an example of a logical configuration of moths lower multiplying circuits dedicated hardware when primitive polynomial is X ⁴ = X ¹ + ^1,

 FIG. 33 is a block diagram showing an example of a Galois multiplier circuit based on the R0M method.

 Fig. 34 is an explanatory diagram of a communication system model that employs Galois field error correction.

 Fig. 35 is an explanatory diagram of a storage model that adopts error correction by Galois field,

FIG. 36 is an explanatory diagram showing elements of the Galois field GF (2 ³ ),

Fig. 37 is an explanatory diagram showing the elements of the Galois field GF (2 ⁴ ) in the case of the primitive polynomial X ⁴ + X ¹ + 1,

Fig. 38 is an explanatory diagram showing the elements of the Galois field GF (2 ⁴ ) in the case of the primitive polynomial X ⁴ + X ³ + 1,

3 9 FIG Galois field GF; explanatory view showing an example of a base click Bokuru representation and polynomial representation of the original, (2 ⁴⁾

4 0 is an explanatory diagram showing an example of a polynomial representation preparative base key representation of the original Galois field GF (2 ^4). BEST MODE FOR CARRYING OUT THE INVENTION

 << Semiconductor integrated circuit including general-purpose Galois multiplier >>

FIG. 1 shows an example of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 1 shown in FIG. 1 includes a Galois multiplier 2 and a coefficient It includes the setting means 3 and is formed on one semiconductor substrate such as single crystal silicon, for example, by a known CMOS integrated circuit manufacturing technique.

The Galois multiplier 2 and the coefficient setting means 3 are used for Galois multiplication between elements of the Galois field GF ( ²ⁿ ). The Galois multiplier 2, and the original coefficients of the Galois field GF that is a multiplier (2 ⁿ⁾ (n bits) 4, the original coefficients of the multiplicand and is Ru Galois field GF (2 ⁿ⁾ (n bits) 5 and the coefficient (n bits) 6 of the primitive polynomial are input, and the operation of the coefficient for obtaining the Galois multiplication result is performed for a plurality of different primitive polynomials with the same hardware. The coefficient setting means 3 is a circuit that provides the Galois multiplier 2 with the coefficients of the primitive polynomial of the Galois field GF (2 ".

 The coefficient setting unit 3 may be a storage unit such as a register that stores the coefficients of the primitive polynomial in a rewritable manner and outputs the stored coefficients of the primitive polynomial to the Galois multiplier 2. Further, the coefficient setting means 3 may be a means such as a ROM which stores a plurality of types of primitive polynomial coefficients and outputs a coefficient selected from the stored coefficients to the Galois multiplier 2. The coefficient setting of the primitive polynomial or the coefficient selection of the primitive polynomial for the coefficient setting means 3 can be given from inside the semiconductor integrated circuit 1 via a signal line 7 or from outside the semiconductor integrated circuit via a signal line 8.

 According to the semiconductor integrated circuit 1, the Galois multiplier 2 can perform multiplication on the Galois field according to the coefficients of the primitive polynomial given from the coefficient setting means 3. Therefore, the semiconductor integrated circuit 1 can be generally used for encoding or decoding of an error correction code or the like using a different Galois field defined for each primitive polynomial. Even when the semiconductor integrated circuit 1 is applied to a system for, for example, MO or DVD, it is not necessary to redesign the Galois multiplier.

For example, information recording and recorded information reproduction for both M0 and DVD Even when the semiconductor integrated circuit 1 is applied to a data processing system to be performed, the single semiconductor integrated circuit 1 can be used for encoding and decoding error correction codes for both M0 and DVD. For example, assuming a data processing system that requires Galois multipliers using N types of primitive polynomials, individual Galois multipliers using hardwired logic as dedicated hardware individually corresponding to each primitive polynomial When the data processing system is configured using the semiconductor integrated circuit 1, the circuit size of the Galois multiplier required for the entire system is about 1 unit for the former. / N, and the more primitive polynomials that need to be supported, the greater the effect of circuit scale reduction. 《First example of Galois multiplier》

As shown in (Equation 10) to (Equation 16) of the above multiplication, in the multiplication of the n-bit GaP number, the higher the order of (n + 1) bits, the higher the primitive polynomial. The order can be reduced in order from the next term to get the final result. For example, in order to enable multiplication of all primitive polynomials in the Galois field GF (2 ⁴ ), the primitive polynomials in (Equation 13) and (Equation 15) need to be expressed in a general form. This is shown in (Equation 17).

(Equation 17) X ⁴ 2 C ₃ X + C ₂ X ² + CTX ¹ † C ₀ X °

4 bits Bok Galois number Xa (Equation 4) and Xb state that organizes polynomial multiplication result against the (Equation 5) for each degree of Galois field GF (2 ⁴⁾ is shown in the column of partial product addition of the second view Have been. As is clear from the description of the partial product addition column, in the polynomial multiplication, since the orders X ⁶ , x ⁵ , and X ⁴ are higher-order terms, the higher-order terms are calculated using (Equation 17). When the order of is reduced, it becomes as shown in (Equation) to (Equation 20).

(Equation 18) X ⁶ = X ⁴ X ² = (c ₃ x ³ + c ₂ x ² + c ^ ¹ † c. X.) X ²

^{_{= C 3 X 5 + C 2}} X +. ³ + C ₀ X ' = C ₃ (C ₃ X ³ + C ₂ X ² + CTX ¹ + C ₀ X °) X ¹

+ C ₂ (C ₃ X ³ + C ₂ X ² + CTX ¹ † C ₀ X °) + CTX ³ † C ₀ X ²

Two C ₃ (C ₃ X + C ₂ X ³ + C, X ² + CQX ¹ )

+ C ₂ (C ₃ X ^J + C ₂ X ² + CTX ¹ + C ₀ X °) + C, X ³ + C ₀ X ²

Two _{C 3 (C 3 (C 3} X 3 + C 2 X 2 + C] + C 0 X °) + C 2 X 3 + CTX 2 + C 0 X ') + c 2 (c 3 x 3 + C 2 X ² + c, x ¹ + cx.) + C, x ³ + C ₀ X ²

one

+ c ₂ c ₃ x ³ + C ₂ X ² + C ^ TX ¹ † C ₂ C ₀ X ° + CTXH C ₀ X ²

= (c ₃ + cj x ³ + (c ₂ + C ₀ + 0 ₃ 0, + C ₃ C ₂ ) X ² + (c ₃ c ₀ + ₃ C ^ ₂ C ^) X ¹

+ (c ₂ c ₀ + C ₃ C ₀ ) x °

(Equation 19) X ⁵ = X ⁴ X ¹ = (C ₃ X ³ + C ₂ X ² + CQX ^ X ¹

2 C ₃ X ⁴ + C ₂ X ³ + C, X ² + CQX ¹

= c ₃ (c ₃ x ³ + c ₂ x ² + c, x ¹ + c ₀ x °) + c ₂ x ³ + c, x ² + C ₀ X ¹

= C ₃ X ³ + C ₃ C ₂ X ² + CgC! X ¹ † c ₃ cx ° + C ₂ X ³ + c, x ² + C ₀ X ¹ two (c ₃ + c ₂ ) x ^J + (c + c ₃ c ₂ ) x ² + (c ₀ + C ₃ C!) x ¹ + C ₃ C ₀ x ° (Equation 20) x ⁴ = c ₃ x ³ + c ₂ x ² + cx ¹ + c ₀ x °

 By substituting (Equation 17) to (Equation 20) into (Equation 10), (Equation 21) is obtained.

(Equation 21) Xa * Xb = (a 3 b 3) ((c 3 + c) x 3 + (c 2 + c + c i c + c 3 c 2) x 2

+ (C ₃ C ₀ + 0 ₃ 0! + CjC,) x ¹ + (c ₂ c ₀ + C ₃ C ₀ ) x °)

+ (a ₃ b ₂ + a ₂ b ₃ ) ((c ₃ + c ₂ ) x ° + (c, + c ₃ c ₂ ) x ² + (c ₀ + CgC,) x, + c ₃ c ₀ x °) + (a ₃ b ₁ + a ₂ b ₂ + a ₁ b ₃ ) (c ₃ x ³ + c ₂ x ² + ο, χ ^ c ₀ x °)

+ (a ₃ b _o + a ₂ b, + a ₁ b ₂ + a ₀ b ₃ ) x ³ + (a ₂ b ₀ + a _l b ₁ + a _o b ₂ ) x ²

+ (a ^ o + aob x ¹ + (a ₀ b ₀ ) x °

The meaning of the above (Equation 21) will be clear from the above, but it is further added that Using the general form of the primitive polynomial of (Equation 17), the higher-order terms x ⁶ , X ⁵ , and X ⁴ of the partial product obtained by the equation multiplication are calculated using the lower-order terms X ³ , X ² , It is replaced with X ¹ and X ⁰ . The calculation formula shown in the column of correction term addition in FIG. 2 is a formula in which the higher-order terms X ⁶ , x ⁵ , and X ⁴ are replaced with lower-order terms X ³ , x ² , x ¹ , and x °. is there. Correction term added to operations for such replacement, the correction term was collected using cowpea in addition low-order sections ^{x 3, x 2, X 1} , x ° is referred to as a correction term. As exemplified in the column of partial product addition in FIG. 2, a polynomial multiplication of two Galois numbers is called partial product addition, and each term obtained by that is called a partial product.

As can be understood from the description of the above (Equation 21), in order to multiply the Galois number for general purpose, the coefficient c of the primitive polynomial of (Equation 21) is used. In ~ c _3, by setting the coefficient of the necessary primitive polynomial multiplication result for any primitive polynomial is obtained, et al. Alternatively, a value that is a coefficient of each order of (Equation 21) is set in advance c. Leave obtained by logical operation between ~ c _3, Ri by the setting these values, the multiplication result for any primitive polynomial is obtained.

The multiplications performed in (Equation 14) and (Equation 16) will be applied to (Equation 21). Multiplier: coefficients _{(X a) (a 3,} a 2, a ,, a 0) = (1, 0, 1, 0), the multiplicand (: X b) the coefficient of (b _3, b _2, bb ₀ ) = (0, 1, 1, 1),

The primitive polynomial 1: coefficients of ^{(x 4 + x 1 + 1} = 0) is made to correspond to one般形of the equation (17),

(c ₃ , c ₂ c, c ₀ ) = (0, 0, 1, 1),

Therefore, if the above coefficients are substituted into the above (Equation 21), the multiplication is as follows.

Xa * Xb = (1 * 0) ((0 +0) χ ³ + (0 + 1 + 0 + 0) χ ² + (0 + 0 + 0) χ ¹ + (0 + 0) χ °)

+ (1 * 1 + 0 * 0) ((0 + 0) χ ³ + (1 +0) χ ² + (1 + 0) χ ¹ + 0χ °)

+ (1 * 1 + 0 * 1 + 1 * 0) (0χ ³ + 0χ ² + 1χ ¹ + 1χ °) + (1 * 1 + 0 * 1 + 1 * 1 + 0 * 0) x ³ + (0 * 1 + 1 * 1 + 0 * 1) x ^z

+ (1 * 1 + 0 * 1) x ¹ + (0 * 1) x °

Two x ¹ + 1

With the same multiplier (: X a) and multiplicand (: X b) as above, the coefficients (c ₃ , c ₂ , c ,, c ₀ ) of primitive polynomial 2 (: x ⁴ + x ³ + 1 = ₀ ) Applying (Equation 21) to = (1, 0, 0, 1) and substituting each coefficient into (Equation 21), the multiplication is as follows.

Xa * Xb 2 (1 * 0) ((1 + 0) x ³ + (0 + 1 +0 + 0) x ² + (1 +0 + 0) x ¹ + (0 + 1) x °)

+ (1 氺 1 + 0 * 0) ((1 + 0) x ³ + (0 +0) x ² + (1 + 0) xH 1x °) + (1 * 1 + 0 * 1 + 1 * 0) (IxHOx Ox ^ lx ⁰ )

+ (1 氺 1 + 0 * 1 + 1 氺 1 + 0 * 0) x ³ + (0 * 1 + 1 氺 1 + 0 氺 1) x ² + (1 * 1 + 0 * 1) x ^ CO * 1) x °

: X ²

This shows that the same results as (Equation 14) and (Equation 16) can be obtained.

FIG. 3 shows a specific example of the Galois multiplier 2 having the logic according to the above method. The Galois multiplier 2 includes a partial product adder 11, a correction term adder 12, and an output adder 13. The partial product adder 11 performs partial product addition of a multiplier coefficient and a multiplicand coefficient for each partial product of the Galois field GF (2 ⁿ ) and the multiplicand. Specifically, the logic shown in the column of partial product addition in FIG. 2 is realized as it is. The correction term addition unit 12 performs an operation of correcting the coefficient of the π + 1 or higher order partial product obtained by the partial product addition unit 11 into the coefficient of the nth order or lower partial product. Specifically, the logic shown in the column of correction term addition in FIG. 2 is realized as it is. The output adder 13 is a Galois sum of the output of the correction term adder 12 and the lower n-bit partial product coefficient of the partial product adder 11 (similar to the addition process for a 2-bit Galois field) To Calculate. Specifically, the outputs ο _{0 to} ο ₃ are obtained by adding the coefficients of the corresponding orders by exclusive OR.

As described above, the multiplication between the elements of the Galois field GF (2 ⁿ ) is defined by addition of a polynomial, and the coefficients of the polynomial are elements of GF (2). Since the calculation can be performed, the partial product addition unit 11, the correction term addition unit 12, and the addition output unit 13 are configured by using an AND gate and an exclusive OR gate (ex OR). ing.

In FIG. 3, the correction term adding section 12 can be classified into first to third logical operation circuits. The first logical operation circuit converts the correction information for correcting the coefficient of the partial product of order n + 1 or higher obtained by the partial product adder 11 into the coefficient of the partial product of order n or less into the coefficient c of the primitive polynomial. _{3 to} c. This is a logic circuit that calculates in advance on the basis of, and is composed of gate rows 12G and 12E. The second logic operation circuit is a logic circuit that takes, for each coefficient of the n + 1 or higher-order partial product obtained by the partial product addition unit 11, a product of the coefficient and the corresponding correction information, It is composed of gate rows 12B, 12D, and 12F. The third logical operation circuit is a logical circuit for adding the outputs of the respective second logical operation circuits, and is constituted by gate arrays 12A and 12C.

According to this configuration, the output of the first logical operation circuit constituted by the gate trains 12 G and 12 E has the coefficients C ₃ to C of the primitive polynomial. , The result of the correction term addition operation can be immediately obtained by inputting the result of the partial product addition by the partial product addition unit.

The number of gates used in the configuration of Fig. 3 is 25 for the partial product adder 11, 11 for the correction term adder 12, and 4 for the output adder 13. 64 AND elements and exOR are required. In Fig. 3, the circled numbers indicate the signal transmission of each of eXOR and the AND element. When the interval is set to 1, it means the required transmission time from the input to the point marked with the number. The critical path is a path for obtaining the output bit Bok o _3. The outputs of the first logical operation circuit composed of the gate arrays 12 G and 12 E are the primitive polynomial coefficients C ₃ to C ₃ . , The transmission time until the output of the gate train 12F is determined is set to ②.

 《Second example of Galois multiplier》

 If the regularity of the logic of the correction term addition in the Galois multiplier 2 increases, the layout of the logic gates for constructing the logic becomes simple. In addition, if the number of gate series stages is reduced, the arithmetic processing of correction and addition can be sped up.

Another example of the correction term adding unit will be described. A description will be given of a logical configuration in which the operations of the correction terms are regularly performed in the operations of (Equation 18) to (Equation 20). Here, the 4-bit Galois number as described above is taken as an example. (Equation 22) to (Equation 24) show other expansions for replacing higher-order terms of X ⁶ , X ⁵ , and X ⁴ with lower-order terms.

(Equation 22) X ⁶ = X ⁴ X ² (c ₃ x ³ + c ₂ x ² + c, x ¹ + c ₀ x °) x ²

^{_{= C 3 X 5 + C 2}} X 4 + C, X 3 + C 0 X '

= c ₃ (c ₃ x ⁴ + c ₂ x ³ + c, x ² + c ₀ x ¹ ) + c ₂ x ⁴ + c, x ^d + C ₀ X ²

_{: (C 3 + C 2)} X 4 + C 3 (C 2 X 3 + CTX 2 + CQX 1) + c, x 3 + C 0 X 2 two _{(c 3 + c 2) (} c 3 x 3 + c ₂ x ² + c ^ x ^] + c ₀ x °)

+ c ₃ (c ₂ x ³ + c, x ² + C ₀ X ¹ ) + ο, χ ³ + C ₀ X ²

(Equation 23) ^{δ δ} = x ⁴ x ¹ = (c ₃ x ³ + c ₂ x ² + c, x ¹ + c ₀ x °) x ¹

= c ₃ x ⁴ + c ₂ x ³ + c, x ² + c ₀ x ¹

= C ₃ (C ₃ X ³ + C ₂ X ² + C, X ¹ + C ₀ X °) + C ₂ X ³ + C, X ² + CQX ¹ (Equation 24) x ⁴ : c ₃ x ³ + c ₂ x ² + c, x ¹ + c ₀ x °

Substituting the above (Equation 22) to (Equation 24) into the above (Equation 10) and rearranging, 4 The calculation formula shown in the column for adding correction terms in the figure can be obtained. This is an expression in which the higher-order terms X ⁶ , X ⁵ , and X ⁴ are replaced with lower-order terms X ³ , X ² , x ¹ , and x °, as described above.

 FIG. 5 shows a correction term adder 14 that realizes the logic described in the column of correction term addition in FIG. As is apparent from the logical configuration of the correction term adding unit 14, the arrangement of the exclusive OR gate and the AND gate is more regular than that in FIG. Therefore, the layout design of the semiconductor integrated circuit in FIG. 5 can be easier than that in FIG.

 In the correction term adding unit 14 in FIG. 5, the first logic circuit is constituted by gate rows 14G and 14E. The second logical operation circuit is constituted by gate rows 14B, 14D, and 14F. The third logical operation circuit is constituted by gate rows 14A and 14C.

The number of gates used in the configuration of FIG. 5 is the same as that of FIG. 3 for the partial product adder 11 and the output adder 13, but the correction term adder 12 has 39 In this case, 68 AND elements and exOR are required as a whole. In Fig. 5, the circled numbers indicate the required transmission time from the input to the point where the number is given, assuming that the signal transmission time of each of eXOR and the AD element is 1. means. Critical paths are the paths for output bit Bok o _3. Therefore, the Galois multiplier shown in FIG. 5 is not substantially different from the configuration in FIG. 3 in terms of the operation speed, but is superior in the layout of the correction term adder 14 as described above. I have.

 《Third example of Galois multiplier》

The two examples of the Galois multiplier are based on a method of replacing the higher-order terms X ⁶ , χ ⁵ , and X ⁴ with lower-order terms x ³ , x ² , x ¹ , and x ° as coefficients of a primitive polynomial c _n The calculation of the multiplier and the multiplicand coefficients _an and b _n I did it. Here, as a method of lowering the order of the higher-order terms X ³ , X ² , x ¹ , and x °, the coefficients c _n and the multiplier of the primitive polynomial and the coefficients a _n and b _n of the multiplicand are calculated successively. Explain the configuration to reduce the order for each order o

When the order of each of the terms X ⁶ , x ⁵ , and X ⁴ in (Equation 18) to (Equation 20) is reduced by one,

(Equation 25) x ⁶ = c ₃ x ⁵ + c ₂ x ^, + c, x ³ + c ₀ x ²

(Equation 26) x ⁵ 2 c ₃ x ⁴ + c ₂ x ³ + c, x ² + c ₀ x ¹

(Equation 27) x ⁴ = c ₃ x ³ + c ₂ x ² + c, x ¹ + c ₀ x °

Becomes Substituting these into (Equation 10) above and sequentially reducing the order, (Equation 28) Xa * Xb = (a ₃ b ₃ ) (c ₃ x ⁵ + c ₂ x ⁴ + c, x ³ + c ₀ x ² )

+ (a ₃ b ₂ + a ₂ b ₃ ) x ⁵

+ (a ₃ b _l + a ₂ b ₂ + a ₁ b ₃ ) x ⁴

+ (a ₃ b ₀ + a ₂ b _l + a ₁ b ₂ + a ₀ b ₃ ) x ³ + (a ₂ b ₀ + a ₁ b _l + a ₀ b ₂ ) x ² + (a + aobJ x ¹ + (a.b.) x °

Two _{((a 3 b 3) c} 3 + (a 3 b 2 + a 2 b 3)) (c 3 x 4 + c 2 x 3 + c, x 2 + c.x,) + (a 3 b 3 ) (c ₂ x ⁴ + c, x ³ + c. x ² )

+ (a ₃ b ₁ + a ₂ b ₂ + a ₁ b ₃ ) x ⁴

+ (a ₃ b ₀ + a ₂ b ₁ + a ₁ b ₂ + a ₀ b ₃ ) x ³ + (a ₂ b ₀ + a _l b ₁ + a ₀ b ₂ ) x ² + (a ^ o + aob !) x ¹ + (a ₀ b ₀ ) x °

= (((a ₃ b ₃ ) c ₃ + (a ₃ b ₂ + a ₂ b ₃ )) c ₃ + (a ₃ b ₃ ) C2

+ (a ₃ b _l + a ₂ b ₂ + a ₁ b ₃ )) x ⁴

+ ((a ₃ b ₃ ) c ₃ + (a ₃ b ₂ + a ₂ b ₃ )) (c ₂ x ³ + c, x ² + c.x ¹ ) + (a ₃ b ₃ ) (c, x ³ + c ₀ x ² )

_{+ (A 3 b 0 + a} 2 b 1 + a l b 2 + a o b 3) x 3 + (a 2 b 0 + a l b 1 + a 0 b 2) x 2 + (a ^ o + aob x ¹ + (a ₀ b ₀ ) x ° Two (((a ₃ b ₃ ) c ₃ + (a ₃ b ₂ + a ₂ b ₃ )) c ₃ + (a ₃ b ₃ ) c ₂

+ (a ₃ b ₁ + a ₂ b ₂ + a _l b ₃ )) (c ₃ x ³ + c ₂ x ² + c, x ¹ + c ₀ x °) + ((a ₃ b ₃ ) c ₃ + (a ₃ b ₂ + a ₂ b ₃ )) (c ₂ x ³ + c, x ² + c.x ¹ ) + (a ₃ b ₃ ) (c, x ³ + c.x ² )

+ (a ₃ b ₀ + a ₂ b ₁ + a ₁ b ₂ + a ₀ b ₃ ) x ³

+ (a ₂ b ₀ + a ₁ b ₁ + a ₀ b ₂ ) x ²

+ (a ^ o + aob!) x ¹ + (a ₀ b ₀ ) x °

Becomes By rearranging the contents of the above equation, the contents are as described in the column for adding correction terms in Fig. 6. If this logic is realized by a logic circuit, the correction term adding unit 15 in FIG. 7 can be realized.

That is, in FIG. 7, an example is shown in which the correction term adder 15 is applied to Galois field multiplication with respect to the Galois field GF (2 ⁿ ), particularly the 4-bit Galois number when _n = 4. Explaining this, the correction term adder 15 has an array of n (= 4) unit circuits 15 A in n−1 (= 3) columns, and the column-wise unit circuit 15 A The order is from 1 to 2 n— 2 (= 6), the array in the first column is n (= 4), the order is 2 n-2 (= 6), and the array in the second column is n ( = 4) -th order is 2 n-3 (= 5), and the array of the n- 1 (= 3) -th column is sequentially reduced in order. ). The unit circuit in each column of the array is an exclusive OR gate (e X) of the output of the uppermost unit circuit of the array in the preceding column and the corresponding partial product addition value as a common input for each column. 0 R) Receives the Galois sum of 15 B, and this common input and n (= 4) bits of the primitive polynomial coefficients C _{3 to} C that are commonly input to the unit circuits of each column. In response to this, an AND gate is generated by the AND gate 15 C, and an exclusive OR gate (eXOR) 1 of the value of the AND and the output of the unit circuit at the same order position in the front row is generated. It has a function to generate Galois sum by 5D and output it. The unit circuits in the first column have the common input The exclusive OR gate (exclusive OR circuit) 15D to which the value of the order 2 n−1 (= 7), which is the highest order of the partial product addition, is input. The unit circuits of the second column and lower arrays are the exclusive OR of the output of the uppermost unit circuit of the immediately preceding array and the corresponding partial product addition value as the common input. Gate (ex OR) Generates output by receiving Galois sum by 15B. The lowest unit circuit of each array does not have the exclusive OR gate 15D. The correction term adder 15 configured in this way uses the outputs of the n (2 4) unit circuits in the n-1 (= 3) column as the output of the correction term addition, and outputs the output of the correction term addition and Obtain the Galois sum with the lower n (2 4) bits of the partial product addition and obtain the multiplication result.

 As is clear from the logical configuration of the correction term adder 15, the arrangement of the exclusive OR gate and the AND gate is much more regular than in FIG. Therefore, the layout design of the semiconductor integrated circuit in FIG. 7 can be easier than that in FIG.

In the configuration of FIG. 7, the partial product adder 11 and the output adder 13 are the same as those in FIG. 5. The force correction term adder 15 is composed of 20 gates. This is realized by 49 AND elements and exOR. Also, in FIG. 7, the numbers enclosed by circles are, as described above, the distance from the input to the point where the number is attached when the signal transmission time of each of the eXOR and the AND element is set to 1. Means the required transmission time. The critical path is a path for obtaining the output bit Bok o _3, that time has become <length than the fifth FIG. Therefore, the Galois multiplier shown in FIG. 7 is inferior to the configuration of FIG. 5 in terms of operation speed, but is much better in terms of the layout of the correction term adder 15.

 《Fourth example of Galois multiplier》

The Galois multipliers described so far are based on the number of bits in the multiplier and multiplicand. The logic was constructed using the general formula as shown in the above (Equation 17) which does not limit the primitive polynomial at all. However, for example, from a primitive polynomial of 4 bits Bok Gallo § body GF (2 ⁴⁾ are known to be two types, there is a waste in the logical structure of the primitive polynomial and complete formula. Therefore, if the primitive polynomial is limited to the extent that it can be used, some order coefficients may always be zero, which may make the hardware of the correction term adder for those coefficients inefficient. It can be partially omitted, and it becomes possible to configure a Gaa multiplier with a small logical scale. In the example of 4-bit Bok moth lower numbers described so far, examples of the primitive polynomial (Equation 13), (Equation 15) There is, coefficients c ₂ of degree X ² even when dealing with both primitive polynomial is zero is there. Was but connexion, for example, logic associated with the correction term addition or c ₂ correction term addition section 1 5 in FIG. 6 and FIG. 7 is substantially unnecessary.

The FIG. 8, in the general form of the primitive polynomial (Equation 17), when assuming a case coefficients c ₂ of degree X ² is zero, the logic of the correction term addition portion of the auxiliary Seiko addition field Is shown in FIG. 9 shows a configuration of the correction term adder 16 that realizes the logic.

With such a configuration, the logical scale of the correction term adding unit 16 is reduced, the number of gate serial stages is reduced, and both simplification of the layout and enhancement of the arithmetic processing speed can be promoted. FIG. 9 shows, as an example, a structure obtained by further developing the configuration of FIG. 7, but also for the configurations of FIGS. 2 and 3, and FIGS. 4 and 5, c It is possible to omit the logic related to ₂ and make the same improvement as above.

 《Fifth example of Galois multiplier》

FIG. 10 shows an example of a Galois multiplier in which the logical configuration of FIGS. 6 and 7 is extended to multiplication of an 8-bit Galois number. In the example of Fig. 10, the partial product adder 11X and the correction term adder 15X both use the same unit circuit 19. Have been. As shown in FIG. 10, the unit circuit 19 is an AND gate 17 which takes a logical product of the inputs P and A, and an exclusive logic is provided for the output of the AND gate and the input B. Exclusive OR gate 18 for taking the sum. GD is the ground potential of the circuit and supplies a signal with a logical value of "0".

According to the configuration of FIG. 10, a Galois multiplier can be realized by a very regular gate arrangement. In Fig. 10, the circled numbers mean the required transmission time from the input to the point marked with the number, assuming that the signal transmission time of each of eXOR and the AND element is 1. I do. Critical path is a path for obtaining the output bit o _7.

FIG. 11 shows an embodiment for increasing the speed of the embodiment of FIG. In the example of FIG. 10, the delay time until the multiplication output is obtained is relatively long. This is mainly because the correction term adder 15 X employs a configuration in which the order is reduced successively and linearly while calculating the coefficient c _{n of the} primitive polynomial and the multipliers a _n and b _n of the multiplicand. At this time, a signal which is commonly applied to the output of the uppermost unit circuit 19 of the array via the exclusive OR gate 15B is provided to the next unit circuit 19. In the Galois multiplier of FIG. 11, the speed of the drive input signal D k (k 2 2 to 8) of each column in the correction term adder 15 Y is increased.o

That is, in the configuration of FIG. 10, the drive input signal Dk of each column is obtained by exclusive-ORing the drive input signal Dk-1 of the previous array with the AND gate 17 of the unit circuit 1.9. — Formed through gate 18 and exclusive OR gate 15B. In Fig. 11, such an exclusive OR gate 15B has been abolished. Assuming that the signal transmission time in each of the AND gate 17 and the exclusive OR gate 18 is 1 as shown in FIG. 10, the delay time between the signal Dk and the signal Dk-1 is 2 Becomes To shorten this, Figure 11 shows that the C7 signal in each column is Receiving unit circuit 19 A, 19 B and unit circuit 19 B, 19 A in the final array of correction term addition Combining exclusive OR circuit 18 A, 18 C with selector circuit 18 B The exclusive OR circuit 13A for receiving the Kn and Zn signals in FIG. 10 and the exclusive OR circuit 15B in FIG. 10 are omitted. The selection signal of the selector circuit 18B is a drive input signal Dk of each column. The unit circuit 19 A receiving the signals C 7 and D 8 and the unit circuit 19 A receiving the signals C 0 and D 2 select the exclusive OR circuit 18 A and its one input and output It is composed of a selector circuit 18B. A unit circuit 18B that receives the signal C7 and other Dk signals and outputs Z2 to Z8 in the last column is a unit circuit 19B, which is an exclusive OR circuit 18A and one of its inputs. In addition to the selector circuit 18B that selects the output, the signal is output through an exclusive OR circuit 18C that takes the exclusive OR of the output of the selector circuit 18B and the output from the front row. .

 The transmission time of the selector circuit 18B is faster than that of an AND gate or an exclusive OR circuit, and the transmission time is about 0.5, so that signal transmission can be performed. Therefore, the delay time between the signal Dk and the signal Dk-1 in this embodiment is 0.5, C7 and other Dk signals in the unit circuit 19A receiving the signals C7 and D8. The receiving unit circuit 19 B is 1.5. As a result, as shown in Fig. 11, the total delay time until obtaining the multiplication output is 13 and it is possible to speed up by 38% compared to the delay time 2 1 in Fig. 10. There are advantages.

 << Sixth example of Galois multiplier >>

As shown in FIG. 12, the Galois multipliers described so far have a small number of <and a partial product adder 1 1 (1 1 X) and a correction term adder 1 2 (1 4, 15, 1). 6, 15X, 15Y), and when the correction term adding section does not have an output adding function, an output adding section 13 (13X) is further provided. Correction term adder Is given a coefficient of a primitive polynomial by coefficient setting means.

FIG. 13 shows an example of a Galois multiplier that can supply the coefficients of a primitive polynomial via a decoder. That is, a decoder 20 that decodes the primitive polynomial and supplies the decoded result to the correction term adder 21 is added. FIG. 14 shows an example of the decoder 20 and the correction term adder 21 shown in FIG. FIG. 14 shows the configuration when a decoder is added to the configuration of FIG. In FIG. 14, an example is shown in which the correction term adder 21 is applied to Galois multiplication of a Galois field GF (2 ⁿ ), in particular, a 4-bit Galois number in the case of n24. Explaining this, the correction term adder 2 1 has an array of n (= 4) unit circuits 21 A and 21 B in n-1 (= 3) columns, and the unit circuit 2 1 The order in the column direction of A, 2 1 B is from 1 to 2 门 2 (d 6), and the array in the first column is the order 2 n — 2 (= 6) for the n (= 4) th array In the array of the second column, the order of n (= 4) is 2 n—3 (= 5). 4) The n-th order is the order n (2 4). The unit circuits 21 B having the order of n + 1 (= 5) or more in each column of the array receive the partial product addition values G ₄ and G ₃ of the corresponding bit positions as common inputs for each array, and And a signal obtained by decoding the coefficients of n (= 4) bits of primitive polynomials input to the unit circuits of each column, and a product is generated by AND gate 21C, and the same order of the front column is generated. The exclusive OR circuit 21D receives the output from the unit circuit 21B at the position and the product and generates and outputs a first Galois sum, and the order n of each column is provided. Of the unit circuits 2 1 B of +1 or more (= 5) or more, the output of the unit circuit 2 1 B at the highest position in the array is exclusive with the corresponding partial product addition values G ₃ and G ₂ The second Galois sum is generated by the OR circuit 21E.

The unit circuit 21A having an order n or less of each column of the array receives the second Galois sum as a common input, and receives the common input and the unit circuit 21A of each column. In response to the input coefficients of the primitive polynomial and the corresponding coefficients, a product is generated by an AND gate 21F, and an exclusive logic is generated by receiving the output from the unit circuit 21A at the same order position in the front row and the product. It has the function of generating and outputting the third Galois sum by the sum circuit 21G.

In the unit circuit in the first column, the value (G ₄ ) of the highest order 2 n−1 of partial product addition is input as a common input for the order n + 1 or more and the order n or less, and an output is generated. In the unit circuits below the column, the input common to the order n + 1 or more is the corresponding partial product addition value (G ₃ ). Similarly, for the unit circuit below the second column, the input common to the order n or less is Is the third Galois sum output from the corresponding exclusive OR circuit 21E.

 The output of n (= 4) unit circuits 2 1 A in the n-1 (= 3) column is the output of the correction term addition, and the output of the correction term addition and the lower n (= 4) of the partial product addition The Galois sum with the bit is the result of the multiplication.

FIG. 15 shows the differences between the signal logic of nodes D ₂ , D ₃ and D ₄ in FIG. 7 and the signal logic of the same nodes D ₂ , D ₃ and D ₄ in FIG. . As is clear from the relational expression before the expansion, in the configuration of FIG. 7, the value of the node D ₃ depends on the value of the node D _{4 in} the preceding stage, and the value of the node D ₂ is in the preceding stage. It depends on the values of the nodes D ₃ and D ₄ . On the other hand, according to the expanded relation corresponding to the configuration in FIG. 14, the value of the node D ₃ does not depend on the value of the preceding node D _{4 but} the value of the node D ₂ Is a logical configuration that does not depend on the values of the preceding nodes D ₃ and D ₄ . Relationship after deployment of the first 5 diagrams are those from the right side expression of more substitution method was erased D _3, D _4. As is clear from the relational expression after the expansion in FIG. 15, if the decoder 20 is used, the values of the nodes D ₂ and D ₃ of the correction term adder 21 are theoretically the values of the nodes at the subsequent stage. It will be appreciated that it has no time effect on the confirmation. Therefore, the Galois multiplier employing the correction term adder 21 and the decoder 20 shown in FIG. The calculation processing can be performed at a higher speed than in the figure. That is, the critical path output Z ₄ signal transmission time of the correction term addition unit 2 1 is a ⑦, are shorter than ⑧ in the case of Figure 7. The numbers with circles have the same meaning as described above.

FIG. 16 shows an example in which a decoder 22 is employed for the configuration of the correction term adder of FIG. The first 7 Figure differs from the signal logic of the same node D ₂ ~ D ₈ of the signal logic and the first 4 view of nodes D ₂ to D ₈ of the first 0 diagram is shown. As in the case of FIGS. 14 and 15, if the decoder 22 is used, the values of the nodes D _{2 to} D ₈ of the correction term adder 23 are theoretically determined by the nodes at the subsequent stages. It has no effect on the time. Therefore, the Gaa multiplier employing the correction term adder 23 and the decoder 22 shown in FIG. 16 can realize a higher speed of the arithmetic processing as compared with FIG. That is, during the time of signal transmission of the output Z ₈ of the critical path in the correction term addition unit 2 3 is a ⑪, is reduced to about half of the ⑳ in the case of the first 0 FIG. The circled numbers have the same meaning as described above.

 << Seventh example of Galois multiplier >>

 FIG. 18 shows a block diagram of a Galois multiplier in which the partial product adder and the correction term adder are further speeded up. In the Galois multiplier shown in the figure, the n-bit multiplicand is decoded by the decoder 30 and supplied to the partial product adder 31. The output of the partial product adder 31 is decoded by the decoder 26. To the correction term adder 25.

FIG. 19 shows the logical configuration of the partial product adder 31 corresponding to the configuration of FIG. As shown in columns (1) and (2) of Fig. 19, the coefficient of the partial product of Xa * Xb is calculated for each degree by b. , T ^, organized in b _{2 J} b _3. Then, the coefficients in column (2) are selected according to the decoding results of the coefficients b ₃ and b ₂ of the multiplicand x ³ and X ² , and the coefficients in column (1) are similarly calculated by the multiplicand X ¹ , x ° coefficient bb. Select according to the decoding result of. Before that, the manner of selection in each of columns (1) and (2) is shown in column (3) of FIG.

FIG. 20 shows an example of the decoder 30 and the partial product adder 31 that specifically realize the logic of FIG. Decoder 30 is multiplicand b. , B ₁ , b ₂₎ Convert each bit of b ₃ into inverted and non-inverted signals. The partial product adder 31 has two arrays of selectors 32, 33, 33, 33, 33, 32, and the selector of each array is in accordance with the logic in the column (3) in FIG. Select input.

An example of the selector 32 is shown in FIG. 21 and an example of the selector 33 is shown in FIG. The circled numbers shown in Fig. 20 indicate that the signal transmission time of each of the exclusive OR gate and AND gate is 1 and that the signal transmission time of Imba overnight is 0.5, from the input to that point. This shows the signal transmission delay time. The transmission time to the output K ₄ in the partial product addition unit 11 in FIG. 7 is ④, and the signal transmission time to the output Κ ₄ can be reduced to ③ in the configuration of FIG. This reduction rate of the transmission time becomes more remarkable when the number of bits of the multiplier and the multiplicand (the number of bits of the Galois number) is increased. For example, the second 3 when applying 8 to the partial-product addition unit 3 first Galois multiplier which candidate operation Galois number of bits Bok FIG. 20 of the configuration shown in FIG., The first 0 in the structure of kappa ₈ The delay time until the output is obtained is ⑧, but it can be reduced to （(about half (5/8)). In other words, the processing speed of partial product addition is about twice as fast. Also in the partial product adder 31 shown in FIG. 23, the decoder 30 performs decoding in units of two bits, and the selectors 32, 33, 33, 33, 33, 33, 33, 33 There are provided four rows of 33 and 32 arrays. The actual logic in FIG. 23 can be easily understood by referring to the logic in FIG. 19, and is not shown. 《Error correction by lidoso-Romon code》

 FIG. 24 shows an example of a typical flow chart of the error correction processing using the Reed-Solomon code. The error correction processing flow is as follows: Syndrome operation (S 1), input operation (Euclidean algorithm) S 2, Chien search (error position search) S 3, error value calculation S for input data 4 and correction S5. The syndrome operation S 1 calculates a coefficient of a syndrome polynomial using a series of received codes as inputs. Here, if the coefficients of the syndrome polynomial are all zero, it is understood that there is no error in the received code. If it is determined that there is no error, the processing after S2 is omitted and the processing ends. If you find an error, start the correction process. First, an error locator polynomial and an error numerical polynomial are calculated from the syndrome polynomial by a step operation S2. By finding the root of the error locator polynomial in Chien search S 3, the position of the error and the number of errors are obtained. At this time, if the number of errors exceeds the specified number, it can be understood that an error has occurred that exceeds the code correction capability. At this time, it outputs that the correction is not possible and skips the following processing and ends. If the position of the error and the number of errors are properly obtained, the numerical value of the error is calculated based on the position (S 4), the error is corrected S 5, and the process is terminated.

 The Reed-Solomon code is defined using the number of Galois fields, and the above-described addition and multiplication on the Galois field are frequently used in the processing of the syndrome operation S1, the Euclidean operation S2, and the Chien search S3. Is done. The Galois multiplier can be used for such multiplication.

FIG. 25 is a block diagram showing an example of a circuit for performing a syndrome operation, a leak operation, and a Chien search. Each circuit block is provided with two Galois multipliers 40 and an adder 41. The Galois multiplier 40 has any configuration described with reference to FIGS. 1 to 24. In this example Accordingly, the circuits for performing the syndrome operation, the Euclidean operation, and the Chien search have their own hardware and are configured as one semiconductor integrated circuit. Primitive polynomials are commonly given to the respective Galois multipliers 40 from the coefficient setting means 3. X a and X b are a multiplier and a multiplicand. Therefore, when different primitive polynomials are set in different systems, the coefficients of the primitive polynomial can be set arbitrarily.

 Figure 26 shows a block diagram of an example of a microphone processor specialized in error correction using the read'Solomon code. The microprocessor 50 shown in the figure includes a program memory 55 storing an operation program of the microprocessor 50, and a control unit 5 which decodes an instruction fetched from the program memory 55 and generates a control signal. 1, an operation unit 52 controlled by the control signal, an interface unit 53 for interfacing the operation unit 52 with the outside, and a memory unit 54 used as a work area of the operation unit 52 And a single semiconductor substrate such as single crystal silicon.

The operation unit 52 has a Galois multiplier 56, an adder 57, a register 58, and the like. The Galois multiplier 5 6 is used for Galois multiplication between the elements of the Galois field GF (2 ⁿ ), and the Galois field GF (the coefficient of the two elements and the Galois field GF The original coefficient of (2 ⁿ ) and the coefficient of primitive polynomial are input, and the calculation of the coefficient for obtaining the Galois multiplication result is performed on a plurality of different primitive polynomials by the same hardware. It has any of the configurations described in Fig. 1 to Fig. 24. The coefficients of the primitive polynomial are provided from the control unit 51 according to a program, for example.

The microprocessor 50 executes, for example, the syndrome calculation, the Euclidean calculation, and the Chien search in accordance with the operation program stored in the program memory 55. That is, Sof Twe The functions equivalent to those in Fig. 25 are realized by the software.

FIG. 27 is a block diagram of a disk drive system used for recording information on a storage medium and reproducing recorded information. The storage media handled by the disk drive system shown in the figure is not particularly limited, but is both the MO and DVD media 60. The medium 60 is driven to rotate by the disk drive 61. Although not particularly limited, the pickup section 62 includes a pickup for M0 and a pickup for DVD, and includes an actuator for focusing and tracking. The servo control of the pickup is performed by the servo circuit 64. The information read from the pickup is amplified by the preamplifier 63, the high-frequency signal is given to the encoding / decoding processing section 67, and the servo error signals for tracking and intelligent focusing are sent to the servo circuit 64. Given to. The write signal to the medium 60 is supplied from the encoding / decoding processing section 67 to the pickup section 62 via the driver 65. The control unit 66 is interfaced with a host system (not shown), and controls the entire disk drive system. The encoding / decoding processing unit 67 is interfaced with a host system (not shown), and decodes information read from the medium 60 and encodes information to be written to the medium 60. At the time of encoding, a parity for error correction is generated. Error correction is performed in decoding. Error correction at the time of decoding is performed by the error correction unit 68. The error correction unit 68 includes any one of the Galois multipliers described with reference to FIGS. 1 to 24, and performs error correction using a lead-Solomon code using the Galois multiplier and the adder. The error correction processing unit 68 uses a primitive polynomial selected from a plurality of types of primitive polynomials. The error correction processing section 68 can be constituted by the microprocessor 50 or the like. In the configuration shown in FIG. 27, the servo circuit 64 performs servo control according to the type of medium. Servo circuit 64 is used to recognize the type of medium. First, at the beginning of the training period, a tracking and focusing servo for M0 is performed. Since the depth of focus and the track pitch differ depending on the type of the medium 60, the tracking and focusing servo errors actually exceed the allowable range when a DVD is mounted. When detecting this state, the servo circuit 64 recognizes that the mounted medium is a DVD. If the servo error is within the allowable range, the mounted medium is recognized as MO. In this sense, the servo circuit 64 in the system shown in FIG. 27 is an example of a medium recognizing means.

 The medium recognition result by the servo circuit 64 is given to the selector 69 as an automatic switching signal 71. The selector 69 is supplied with a manual switching signal 72 via the switch 70. The selector 69 selects either the automatic switching signal 71 or the manual switching signal 72 according to the operation mode of the system. The selected switching signal selects a primitive polynomial to be supplied to the error correction processing unit 68.

Primitive polynomial is normalized to the MO, an ^{x 8 + x 5 + x 3} + x 2 + 1, primitive polynomial that is standardized on a ^{DVD, x 8 + x 4 + x} 3 + x 2 + Is one. When the switching signal 73 selected by the selector 69 indicates ΜΟ, the former primitive polynomial is supplied to the error correction processor 68, and in the case of DVD, the latter primitive polynomial is supplied to the error correction processor 68.

As a result, error correction processing can be performed on media 60 having different primitive polynomials using the same Galois multiplier in hardware. The switching of primitive polynomials can be performed automatically, and manual switching is also possible. FIG. 28 shows a block diagram of a satellite broadcast receiving apparatus used for reproducing information from broadcast media. The broadcast media handled by the satellite broadcast receiving apparatus shown in the figure is not particularly limited, but broadcasts A and A from representative broadcast stations 80 and 81 are shown. Broadcast A, Β uses geostationary satellite 82 It can be received by the satellite-side transmitting / receiving device 89. The satellite transmission / reception device 89 receives the broadcasts A and B with the tuner 83. The broadcast to be received by the tuner 83 can be selected by the switch 84. The video signal and the audio signal received by the tuner 83 are encoded by the encoding processing unit 85, subjected to error correction, and given to the image forming unit 88 for reproduction.

 Error correction at the time of decoding is performed by the error correction processing unit 86. The error correction processing unit 86 includes any one of the Galois multipliers described with reference to FIGS. 1 to 24, and performs error correction using the read-Solomon code using the Galois multiplier and the adder. Do. The error correction processing unit 86 uses a primitive polynomial selected from a plurality of types of primitive polynomials. The error correction processing unit 86 can be constituted by the microprocessor 50 or the like.

 The selection of the primitive polynomial is synchronized with the tuning by the switch 84. In this example, the primitive polynomial used for each broadcasting station is different. Therefore, by switching the switch 84 for switching the broadcast by the receiver, the error correction can be performed using the same Galois multiplier on the same system even in the broadcast with different primitive polynomials.

 Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it is needless to say that various modifications can be made without departing from the gist of the invention. .

 For example, the number of Galois bits to be multiplied is not limited to 4 bits or 8 bits, but may be other values. The location is not limited to MO or DVD, but may be another medium such as CD-ROM. Industrial applicability

As described above, the present invention provides a Galois multiplier and a CD-ROM used for encoding or decoding a Reed-Solomon code defined using the number of Galois fields. (Compact Disc-Read Only Memory) ^ Error correction processing in a recording information reproduction device or information recording / reproduction device for recording media such as DVD (Digital Video Disc M0 (Magnet Optics)), and in a data processing system such as a satellite communication terminal It can be widely applied.

Claims

The scope of the claims

1. Galois field G F (including a Galois multiplier used for Galois multiplication between two elements,

The Galois multiplier inputs the original coefficients of the Galois field GF that is a multiplier (2 ^n), and the original coefficients of the Galois field GF (2 ⁿ⁾ which is the multiplicand, and a coefficient of a primitive polynomial, the Galois The Galois multiplier includes a Galois multiplier that performs the calculation of the coefficient to obtain a multiplication result for a plurality of different primitive polynomials with the same hardware, and further includes the Galois multiplier with the Galois field GF (2 ⁿ ). A semiconductor integrated circuit comprising coefficient setting means for giving a coefficient of a primitive polynomial.

 2. The coefficient setting means according to claim 1, wherein the coefficient setting means is a storage means for rewritably storing coefficients of a primitive polynomial, and outputting the stored coefficients of the primitive polynomial to the Galois multiplier. Semiconductor integrated circuit.

3. The coefficient setting means according to claim 1, wherein the coefficient setting means stores coefficients of a plurality of types of primitive polynomials and outputs a coefficient selected from the stored coefficients to the Galois multiplier. 13. A semiconductor integrated circuit according to claim 1.

4. The Galois multiplier has a partial product adder and a correction term adder, and the partial product adder performs partial product addition of a multiplier coefficient and a multiplicand coefficient for each partial product of the multiplier and the multiplicand. ,

 The correction term adding unit performs an operation of correcting a coefficient of a partial product of n + 1 or higher order obtained by the partial product adding unit to a coefficient of a partial product of nth or lower order. 2. The semiconductor integrated circuit according to claim 1.

5. The correction term adding unit calculates correction information for correcting the coefficient of the partial product of degree n + 1 or higher obtained by the partial product addition unit into the coefficient of partial product of degree n or less based on the coefficient of the primitive polynomial. A first logical operation circuit that pre-calculates A second logical operation circuit that takes a product of the coefficient and the corresponding correction information for each coefficient of the n + 1 or higher order partial product obtained by the partial product adder, and a second logical operation circuit 5. The semiconductor integrated circuit according to claim 4, further comprising a third logical operation circuit for adding the outputs of the first and second logic circuits.

6. The correction term adder includes n-1 arrays of n unit circuits, and the order of the unit circuits in the column direction is from 1 to 2 n-2, and the array of the first column is n The order is 2 n—2 in the array, the n-th array in the second column is the order 2 n—3, the order is lowered sequentially, and the n-th array in the n-th column is the n-th order, The unit circuit of each column of the array receives, as a common input for each column, a first Galois sum of the output of the highest-order unit circuit of the array of the previous column and the corresponding partial product addition value, Of the primitive polynomial and the coefficient of the primitive polynomial commonly input to the unit circuits of each column, and generates a logical product.

—Has the function of generating and outputting a second Galois sum with the output of the order position, and the unit circuits in the first column each have the highest order of partial product addition 2 n − The value of 1 is supplied and the output is generated without generating the second Galois sum, and the unit circuits of the second column and the lower array are used as the common input in the previous array. Receiving the first Galois sum of the output of the uppermost unit circuit and the value of the partial product addition corresponding to the output, generates an output, and corrects the outputs of the n unit circuits in the n-1st column. 5. The semiconductor according to claim 4, wherein an output of the addition is obtained, and an output of the correction term addition is obtained as a multiplication result by taking a Galois sum with lower n bits of the partial product addition. Integrated circuit.

7. The correction term adder has n-1 arrays of n unit circuits, the order of the unit circuits in the column direction is 1 to 2 n-2, and the array of the first column is n The order is 2 n—2 in the array, the n-th array in the second column is the order 2 n—3, the order is reduced in order, and the n-th array in the n-th column is the n-th order, Unit circuits of order n + 1 or more in each column of the array receive the value of the partial product addition at the corresponding bit position as a common input for each array, and are input to this common input and the unit circuit of each column. A signal obtained by decoding the coefficients of the n-bit primitive polynomial to generate a product, and generate a first Galois sum of the output from the unit circuit at the same order position in the front row and the product. The output of the unit circuit at the highest position of the array among the unit circuits of order n + 1 or more of each array is the second Galois sum together with the corresponding partial product addition value. Generate

 A unit circuit of order n or less of each column of the array receives the second Galois sum as a common input, and the common input and a corresponding coefficient of a primitive polynomial input to the unit circuit of each column. And a function of generating a third Galois sum of the output from the unit circuit at the same order position in the front row and the product, and generating an output,

 The unit circuit in the first column receives the value of the highest order 2 n-1 of the partial product addition as a common input for the order n + 1 or more and the order n or less and generates an output. In the circuit, the input common to the order n + 1 or more is the value of the corresponding partial product addition, and the input common to the order n or less in the unit circuit in the second column and below is the value of the corresponding second Galois sum And

 The output of the n unit circuits in the n-1st column is the output of the correction term addition, and the output of the correction term addition is the result of multiplication by taking the Galois sum with the lower n bits of the partial product addition 5. The semiconductor integrated circuit according to claim 4, wherein:

8. The correction term adding unit is characterized in that, when handling a limited plurality of primitive polynomials, hardware relating to an order having a coefficient commonly set to zero in a plurality of primitive polynomials is omitted. The semiconductor integrated circuit according to claim 4.

9. The partial product adder generates n−1 bits of the Galois sum of adjacent two bits of the multiplier, and further decodes every two consecutive bits of the multiplicand to obtain 4 bits for each two bits. , The number of columns of the partial product is set to 1/2, the bit values of adjacent multipliers, the Galois sum of adjacent two bits of the multipliers as inputs for each bit position of each column of the partial product, And zero, and the input is selected based on the four decoded outputs, and the Galois sum of the selected input and the partial product of the preceding column is output to the succeeding column as an output. A semiconductor integrated circuit according to claim 4.

10. A Galois multiplier used for Galois multiplication between elements of the Galois field GF (2 ⁿ ), and a setting means for setting a primitive polynomial of the Galois multiplier,

The Galois multiplier inputs the original coefficients of the Galois field GF that is a multiplier (2 ^n), and the original coefficients of the Galois field GF (2 ⁿ⁾ which is the multiplicand, and a coefficient of a primitive polynomial, the Galois A data processing system for calculating the coefficient for obtaining a multiplication result for a plurality of different primitive polynomials with the same hardware, and wherein the coefficient of the primitive polynomial is given from the setting means; .

 11. The data processing system according to claim 10, wherein said setting means determines a primitive polynomial to be set in accordance with an operation state of a selection switch.

 1 2. Recognition means for recognizing the type of information recording medium, access means capable of accessing a plurality of types of information recording media, and error correction used for error correction of recorded information read from the information recording medium by the access means A data processing system comprising:

The Galois multiplier is used for Galois multiplication between the original and the original Galois field GF (2 ^n), and the original coefficients of the Galois field GF (2 ⁿ⁾ which is the multiplier, multiplicand The original coefficient of the Galois field GF (2 ⁿ ) and the coefficient of the primitive polynomial are input, and the calculation of the coefficient for obtaining the Galois multiplication result is performed on the same hardware for a plurality of different primitive polynomials. Wherein the coefficient of the primitive polynomial given to the Galois multiplier is determined according to the result of recognition of the type of information recording medium by the recognition means.

 13. A data processing system comprising: control means for decoding a fetched instruction to generate a control signal; arithmetic means controlled by the control signal; and interface means for interfacing the arithmetic means with the outside. hand,

The arithmetic means includes a Galois multiplier used for Galois multiplication between elements of a Galois field GF (2 ⁿ ),

The Galois multiplier inputs the original coefficients of the Galois field GF that is a multiplier (2 ^n), and the original coefficients of the Galois field GF (2 ⁿ⁾ which is the multiplicand, and a coefficient of a primitive polynomial, the Galois The operation of the coefficient for obtaining the multiplication result is performed on a plurality of different primitive polynomials by the same hardware, and the coefficient of the primitive polynomial given to the Galois multiplier is determined by the control of the control means. A data processing system, characterized in that:

 14. The data processing system according to claim 13, wherein the microprocessor is a microprocessor formed on a single semiconductor substrate.