WO1999016175A1 - Circuit integre a semi-conducteurs et systeme de traitement de donnees - Google Patents

Circuit integre a semi-conducteurs et systeme de traitement de donnees Download PDF

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Publication number
WO1999016175A1
WO1999016175A1 PCT/JP1997/003367 JP9703367W WO9916175A1 WO 1999016175 A1 WO1999016175 A1 WO 1999016175A1 JP 9703367 W JP9703367 W JP 9703367W WO 9916175 A1 WO9916175 A1 WO 9916175A1
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Prior art keywords
galois
coefficient
multiplier
order
column
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PCT/JP1997/003367
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English (en)
Japanese (ja)
Inventor
Toshimitsu Ozawa
Kenji Kaneko
Hirotsugu Kojima
Tsukasa Yamauchi
Yukari Katayama
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Hitachi, Ltd.
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Priority to PCT/JP1997/003367 priority Critical patent/WO1999016175A1/fr
Publication of WO1999016175A1 publication Critical patent/WO1999016175A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/47—Error detection, forward error correction or error protection, not provided for in groups H03M13/01 - H03M13/37
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

Definitions

  • the present invention relates to a semiconductor integrated circuit including a Galois multiplier used for multiplication on a Galois field, for example, encoding or decoding for error correction using a Read-Solomon code defined using the number of Galois fields. Multiplier used for multiplexing, and recording of CD-R0M (Compact Disc-Read Only Memory), DVD (Digital Video Desc), M0 (Magnet Optics), etc.
  • the present invention relates to a technology effective when applied to error correction processing in a data processing system such as a recorded information reproducing apparatus or information recording / reproducing apparatus for a medium, and a satellite communication terminal apparatus. Background art
  • a code word capable of correcting a reading error occurring in a recording medium is used in the recording information reproducing device or the information recording / reproducing device.
  • a codeword can be defined by a special set of numbers called the Galois field and special operations defined with it. Code error correction is performed by data processing using the number of Galois fields and the above operation.
  • the most frequently used codeword is a lead-Solomon code, which is particularly used for an error correction code in a data storage system (data recording system) or a communication system in which errors are easily concentrated in a part.
  • Lead-Solomon codes are defined using the number of Galois fields, and encoding or decoding is performed by operations on the Galois field. For this encoding or decoding processing, addition and multiplication on Galois fields are frequently used.
  • the set of numbers in the Galois field is defined by a primitive polynomial, and the set of numbers is defined. Multiple types of definitions are possible depending on the underlying polynomial to be defined. At the same time, operations on Galois fields are defined differently depending on the primitive polynomial. At present, different standards are defined for primitive polynomials that define Galois fields used in lead Solomon codes for each medium such as M0 and DVD. Further, in the storage system and communication system, codewords are continuously read or received, and there is a limit to the time allowed for reading or processing of received data including error correction. In other words, processing such as error correction must be performed at high speed without impairing the real-time performance.
  • multipliers on Galois fields used for error correction and the like have been composed of hardware dedicated to primitive polynomials conforming to the standard of the system to which the multipliers are applied.
  • Galois multiplier dedicated to a particular primitive polynomial cannot be applied to systems using different primitive polynomials. Therefore, in an information recording / reproducing apparatus that can support both MO and DV with different primitive polynomial standards, Galois multipliers must be separately mounted for each of MO and DVD.
  • a Galois field is a Galois field in which a finite number of element sets are free to perform the four arithmetic operations and are in a closed configuration.
  • the field means a set of elements that can freely perform the four arithmetic operations and its calculation rules.
  • a primitive polynomial is defined in the Galois field.
  • the Galois number is defined. In other words, a set of numbers that satisfies that the primitive polynomial is zero is a Galois field.
  • Error correction is performed by performing arithmetic operations on Galois numbers.
  • the error correction process uses the error correction code on the transmitting side (recording side) and the receiving side (reproducing side; Error correction decoding. Error correction is achieved by combining code and decoding.
  • the four basic arithmetic operations of the most basic Galois field GF (p) will be described.
  • mod p is used for the elements of 0, 1, 2,.
  • mod is an abbreviation for modulo (remainder)
  • p is a prime number.
  • addition and multiplication by the mod p algorithm are performed as usual, and if the result is greater than or equal to P, the remainder can be obtained by dividing by P.
  • the X means X 2 1 / a: a- 1 mod p. This X is called the multiplicative inverse of a, and is expressed as a- 1 . Division by a is the multiplication of a by the multiplicative inverse a- 1 .
  • the Galois field GF (p) is a further development of the Galois field GF (2 m ).
  • the Galois field GF (2) there are two types of elements, 0 and 1, between which the four arithmetic operations are performed. I did it.
  • the Galois field GF (2 m ) In the Galois field GF (2 m ), on the other hand, there are 2 m elements, and the four arithmetic operations can be performed freely between those elements.
  • the 2 m elements can be represented by m-dimensional vectors on GF (2) or polynomials of degree m ⁇ 1 or less on GF (2). The former is called vector display, and the latter is called polynomial display.
  • the vector representation can be considered as a coefficient of each order in a polynomial.
  • the addition between the elements of the Galois field GF (2 m ) is defined by the addition of vectors (addition of polynomials). That is, the addition of the vector elements (coefficients of the same order of the polynomial). However, the elements or coefficients are elements of GF (2). The addition may be performed by mod 2 calculation. The same applies to subtraction.
  • the multiplication between the elements of the Galois field GF (2 m ) is usually performed by polynomial multiplication, and when the result is equal to or higher than the highest degree of the primitive polynomial, the result is divided by the primitive polynomial, and the remainder is the result.
  • the result can be obtained by multiplying by a * x.
  • the addition between the elements of the Galois field GF (2 m ) is the addition of the coefficients of the same order of the polynomial, and the coefficients are elements of GF (2).
  • the calculation of mod 2 may be performed.
  • the multiplication between the elements of the Galois field GF (2 m ) after performing a polynomial multiplication as usual, if the result exceeds the highest order of the primitive polynomial, divide by the primitive polynomial, and the remainder is the result. I just need.
  • the addition of coefficients of the same order in multiplication may be performed by the calculation of mod 2 as described above.
  • error correction uses a numerical system called the Galois field, and frequently performs operations mainly on multiplication and addition.
  • this numerical system four arithmetic operations are defined for a set of numbers, and the number of results of the four arithmetic operations is included in the original set of numbers.
  • moths lower number of defined operations 4 bits Bok Galois field GF (2 4).
  • a primitive polynomial is defined, and the Galois number is defined as the root of the primitive polynomial.
  • 4 bits Bok moth lower body GF (2 4) In the following two primitive polynomials exist.
  • Equation 1 primitive polynomial 1: x 4 + x 1 ⁇ 1
  • Equation 2 the primitive polynomial 2: x + x 3 + 1
  • a set of numbers that satisfies that the above primitive polynomial is a Zeguchi is a Gaguchi field.
  • the number of Galois fields can be represented by a polynomial as described above, and in the 4-bit Galois field GF (2 4 )
  • multiplication differs from ordinary multiplication in that the result of multiplication differs depending on the primitive polynomial of the Galois field GF (2 4 ).
  • Fig. 37 shows a Galois field for the primitive polynomial 1
  • Fig. 38 shows a Galois field for the primitive polynomial 2.
  • the Galois field GF (2 4 ) is expressed by showing the coefficients of x 3 , X 2 , X 1 , and x ° for each element.
  • the conventional hardwired Galois multiplier employs, for example, a method in which the above equation is directly constituted by a logic circuit.
  • the dedicated hardware multiplier forms the logic shown in FIG. 31 by the dedicated logic circuit shown in FIG.
  • the multiplication of the element X 2 of GF (2 3 ) in the above polynomial expression and x + 1 is performed by a power expression.
  • FIG. 33 shows an example of a Galois multiplier, which is not publicly known, for performing multiplication in a power expression using a ROM.
  • the vector representation data corresponding to the Galois numbers ⁇ ⁇ and m is decoded by the first and second Galois number decoding logic.
  • exponents (power numbers) n and m of Galois numbers according to the decoding result by the first and second Galois number decoding logic are stored in advance. The exponent is read from the first and second R ⁇ M according to the decoding result.
  • the exponents n and m read from both ROMs are added, and the addition result is encoded by the encoder.
  • the third R receiving the output of the encoder stores the Galois number according to the value of the exponent + n and the vector representation data of m + n in advance, and the Galois number according to the result of the encoding.
  • the vector representation of am + n is output.
  • the Galois multiplier shown in Fig. 33 which employs the power multiplication method, must have several types of ROMs, so the circuit size of the Galois multiplier becomes large.
  • the OM when used, if the primitive polynomial changes, the stored data of R0M may be rewritten accordingly, but as the number of bits N in the Galois field increases, the R ⁇ M capacity becomes 2 N times increase, circuit rule There are more and more models.
  • the primitive polynomials when applied to different primitive polynomials,
  • the present invention has been made in view of the above circumstances, and has a semiconductor integrated circuit including a Galois multiplier that has a smaller circuit size than that using a ROM and enables multiplication using a plurality of different primitive polynomials.
  • Another object of the present invention is applied to an information recording system, an information communication system, and the like, which can reduce a circuit scale for performing error correction on a plurality of types of information using codewords related to a plurality of different primitive polynomials.
  • a data processing system To provide a data processing system.
  • a semiconductor integrated circuit includes a Galois multiplier used for Galois multiplication between elements of a Galois field GF ( 2n ), wherein the Galois multiplier is a Galois field GF (2 n ), the original coefficient of the Galois field GF (2 n ), which is the multiplicand, and the coefficient of a primitive polynomial.
  • the same hardware is used for primitive polynomials.
  • the Galois multiplier is provided with coefficient setting means for giving a primitive polynomial coefficient of the Galois field GF ( 2n ).
  • the Galois multiplier can perform multiplication on the Galois field in accordance with the primitive polynomial given from the coefficient setting means. Therefore, the semiconductor integrated circuit can be generally used for encoding or decoding of an error correction code or the like based on different Galois fields defined for each primitive polynomial.
  • the coefficient setting means stores the coefficients of the primitive polynomial in a rewritable manner, and It may be storage means such as a register for outputting the stored coefficients of the primitive polynomial to the Galois multiplier. Further, the coefficient setting unit may be a unit such as a ROM that stores a plurality of types of primitive polynomial coefficients and outputs a coefficient selected from the stored coefficients to the Galois multiplier.
  • the Galois multiplier includes a partial product adder and a correction term adder, and the partial product adder performs partial product addition of a multiplier coefficient and a multiplicand coefficient for each partial product of the multiplier and the multiplicand.
  • the correction term adding unit can be configured to perform an operation of correcting the coefficient of the partial product of order n + 1 or more obtained by the partial product adding unit to the coefficient of the partial product of order n or less.
  • the coefficients of the primitive polynomial are set in advance by the coefficient setting means.
  • the correction term addition unit has previously input the coefficients of the primitive polynomial set in advance in such a manner, and can immediately perform the correction operation by inputting the partial product addition result by the partial product addition unit.
  • the correction term addition unit calculates correction information for correcting the coefficient of the partial product of n + 1 or higher order obtained by the partial product addition unit to the coefficient of the partial product of nth or lower order by using a primitive polynomial.
  • a first logical operation circuit that calculates in advance based on the coefficient; and a second logic operation circuit that obtains, for each coefficient of the n + 1 or higher order partial product obtained by the partial product addition unit, a product of the coefficient and the corresponding correction information. It can be composed of two logical operation circuits and a third logical operation circuit that adds the outputs of the respective second logical operation circuits.
  • the correction term adder uses a method to reduce the order of the higher-order terms, performing partial product operations of the coefficients of the primitive polynomial and the coefficients of the multiplier and the multiplicand. A configuration in which the order is reduced every time can be adopted.
  • the correction term adder that realizes this is provided with an array of n unit circuits of n-1 columns, the order of the unit circuits in the column direction is from 1 to 2 n-2, and the array of the first column is n The order is 2 n-2, the n-th array in the second column is the order 2 n— 3, and the order is reduced sequentially.
  • the n-th array in the n-th column is the n-th order. .
  • the unit circuit of each column of the array receives, as a common input for each column, a first Galois sum of the output of the uppermost unit circuit of the array of the preceding column and the value of the partial product addition corresponding thereto, and A logical product is generated by receiving the input and a coefficient of a primitive polynomial commonly input to the unit circuits of each column, and a second logical product of the value of the logical product and the output of the unit circuit at the same order position in the preceding column is obtained. It has a function to generate Galois sums and output them.
  • Each of the unit circuits in the first column is supplied with the value of the order 2 n ⁇ 1, which is the highest order of partial product addition, as the common input, and generates an output without generating the second Galois sum. I do.
  • the unit circuits of the second column and the lower array are used as the common input as the first Galois sum of the output of the uppermost unit circuit of the immediately preceding array and the corresponding partial product addition value. Receives and produces output. Then, the outputs of the n unit circuits in the n_1st column are output as the correction term additions.
  • the Galois sum of the output of the correction term addition and the lower n bits of the partial product addition is used as the multiplication result.
  • the correction term adder which further speeds up the arithmetic processing by the correction term adder, includes an array of n unit circuits in n-1 columns, and the order of the unit circuits in the column direction is 1 to 2 n ⁇ 2.
  • the n-th array has the order 2 n—2
  • the n-th array has the order 2 n— 3.
  • the n-th array has the degree n.
  • Unit circuits of order n + 1 or higher in each column of the array receive the value of the partial product addition at the corresponding bit position as a common input for each array, and are input to this common input and the unit circuit in each column.
  • Generates a product by receiving the signal obtained by decoding the coefficients of the n-bit primitive polynomial And a function of generating and outputting the first Galois sum of the output from the unit circuit at the same order position in the front row and the product, and among the unit circuits of the order n + 1 or more in each column, the array
  • the output of the unit circuit at the uppermost position generates a second Galois sum with the corresponding partial product addition value.
  • a unit circuit of order n or less in each column of the array receives the second Galois sum as a common input, and calculates the common input and a corresponding coefficient of a primitive polynomial input to the unit circuit of each column.
  • a third Galois sum of the output from the unit circuit at the same order position in the front row and the product is output.
  • the unit circuit in the first column receives the value of the highest order 2 n-1 1 of partial product addition as a common input for the order n + 1 or more and the order n or less and generates an output.
  • the unit circuit in the second column or less In this case, the input common to the order n + 1 or more is the corresponding partial product addition value, and the input common to the order n or less is the corresponding value of the second Galois sum in the unit circuits in the second column and below.
  • You. n — The output of the n unit circuits in the first column is the output of the correction term addition.
  • the Galois sum of the output of the correction term addition and the lower n bits of the partial product addition is used as the multiplication result.
  • Decoding logic that decodes the coefficients of n-bit primitive polynomials simplifies the logic of generating correction information based on partial product addition results of degree n + 1 or more and coefficients of primitive polynomials, and reduces the number of gate series stages. Less.
  • the correction term adder can be configured by omitting hardware relating to an order whose coefficient is commonly set to zero among a plurality of primitive polynomials.
  • the primitive polynomials corresponding to it are limited to several types.At this time, in the order where the coefficient is always zero in all primitive polynomials, Hardware can be omitted. This promotes faster arithmetic processing by reducing the number of gate series stages.
  • the partial product adder calculates the Galois sum of adjacent two bits of the multiplier as n ⁇ 1 bits. , And further decodes every two consecutive bits of the multiplicand to generate four outputs for every two bits.
  • the number of columns of the partial product is set to 1/2, and each column of the partial product is output.
  • the input of the bit position has four inputs: a bit value of an adjacent multiplier, a Galois sum of two adjacent bits of the multiplier, and zero, and selects an input based on the four outputs decoded as described above.
  • the Galois sum of the selected input and the partial product of the front row can be output to the back row as an output. Even with such a configuration in which partial product addition is performed by the selector method, the number of gate series stages in the signal path can be reduced, and high-speed arithmetic processing is realized.
  • the data processing system includes a Galois multiplier used for Galois multiplication between elements of a Galois field GF ( 2n ), and setting means for enabling a primitive polynomial of the Galois multiplier to be reset.
  • the Galois multiplier, and the original coefficients of the Galois field GF (2 n) which is the number of multiplication, and the original coefficients of the Galois field GF (2 n) which is the multiplicand, and a coefficient of a primitive polynomial The input and the calculation of the coefficients for obtaining the Galois multiplication result are performed on the same hardware for a plurality of different primitive polynomials.
  • the coefficients of the primitive polynomial may be provided from the setting means.
  • the setting means may be configured to determine a primitive polynomial to be set in accordance with an operation state of a selection switch.
  • Another data processing system includes a recognizing unit that recognizes the type of the information recording medium, an access unit that can access a plurality of types of information recording media, and a recording unit that reads the recording information read from the information recording medium by the access unit.
  • Error correction circuit used for error correction.
  • the Galois multiplier is used for Galois multiplication between the original and the original Galois field GF (2 n), and the original coefficients of the Galois field GF (2 n) which is a multiplier, is the multiplicand
  • the original coefficients of the Galois field GF (2 n ) and the coefficients of the primitive polynomial are input, and the calculation of the coefficients for obtaining the result of the Galois multiplication is the same for a plurality of different primitive polynomials. This is done with one hardware.
  • the primitive polynomial coefficient may be determined according to the result of recognition of the type of the information recording medium by the recognition means.
  • either of the recording media is used for reproducing the recorded information and for recording the information.
  • the Galois multiplier can also be used in common for the body, which contributes to the miniaturization of the system.
  • Still another data processing system includes control means for decoding a fetched instruction to generate a control signal, arithmetic means controlled by the control signal, and interface means for interfacing the arithmetic means with the outside.
  • the arithmetic means includes a Galois multiplier used for Galois multiplication between elements of the Galois field GF (2 n ), and the Galois multiplier is a Galois field GF (2 n ), The original coefficient of the Galois field GF (2 n ), which is the multiplicand, and the coefficient of the primitive polynomial, and the calculation of the coefficient to obtain the Galois multiplication result is performed by a plurality of different primitives.
  • a Galois multiplier that performs the same hardware with respect to the polynomial may be included, and a coefficient of the primitive polynomial may be determined by control of the control unit.
  • This data processing system can be configured as a microprocessor formed on a single semiconductor substrate.
  • Fig. 1 is an explanatory diagram conceptually showing a Galois multiplier that enables multiplication of multiple types of primitive polynomials with the same hardware.
  • Fig. 2 is an explanatory diagram showing the first calculation example of partial product addition and correction term addition
  • Fig. 3 is a Galois multiplier realized by dividing the logic shown in the calculation example of Fig. 2 into a partial product and a correction term.
  • Example logic circuit diagram Fig. 4 is an explanatory diagram showing a second calculation example of partial product addition and correction term addition
  • Fig. 5 is a Galois multiplier that realizes the logic shown in the calculation example of Fig. 4 by dividing it into a partial product and a correction term.
  • Fig. 6 is an explanatory diagram showing a third calculation example of partial product addition and correction term addition
  • Fig. 7 is a Galois multiplier that implements the logic shown in the calculation example of Fig. 6 by dividing it into a partial product and a correction term.
  • FIG. 8 is an explanatory diagram showing a calculation example of a partial product adding a complement Seiko addition in the case of considering that the coefficients C 2 both primitive polynomial in X 2 is zero at the primitive polynomial of the two there quartic ,
  • Fig. 9 is an example logic circuit diagram of a Galois multiplier realized by dividing the logic shown in the calculation example of Fig. 8 into partial products and correction terms,
  • FIG. 10 is an example logic circuit diagram of a Galois multiplier when the logic of FIGS. 6 and 7 is applied to an 8-bit Galois field
  • FIG. 11 is a logic circuit diagram of an example of a Galois multiplier which is further speeded up from the configuration of FIG. 10,
  • Fig. 12 is an explanatory diagram that functionally shows the configuration of a Galois multiplier that performs Galois multiplication by dividing into the partial product addition and the correction term addition specifically shown in Fig. 3, etc.
  • Fig. 13 is the correction term.
  • Explanatory diagram functionally showing the configuration of a Galois multiplier that decodes the coefficients of a primitive polynomial in an adder in advance and supplies the decoded data to a correction term adder.
  • FIG. 14 is an explanatory diagram specifically showing the configurations of the correction term adder and the decoder when the 4-bit circuit configuration of FIG. 7 is expanded to the decoding system of FIG.
  • FIG. 15 is an explanatory diagram showing an example of expansion of a correction term using the decoder of FIG. 14,
  • Fig. 16 shows the case where the decoding method is applied to an 8-bit Galois multiplier.
  • FIG. 17 is an explanatory diagram showing an example of expansion of a correction term using the decoder of FIG. 16,
  • FIG. 18 is an explanatory diagram functionally showing a Galois multiplier in which a decoder is provided for both the input of the partial product addition unit and the input of the correction term addition unit to further speed up the processing;
  • FIG. 19 is an explanatory diagram logically showing a configuration based on a selector system for further accelerating the arithmetic processing in the partial product addition unit.
  • FIG. 20 is a logic circuit diagram of a partial product adder when the selector method shown in FIG. 19 is applied to a 4-bit Galois multiplier.
  • FIG. 21 is a circuit diagram of an example of a first selector applied to the partial product adder of FIG. 20,
  • FIG. 22 is a circuit diagram of an example of a second selector applied to the partial product adder of FIG. 20,
  • FIG. 23 is a logic circuit diagram of the partial product adder when the selector system of FIGS. 19 and 20 is extended to an 8-bit Galois multiplier,
  • FIG. 24 is a flow chart showing an example of the read'Solomon error correction decoding process
  • FIG. 25 is a schematic diagram showing the internal configuration of each of the circuits for the Sindom operation, the leak operation and the Chien search. Block diagram shown,
  • FIG. 26 is a block diagram of a processor for performing the read 'Solomon error correction decoding process shown in FIG. 24,
  • Fig. 27 is a block diagram of an example of a data processing system that records or reproduces information on storage media such as DVDs.
  • Figure 28 is an example block diagram of a data processing system used for communication systems such as satellite broadcasting.
  • FIG. 29 is an explanatory diagram showing an example of multiplication calculation of a Galois number represented by a polynomial expression.
  • FIG. 30 is an explanatory diagram showing a calculation example when a numerical value is inserted in the coefficient of each order of the multiplier and the multiplicand and the Galois number is multiplied,
  • FIG. 33 is a block diagram showing an example of a Galois multiplier circuit based on the R0M method.
  • Fig. 34 is an explanatory diagram of a communication system model that employs Galois field error correction.
  • Fig. 35 is an explanatory diagram of a storage model that adopts error correction by Galois field
  • FIG. 36 is an explanatory diagram showing elements of the Galois field GF (2 3 ),
  • Fig. 37 is an explanatory diagram showing the elements of the Galois field GF (2 4 ) in the case of the primitive polynomial X 4 + X 1 + 1,
  • Fig. 38 is an explanatory diagram showing the elements of the Galois field GF (2 4 ) in the case of the primitive polynomial X 4 + X 3 + 1,
  • FIG Galois field GF explanatory view showing an example of a base click Bokuru representation and polynomial representation of the original, (2 4)
  • 4 0 is an explanatory diagram showing an example of a polynomial representation preparative base key representation of the original Galois field GF (2 4).
  • FIG. 1 shows an example of a semiconductor integrated circuit according to the present invention.
  • the semiconductor integrated circuit 1 shown in FIG. 1 includes a Galois multiplier 2 and a coefficient It includes the setting means 3 and is formed on one semiconductor substrate such as single crystal silicon, for example, by a known CMOS integrated circuit manufacturing technique.
  • the Galois multiplier 2 and the coefficient setting means 3 are used for Galois multiplication between elements of the Galois field GF ( 2n ).
  • the Galois multiplier 2, and the original coefficients of the Galois field GF that is a multiplier (2 n) (n bits) 4, the original coefficients of the multiplicand and is Ru Galois field GF (2 n) (n bits) 5 and the coefficient (n bits) 6 of the primitive polynomial are input, and the operation of the coefficient for obtaining the Galois multiplication result is performed for a plurality of different primitive polynomials with the same hardware.
  • the coefficient setting means 3 is a circuit that provides the Galois multiplier 2 with the coefficients of the primitive polynomial of the Galois field GF (2 ".
  • the coefficient setting unit 3 may be a storage unit such as a register that stores the coefficients of the primitive polynomial in a rewritable manner and outputs the stored coefficients of the primitive polynomial to the Galois multiplier 2. Further, the coefficient setting means 3 may be a means such as a ROM which stores a plurality of types of primitive polynomial coefficients and outputs a coefficient selected from the stored coefficients to the Galois multiplier 2.
  • the coefficient setting of the primitive polynomial or the coefficient selection of the primitive polynomial for the coefficient setting means 3 can be given from inside the semiconductor integrated circuit 1 via a signal line 7 or from outside the semiconductor integrated circuit via a signal line 8.
  • the Galois multiplier 2 can perform multiplication on the Galois field according to the coefficients of the primitive polynomial given from the coefficient setting means 3. Therefore, the semiconductor integrated circuit 1 can be generally used for encoding or decoding of an error correction code or the like using a different Galois field defined for each primitive polynomial. Even when the semiconductor integrated circuit 1 is applied to a system for, for example, MO or DVD, it is not necessary to redesign the Galois multiplier.
  • the single semiconductor integrated circuit 1 can be used for encoding and decoding error correction codes for both M0 and DVD.
  • the circuit size of the Galois multiplier required for the entire system is about 1 unit for the former. / N, and the more primitive polynomials that need to be supported, the greater the effect of circuit scale reduction.
  • Equation 21 The meaning of the above (Equation 21) will be clear from the above, but it is further added that Using the general form of the primitive polynomial of (Equation 17), the higher-order terms x 6 , X 5 , and X 4 of the partial product obtained by the equation multiplication are calculated using the lower-order terms X 3 , X 2 , It is replaced with X 1 and X 0 .
  • the calculation formula shown in the column of correction term addition in FIG. 2 is a formula in which the higher-order terms X 6 , x 5 , and X 4 are replaced with lower-order terms X 3 , x 2 , x 1 , and x °. is there.
  • correction term added to operations for such replacement the correction term was collected using cowpea in addition low-order sections x 3, x 2, X 1 , x ° is referred to as a correction term.
  • a polynomial multiplication of two Galois numbers is called partial product addition, and each term obtained by that is called a partial product.
  • Equation 21 in order to multiply the Galois number for general purpose, the coefficient c of the primitive polynomial of (Equation 21) is used.
  • ⁇ c 3 by setting the coefficient of the necessary primitive polynomial multiplication result for any primitive polynomial is obtained, et al.
  • a value that is a coefficient of each order of (Equation 21) is set in advance c. Leave obtained by logical operation between ⁇ c 3, Ri by the setting these values, the multiplication result for any primitive polynomial is obtained.
  • FIG. 3 shows a specific example of the Galois multiplier 2 having the logic according to the above method.
  • the Galois multiplier 2 includes a partial product adder 11, a correction term adder 12, and an output adder 13.
  • the partial product adder 11 performs partial product addition of a multiplier coefficient and a multiplicand coefficient for each partial product of the Galois field GF (2 n ) and the multiplicand.
  • the logic shown in the column of partial product addition in FIG. 2 is realized as it is.
  • the correction term addition unit 12 performs an operation of correcting the coefficient of the ⁇ + 1 or higher order partial product obtained by the partial product addition unit 11 into the coefficient of the nth order or lower partial product.
  • the logic shown in the column of correction term addition in FIG. 2 is realized as it is.
  • the output adder 13 is a Galois sum of the output of the correction term adder 12 and the lower n-bit partial product coefficient of the partial product adder 11 (similar to the addition process for a 2-bit Galois field) To Calculate. Specifically, the outputs ⁇ 0 to ⁇ 3 are obtained by adding the coefficients of the corresponding orders by exclusive OR.
  • the multiplication between the elements of the Galois field GF (2 n ) is defined by addition of a polynomial, and the coefficients of the polynomial are elements of GF (2). Since the calculation can be performed, the partial product addition unit 11, the correction term addition unit 12, and the addition output unit 13 are configured by using an AND gate and an exclusive OR gate (ex OR). ing.
  • the correction term adding section 12 can be classified into first to third logical operation circuits.
  • the first logical operation circuit converts the correction information for correcting the coefficient of the partial product of order n + 1 or higher obtained by the partial product adder 11 into the coefficient of the partial product of order n or less into the coefficient c of the primitive polynomial. 3 to c.
  • This is a logic circuit that calculates in advance on the basis of, and is composed of gate rows 12G and 12E.
  • the second logic operation circuit is a logic circuit that takes, for each coefficient of the n + 1 or higher-order partial product obtained by the partial product addition unit 11, a product of the coefficient and the corresponding correction information, It is composed of gate rows 12B, 12D, and 12F.
  • the third logical operation circuit is a logical circuit for adding the outputs of the respective second logical operation circuits, and is constituted by gate arrays 12A and 12C.
  • the output of the first logical operation circuit constituted by the gate trains 12 G and 12 E has the coefficients C 3 to C of the primitive polynomial.
  • the result of the correction term addition operation can be immediately obtained by inputting the result of the partial product addition by the partial product addition unit.
  • the number of gates used in the configuration of Fig. 3 is 25 for the partial product adder 11, 11 for the correction term adder 12, and 4 for the output adder 13. 64 AND elements and exOR are required.
  • the circled numbers indicate the signal transmission of each of eXOR and the AND element.
  • the critical path is a path for obtaining the output bit Bok o 3.
  • the outputs of the first logical operation circuit composed of the gate arrays 12 G and 12 E are the primitive polynomial coefficients C 3 to C 3 .
  • the transmission time until the output of the gate train 12F is determined is set to 2.
  • FIG. 5 shows a correction term adder 14 that realizes the logic described in the column of correction term addition in FIG.
  • the arrangement of the exclusive OR gate and the AND gate is more regular than that in FIG. Therefore, the layout design of the semiconductor integrated circuit in FIG. 5 can be easier than that in FIG.
  • the first logic circuit is constituted by gate rows 14G and 14E.
  • the second logical operation circuit is constituted by gate rows 14B, 14D, and 14F.
  • the third logical operation circuit is constituted by gate rows 14A and 14C.
  • the number of gates used in the configuration of FIG. 5 is the same as that of FIG. 3 for the partial product adder 11 and the output adder 13, but the correction term adder 12 has 39 In this case, 68 AND elements and exOR are required as a whole.
  • the circled numbers indicate the required transmission time from the input to the point where the number is given, assuming that the signal transmission time of each of eXOR and the AD element is 1. means.
  • Critical paths are the paths for output bit Bok o 3. Therefore, the Galois multiplier shown in FIG. 5 is not substantially different from the configuration in FIG. 3 in terms of the operation speed, but is superior in the layout of the correction term adder 14 as described above. I have.
  • the two examples of the Galois multiplier are based on a method of replacing the higher-order terms X 6 , ⁇ 5 , and X 4 with lower-order terms x 3 , x 2 , x 1 , and x ° as coefficients of a primitive polynomial c n
  • the calculation of the multiplier and the multiplicand coefficients an and b n I did it.
  • the coefficients c n and the multiplier of the primitive polynomial and the coefficients a n and b n of the multiplicand are calculated successively.
  • the unit circuit in each column of the array is an exclusive OR gate (e X) of the output of the uppermost unit circuit of the array in the preceding column and the corresponding partial product addition value as a common input for each column.
  • e X exclusive OR gate
  • an AND gate is generated by the AND gate 15 C, and an exclusive OR gate (eXOR) 1 of the value of the AND and the output of the unit circuit at the same order position in the front row is generated. It has a function to generate Galois sum by 5D and output it.
  • the unit circuits in the first column have the common input
  • the unit circuits of the second column and lower arrays are the exclusive OR of the output of the uppermost unit circuit of the immediately preceding array and the corresponding partial product addition value as the common input.
  • Gate (ex OR) Generates output by receiving Galois sum by 15B. The lowest unit circuit of each array does not have the exclusive OR gate 15D.
  • the force correction term adder 15 is composed of 20 gates. This is realized by 49 AND elements and exOR. Also, in FIG. 7, the numbers enclosed by circles are, as described above, the distance from the input to the point where the number is attached when the signal transmission time of each of the eXOR and the AND element is set to 1. Means the required transmission time.
  • the critical path is a path for obtaining the output bit Bok o 3, that time has become ⁇ length than the fifth FIG. Therefore, the Galois multiplier shown in FIG. 7 is inferior to the configuration of FIG. 5 in terms of operation speed, but is much better in terms of the layout of the correction term adder 15.
  • the Galois multipliers described so far are based on the number of bits in the multiplier and multiplicand.
  • the logic was constructed using the general formula as shown in the above (Equation 17) which does not limit the primitive polynomial at all.
  • Bok Gallo ⁇ body GF (2 4) are known to be two types, there is a waste in the logical structure of the primitive polynomial and complete formula. Therefore, if the primitive polynomial is limited to the extent that it can be used, some order coefficients may always be zero, which may make the hardware of the correction term adder for those coefficients inefficient. It can be partially omitted, and it becomes possible to configure a Gaa multiplier with a small logical scale.
  • FIG. 8 in the general form of the primitive polynomial (Equation 17), when assuming a case coefficients c 2 of degree X 2 is zero, the logic of the correction term addition portion of the auxiliary Seiko addition field Is shown in FIG. 9 shows a configuration of the correction term adder 16 that realizes the logic.
  • FIG. 9 shows, as an example, a structure obtained by further developing the configuration of FIG. 7, but also for the configurations of FIGS. 2 and 3, and FIGS. 4 and 5, c It is possible to omit the logic related to 2 and make the same improvement as above.
  • FIG. 10 shows an example of a Galois multiplier in which the logical configuration of FIGS. 6 and 7 is extended to multiplication of an 8-bit Galois number.
  • the partial product adder 11X and the correction term adder 15X both use the same unit circuit 19.
  • the unit circuit 19 is an AND gate 17 which takes a logical product of the inputs P and A, and an exclusive logic is provided for the output of the AND gate and the input B.
  • GD is the ground potential of the circuit and supplies a signal with a logical value of "0".
  • a Galois multiplier can be realized by a very regular gate arrangement.
  • the circled numbers mean the required transmission time from the input to the point marked with the number, assuming that the signal transmission time of each of eXOR and the AND element is 1. I do.
  • Critical path is a path for obtaining the output bit o 7.
  • FIG. 11 shows an embodiment for increasing the speed of the embodiment of FIG.
  • the delay time until the multiplication output is obtained is relatively long.
  • the correction term adder 15 X employs a configuration in which the order is reduced successively and linearly while calculating the coefficient c n of the primitive polynomial and the multipliers a n and b n of the multiplicand.
  • a signal which is commonly applied to the output of the uppermost unit circuit 19 of the array via the exclusive OR gate 15B is provided to the next unit circuit 19.
  • the speed of the drive input signal D k (k 2 2 to 8) of each column in the correction term adder 15 Y is increased.o
  • the drive input signal Dk of each column is obtained by exclusive-ORing the drive input signal Dk-1 of the previous array with the AND gate 17 of the unit circuit 1.9. — Formed through gate 18 and exclusive OR gate 15B. In Fig. 11, such an exclusive OR gate 15B has been abolished. Assuming that the signal transmission time in each of the AND gate 17 and the exclusive OR gate 18 is 1 as shown in FIG.
  • FIG. 10 the delay time between the signal Dk and the signal Dk-1 is 2 Becomes To shorten this, Figure 11 shows that the C7 signal in each column is Receiving unit circuit 19 A, 19 B and unit circuit 19 B, 19 A in the final array of correction term addition Combining exclusive OR circuit 18 A, 18 C with selector circuit 18 B
  • the exclusive OR circuit 13A for receiving the Kn and Zn signals in FIG. 10 and the exclusive OR circuit 15B in FIG. 10 are omitted.
  • the selection signal of the selector circuit 18B is a drive input signal Dk of each column.
  • the unit circuit 19 A receiving the signals C 7 and D 8 and the unit circuit 19 A receiving the signals C 0 and D 2 select the exclusive OR circuit 18 A and its one input and output It is composed of a selector circuit 18B.
  • a unit circuit 18B that receives the signal C7 and other Dk signals and outputs Z2 to Z8 in the last column is a unit circuit 19B, which is an exclusive OR circuit 18A and one of its inputs.
  • the signal is output through an exclusive OR circuit 18C that takes the exclusive OR of the output of the selector circuit 18B and the output from the front row. .
  • the transmission time of the selector circuit 18B is faster than that of an AND gate or an exclusive OR circuit, and the transmission time is about 0.5, so that signal transmission can be performed. Therefore, the delay time between the signal Dk and the signal Dk-1 in this embodiment is 0.5, C7 and other Dk signals in the unit circuit 19A receiving the signals C7 and D8.
  • the receiving unit circuit 19 B is 1.5.
  • the total delay time until obtaining the multiplication output is 13 and it is possible to speed up by 38% compared to the delay time 2 1 in Fig. 10.
  • the Galois multipliers described so far have a small number of ⁇ and a partial product adder 1 1 (1 1 X) and a correction term adder 1 2 (1 4, 15, 1). 6, 15X, 15Y), and when the correction term adding section does not have an output adding function, an output adding section 13 (13X) is further provided.
  • FIG. 13 shows an example of a Galois multiplier that can supply the coefficients of a primitive polynomial via a decoder. That is, a decoder 20 that decodes the primitive polynomial and supplies the decoded result to the correction term adder 21 is added.
  • FIG. 14 shows an example of the decoder 20 and the correction term adder 21 shown in FIG. FIG. 14 shows the configuration when a decoder is added to the configuration of FIG.
  • an example is shown in which the correction term adder 21 is applied to Galois multiplication of a Galois field GF (2 n ), in particular, a 4-bit Galois number in the case of n24.
  • the n-th order is the order n (2 4).
  • the exclusive OR circuit 21D receives the output from the unit circuit 21B at the position and the product and generates and outputs a first Galois sum, and the order n of each column is provided.
  • the output of the unit circuit 2 1 B at the highest position in the array is exclusive with the corresponding partial product addition values G 3 and G 2
  • the second Galois sum is generated by the OR circuit 21E.
  • the unit circuit 21A having an order n or less of each column of the array receives the second Galois sum as a common input, and receives the common input and the unit circuit 21A of each column.
  • a product is generated by an AND gate 21F, and an exclusive logic is generated by receiving the output from the unit circuit 21A at the same order position in the front row and the product. It has the function of generating and outputting the third Galois sum by the sum circuit 21G.
  • the value (G 4 ) of the highest order 2 n ⁇ 1 of partial product addition is input as a common input for the order n + 1 or more and the order n or less, and an output is generated.
  • the input common to the order n + 1 or more is the corresponding partial product addition value (G 3 ).
  • the input common to the order n or less is Is the third Galois sum output from the corresponding exclusive OR circuit 21E.
  • the Galois sum with the bit is the result of the multiplication.
  • FIG. 15 shows the differences between the signal logic of nodes D 2 , D 3 and D 4 in FIG. 7 and the signal logic of the same nodes D 2 , D 3 and D 4 in FIG. .
  • the value of the node D 3 depends on the value of the node D 4 in the preceding stage, and the value of the node D 2 is in the preceding stage. It depends on the values of the nodes D 3 and D 4 .
  • the value of the node D 3 does not depend on the value of the preceding node D 4 but the value of the node D 2 Is a logical configuration that does not depend on the values of the preceding nodes D 3 and D 4 .
  • Relationship after deployment of the first 5 diagrams are those from the right side expression of more substitution method was erased D 3, D 4.
  • the values of the nodes D 2 and D 3 of the correction term adder 21 are theoretically the values of the nodes at the subsequent stage. It will be appreciated that it has no time effect on the confirmation. Therefore, the Galois multiplier employing the correction term adder 21 and the decoder 20 shown in FIG. The calculation processing can be performed at a higher speed than in the figure. That is, the critical path output Z 4 signal transmission time of the correction term addition unit 2 1 is a 7, are shorter than 8 in the case of Figure 7.
  • the numbers with circles have the same meaning as described above.
  • FIG. 16 shows an example in which a decoder 22 is employed for the configuration of the correction term adder of FIG.
  • the first 7 Figure differs from the signal logic of the same node D 2 ⁇ D 8 of the signal logic and the first 4 view of nodes D 2 to D 8 of the first 0 diagram is shown.
  • the Gaa multiplier employing the correction term adder 23 and the decoder 22 shown in FIG. 16 can realize a higher speed of the arithmetic processing as compared with FIG. That is, during the time of signal transmission of the output Z 8 of the critical path in the correction term addition unit 2 3 is a 11, is reduced to about half of the 20 in the case of the first 0 FIG.
  • the circled numbers have the same meaning as described above.
  • FIG. 18 shows a block diagram of a Galois multiplier in which the partial product adder and the correction term adder are further speeded up.
  • the n-bit multiplicand is decoded by the decoder 30 and supplied to the partial product adder 31.
  • the output of the partial product adder 31 is decoded by the decoder 26.
  • To the correction term adder 25 To the correction term adder 25.
  • FIG. 19 shows the logical configuration of the partial product adder 31 corresponding to the configuration of FIG.
  • the coefficient of the partial product of Xa * Xb is calculated for each degree by b. , T ⁇ , organized in b 2 J b 3.
  • the coefficients in column (2) are selected according to the decoding results of the coefficients b 3 and b 2 of the multiplicand x 3 and X 2 , and the coefficients in column (1) are similarly calculated by the multiplicand X 1 , x ° coefficient bb. Select according to the decoding result of. Before that, the manner of selection in each of columns (1) and (2) is shown in column (3) of FIG.
  • FIG. 20 shows an example of the decoder 30 and the partial product adder 31 that specifically realize the logic of FIG. Decoder 30 is multiplicand b. , B 1 , b 2) Convert each bit of b 3 into inverted and non-inverted signals.
  • the partial product adder 31 has two arrays of selectors 32, 33, 33, 33, 33, 32, and the selector of each array is in accordance with the logic in the column (3) in FIG. Select input.
  • FIG. 21 An example of the selector 32 is shown in FIG. 21 and an example of the selector 33 is shown in FIG.
  • the circled numbers shown in Fig. 20 indicate that the signal transmission time of each of the exclusive OR gate and AND gate is 1 and that the signal transmission time of Imba overnight is 0.5, from the input to that point. This shows the signal transmission delay time.
  • the transmission time to the output K 4 in the partial product addition unit 11 in FIG. 7 is 4, and the signal transmission time to the output ⁇ 4 can be reduced to 3 in the configuration of FIG. This reduction rate of the transmission time becomes more remarkable when the number of bits of the multiplier and the multiplicand (the number of bits of the Galois number) is increased.
  • the second 3 when applying 8 to the partial-product addition unit 3 first Galois multiplier which candidate operation Galois number of bits Bok FIG. 20 of the configuration shown in FIG.,
  • the first 0 in the structure of kappa 8 The delay time until the output is obtained is 8, but it can be reduced to ((about half (5/8)). In other words, the processing speed of partial product addition is about twice as fast.
  • the decoder 30 performs decoding in units of two bits, and the selectors 32, 33, 33, 33, 33, 33, 33, 33, 33, 33 There are provided four rows of 33 and 32 arrays.
  • the actual logic in FIG. 23 can be easily understood by referring to the logic in FIG. 19, and is not shown. ⁇ Error correction by lidoso-Romon code ⁇
  • FIG. 24 shows an example of a typical flow chart of the error correction processing using the Reed-Solomon code.
  • the error correction processing flow is as follows: Syndrome operation (S 1), input operation (Euclidean algorithm) S 2, Chien search (error position search) S 3, error value calculation S for input data 4 and correction S5.
  • the syndrome operation S 1 calculates a coefficient of a syndrome polynomial using a series of received codes as inputs. Here, if the coefficients of the syndrome polynomial are all zero, it is understood that there is no error in the received code. If it is determined that there is no error, the processing after S2 is omitted and the processing ends. If you find an error, start the correction process.
  • an error locator polynomial and an error numerical polynomial are calculated from the syndrome polynomial by a step operation S2.
  • the position of the error and the number of errors are obtained.
  • the numerical value of the error is calculated based on the position (S 4), the error is corrected S 5, and the process is terminated.
  • the Reed-Solomon code is defined using the number of Galois fields, and the above-described addition and multiplication on the Galois field are frequently used in the processing of the syndrome operation S1, the Euclidean operation S2, and the Chien search S3. Is done.
  • the Galois multiplier can be used for such multiplication.
  • FIG. 25 is a block diagram showing an example of a circuit for performing a syndrome operation, a leak operation, and a Chien search.
  • Each circuit block is provided with two Galois multipliers 40 and an adder 41.
  • the Galois multiplier 40 has any configuration described with reference to FIGS. 1 to 24.
  • the circuits for performing the syndrome operation, the Euclidean operation, and the Chien search have their own hardware and are configured as one semiconductor integrated circuit.
  • Primitive polynomials are commonly given to the respective Galois multipliers 40 from the coefficient setting means 3.
  • X a and X b are a multiplier and a multiplicand. Therefore, when different primitive polynomials are set in different systems, the coefficients of the primitive polynomial can be set arbitrarily.
  • FIG 26 shows a block diagram of an example of a microphone processor specialized in error correction using the read'Solomon code.
  • the microprocessor 50 shown in the figure includes a program memory 55 storing an operation program of the microprocessor 50, and a control unit 5 which decodes an instruction fetched from the program memory 55 and generates a control signal. 1, an operation unit 52 controlled by the control signal, an interface unit 53 for interfacing the operation unit 52 with the outside, and a memory unit 54 used as a work area of the operation unit 52 And a single semiconductor substrate such as single crystal silicon.
  • the operation unit 52 has a Galois multiplier 56, an adder 57, a register 58, and the like.
  • the Galois multiplier 5 6 is used for Galois multiplication between the elements of the Galois field GF (2 n ), and the Galois field GF (the coefficient of the two elements and the Galois field GF).
  • the original coefficient of (2 n ) and the coefficient of primitive polynomial are input, and the calculation of the coefficient for obtaining the Galois multiplication result is performed on a plurality of different primitive polynomials by the same hardware. It has any of the configurations described in Fig. 1 to Fig. 24.
  • the coefficients of the primitive polynomial are provided from the control unit 51 according to a program, for example.
  • the microprocessor 50 executes, for example, the syndrome calculation, the Euclidean calculation, and the Chien search in accordance with the operation program stored in the program memory 55. That is, Sof Twe The functions equivalent to those in Fig. 25 are realized by the software.
  • FIG. 27 is a block diagram of a disk drive system used for recording information on a storage medium and reproducing recorded information.
  • the storage media handled by the disk drive system shown in the figure is not particularly limited, but is both the MO and DVD media 60.
  • the medium 60 is driven to rotate by the disk drive 61.
  • the pickup section 62 includes a pickup for M0 and a pickup for DVD, and includes an actuator for focusing and tracking.
  • the servo control of the pickup is performed by the servo circuit 64.
  • the information read from the pickup is amplified by the preamplifier 63, the high-frequency signal is given to the encoding / decoding processing section 67, and the servo error signals for tracking and intelligent focusing are sent to the servo circuit 64. Given to.
  • the write signal to the medium 60 is supplied from the encoding / decoding processing section 67 to the pickup section 62 via the driver 65.
  • the control unit 66 is interfaced with a host system (not shown), and controls the entire disk drive system.
  • the encoding / decoding processing unit 67 is interfaced with a host system (not shown), and decodes information read from the medium 60 and encodes information to be written to the medium 60.
  • a parity for error correction is generated. Error correction is performed in decoding. Error correction at the time of decoding is performed by the error correction unit 68.
  • the error correction unit 68 includes any one of the Galois multipliers described with reference to FIGS.
  • the error correction processing unit 68 uses a primitive polynomial selected from a plurality of types of primitive polynomials.
  • the error correction processing section 68 can be constituted by the microprocessor 50 or the like.
  • the servo circuit 64 performs servo control according to the type of medium. Servo circuit 64 is used to recognize the type of medium. First, at the beginning of the training period, a tracking and focusing servo for M0 is performed. Since the depth of focus and the track pitch differ depending on the type of the medium 60, the tracking and focusing servo errors actually exceed the allowable range when a DVD is mounted.
  • the servo circuit 64 When detecting this state, the servo circuit 64 recognizes that the mounted medium is a DVD. If the servo error is within the allowable range, the mounted medium is recognized as MO. In this sense, the servo circuit 64 in the system shown in FIG. 27 is an example of a medium recognizing means.
  • the medium recognition result by the servo circuit 64 is given to the selector 69 as an automatic switching signal 71.
  • the selector 69 is supplied with a manual switching signal 72 via the switch 70.
  • the selector 69 selects either the automatic switching signal 71 or the manual switching signal 72 according to the operation mode of the system.
  • the selected switching signal selects a primitive polynomial to be supplied to the error correction processing unit 68.
  • Primitive polynomial is normalized to the MO, an x 8 + x 5 + x 3 + x 2 + 1, primitive polynomial that is standardized on a DVD, x 8 + x 4 + x 3 + x 2 + Is one.
  • the switching signal 73 selected by the selector 69 indicates ⁇
  • the former primitive polynomial is supplied to the error correction processor 68
  • the latter primitive polynomial is supplied to the error correction processor 68.
  • FIG. 28 shows a block diagram of a satellite broadcast receiving apparatus used for reproducing information from broadcast media.
  • the broadcast media handled by the satellite broadcast receiving apparatus shown in the figure is not particularly limited, but broadcasts A and A from representative broadcast stations 80 and 81 are shown.
  • Broadcast A, ⁇ uses geostationary satellite 82 It can be received by the satellite-side transmitting / receiving device 89.
  • the satellite transmission / reception device 89 receives the broadcasts A and B with the tuner 83.
  • the broadcast to be received by the tuner 83 can be selected by the switch 84.
  • the video signal and the audio signal received by the tuner 83 are encoded by the encoding processing unit 85, subjected to error correction, and given to the image forming unit 88 for reproduction.
  • Error correction at the time of decoding is performed by the error correction processing unit 86.
  • the error correction processing unit 86 includes any one of the Galois multipliers described with reference to FIGS. 1 to 24, and performs error correction using the read-Solomon code using the Galois multiplier and the adder. Do.
  • the error correction processing unit 86 uses a primitive polynomial selected from a plurality of types of primitive polynomials.
  • the error correction processing unit 86 can be constituted by the microprocessor 50 or the like.
  • the selection of the primitive polynomial is synchronized with the tuning by the switch 84.
  • the primitive polynomial used for each broadcasting station is different. Therefore, by switching the switch 84 for switching the broadcast by the receiver, the error correction can be performed using the same Galois multiplier on the same system even in the broadcast with different primitive polynomials.
  • the number of Galois bits to be multiplied is not limited to 4 bits or 8 bits, but may be other values.
  • the location is not limited to MO or DVD, but may be another medium such as CD-ROM.
  • the present invention provides a Galois multiplier and a CD-ROM used for encoding or decoding a Reed-Solomon code defined using the number of Galois fields.
  • a Galois multiplier and a CD-ROM used for encoding or decoding a Reed-Solomon code defined using the number of Galois fields.
  • Error correction processing in a recording information reproduction device or information recording / reproduction device for recording media such as DVD (Digital Video Disc M0 (Magnet Optics)
  • a data processing system such as a satellite communication terminal

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Abstract

L'invention concerne un circuit intégré à semi-conducteurs comportant un multiplicateur de Galois permettant la multiplication à l'aide d'une pluralité de polynômes primitifs différents. Ce circuit intégré à semi-conducteurs (1) renferme un multiplicateur de Galois (2) utilisé pour la multiplication de Galois des éléments d'un corps de Galois GF (2n). Les coefficients (5, 4) des éléments du corps de Galois GF (2n), lesquels sont le multiplicateur et le multiplicande, et les coefficients (6) des polynômes primitifs sont introduits dans le multiplicateur de Galois. Ces coefficients sont soumis à des opérations arithmétiques pour différent polynômes primitifs, avec le même matériel, en vue d'obtenir les résultats de la multiplication de Galois. Un organe de réglage de coefficients (3) fournit les coefficients des polynômes primitifs du corps de Galois GF (2n). Cette structure permet au multiplicateur de Galois d'effectuer la multiplication sur le corps de Galois correspondant aux polynômes primitifs fournis par l'organe de réglage de coefficients. Ce circuit intégré à semi-conducteurs peut donc s'utiliser avec une grande souplesse pour le codage ou le décodage des codes de correction d'erreurs des différents corps de Galois qui sont respectivement définis pour les différents polynômes primitifs.
PCT/JP1997/003367 1997-09-24 1997-09-24 Circuit integre a semi-conducteurs et systeme de traitement de donnees WO1999016175A1 (fr)

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Cited By (7)

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JP2001056640A (ja) * 1999-08-19 2001-02-27 Toyo Commun Equip Co Ltd 積和演算装置及びこれを用いた暗号・復号装置
JP2001109376A (ja) * 1999-10-04 2001-04-20 Toyo Commun Equip Co Ltd 演算回路および演算プロセッサ
JP2006503382A (ja) * 2002-10-09 2006-01-26 アナログ デバイシーズ インク 小型ガロア体乗算器エンジン
JP2010102351A (ja) * 2003-05-16 2010-05-06 Analog Devices Inc 複合ガロア体エンジンおよびガロア体除算器および平方根エンジンおよび方法
KR20140034677A (ko) * 2012-09-12 2014-03-20 삼성전자주식회사 갈로아체 연산 회로 및 메모리 장치
KR20140034678A (ko) * 2012-09-12 2014-03-20 삼성전자주식회사 에러 검출 정정 회로 및 반도체 메모리
KR20140039980A (ko) * 2012-09-24 2014-04-02 삼성전자주식회사 오류 위치 탐색 회로, 그리고 그것을 포함하는 오류 검출 정정 회로 및 메모리 장치

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JP2001056640A (ja) * 1999-08-19 2001-02-27 Toyo Commun Equip Co Ltd 積和演算装置及びこれを用いた暗号・復号装置
JP2001109376A (ja) * 1999-10-04 2001-04-20 Toyo Commun Equip Co Ltd 演算回路および演算プロセッサ
JP2006503382A (ja) * 2002-10-09 2006-01-26 アナログ デバイシーズ インク 小型ガロア体乗算器エンジン
JP4739020B2 (ja) * 2002-10-09 2011-08-03 アナログ デバイシーズ インク 小型ガロア体乗算器エンジン
JP2010102351A (ja) * 2003-05-16 2010-05-06 Analog Devices Inc 複合ガロア体エンジンおよびガロア体除算器および平方根エンジンおよび方法
KR20140034677A (ko) * 2012-09-12 2014-03-20 삼성전자주식회사 갈로아체 연산 회로 및 메모리 장치
KR20140034678A (ko) * 2012-09-12 2014-03-20 삼성전자주식회사 에러 검출 정정 회로 및 반도체 메모리
KR102027949B1 (ko) 2012-09-12 2019-10-02 삼성전자주식회사 에러 검출 정정 회로 및 반도체 메모리
KR102064857B1 (ko) 2012-09-12 2020-02-11 삼성전자주식회사 갈로아체 연산 회로 및 메모리 장치
KR20140039980A (ko) * 2012-09-24 2014-04-02 삼성전자주식회사 오류 위치 탐색 회로, 그리고 그것을 포함하는 오류 검출 정정 회로 및 메모리 장치
KR102021560B1 (ko) 2012-09-24 2019-09-16 삼성전자주식회사 오류 위치 탐색 회로, 그리고 그것을 포함하는 오류 검출 정정 회로 및 메모리 장치

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