JPH04365139A - Syndrome operation circuit for error correction processing - Google Patents

Abstract

PURPOSE:To increase the processing speed by increasing the number of bus lines between a data storage memory and a syndrome operation circuit and processing the syndrome operation in parallel to reduce the data transfer rate between these memory and operation circuit. CONSTITUTION:The number of bus lines between a data storage memory 1 and a syndrome operation circuit 1 is increased to process the syndrome operation in parallel. That is, alpha is defined as the primitive element of a Galois field GF(q<m>) (q: prime number m: natural number), and (k) is defined as a natural number which can divide (n). At this time, (n) information words D0...Dn-1 in every (k) words of the memory 1 are collected to generate a matrix of (k) rows and (n/k) columns. Respective rows are successively or simultaneously inputted to a dividing circuit 6 of (k) polynomials (x-alpha<ki>) from data of (n/k) columns through (k) bus lines. (k) outputs are added after passing multipliers 3, 4, and 5 of (alpha<0>...alpha<(k-i)i>. Thus, the operation is possible with 1/k transfer rate.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction code device used for recording and reproducing digital data.

0002

2. Description of the Related Art Conventional techniques are shown below.

[0003] The target data string is {D0, D1, D
2, ... D(n-2}, D(n-1)}. This is first stored in memory. For example, when performing error correction processing using a Reed-Solomon code, the minimum distance is d. It is possible to correct errors up to int((d-1)/2) words and detect errors up to int(d-1) words, but in order to perform these operations, a syndrome expressed by the following formula is required. It is known that in Si, (d-1) syndromes from i=t to (t+d-2) are required, where t is 0 or any natural number.

As a calculation method for these syndromes, n pieces of data stored in memory are sequentially input one by one from D(n-1) to a division circuit using a polynomial (x-αi) shown in FIG. The method used is to obtain the output after inputting all data.

[0005]

[Problem to be solved by the invention] The error correction processing time is
It is known that when the correction ability of decoding is low or during encoding, the syndrome calculation time during the processing becomes dominant. According to the conventional technology, data is read out from the memory one by one, so there is a problem in that if a memory with a slow access time is used, the processing time will be significantly increased. This effect is particularly large when the data length is long.

[0006]

[Means for solving the problem] In an error correction device used for recording and reproducing digital data, α is set to a Galois field G.
When F(qm) is a k primitive element, and k is a natural number that divides n, then n information words D0, input to the memory,
D1,...D(n-2), D(n-1) are grouped into k words to generate a matrix of k rows and n/k columns as shown below, D0 Dk ・
... D(n-k)D1 D(k
+1)...D(n-k+1)・
・
・・・
・・・
・ ・D(k-
1) D(2k-1)...
Each row of D(n-1) is input sequentially from data in (n/k) columns, and data on the same column is simultaneously input to a division circuit using k polynomials (x-αki) through k bus lines. do.

Since the k outputs are as follows,
1st line: α(n-k) iD(n-k) +α(n-2
k) iD(n-2k) +...+αkiDk
+D0 2nd row: α(n-k)iD(n-k+1)+α
(n-2k)iD(n-2k+1)+...+αkiD
(k+1)+D1 ・
・
・ ・
・
・ ・
・ ・
・
・ ・Kth line: α(
n-k)iD(n-1)+α(n-2k)iD(n-k
-1)+...+αkiD(2k-1)+D(k-1) Syndrome is created by adding after passing through the multipliers of α0(=1), αi, ...α(k-1)i, respectively. Si
seek.

In addition, if k is a natural number that does not divide n, a matrix of k rows and ((n+h/k) columns is generated as shown below using h zeros for the missing data, and similarly to ask.

[0009] D0 Dk...
D(n-2}D1 D(k+1
) ... D(n-1)D2
D(k+2)...0・
・ ・
・ ・
・・・
・D(k-1) D
(2k-1) ... 0

0010

[Operation] The above means makes it possible to perform syndrome calculations while reducing the data transfer rate from the memory to 1/k of the conventional rate. In other words, the number of times data is read from the memory is reduced to 1/k of the conventional rate. Even if a memory with a slow time is used, an increase in correction processing time can be prevented.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to FIG.

FIG. 1 shows a syndrome calculation circuit for error correction processing according to an embodiment of the present invention, and shows one embodiment in which k=3 and n=12.

In FIG. 1, 1 is a data storage memory;
2 is a flip-flop, 3 is α3i multiplier, 4 is αi
, 5 is the multiplier for α2i, 6 is the polynomial (x-α3
i) is a division circuit, and 7 is an adder.

First, the 12 information words D0, D1, . . . D10, D11 stored in the memory 1 are grouped into three words to generate a matrix with 3 rows and 4 columns as shown below.

0015 D0 D3 D6 D9D1
D4 D7 D10 D2 D5 D8 D11 In this matrix [D0 D3 D6
D9] is the 1st row, [D1 D4 D7D10] is the 2nd row, and [D2 D5 D8 D11] is the 3rd row, and data on the same column is written one by one from D9, D10, and D11 in each row at the same time. , three polynomials (x−α
3i) is input to the division circuit 6. After inputting all data, the output is: 1st line: α9iD9 + α6iD6 + α3iD3 + D0
2nd row: α9iD10+α6iD7+α3iD4+D1
3rd row: α9iD11+α6iD8+α3iD5+D2
becomes. If this is added after the first row is passed through the multiplier 4 of αi in the second row, and the multiplier 5 of α2i is added in the third row, the syndrome Si is obtained as Si = 3rd row × α2i + 2nd row × αi + 1st row =
α11iD11+α10iD10+α9iD9+α8i
D8+α7iD7+α6iD6
+α5iD5+α4iD4+α3iD3+α2iD
2+αiD1+D0 is obtained. Since the data on the same column in the first, second, and third rows are read out from memory 1 one by one at the same time,
The number of times of reading is only four times for 12 pieces of data.

[0016] Also, if n is not divisible by 3 (=k), add zero to the missing part to make 3 as shown in the example below.
You can use the same procedure for a matrix of rows.

D0 D3...D(n-2)
D0 D3...D(n-1) D1 D4
...D(n-1) D1 D4
...0 D2 D5 ...0
D2 D5...0

[0018]

As is clear from the above explanation, the syndrome calculation circuit of the present invention enables syndrome calculation with the data transfer rate from the memory reduced to 1/k of the conventional rate, thereby improving data storage. Even if the access time of the storage memory is slow, it can be operated at high speed, contributing to speeding up the correction processing time.

[Brief explanation of the drawing]

FIG. 1 is an embodiment of a syndrome calculation circuit for error correction processing according to the present invention.

[Figure 2] Polynomial (x-αi
) is a division circuit.

[Explanation of symbols]

1 Data storage memory 2 Flip-flop 3 α3i multiplier 4 αi multiplier 5 α2i multiplier 6 Division circuit using polynomial (x-α3i) 7 Adder

Claims (2)

[Claims] Claim 1: In an error correction device used for recording and reproducing digital data, α is expressed as a Galois field GF(qm) (
q: prime number, m: natural number), and k is a natural number that divides n, then n information words D0, D1, ... D(n-2), D( n-1)
are grouped into k words, k lines as shown below, (n/k)
Generate a matrix of columns, D0 Dk...
D(n-k)D1 D(k+1
)...D(n-k+1)・
・・・
・
・・・
・D(k-1) D(
2k-1) ... Each row of D(n-1) is sequentially processed from the data in the (n/k) columns, and the data on the same column is simultaneously processed using k polynomials (x
- αki), and the k outputs are added after passing through multipliers α0 (=1), αi, ...α(k-1)i, respectively. Syndrome calculation circuit for error correction processing. Claim 2: In an error correction device used for recording and reproducing digital data, α is expressed as a Galois field GF(qm) (
q: integer, m: natural number), and k is a natural number that does not divide n, then n information words D0, D1, ... D (n-2), D input to the memory (n-
1) for each word, and use h zeros for missing data to generate a matrix of k rows and ((n+h)/k) columns as shown below, D0 Dk...
D(n-2)D1 D(k+1)
... D(n-1)D2
D(k+2)...0・
・ ・
・ ・
・・・
・D(k-1) D(2
k-1) ... 0 each row ((n
+h)/k) column data sequentially, and data on the same column are simultaneously transmitted through k bus lines to k polynomials (x
- αki), and the k outputs are added after passing through multipliers α0 (=1), αi, ...α(k-1)i, respectively. Syndrome calculation circuit for error correction processing.