JPH07226687A - Error correction processor - Google Patents

Abstract

PURPOSE:To obtain an error correction processor which is capable of performing the high speed processings of the encoding for which Reed Solomon(RS) code is used and the calculation of a syndrome with small circuit scale. CONSTITUTION:For input information 7, the encoding of an error correction or the calculation of a syndrome is performed. This device is provided with a ROM 1 storing the data of the generation matrix (G-Matrix) or the inspection matrix (H-Matrix) of a RS code, a multiplier 2 performing the multiplication of the data outputted from the ROM and the input information 7, an adder 3 performing the cumulative addtion of the output of the multiplier and latches 41 to 44 holding the addition values outputted from the adder. The values of the inspection bit and the syndrome in the encoding of the error correction are calculated in the form of a matrix calculation by the multiplier and the adder. In this device, circuitry can be made into small scale as compared with a conventional device using a shift register because the device becomes the circuit where the multiplication is mainly performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention performs error correction coding on data to be stored so that data can be stored correctly even if there is a defective portion in a part of a semiconductor memory or the like, and corrects errors when reading data. Error correction processing device,
In particular, it enables high-speed processing.

[0002]

2. Description of the Related Art In recent years, semiconductors have been highly integrated,
Therefore, disabling the entire chip when a part thereof has a defect causes a large loss. Therefore, various methods for relieving the defective portion have been considered.

One of the methods is a method in which an extra memory cell is made in advance inside a semiconductor, and when an initially defective cell is found, it is replaced with another cell. For example,
As shown in FIG. 3, when the capacity is satisfied by n memory cells, the memory cell 3 has a redundant portion of n + 1 or more, and when the memory cell 3 is initially defective, the memory cell 3 is replaced by the memory cell n + 1. . If the number of defects is less than the redundant portion, this method can repair the defective cell. However, although this method can remedy the initial failure that occurred during the manufacturing process of the semiconductor memory, it cannot deal with the failure of the memory cell that occurs during use.

When a semiconductor memory is used as a main memory of a computer, data is subjected to error correction processing in order to remedy a wide range of memory cell defects including cell defects that occur during use. Has been. In this method, when data is stored in the memory, error correction coding is performed on the data and the redundant data is stored in the memory. When data is read, error correction decoding is performed using the data read from the plurality of memory cells to obtain correct data. Therefore, even if a defective cell exists and the data is erroneously stored, the correct data can always be read.

Several types have been devised as codes used for error correction coding. SEC-DE
In the method using the D code, the matrix illustrated in FIG. 4 is used as the parity check matrix. The SEC-DED code is
It has the advantages that the encoder and decoder have simple circuit configurations and that the processing time for encoding and decoding is fast, but it has the drawback of high redundancy and consequently high memory costs. FIG. 5 shows the configurations of an encoder and a decoder for the SEC-DED code. The detailed description is omitted.

The RS code (Reed-Solomon code) is known as a code having the lowest redundancy among linear codes having the same code length and correction capability, and is used for satellite communication, magnetic disks, compact disks. It is widely used for error correction (Japanese Patent Laid-Open No. 63-164629).

The RS code is a kind of cyclic code. In the case of the cyclic code, the following coding is performed.
When the number of information points is k, the information is made to correspond to the coefficient of the information polynomial P (x) of order k−1, and then P (x) is set to x ^nk
This is multiplied, and this x ^nk P (x) is divided by the generator polynomial G (x) to obtain the remainder R (x).

X ^nk P (x) = Q (x) G (x) + R (x) (1) Then, the code polynomial F (x) is obtained by the sum of this x ^nk P (x) and the remainder R (x). Make up.

F (x) = x ^nk P (x) + R (x) = Q (x) G (x) (2) In equation (2), the exclusive logic of R (x) and R (x) Since the sum is 0, the code polynomial F (x) is always G (x)
Divisible by.

The syndrome for detecting a code error when decoding a cyclic code is a reception polynomial r (x).
And the quotient q when it is divided by the generator polynomial G (x)
It is calculated by the following equation using (x) and.

S (x) = r (x) −q (x) G (x) (3) The syndrome S (x) becomes 0 if the receiving polynomial r (x) does not include an error. Further, if an error is included, the value is not 0, and the error position and size information is included.

FIG. 6 shows a conventional cyclic code error correction coding circuit. Information bits are sequentially input to the encoding circuit, and the information bits are sequentially output to the communication path, and at the same time, input to the division circuits connected in multiple stages of the shift register. In the division circuit, division is performed by the generator polynomial G (x), and when the input of information is completed, the remainder in this division remains in the shift register, and this remainder is output to the communication path following the information. Also, the calculation of the syndrome is performed by the same circuit.

[0013]

The error correction method using the RS code has the advantages of low redundancy and high correction capability, but the RS code is used to perform the coding process and the error correction process. Since the conventional error correction processing device has a configuration in which information bits are input one by one and sequentially processed, it takes a lot of time for encoding and calculation of the syndrome, and a configuration such as GF (2 ⁸ ). When a finite field having a large number of bits is targeted, there is a problem that the number of stages of the shift register increases, the number of flip-flops and the like used increases, and the circuit becomes large in scale.

The present invention solves these conventional problems, and provides an error correction processing apparatus capable of high-speed processing of encoding using RS codes and calculation of syndromes with a small circuit scale. The purpose is to do.

[0015]

Therefore, according to the present invention, a Reed-Solomon (RS) code generation matrix (G-G) is used in an error correction processing apparatus that performs error correction coding or syndrome calculation on input information. R that stores data of Matrix) or check matrix (H-Matrix)
OM, a multiplier that multiplies the data output from the ROM and the input information, and a first that cumulatively adds the outputs of the multipliers
An adder and a latch that holds the added value output from the first adder are provided.

A plurality of multipliers are provided, and each multiplier is caused to multiply the data output from the ROM by the input information in parallel, and the outputs of the plurality of multipliers are added. Two adders are provided, and the output of the second adder is output to the first adder.

Further, the error correction processing device performs error correction coding of data stored in the semiconductor memory or operation of the syndrome of data read from the semiconductor memory.

[0018]

Therefore, the check bit and the value of the syndrome in the error correction coding are calculated by the multiplier and the first adder.
It is calculated in the form of matrix operation. This error correction processing device
Since the main circuit is multiplication, the circuit configuration can be reduced in scale as compared with the conventional one using a shift register.

Further, by providing a plurality of multipliers,
This operation can be processed in parallel, and the processing time can be shortened. Therefore, even when data is transmitted / received to / from a semiconductor memory that inputs / outputs data in units of 8 bits or 16 bits, error correction processing can be performed without delay.

[0020]

【Example】

(Embodiment 1) In the error correction processing apparatus of the embodiment, encoding by RS code and calculation of syndrome are obtained by matrix operation. Therefore, the matrix calculation formula will be described first.

The RS code is a kind of linear code, and the information i
= (I ₁ , i ₂ , i ₃ , ... i _k ) is codeword x = (i ₁ , i ₂ ,
i ₃ , ... I _k , P ₁ , P ₂ , ... P _nk ). The check symbols P ₁ , P ₂ , ... P _{nk at} this time are given by the following equations.

P ₁ = p ₁ , ₁ i ₁ + p ₁ , ₂ i ₂ + ... P ₁ , _{k ik} P ₂ = p ₂ , ₁ i ₁ + p ₂ , ₂ i ₂ + ... P ₂ , _{k i k ............ P nk = p} nk, 1 i 1 + p nk, 2 i 2 + ......... p nk, k i k (4)

Therefore, the generator matrix (G-Mat
rix)

[Equation 5] Codeword x = (i ₁ , i ₂ , i ₃ , ... I _k , P ₁ , P ₂ , ... P
_nk ) is given by x = iG (6).

The linear code is a simultaneous linear equation which is a parity check equation: h ₁₁ x ₁ + h ₁₂ x ₂ + ... ...... h _1n x _n = 0 h ₂₁ x ₁ + h ₂₂ x ₂ + ... ...... h _2n x _n = 0 …………………………… h _l1 x ₁ + h _l2 x ₂ + ……… h _ln x _n = 0 The solution x of (7) x = (x ₁ , x ₂ , ……… x _n ) Can be defined as any set of. This system of linear equations uses the parity check matrix given by

[Equation 8] It can be described as follows. xH ^T = 0 (9) The syndrome S has a reception code y = (y ₁ , y ₂ , ...
_n ) is converted by a parity check matrix, and S = yH (10). Therefore, each element of the syndrome is s ₀ = h ₁₁ y ₁ + h ₁₂ y ₂ + ... …… h _1n y _n s ₁ = h ₂₁ y ₁ + h ₂₂ y ₂ + ……… h _2n y _n ………… ... it is given by _{............... s l = h l1 y 1} + h l2 y 2 + ......... h ln y n (11). This syndrome includes the position and size of the error.

Now, the error correction processing apparatus of the first embodiment will be described. This error correction processing device can execute both RS coding and syndrome calculation. As shown in FIG. 1, this device includes a ROM 1 that stores a generator matrix G in the case of encoding and a check matrix H in the case of calculating a syndrome as data.
A multiplication circuit 2 that multiplies the input bit by the data stored in the ROM 1, an addition circuit 3 that cumulatively adds the outputs of the multiplication circuit 2, and latches 41, 42, 43, 44 that hold the intermediate result and final result of the operation. A selector 5 for sequentially selecting and outputting the data held in the latches 41 to 44; a selector 6 for distinguishing and outputting information and check symbols; and an input port 7.
And an output port 8. This input port 7
The information to be encoded is input at the time of encoding, and the code word read from the memory is input at the time of decoding. Further, from the output port 8, a code word is output at the time of encoding, and a calculation result of the syndrome is output at the time of decoding.

The operation in the case of using this apparatus to perform encoding using GF (2 ⁸ ), that is, an RS code having an original number of 2 ⁸ and a minimum distance of 5 will be described.

When the minimum code distance is 5, there are _four check symbols P ₁ , P ₂ , P ₃ , and P ₄ added to the codeword. In this case, four latches 41 to 44 are prepared (or four of many prepared latches are used). That is, the number of latches is the same as the number of check symbols, and is the value obtained by subtracting 1 from the minimum distance.

In the case of encoding, the information i = (i ₁ , i ₂ , i ₃ , ... I _k ) input from the input port 7 is the code word x =
(I ₁ , i ₂ , i ₃ , ..., i _k , P ₁ , P ₂ , P ₃ , P ₄ ) are encoded and output from the output port 8. The check symbols P ₁ , P ₂ , P ₃ , and P _{4 at} this time are given by the following equations.

P ₁ = p ₁ , ₁ i ₁ + p ₁ , ₂ i ₂ + ... P ₁ , _{k ik} P ₂ = p ₂ , ₁ i ₁ + p ₂ , ₂ i ₂ + ... P ₂ , _{k ik} P ₃ = p ₃ , ₁ i ₁ + p ₃ , ₂ i ₂ + ... p ₃ , _{k ik} P ₄ = p ₄ , ₁ i ₁ + p ₄ , ₂ i ₂ + ... p ₄ , _k i _k (12)

In the case of encoding, first, when the information i ₁ is input to the input port 7, this information i ₁ is sent to the selector 6 and the multiplication circuit 2. At this time, the ROM ₁ sequentially reads p ₁ , ₁ , p ₂ , ₁ , p ₃ , ₁ , p ₄ , ₁ from the stored elements of the generator matrix and outputs them to the multiplication circuit 2. The multiplication circuit 2 is
The elements of the read generator matrix are sequentially multiplied by the information i ₁ ,
p ₁ , ₁ i ₁ , p ₂ , ₁ i ₁ , p ₃ , ₁ i ₁ , p ₄ , ₁ i ₁ are added to adder circuit 3
Output to. When p ₁ and ₁ i ₁ are input from the multiplication circuit 2 to the addition circuit 3, the selector 5 selects the latch 41 and outputs the value held by the latch 41 to the addition circuit 3. However, since the initial values of the latches 41 to 44 are all 0,
0 is output from the selector 5. The adder circuit 3 adds the value 0 output from the selector 5 and the p ₁ , ₁ i ₁ output from the multiplier circuit 2 and outputs the added value p ₁ , ₁ i ₁ .
The added values p ₁ and ₁ i ₁ are held in the latch 41.

Next, when p ₂ , ₁ i ₁ is input to the adder circuit 3, the selector 5 selects the latch 42, and the latch 42 is selected.
The value held by is output to the adder circuit 3. Adder circuit 3
Outputs the added value of the value (0) output from the selector 5 and p ₂ , ₁ i ₁ output from the multiplication circuit 2, and the added value p ₂ , ₁ i ₁ is held in the latch 42. . The same procedure is repeated, and the latch 43 receives p ₃ , ₁ i ₁ and the latch 44 receives p ₄ , ₁ i ₁ .
₁ i ₁ is retained.

On the other hand, at this stage, the selector 6 selects the data i ₁ input to the input port 7 and outputs it to the output port 8
Output from.

When the next information i ₂ is input to the input port 7, this information i ₂ is sent to the selector 6 and the multiplication circuit 2, and the ROM 1 selects p ₁ from the elements of the stored generator matrix. ₂ , p ₂ , ₂ , p ₃ , ₂ , p ₄ , ₂ are sequentially read and output to the multiplication circuit 2. The multiplication circuit 2 sequentially multiplies the read element of the generator matrix by the information i ₂ to obtain p ₁ , ₂ i ₁ , p ₂ ,
₂ i ₁ , p ₃ , ₂ i ₁ , p ₄ , ₂ i ₁ are output to the adder circuit 3. When p ₁ and ₂ i ₁ are input from the multiplying circuit 2 to the adding circuit 3, the selector 5 selects the latch 41 and supplies the values p ₁ and ₁ i ₁ held by the latch 41 to the adding circuit 3. Output and adder circuit 3
Is the p ₁ , ₁ i ₁ and the p ₁ , ₂ i ₁ output from the multiplication circuit 2.
The added value p ₁ , ₁ i ₁ + p ₁ , ₂ i ₁ obtained by adding and is output, and the added value is held in the latch 41.

[0034] Similarly, when p _{2, 2} i ₁ is inputted to the adding circuit 3, selector 5, p ₂ which holds the latch 42,
₁ i ₁ is output to the adder circuit 3, and the adder circuit 3 outputs the added value p ₂ ,
₁ i ₁ + p ₂ , ₂ i ₁ is output, and the added value is held in the latch 42. The same procedure is repeated, and the latch 43 receives p ₃ , ₁ i ₁
+ P ₃ , ₂ i ₁ and the latch 44 has p ₄ , ₁ i ₁ + p ₄ , ₂ i ₁
Is retained.

On the other hand, even at this stage, the selector 6 selects the data i ₂ input to the input port 7 and outputs it to the output port 8
Output from.

The above operation is repeated until the input of i _k is completed. When the input of i _k is completed, the latch
The _{41, p 1, 1 i 1} + p 1, 2 i 2 + ......... p 1, k i k is the latch _{42, p 2, 1 i 1} + p 2, 2 i 2 + ......... p _{2, k} i _k is the latch _{43, p 3, 1 i 1} + p 3, 2 i 2 + ......... p 3, k i k is,
Further, the latch _{44, p 4, 1 i 1 +} p 4, 2 i 2 + ......... p 4,
_k i _k is retained. During this period, i ₁ , i ₂ , ..., I _k are sequentially output from the output port 8. After the output of i _k is completed, the selector 5 determines that the latch 41, the latch 42, the latch 4
The data held in each latch is sequentially output in the order of 3 and the latch 44, and the selector 6 outputs the data output from the selector 5 to the output port 8.

Thus, from the output port 8, the code word x
= (I ₁ , i ₂ , i ₃ , ..., i _k , P ₁ , P ₂ , P ₃ , P ₄ ) is output.

Further, in the calculation of the syndrome at the time of decoding, the received codes y = (y ₁ , y ₂ , ... Y _n ) are sequentially input from the input port 7, and the ROM 1 is parity-checked according to the input of the received code. The elements h ₁₁ , h ₂₁ , h ₃₁ , ... Of the check matrix are output to the multiplication circuit 2, and the selector 6 causes the selector 5 to operate.
Is substantially the same as the case of encoding except that only the data finally output from is output to the output port 8.

This error correction processing apparatus can process the encoding and the calculation of the syndrome with the same circuit. Further, this device has an advantage that a circuit amount is smaller than that of a division circuit using a shift register, since a multiplication circuit mainly composed of a gate is the center of the circuit.

On a magnetic disk or magnetic tape, information is recorded and read in 1-bit units. On the other hand, in the semiconductor memory, recording and reading of information is performed in units of 8 bits or 16 bits. The error correction processing device of the embodiment can be used for any of them.
When handling 8-bit information, i _k and y _k are input to the input port 7 as 8-bit information.

(Embodiment 2) The error correction processing apparatus of the second embodiment enables the processing time to be shortened by parallelly multiplying the elements of the generator matrix or check matrix by the input bits. As shown in FIG. 2, this device includes two multiplication circuits 21 and 22 and two addition circuits 31 and 32.
The other structure is the same as that of the device of the first embodiment.

In this device, in the case of encoding, i ₁ and i
Paired information such as ₂ , i ₃ and i ₄ , ... Is input from the input port 7. An odd number of information i in this pair of information
₁ , i ₃ ... Are supplied to the multiplication circuit 21, and even-numbered information i ₂ , i 3
₄ ... Are input to the multiplication circuit 22, respectively. ROM1 is i
_When a pair of ₁ and i ₂ is input, p of the element of the generative determinant is
₁ , _1, and p ₁ , ₂ , p ₂ , _1, and p ₂ , ₂ , p ₃ , _1, and p ₃ , _2, and p
Output each pair of ₄ , ₁ and p ₄ , ₂ in order. Of this pair, p
₁ , ₁ , p ₂ , ₁ , p ₃ , ₁ , p ₄ , ₁ are input to the multiplication circuit 21, and p ₁ ,
₂ , p ₂ , ₂ , p ₃ , ₂ , p ₄ , ₂ are input to the multiplication circuit 22, respectively. When the ROM ₁ outputs p ₁ , ₁ and p ₁ , ₂ , the multiplication circuit 21 multiplies p ₁ , ₁ and i ₁ and outputs p ₁ , ₁ i ₁ , while the multiplication circuit 22 p ₁ , ₂ is multiplied by i ₂ to obtain p ₁ , ₂
i ₂ is output. In response to this, the adder circuit 32 changes the multiplication circuit.
The outputs of 21 and 22 are added, and p ₁ , ₁ i ₁ + p ₁ , ₂ i ₂ is output to the adder circuit 31. The operation after the adder circuit 31 is the same as that of the device of the first embodiment. The adder circuit 31 performs cumulative addition of the output of the adder circuit 32, and the added value is held in the latch 41.

Thus, the addition circuit 32 outputs the information i ₁
And i ₂ are input, p ₁ , ₁ i ₁ + p ₁ , ₂ i ₂ , p ₂ , _{1
i 1 + p 2, 2 i} 2, p 3, 1 i 1 + p 3, 2 i 2, p 4, 1 i 1 + p 4, 2
i ₂ are sequentially output, and the next pair of information (i ₃ and i
₄₎ When _{entered, p 1, 3 i 3 +} p 1, 4 i 4, p 2, 3 i 3 +
p ₂ , ₄ i ₄ , p ₃ , ₃ i ₃ + p ₃ , ₄ i ₄ , p ₄ , ₃ i ₃ + p ₄ , ₄ i ₄ are sequentially output. That is, the added value of the two terms of Expression (12) is sequentially output, and as a result, the encoding processing time is reduced to half that of the device of the first embodiment. The same can be said for the calculation of the syndrome.

Further, by further increasing the number of the multiplying circuits 21 and 22 and processing the multiplication of the elements of the generator matrix and the check matrix by the input information in parallel, the processing speed of encoding and syndrome calculation is further increased. be able to. For example, when there are two multiplication circuits, 16
Multiply circuit that sends and receives bit data and multiplies each 8 bits
21 and the multiplication circuit 22 can be processed. However, when the number of the multiplication circuits 21 and 22 is increased to 4, the exchange of data with the semiconductor memory is increased to 32 bits,
It becomes possible to process them in parallel at the same time. Therefore, the processing speed of error correction is significantly improved.

[0045]

As is apparent from the above description of the embodiments, the error correction processing apparatus of the present invention is a Reed-Solomon (R
S) The data of the generator matrix (G-Matrix) or the check matrix (H-Matrix) of the code is stored in the ROM, and the encoding or the syndrome calculation is performed by the matrix operation, so that the circuit scale can be reduced. .

By processing the multiplications in the matrix operation in parallel, the encoding and syndrome operations can be processed at high speed.

Therefore, the error correction processing device of the present invention is
Even when exchanging data with a semiconductor memory that inputs / outputs 8-bit, 16-bit, or 32-bit information, error correction processing of the data can be performed sufficiently following the speed. When used as a correction processing device, a particularly excellent effect can be exhibited.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an error correction processing device according to a first embodiment of the present invention,

FIG. 2 is a block diagram showing a configuration of an error correction processing device according to a second embodiment of the present invention,

FIG. 3 is a conceptual diagram showing a conventional defective portion replacement method for a semiconductor memory;

FIG. 4 is a diagram showing a parity check matrix of a conventional SEC-DED code;

FIG. 5 is a diagram showing a configuration of an encoding / decoding circuit using a conventional SEC-DED code;

FIG. 6 is a block diagram showing a configuration of a conventional encoding circuit using an RS code.

[Explanation of symbols]

 1 ROM 2, 21, 22 Multiplier circuit 3, 31, 32 Adder circuit 41-44 Latch 5, 6 Selector 7 Input port 8 Output port

Claims (3)

[Claims] 1. A Reed-Solomon (RS) code generation matrix (G-Matr) in an error correction processing device that performs error correction coding or syndrome calculation on input information.
ix) or a parity check matrix (H-Matrix) data, a multiplier that multiplies the data output from the ROM by the input information, and a first adder that cumulatively adds the outputs of the multipliers. And an latch for holding the added value output from the first adder. 2. A plurality of the multipliers are provided, wherein each multiplier multiplies the data output from the ROM by the input information in parallel, and adds the outputs of the plurality of multipliers. The error correction processing apparatus according to claim 1, wherein a two adder is provided, and an output of the second adder is output to the first adder. 3. The error correction processing apparatus according to claim 1 or 2, wherein error correction encoding or syndrome calculation is performed on the information exchanged with the semiconductor memory.