KR100480685B1 - Error correction circuit - Google Patents

Abstract

The error correction circuit reduces the processing time by modifying the algorithm of the Chien and Forney search blocks used in the Reed-Solomon error correction channel coding block. An adder for adding an omega value and an intermediate value fed back, a multiplier for multiplying the addition result of the adder and an input α exponent value, and a register for feeding back the output of the multiplier to the adder, 2t (t being an error correctable number) N-1 (N is the number of data in the block) consisting of zero detectors that form a magnetic loop for zero cycles and zero detectors by adding outputs of registers sequentially input for two t cycles. Simultaneously outputs results for N α exponents after 2t cycles, reducing processing time and reducing gate count At the same time, a small constant multiplier is used to reduce the size of the Chien or search block, while also reducing the critical path to enable faster clocks.

Description

Error correction circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction circuit, and more particularly, to modify and process the algorithms of the Chien and Forney search blocks used in Reed-Solomon error correction channel coding blocks. Error correction circuit that reduces time and simultaneously reduces the number of gates and critical paths.

In general, the Chien block is one of algorithms used to find an error position, and finds an error position by obtaining a root of a gamma (γ) polynomial γ (X) shown in Equation 1 below.

That is, when an index is increased to 0 by sequentially increasing the exponent from α ^{-N + 1} to α ⁰ in the gamma polynomial shown in Equation 1, the corresponding index of α becomes a position where an error occurs. .

If α ^p is the error position polynomial γ (X) = 0, then p is the error position value.

The pony block is one of algorithms for calculating an error correction value corresponding to an error position obtained from the chien block by substituting an α ⁱ value of 0 in the chien block into an omega polynomial. Omega (ω) polynomials such as

If the value of α ⁱ is substituted, the resulting polynomial value is a correction value of the error corresponding to the position of the error.

The circuit implementing this is shown in FIG. 1, and the Cien search block and the Pony search block have the same structure.

1 is a Chien search or Pony search block diagram for the i th term, the control unit 10 for outputting a calculation and selection signal of α ^{(−N + 1) i} (1 ≦ i ≦ 2t), and the control unit ( According to the selection signal of 10), the first multiplexer 11 and the control unit for selecting and outputting the i-th gamma value γ _i or the i-th omega value ω _i value initially input in parallel, and then selectively outputting the accumulated intermediate value. The second multiplexer 12, and the first and second multiplexers 11 and 12, which initially select and output α ^{(-N + 1) i and} then selectively output the α ⁱ value according to the selection signal of 10). And a register 14 for temporarily storing the output of the multiplier 13 and outputting the multiplier 13 to the adder tree 15 and feeding it back to the first multiplexer 11.

Referring to the case of the Chien search block in FIG. 1 configured as described above, the control unit 10 calculates and stores the α ^{(−N + 1) i} value in advance and simultaneously selects the selection signals to the first and second multiplexers 11 and 12. Outputs

Here, it is assumed that the controller 10 initially outputs '0' and then '1' as a selection signal.

Therefore, since the selection signal of the controller 10 is '0' initially, the first multiplexer 11 selects and outputs an externally input gamma γ _i value to the multiplier 13, and the second multiplexer 12 The value of α ^{(-N + 1) i} is selectively outputted to the multiplier 13.

Since the multiplier 13 multiplies the outputs of the first and second multiplexers 11 and 12, the output of the multiplier 13 is γ _i α ^{(−N + 1) i} .

The register 14 stores the output γ _i α ^{(−N + 1) i} of the multiplier 13, outputs it to the adder tree 15, and feeds it back to the first multiplexer 11.

At this time, the controller 10 converts the selection signal to '1', and the first multiplexer 11 selects and outputs the γ _i α ^{(−N + 1) i} value fed back to the multiplier 13 and the second multiplexer. (12) selectively outputs the alpha ⁱ value to the multiplier (13).

The output of the multiplier 13 is γ _i α ^{(-N + 1) i} Since it is α ⁱ , rewriting it becomes γ _i α ^{(-N + 2) i} , and this value γ _i α ^{(-N + 2) i} is outputted to the adder tree 15 through the register 14 and again added. 1 is fed back to the multiplexer 11.

This process is performed for N cycles.

Where N is the number of data in the block.

In this case, since FIG. 1 is a chien search or pony search block diagram for the i th term, in order to implement a gamma polynomial or an omega polynomial, the circuit of FIG. 1 is configured in parallel with 2t of chien and pony search blocks, respectively. .

Where t is the number that can be error corrected.

That is, 2t multipliers, 2t 8-bit registers, and 2t + 2t multiplexers are needed separately for the Chien and Pony Search blocks.

The controller 10 may be shared in the Chien and Pony search blocks, and a multiplier and a register may be used to calculate and store α index values α ^{(−N + 1) i} and α ^{i in the} controller 10. Additionally needed.

In this case, when the multiplier is implemented as a serial multiplier, 2t registers and one multiplier are required.

The adder tree 16 is an 8-bit adder, which has a tree structure and is actually an exclusive oar gate.

Therefore, 2t-1 8-bit adders are needed, and the values of the terms output from each register composed of 2t in parallel are sequentially added.

In the case of the Chien search block, a zero detector 17 for checking whether the value of the gamma polynomial is zero is required, and no zero detector is needed because the pony search block does not need to be checked for zero.

That is, if the values output from the 2t Chien search blocks are 0, all of the outputs of the adder tree 15 become 0, so the zero detector 16 detects this and the α index at that time is the position where the error occurred.

The result obtained by substituting the α index when the result of the gamma polynomial becomes zero into the omega polynomial becomes an error correction value at the error position.

In this way, the above-described Chien or Pony Search block initially inputs gamma and omega in parallel, and then sequentially obtains the result for N cycles in series to obtain an error position and an error correction value at the error position.

To this end, the control unit 10 calculates a gamma polynomial or an omega polynomial by substituting α ^{−N + 1} at an initial stage and continuously inputting the value of X in a form of multiplying α ¹ .

Therefore, the conventional Chien or Pony search block described above takes 2t + N cycles of processing time, and a critical path may occur due to the 2t-1 tree structure of the 8-bit adder.

This slows down the clock and lengthens the clock period.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to sequentially input gamma and omega in series, and to simultaneously obtain N results in parallel after 2t cycles, thereby reducing processing time and reducing the number of gates. An error correction circuit for reducing a critical path is provided.

A feature of an error correction circuit according to the present invention for achieving the above object is an adder for adding a gamma value input in series and an intermediate value fed back, and a multiplier for multiplying the addition result of the adder and the input α exponent value. And zero for detecting zero by adding the outputs of the registers sequentially input during 2t cycles, forming a magnetic loop for 2t cycles (t being an error correctable number) cycles. The Cien search block composed of detectors is composed of N-1 (N is the number of data in the block), and outputs the results of N α exponent values simultaneously after 2t cycles.

Another feature of the error correction circuit according to the present invention includes an adder for adding an omega value input in series and an intermediate value fed back, a multiplier for multiplying the addition result of the adder and an input α exponent value, and outputting the output of the multiplier. The registers fed back to the adder form N-1 (N is the number of data in the block) for 2t (t is an error correctable number) cycle and form a magnetic loop. It is to output the result for the exponent value simultaneously.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a Chien or pony search block diagram of an error correction circuit according to the present invention;

Equation 1 may be expressed as Equation 3 below.

Referring to Equation 3, it can be seen that X + α ⁱ + Y form, the result is a recursive form.

Therefore, FIG. 2 is implemented for all α values, that is, α ^-1 to α ^{-N + 1} , and is composed of N-1 chien or pony search blocks 21 to 2N-1.

Referring to the first Chien or Pony Search block 21, a constant that multiplies the result of the adder 21-1 and the adder 21-1, which adds the gamma or omega input in series with the intermediate value fed back, and the value of α- ¹ . A multiplier 21-2 and a register 21-3 which outputs the result of the multiplier 21-2 to the zero detector 21-4 and feeds back to the adder 21-1.

At this time, the cycle of feeding back the result of the register 21-3 is for 2t.

That is, when the first chien or pony search block 21 loops for 2t cycles,

The gamma polynomial becomes as shown in Equation 4 below.

The second to N-th pony or search blocks 22 to 2N-1 also have the same structure as the first chien or pony search block.

In this case, gamma or omega is stored in a storage medium such as a ROM, and is commonly input to the adders of the first to N-1 chien or pony search blocks 21-2N-1 in series, and the α exponent values are first to third in parallel. Input to the multiplier of the N-1 chien or pony search block 21-2N-1 eliminates the need for multipliers and registers to calculate and store the α exponent, and only an 8-bit empty register to send α ⁰ . I need one.

Therefore, in order to implement a gamma polynomial or an omega polynomial, N 8-bit registers, N-1 constant multipliers, and N-1 8-bit adders are required for the Chien and the search blocks, respectively.

In the case of the Chien search block, N-1 zero detectors are required to check whether the value of the gamma polynomial is zero, and the Pony search block does not need to check whether it is 0.

That is, if the value output from the register of each search engine block is 0 for 2t cycles, the zero detector detects this, and the α index input to the search engine block becomes the position where an error occurs.

The result obtained by substituting the α index into the pony search block is an error correction value at the error position.

Therefore, the zero detector can be shared between the Chien search block and the Pony search block.

In addition, the calculation of gamma polynomials and omega polynomials is performed simultaneously in the Chien and Pony search blocks described above.

As described above, the chien or pony search block of the present invention inputs gamma and omega in series and sequentially obtains N results in parallel after 2t + 1 cycles to obtain an error position and an error correction value at the error position.

Therefore, the processing time of 2t + 1 cycles is required to find the error position and the error correction value at the error position.

At this time, since the number N of data in the block is usually larger than 2t (t is the number of error correction possible), the present invention can shorten the processing time much compared with the prior art.

In addition, the use of 8-bit zero detectors rather than the 8-bit adder's tree structure reduces the threshold path, enabling faster clock operation.

In general, since the constant multiplier is much smaller than the normal multiplier, even if the N-1 constant multiplier is used in the present invention, the constant multiplier is not larger than the conventional 2t normal multiplier.

In addition, since gamma or omega is serially input and shared by the N-1 adders, there is no need for a register for calculating the α exponent value, which makes the size of the Chien and Pony search blocks small.

As described above, the error correction circuit according to the present invention shortens the processing time by inputting gamma and omega in series, and then simultaneously obtaining N results in parallel after 2t cycles.

In addition, the gate count is reduced and a small constant multiplier is used to reduce the size of the Chien or search block, while simultaneously reducing the threshold path, enabling faster clock operation.

1 is a block diagram of a conventional error correction circuit

2 is a block diagram of an error correction circuit according to the present invention;

Explanation of symbols for the main parts of the drawings

21-2N-1: Chien or Pony Search Block 21-1: Adder

21-2: Multiplier 21-3: Register

21-4: Zero Detector

Claims (3)

An adder for adding a gamma value input in series and an intermediate value fed back; A multiplier for multiplying the addition result of the adder by the input α exponent value; A register for feeding back the output of the multiplier to the adder forms a magnetic loop for 2t cycles (t is an error correctable number), and adds the outputs of the sequentially input registers for 2t cycles to detect zero. The Chien search block is composed of N-1 (N is the number of data in the block), and outputs the result of N-1 α exponent values simultaneously after 2t cycles. And an α index inputted by the controller as the position where the error occurred. The method of claim 1, wherein each Chien search block

Error correction circuit, characterized in that designed to satisfy. Where 0 ≦ i ≦ 2t An adder for adding an omega value input in series and an intermediate value fed back; A multiplier for multiplying the addition result of the adder by the input α exponent value; A register that feeds the output of the multiplier back to the adder comprises N-1 (N is the number of data in the block) that constitutes a magnetic loop for 2t (t is an error correctable number) cycle. Subsequently, the results of N-1 α index values are simultaneously output, and the output value of the corresponding Pony search block obtained from the α index which is zero in the Chien search block is determined as an error correction value at the error position. Error correction circuit.

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