KR100226837B1 - Apparatus for error correction of digital tv - Google Patents

Abstract

The present invention relates to an error correction apparatus of a digital TV that occurs during data transmission. In particular, when the syndrome polynomial of the correction data is recalculated and the syndrome polynomial of the correction data is 0, the correction data is output as the final data, and the syndrome polynomial of the correction data is 0. Otherwise, the uncorrected original data is output as final data, thereby preventing errors caused by malfunction of the RS decoder when t or more errors occur on the channel, and further including a syndrome generator, an error position generator, and an error evaluation generator. Multiply by using a constant Galois field multiplier instead of the normal multiplier, and design the error position generator and error estimation generator to have a similar cell-based structure to improve integration density in VLSI. And reduce the cost, the syndrome generator is a syndrome Hangsik outputs in parallel, and shorten the time Dividing operation performed by Euclidean divider to load them in parallel and This reduces the size of the FIFO RAM.

Description

Digital TV's Error Correction Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for correcting errors occurring during data transmission, and more particularly, to a high speed reed-solomon decoder of a digital TV.

A general data transmission system uses a channel coding technique to recover an error caused by external or internal noise during data transmission. The most widely used code is the Reed-Solomon code. In addition, high-definition TV (HDTV) transmission system that requires a high data rate (R-S) code is adopted.

A technique capable of decoding such a wide range of R-S codes is disclosed in US Pat. No. 4,873,688, which is shown in FIG. 1 as a prior art.

Referring to FIG. 1, a syndrome generator 33, an Euclid divider 34, a Euclid multiplier 35, a polynomial solver 36, an inverse ROM A high speed real time RS decoder is implemented by using a Euclidean algorithm composed of Rom (37), an error correcting unit (38), and a First In First Output (FIFO) RAM (39). 1 is configured such that i) syndrome generator 33, ii) Euclidean divider 34 and Euclidean multiplier 35, iii) polynomial analysis unit 36 and error correction unit 38, iv) error correction correction unit ( Since there are four pipeline structures of output data from 39, a FIFO RAM 39 is needed that can store four received block data.

That is, the polynomial 32 received first is input to the syndrome generator 33 and the FIFO RAM 39. The syndrome calculator 33 calculates 2t syndromes (t is an error correctable number) when all data in block units are input, and outputs the syndromes to the Euclidean divider 34 and the Euclidean multiplier 35. The Euclidean divider 34 receives the syndrome and detects the coefficient of the error evaluation polynomial? (X), and the Euclidean multiplier 35 generates the coefficient of the error position polynomial Λ (x) and outputs it to the polynomial analysis unit 36. do. The polynomial analysis unit 36 receives the coefficient of the error evaluation polynomial Ω (x) and the coefficient of the error position polynomial Λ (x) and the root and error position polynomial Λ (x) of the error position polynomial Λ (x). First derivative of Λ '(x) | _{x = root} , Error Evaluation The _{root of the} polynomial Ω (x) Ω (x) | _{You will get x = root} respectively. These values are input to the error correction unit 38 to determine the magnitude of the error, and are exclusively ORed with the original data input from the FIFO RAM 39 to correct the error and output the correction data. .

However, the above-described prior art outputs data directly to the next block without checking whether the error is corrected correctly. Therefore, the RS decoder malfunctions when more than t errors occur on the transmission channel in the t-error correcting RS code. do. That is, if the number of errors that can be corrected by the R-S decoder is t, when the t or more errors occur due to noise on the transmission channel, the originally received data should be output as it is. This is because in this case, if the exclusive value of the error value (incorrectly corrected data) obtained from the error correction unit and the original data are exclusively generated, the error is more likely to occur than the originally received data.

In addition, since the syndrome generator 33 calculates syndromes using a general ordinary multiplier, the number of gates increases, which is difficult to design and complicated when integrating with VLSI, resulting in a low cost and an increase in cost.

In addition, the Euclidean divider 34 is configured to serially load the syndrome polynomial S (x) from cell 0 to the coefficient of the highest order. In this case, since all the coefficients of S (x) are 2t and the number of clock cycles required for the division operation is required up to 2t cycles, a total of 4t clock cycles are required. Therefore, the processing time (Latency) is increased, thereby increasing the size of the FIFO RAM 39.

In addition, since it has four pipeline structures, the FIFO RAM 39 should be able to store up to four received block data, thereby making the size of the FIFO RAM 39 even larger.

The present invention has been made to solve the above problems, an object of the present invention is to digitally improve the integration degree when the RS decoder that conforms to the digital TV standard, such as GA HDTV to the VLSI (Very Large Scale Integrated Circuit) An error correction apparatus for a TV is provided.

Another object of the present invention is to provide an error correction apparatus of a digital TV that performs multiplication by using a constant Galoa field multiplier when a syndrome of received data or corrected data is generated.

It is still another object of the present invention to provide an error correction apparatus of a digital TV which loads syndrome polynomials in parallel for one clock cycle to obtain coefficients of error evaluation polynomials.

It is still another object of the present invention to provide an error correction apparatus for a digital TV that recalculates a syndrome of corrected data to determine whether corrected data is corrected correctly and to selectively output original data or corrected data as final data according to the determination result. In providing.

The error correction apparatus of the digital TV according to the present invention for achieving the above object is a syndrome generator, Euclidean divider / multiplier, an error evaluation generator, an error position generator, an error polynomial generator, an error correction unit, a memory, It is characterized by consisting of error checking and data output.

According to the present invention, if the RS code word polynomial C (x) formed by adding 2t (t is the number of correctable errors) parity bits to the message polynomial M (x) is transmitted, the syndrome generator is a constant Galois field multiplier when performing multiplication. It is characterized by generating a syndrome polynomial S (x) of the polynomial R (x) received using and output in parallel.

The Euclidean divider / multiplier according to the present invention loads the syndrome polynomial S (x) generated in the syndrome generator in parallel to obtain the coefficient of the error evaluation polynomial Ω (x) and the coefficient of the error position polynomial Λ (x), respectively. It is characterized by.

Error evaluation polynomial Ω (x) by sequentially substituting the error evaluation polynomial Ω (x) generated from the Euclidean divider while increasing the exponent from α ^{-N + 1} to α ⁰ . It is characterized by finding the root of.

The error evaluation generator according to the present invention is characterized by performing a multiplication using a constant galoa field multiplier.

The error position polynomial Λ (x) by sequentially substituting the error position polynomial Λ (x) generated by the Euclidean multiplier while increasing the exponent from α ^{-N + 1} to α ⁰ , is increased. It is characterized by generating the position of x = α ⁱ satisfying Λ (α ⁱ ) = 0 by finding the root of.

Position error generation unit according to the invention as extract only the Euclidean then with the error location polynomial generated in multiplier Λ (x) increase in the indices from ^{-N +} α ¹ to α ⁰ is substituted to the sequence of odd coefficient terms The first order differential function Λ '(x) of the error position polynomial Λ (x) is output.

The error position generator according to the present invention is characterized by performing a multiplication using a constant galoa field multiplier.

The error polynomial generator according to the present invention includes an output? (Α ⁱ ) of the error evaluation generator, an error position calculated by the error position generator, and a first-order differential function Λ '(x) of the error position polynomial Λ (x). The error polynomial E (x) is obtained by applying the algorithm.

The error checking and data output unit according to the present invention calculates a syndrome of the data corrected by the error correcting unit to determine whether the corrected data is corrected correctly, and the raw data or data corrected by the error correcting unit according to the determination result. Select output as final data.

1 is a block diagram of an error correction apparatus of a conventional digital TV

2 is a block diagram of an error correction apparatus of a digital TV according to the present invention;

3 is a detailed block diagram of the syndrome generator of FIG.

4 is a detailed block diagram of the Euclidean divider of FIG.

5 is a detailed block diagram of the error position generator of FIG. 2;

FIG. 6 is a detailed block diagram of the error evaluation generator of FIG. 2. FIG.

7 is a detailed block diagram of the error polynomial generator of FIG.

8 is a detailed block diagram of the error checking and data output unit of FIG. 2;

Explanation of symbols for main parts of the drawings

101: syndrome generator 102: Euclidean divider

103: Euclidean multiplier 104: Error evaluation generator

105: error position generator 106: error polynomial generator

107: FIFO RAM 108: error correction unit

109: error check and data output unit

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of an overall error correction apparatus of a digital TV according to the present invention. The syndrome generator 101 generating the syndrome S (x) from the received polynomial R (x) and outputting the syndrome S (x) in parallel, the syndrome generator ( 101. The Euclidean divider 102, which loads the syndrome S (x) generated in parallel and obtains the coefficient of the error evaluation polynomial Ω (x), receives the syndrome generated by the syndrome generator 101, and receives the error position polynomial. The root of the error evaluation polynomial Ω (x) is obtained using the coefficients of the error evaluation polynomial Ω (x) generated by the Euclidean multiplier 103 and the Euclidean divider 102 that calculate the coefficient of Λ (x). An error position estimation unit 104 for estimating an error magnitude by the root position of the error position polynomial Λ (x) of the Euclidean multiplier 103, estimates the error position, and first-order the error position polynomial Λ (x). Error position output to output derivative Λ '(α ⁱ ) · α ⁱ The generation unit 105, the root of the error evaluation polynomial? (X) obtained by the error evaluation generation unit 104, the error position obtained by the error position generation unit 105, and the first derivative of the error position polynomial Λ (x). An error polynomial generator 106 for obtaining an error value using Λ '(α ⁱ ) · α ⁱ , a FIFO RAM 107 for storing the received polynomial, and an error value and FIFO RAM of the error polynomial generator 106. An error correcting unit 108 for correcting the error by exclusively ORing the original data stored in the unit 107, and calculating the syndrome of the corrected data in the error correcting unit 108 to determine and determine whether the corrected data has been corrected correctly. According to a result, the error check and data output unit 109 selects and outputs original data or correction data stored in the FIFO RAM 108 as final data.

In the present invention configured as described above, the R-S codeword polynomial C (x) is made by adding 2t (t is the number of correctable errors) parity symbols to the message polynomial M (x) to be transmitted. This is expressed mathematically as Equation 1 below.

Here, G (x) is a generator polynomial, which is expressed as Equation 2 below, and when the number of errors to be corrected is 10, the 20th order comes out.

As can be seen in Equations 1 and 2, C (x) becomes a multiple of G (x), and a root satisfying G (x) = 0 is satisfied C (x) = 0.

In this case, in the GA HDTV standard, the generated polynomial G (x) and the primitive polynomial P (x) are defined as in Equation 3 below.

As such, when the RS-encoded codeword polynomial C (x) is transmitted on a channel, an error may occur due to noise on the channel, and the data R (x) received at a receiver such as a digital TV may be represented by the following equation. It is expressed as 4.

Therefore, the error polynomial E (x) can be expressed as Equation 5 below if ν symbol errors occur due to channel noise.

Where jk is the position of the k th error and e _jk is the magnitude of the k th error.

In Equation 4, C (x) may define a syndrome polynomial S (x) including information on an error pattern by using a multiple of G (x) as shown in Equation 6 below.

At this time, since C (x) is multiple of G (x), all roots of G (x) satisfy C (x) = 0, and S _j = R (α ^j ) = C (α ^j ) + E (α ^j ) = E (α ^j ).

Therefore, it can be seen that the syndrome polynomial S (x) is independent of R (x) and depends on the error pattern.

In the GA HDTV standard, the roots of G (x) are α ⁰ , α ¹ , ..., α ¹⁸ , α ^19, so that each coefficient of S (x) is α ⁰ to α ¹⁹ . It can be obtained as shown in Equation 7 below.

In Equation 7, the coefficients S _j of the syndrome may be expressed as Equation 8 below.

As shown in Equation 8, the coefficients of each syndrome may be calculated by repetition of addition and multiplication of the Galloa field.

Accordingly, the syndrome generator 101 may be implemented as shown in FIG. 3, and is composed of N (ie, 20) syndrome blocks.

According to an embodiment of the second syndrome block, an adder for adding a serially inputted data symbol and a feedback accumulated value, a first multiplexer for selectively outputting an output of the adder or an inputted data symbol according to a block edge signal, A first Gallo field multiplier for temporarily storing an output of a first multiplexer, multiplying the output of the first register by an α exponent value of the order, i.e., α ¹ (1 ≦ i ≦ 2t), and feeding it back to the adder, A second multiplexer for selectively outputting a syndrome coefficient fed back from a final output terminal S ₀ or an output of the first register according to the block edge signal, and outputting the output of the second multiplexer until one block of data is input; And a second register for storing.

Here, the first syndrome block, the third syndrome block to the Nth syndrome block are also the same as the configuration of the second syndrome block described above.

FIG. 3 configured as described above is an adder of each syndrome block of the syndrome generator 101, in order from the coefficient of the X ^N-1 order term, assuming that the data input symbols are from the highest order coefficient, that is, the (N, K, t) RS code. It is input at the same time. Here, N is the number of symbols in one code block, t is the number of errors that can be corrected, 2t is the parity symbol to be added, and K is N-2t, which is the number of message symbols which are information to be actually sent. Therefore, N = K + 2t symbols.

The adder adds an input symbol and an output of a constant galoa field multiplier to output to the first multiplexer. The first multiplexer selects a data symbol to be input since there is no accumulated data in the first symbol input cycle when one block code is input according to a block edge signal, and selects an addition result of the adder in the remaining intervals. Output to the first register. In this case, the Galois field multiplier are constant if the output value of the exponent α that order, for example, S ₁ block in the first register then fed back to the adder by multiplying the α ^1. That is, the output of the first register feeds only the cell calculating S ₁ to the adder and the remaining cells are used as inputs to the constant Galloa field multiplier.

On the other hand, the output of the first register is input to the second multiplexer, which selects the last output fed back in the first symbol input cycle according to the block edge signal, that is, when one block code is input. In the remaining sections, the output of the first register is selected and output to the second register. The second register outputs the obtained syndrome after inputting one block of data.

In other words, when one block of data is serially input, N syndromes S ₀ to S ₁₉ are simultaneously output from N syndrome blocks.

If the second syndrome block loops for 2t cycles, the syndrome S ₁ is obtained as in Equation 9 below.

In this way, the syndrome generator 101 uses a constant multiplier that is much smaller than the normal multiplier, so that the number of gates can be reduced by about 1/10 compared to the conventional one, so that it is easy to design and reduce the chip size when integrating with VLSI. You can also save money.

The Euclidean divider 102, which receives the syndromes S ₀ to S ₁₉ output in parallel from the syndrome generator 101, obtains the coefficient of the error evaluation polynomial? (X), and the Euclidean multiplier ( 103) obtains the coefficient of the error position polynomial Λ (x).

In the Euclidean divider 102, each cell is connected to each multiplexer from a lower order coefficient of the syndrome polynomial S (x), so that the coefficient of S (x) when the load enable signal is high. Is input to the multiplexer, and if low, the cell output of the front end of each cell is configured to be input to the multiplexer. In this case, the load enable signal is generated by using the edge detection signal and should be high only for one clock cycle. Thus, S (x) is loaded in parallel for one clock cycle into the register of each cell connected to the output of the multiplexer of each cell. 4 described above is performed until the order of the error evaluation polynomial? (X) is smaller than t. Other details are the same as in the prior art, and thus detailed description of the operation is omitted.

As described above, the Euclidean divider loads S (x) into the registers of each cell in parallel at the same time, requiring only a total of 2t clock cycles, reducing the Euclidean divide operation time to about 1/2 of the prior art. Can be.

Then, the error position generator 105 receives the coefficients of the error position polynomial Λ (x) output from the Euclidean multiplier 103 as shown in Λ (x) | Find the α ⁱ that satisfies _{x = α} ⁱ = 0 and differentiate Λ (x) by the first order Λ '(x) | Calculate the value of _{x = α} ⁱ .

That is, FIG. 5 shows the total sum of Λ (α ⁱ ) by exclusively ORing the outputs of the t + 1 cells 51-0 to 51-t and the registers of the cells 51-0 to 51-t. Sum) and extract only the coefficients of the odd term from the output of the register of each cell to output the first order differential function Λ '(x) of the error position polynomial Λ (x) and And a zero detector 57 for estimating the error position by determining whether the output of the exclusive oar gate 56 is zero.

Taking the t-th cell out of the t + 1 cells as an example, the configuration thereof is selected and outputted by t-value Λ _t initially input in parallel in accordance with the selection signal MUX_SEL, and then selectively outputting the accumulated intermediate value. A first multiplexer 52 and a second multiplexer 53 for selectively outputting α ^{(255-N + 1) t} and then selectively outputting an α ^t value according to the selection signal MUX_SEL. The multiplier 54 multiplies the outputs of the second multiplexers 52 and 53, and the output of the multiplier 54 is temporarily stored and output to the exclusive OR gate 56 and fed back to the first multiplexer 52. It is a loop structure composed of registers 55. The configuration of the remaining cells is the same as that of the t-th cell. In this case, the multiplier 54 may improve the integration density when integrated with VLSI using a constant galoa field multiplier.

When the coefficients of the error position polynomial Λ (x) are input in parallel, the error position generating unit 105 configured as described above becomes low in the initial clock cycle, and the selection signal MUX_SEL becomes low, and each cell is selected by the selection signal MUX_SEL. In the first multiplexer of Λ _t , Λ _t-1 , ..., Λ ₁ are selected respectively, and in the second multiplexer the constant α ^{(255-N + 1) t} is selected to multiply each other in the constant Galoa field multiplier. And then stored in each register. From the next clock cycle, the select signal MUX_SEL goes high, and the output of the register of each cell is output to the exclusive OR gate 56 and fed back to the first multiplexer. Accordingly, the value fed back from each register is selected in the first multiplexer of each cell by the selection signal MUX_SEL, and α ^t is selected in the second multiplexer and multiplied with each other in the constant Galloa field multiplier, respectively. Is stored in the register.

This process is carried out for N cycles. Where N is the number of data symbols in the block.

In other words, the calculated value can be obtained every clock by increasing the exponent of Λ (x) from α ^{-N + 1} to α ⁰ sequentially. Then, the output of the registers of the cells 51-0 to 51-t output every clock is exclusively ringed by the exclusive OR gate 56 and output to the zero detector 57, and the zero detector 57 Determines whether the value is zero or not. At this time, when the output of the exclusive OR gate 56, that is, the root of the error position polynomial Λ (x) is 0, the position is the place where the error occurs. If the error position polynomial Λ (x) = 0 in α ^p , the p th is the error position.

On the other hand, the value of Λ '(x), which is the derivative of Λ (x), is an exclusive oar gate of only the coefficients of the odd term (ie, primary, tertiary, fifth order, ...) of the output of each register. 56). For example, Λ (x) = α⁵X³+ α²X²+ αX + α⁷When you say this, you differentiate Λ '(x) = 3⁵X²+ 2α²X^OneEven term of Λ (x) is multiplied by an even number when the derivative is multiplied, so it disappears due to the property of Galoa field addition. Λ '(x) = α⁵X²+ α.

At this time, when the extracted coefficient, only the odd terms in the XOR gate Iowa ^{(56) Λ '(α i} ) values instead of being calculated and output α ⁱ Λ' (α ⁱ⁾ is outputted. However, since the error polynomial generation unit 106 needs the value α ⁱ Λ '(α ⁱ ) when calculating the error magnitude, this value is output as it is.

6 is a detailed block diagram of the error evaluation generator 104 in which coefficients of the error evaluation polynomial? (X) output from the Euclidean divider 102 are input in parallel instead of the coefficient of the error position polynomial Λ (x). The configuration is identical to that of the error position generator of FIG. 5 except that the zero detector is not required, and operates in the same manner. That is, the error evaluation generation unit 104 receives the coefficients of the error evaluation polynomial Ω (x) output from the Euclidean divider 102 in parallel, Ω (α ⁱ ), α ⁱ = α ^{255-N + 1} , α ^{255-N + 2} , ..., α- ¹ , α ⁰ are found.

FIG. 7 is a detailed block diagram of an error polynomial generator 106 that calculates an error polynomial E (x), and corrects an error corresponding to an error position obtained by the error location generator 105 by a Forney algorithm. Find the value.

That is, Figure 7 is the output of the inverse-ROM 71, the inverse-ROM 71 for inverting the Λ '(α ⁱ⁾ · α ⁱ value which is output from the exclusive Iowa gate 56 of the error position generating unit 105 Zero or the multiplier 72 according to a Galloa field multiplier 72 multiplying by Ω (α ⁱ ) output from the error evaluation generator 104, and the error position value calculated by the error position generator 105. It consists of a multiplexer 73 which selects the multiplication result and outputs it to the error polynomial E (x).

FIG. 7 configured as described above is based on Ω (α ⁱ ) calculated by the error evaluation generator 104 and the error position signal and Λ '(α ⁱ ) · α ⁱ values calculated by the error position generator 105. The magnitude of the error is calculated using a pony algorithm as shown in Equation 10 below.

Here, h is an offset and the GA HDTV standard is -1.

가 된다. 그리고, 갈로아 필드 곱셈기(72)에서 상기 인버스 롬(71)의 출력(

)과 에러 평가 발생부(104)에서 계산된 Ω(αⁱ) 값을 곱하면 에러 다항식 E(x)의 계수 즉, 에러 값이 계산된다. 이때, 멀티플렉서(73)는 상기 에러 위치 발생부(105)에서 계산된 에러 위치 신호에 따라 즉, 에러가 발생한 위치에서는 상기 곱셈기(72)에서 구한 에러 다항식 E(x)의 계수를 선택하고 에러가 발생하지 않은 위치에서는 제로 신호를 선택하여 에러 정정부(108)로 출력한다.That is, when the value of Λ '(α ⁱ ) · α ⁱ output from the exclusive OR gate 56 of the error position generator 105 passes through the inverse ROM 71,

Becomes Then, the output of the inverse ROM 71 in the Galloa field multiplier 72 (

) And the value of? (Α ⁱ ) calculated by the error evaluation generator 104 calculates the coefficient of the error polynomial E (x), that is, the error value. At this time, the multiplexer 73 selects the coefficient of the error polynomial E (x) obtained by the multiplier 72 according to the error position signal calculated by the error position generating unit 105, that is, at the position where the error has occurred. At the position that does not occur, the zero signal is selected and output to the error correction unit 108.

The error correction unit 108 is an exclusive OR gate, and corrects the error by exclusively ORing the error value output from the error polynomial generator 106 and the original data stored in the FIFO RAM 107. The data is output to the confirmation and data output unit 109.

8 is a detailed block diagram of the error checking and data output unit 109, which is output from the first FIFO 81 and the error correcting unit 108 that store original data output from the FIFO RAM 107. FIG. A second FIFO 82 for storing correction data, a syndrome calculation unit 83 for calculating a syndrome using the correction data output from the error correction unit 108, and a syndrome calculated by the syndrome calculation unit 83. The original data stored in the first FIFO 81 or the correction data stored in the second FIFO 82 are selected in accordance with a result of the determination by the zero detection unit 84 and the zero detection unit 84 that determine whether The multiplexer 85 outputs the final data.

Here, the syndrome calculator 83 has the same structure as the syndrome calculator 101 of FIG. 3.

The error checking and data output unit 109 of FIG. 8 configured as described above calculates a syndrome with respect to the corrected data in order to confirm whether or not the data corrected by the error correcting unit 108 is corrected or not, and S (x) = 0. Determine whether or not.

That is, the first FIFO 81 stores the original data output from the FIFO RAM 107 and the second FIFO 82 stores the correction data output from the error correction unit 108. The syndrome calculator 83 calculates the syndrome S (x) in the same manner as in FIG. 3 using the correction data.

The zero detector 84 determines whether the syndrome S (x) calculated by the syndrome calculator 83 is 0 or not, and outputs the result as a selection signal of the multiplexer 85. That is, if the syndrome S (x) = 0 of the corrected data means that the data is corrected correctly, the multiplexer 85 selectively outputs the correction data stored in the second FIFO 82 as the final data, If the syndrome S (x) ≠ 0 indicates that t or more errors have occurred on the transmission channel, the multiplexer 85 selects and outputs original data that is not corrected, that is, uncorrected, as the final data in the first FIFO 81. .

Therefore, when t or more errors occur on the channel, it is possible to prevent an error caused by a malfunction of the R-S decoder.

On the other hand, the structure of the R-S decoder used in the present invention can be applied to all (N, K) R-S codes.

As described above, according to the error correction apparatus of the digital TV according to the present invention, if the syndrome polynomial of the correction data is calculated and the syndrome polynomial of the correction data is 0, it means that the data is correctly corrected. If the syndrome polynomial of the data is not 0, it means that more than t errors have occurred on the transmission channel. Therefore, the uncorrected original data is output as final data. When more than t errors occur on the channel, the RS decoder malfunctions. This can prevent errors.

In addition, the syndrome generator, the error position generator, the error evaluation generator, and the error polynomial generator use a constant Galoa field multiplier instead of a general ordinary multiplier, and the error position generator and the error evaluation generator have a similar cell-based structure. Designed to have, VLSI facilitates design, improves integration, reduces chip size, and reduces cost.

In addition, the syndrome generator outputs syndrome polynomials in parallel, and the Euclidean divider loads them in parallel, thereby reducing the execution time of the dividing operation and thereby reducing the size of the FIFO RAM, and also shortening the pipeline structure. This further reduces the size of the FIFO RAM.

Claims (14)

In the error correction apparatus of a digital TV that receives a RS code word polynomial C (x) formed by adding 2t parity bits (t is the number of correctable errors) to the message polynomial M (x), and corrects the error. , A syndrome generator for generating a syndrome polynomial S (x) from the received polynomial R (x) and outputting in parallel; A Euclidean divider for loading the syndrome polynomial S (x) generated by the syndrome generator in parallel to obtain a coefficient of the error evaluation polynomial? (X); A Euclidean multiplier which receives a syndrome generated by the syndrome generator and obtains a coefficient of an error position polynomial Λ (x); An error evaluation generator for estimating an error magnitude by obtaining a root of the coefficient of the error evaluation polynomial? (X) generated in the Euclidean divider; Obtaining the root of the error position polynomial Λ (x) by sequentially substituting the error position polynomial Λ (x) generated by the Euclidean multiplier with increasing exponents from α ^{-N + 1} to α ⁰ , Λ (α ⁱ An error position generator for generating a position of x = α ⁱ that satisfies) = 0 and outputs a first derivative function Λ '(x) of the error position polynomial Λ (x); By using the root of the error evaluation polynomial? (X) of the error evaluation generator, the error position calculated by the error location generator, and the first derivative function Λ '(x) of the error location polynomial Λ (x), the error polynomial E ( an error polynomial generator for finding x); A memory for storing the received polynomial R (x); An error correction unit for logically combining an error polynomial E (x) of the error polynomial generator and original data stored in the memory; An error check for determining whether corrected data is corrected correctly by calculating a syndrome of the corrected data by the error correcting unit, and selectively outputting original data stored in the memory or corrected data as the final data according to the determination result; Error correction apparatus of the digital TV, characterized in that it comprises a data output unit. The method of claim 1, wherein the syndrome generator

Error correction apparatus of the digital TV, characterized in that designed to satisfy. Where N is the number of data symbols in one code block and S _j is the jth syndrome coefficient. The method of claim 1, wherein the syndrome generator An adder for adding data symbols input in series and cumulative values fed back; A first multiplexer for selecting an input data symbol in a first symbol input cycle of one block code and selecting and outputting an addition result of the adder in the remaining intervals; A first register for temporarily storing the output of the first multiplexer, A constant galoa field multiplier for multiplying the output of the first register by an α exponent of the order and feeding it back to the adder; A second multiplexer that selects a syndrome coefficient fed back from a final output stage in a first symbol input cycle of one block code and selects and outputs an output of the first register in the remaining intervals; And a syndrome block comprising a second register for storing syndrome coefficients output from the second multiplexer is provided in order of the syndrome polynomial S (x). The method of claim 3, wherein the syndrome generator The data input symbols are serially inputted from the highest order coefficient to the adder of each syndrome block, and each syndrome coefficient is simultaneously output through the second register of each syndrome block after data input of one block is completed. TV error correction device. The method of claim 1, wherein in the Euclidean divider Each cell is coupled to each multiplexer from a lower order coefficient of the syndrome polynomial S (x), so that the coefficient of S (x) is input to the multiplexer if the load enable signal that is high only for one clock cycle is high. , If low, the cell output of the front end of each cell is input to the multiplexer to obtain a coefficient of the error evaluation polynomial? (X). The method of claim 1, wherein the error position generating unit When the coefficients of the error-position polynomial Λ (x) are input in parallel from the Euclidean multiplier, the initial α exponent values α ²⁵⁵ are selected in the initial clock cycle by selecting Λ _t , Λ _t-1 , ..., Λ ₁ , respectively. ^{-N + 1) i} ; multiply by 1 ≤ i ≤ 2t) and store in each register.In the next clock cycle, select each value fed back from each register and multiply it by the exponent value (α ⁱ ) of the order. A block of cells performing the process of storing each register after N cycles (where N is the number of data symbols in one code block); An exclusive ora gate that logically combines values output from each register of the cell block every clock to obtain the total sum of Λ (α ¹ ); And a zero detector configured to determine whether the sum of Λ (α ¹ ) output from the exclusive OR gate is zero. The method of claim 6, wherein the error position generating unit An error correction apparatus for digital TV, characterized in that the multiplication is performed by using a constant Galoa field multiplier in each cell block. The method of claim 6, wherein the error position generating unit The value of Λ '(x), which is the first derivative of the error position polynomial Λ (x), is obtained by extracting only the coefficients of the odd term from the output of each register (α ⁱ Λ' (α ⁱ )). An error correcting device for a digital TV. The method of claim 1, wherein the error evaluation generation unit When the oil cleaners coefficients of the error evaluation polynomial Ω (x) from Meridian divider are input in parallel in the initial clock cycle _{Ω t, Ω t-1,} ..., select Ω ₁ α respectively to the initial index value ^{(α (255 -N + 1) i} ; multiply by 1 ≤ i ≤ 2t) and store in each register.In the next clock cycle, select each value fed back from each register and multiply it by the exponent value (α ⁱ ) of the order. A block of cells performing the process of storing each register after N cycles (where N is the number of data symbols in one code block); And an exclusive ora gate for calculating the total sum of Ω (α ¹ ) by logically combining values output from each register of the cell block at every clock. The method of claim 1, wherein the error polynomial generator is The error position is generated by applying Ω (α ⁱ ) calculated by the error evaluation generator, the error position signal calculated by the error position generator, and a first order differential function Λ '(α ⁱ ) · α ⁱ to the pony algorithm. And an error value corresponding to an error position obtained by a negative device. The method of claim 1, wherein the error polynomial generator is An inverse ROM for inverting the first derivative function Λ '(α ⁱ ) · α ^{i of} the error position polynomial Λ (X) output from the error position generator; Output of the inverse ROM (

) And a constant Galloa field multiplier that multiplies the output of the error evaluation generator (Ω (α ⁱ )), And a multiplexer which selects zero or a multiplication result of the multiplier according to the error position value calculated by the error position generating unit and outputs the multiplier to the error polynomial E (x). 12. The multiplexer of claim 11 wherein the multiplexer is And selecting a coefficient of the error polynomial E (x) obtained by the multiplier at a position where an error occurs and a zero signal at a position where no error occurs. The method of claim 1, wherein the error checking and data output unit A first first-in first-out memory for storing original data output from the memory; A second first-in first-out memory for storing correction data output from the error correction unit; A syndrome calculation unit for calculating a syndrome of correction data output from the error correction unit; A zero detector for determining whether the syndrome calculated by the syndrome calculator is 0; And a multiplexer for selecting the original data stored in the first-in first-out memory or the correction data stored in the second first-in-first-out memory according to the determination result of the zero detection unit and outputting the final data as final data. . The method of claim 13, wherein the multiplexer If the syndrome S (x) = 0 of the correction data, the correction data stored in the second first-in first-out memory is selectively outputted as final data, and if the syndrome S (x)? And outputting the selected data as final data.

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