KR19990032073A - Error correction device of digital TV - Google Patents

Abstract

A syndrome polynomial of the correction data is recalculated, and when the syndrome polynomial of the correction data is 0, the correction data is output as the final data, and when the syndrome polynomial of the correction data is 0 Alternatively, by outputting the uncorrected original data as the final data, it is possible to prevent an error caused by a malfunction of the RS decoder when more than t errors occur on the channel, and also to prevent an error caused by a syndrome generator, In addition, by performing the multiplication using a constant Galois field multiplier instead of the ordinary multiplier, and by designing the error location generator and the error evaluation generator to have a similar cell basis structure, the degree of integration when integrated into a VLSI is increased, Wherein the syndrome generator comprises a syndrome generator Hangsik outputs in parallel, and shorten the time Dividing operation performed by Euclidean divider to load them in parallel and This reduces the size of the FIFO RAM.

Description

Error correction device of digital TV

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for correcting errors occurring in data transmission, and more particularly to a High Speed Reed-Solomon decoder of a digital TV.

A typical data transmission system uses a channel coding scheme to recover errors caused by external or internal noise in the process of transmitting data. The most widely used code is Reed-Solomon code. In addition, a high-definition television (HDTV) transmission system that requires a high data rate also adopts the R-S code.

A technique capable of decoding such an extensive R-S code is disclosed in U.S. Patent No. 4,873,688 and is shown in Figure 1 as a prior art.

1, a syndrome generator 33, an Euclid divider 34, an Euclidean multiplier 35, a polynomial solver unit 36, an inverse (inverse) Speed real-time RS decoder using an Euclidian algorithm composed of a random access memory (RAM) 37, an error correction unit 38, and a first-in first-out (FIFO) RAM 39. 1 configured as described above includes i) a syndrome generator 33, ii) a Euclidean divider 34 and an Euclidean multiplier 35, iii) a polynomial analysis unit 36 and an error correction unit 38, iv) 39, it is necessary to have a FIFO RAM 39 capable of storing four pieces of received block data.

That is, the received polynomial 32 is input to the syndrome generator 33 and the FIFO RAM 39. The syndrome calculator 33 calculates 2t (t is an error-correctable number) syndromes and outputs the syndrome to the Euclidean divider 34 and the Euclidean multiplier 35 when all data of the block unit is input. The Euclidean divider 34 receives the syndromes and detects the coefficients of the error evaluation polynomial Ω (x). The Euclidean multiplier 35 generates coefficients of the error locator polynomial Λ (x) and outputs the coefficients to the polynomial analysis unit 36 do. The polynomial analyzing unit 36 receives the coefficients of the error evaluation polynomial Ω (x) and the coefficients of the error locator polynomial Λ (x) to calculate the root of the error locator polynomial Λ (x) and the error locator polynomial Λ (x ) Of the first-order differential function Λ '(x) | _{x = root} , error evaluation polynomial Ω (x) Ω (x) | _{x = root} , respectively. These values are input to the error correction unit 38 to determine the magnitude of the error and are exclusive-ORed with the original data input from the FIFO RAM 39 to correct the error and output the correction data .

However, since the above-mentioned conventional technique outputs data immediately without checking whether the error is correctly corrected, and transmits the data to the next block, when an error occurs more than t on the transmission channel in the t-error correction RS code, the RS decoder malfunctions do. That is, if the number of errors that can be corrected by the R-S decoder is t, if t or more errors occur due to noise on the transmission channel, the originally received data must be output as it is. If the error value (erroneously corrected data) obtained from the error correction unit and the original data are exclusive-ORed in this case, it is more likely to generate an error than the originally received data.

Since the syndrome generator 33 calculates a syndrome by using a general ordinary multiplier, the number of gates is increased. As a result, integration in a VLSI makes design difficult and complicated, resulting in low integration and increased cost.

In addition, the Euclidean divider 34 performs serial loading of the syndrome polynomial S (x) from the cell 0 to the coefficient of the highest order. In this case, all the coefficients of S (x) are 2t, and the maximum number of clock cycles required for the division operation is 2t, which requires a total of 4t clock cycles. Therefore, the processing time (latency) increases and the size of the FIFO RAM 39 increases.

In addition, since the FIFO RAM 39 has four pipeline structures, the FIFO RAM 39 must be able to store a maximum of four received block data, thereby increasing the size of the FIFO RAM 39.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a digital multi-scale integrated circuit which can improve the integration degree when integrating an RS decoder conforming to a digital TV standard such as GA HDTV into a VLSI And an error correction apparatus for a TV.

Another object of the present invention is to provide an error correction apparatus for a digital TV that performs a multiplication using a constant Galois field multiplier when a syndrome of received data or corrected data occurs.

It is still another object of the present invention to provide an error correction apparatus for a digital TV that loads a syndrome polynomial in parallel for one clock cycle to obtain coefficients of an error evaluation polynomial.

It is still another object of the present invention to provide an error correction device for a digital TV that recalculates a syndrome of correction data to determine whether the corrected data has been correctly corrected and outputs the original data or correction data as final data according to the discrimination result .

According to another aspect of the present invention, there is provided an apparatus for correcting error in a digital TV, the apparatus including a syndrome generator, an Euclidean divider / multiplier, an error evaluator, an error locator, an error polynomial generator, An error check and a data output unit.

When the RS code word polynomial C (x) generated by adding 2t (t is the number of correctable errors) parity bits to the message polynomial M (x) is transmitted, the syndrome generator generates a constant Galois field multiplier (X) of the received polynomial R (x) and outputs the generated syndrome polynomial S (x) in parallel.

The Euclidean divider / multiplier according to the present invention loads the syndrome polynomial S (x) generated in the syndrome generator in parallel to obtain the coefficients of the error evaluation polynomial Ω (x) and the coefficients of the error location polynomial Λ (x) .

The error evaluation generator according to the present invention generates the error evaluation polynomial Ω (x) by sequentially substituting the error evaluation polynomial Ω (x) generated in the Euclidean divider with increasing indices from α ^{-N + 1} to α ⁰ , Is obtained.

The error evaluation generator according to the present invention is characterized in that a multiplication is performed using a constant Galois field multiplier.

The error location generator according to the present invention generates the error locator polynomial Λ (x) by sequentially substituting the error locator polynomial Λ (x) generated in the Euclidean multiplier with increasing indices from α ^{-N + 1} to α ⁰ , And the position of x = α ⁱ satisfying Λ (α ⁱ ) = 0 is generated.

The error location generator according to the present invention sequentially extracts the coefficients of the odd term after sequentially increasing the index from? ^{-N + 1} to? ⁰ to the error locator polynomial? (X) generated by the Euclidean multiplier, (X) of the error locator polynomial Λ (x).

The error location generator according to the present invention is characterized in that a multiplication is performed using a constant Galois field multiplier.

The error polynomial generating unit according to the present invention generates an error polynomial based on the output Ω (α ⁱ ) of the error evaluation generating unit, the error position calculated in the error position generating unit, and the first-order differential function Λ '(x) Algorithm to find the error polynomial E (x).

The error checking and data output unit according to the present invention calculates a syndrome of corrected data by the error correcting unit to determine whether the corrected data has been corrected correctly and to correct the original data not corrected according to the discrimination result or the corrected data As the final data.

1 is a block diagram of a conventional digital TV error correction apparatus

2 is a block diagram of an apparatus for error correction of a digital TV according to the present invention

Figure 3 is a detailed block diagram of the syndrome generator of Figure 2;

4 is a detailed block diagram of the Euclidian divider of FIG.

5 is a detailed block diagram of the error location generating unit of FIG.

Fig. 6 is a detailed block diagram of the error evaluation generation unit of Fig. 2

FIG. 7 is a detailed block diagram of the error polynomial generating unit of FIG.

Fig. 8 is a detailed block diagram of the error checking and data output unit of Fig. 2

DESCRIPTION OF THE REFERENCE NUMERALS

101: Syndrome generator 102: Euclidean divider

103: Euclidean multiplier 104: Error evaluation generator

105: error position generating unit 106: error polynomial generating unit

107: FIFO RAM 108: error correction unit

109: Error check and data output unit

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is an overall block diagram of an apparatus for error correction of a digital TV according to the present invention, which includes a syndrome generator 101 for generating a syndrome S (x) from a received polynomial R (x) An Euclidean divider 102 for calculating the coefficients of the error evaluation polynomial Ω (x) by loading the syndrome S (x) generated in the syndrome generating unit 101 in parallel, a syndrome generator 102 for receiving the syndrome generated by the syndrome generator 101, (X) of the error evaluation polynomial Ω (x) by using the coefficients of the error evaluation polynomial Ω (x) generated in the Euclidean divider 102. The Euclidean multiplier 103 calculates the coefficients of the error evaluation polynomial Ω (X) of the euclidean multiplier 103 to estimate the error position, and outputs the error locator polynomial Λ (x) of the error locator polynomial Λ And outputs the differential value Λ '(α ⁱ ) · α ⁱ . (X) of the error evaluation polynomial Ω (x) obtained by the error evaluation generation unit 104 and the error position obtained by the error position generation unit 105 and the first derivative of the error position polynomial Λ An error polynomial generating unit 106 for obtaining an error value using Λ '(α ⁱ ) · α ⁱ , a FIFO RAM 107 for storing the received polynomial, an error value of the error polynomial generating unit 106, An error correction unit 108 for exclusive-ORing the original data stored in the error correction unit 107 to correct the error, and a syndrome correction unit 108 for calculating the syndrome of the corrected data in the error correction unit 108 to discriminate whether the correction data has been corrected correctly, And an error check and data output unit 109 for selectively outputting original data or correction data stored in the FIFO RAM 108 as final data according to the result.

In the present invention configured as described above, the RS codeword polynomial C (x) is created by adding 2t (t is the number of correctable errors) parity symbols to the message polynomial M (x) to be transmitted, which is actual data. This can be mathematically expressed by Equation 1 below.

C (x) = M (x) 占^X2t + M 占 x 占^2t MOD G (X)

Here, G (x) is a generator polynomial, expressed as Equation (2) below, and if the number of errors to be corrected is 10, 20 values are obtained.

As can be seen from Equations 1 and 2, C (x) is a multiple of G (x), and a root satisfying G (x) = 0 satisfies C (x) = 0.

In this case, in the GA HDTV standard, the generator polynomial G (x) and the primitive polynomial P (x) are defined as Equation (3).

In this way, an error may be caused by the noise on the channel when the RS encoded codeword polynomial C (x) is transmitted on a certain channel, and the data R (x) received at the receiving end, such as a digital TV, 4.

Therefore, the error polynomial E (x) can be expressed by the following equation (5) if? Symbol error occurs due to the channel noise.

Where jk is the position of the kth error and _ejk is the magnitude of the kth error.

In Equation (4), C (x) can be defined as a syndrome polynomial S (x) including information on an error pattern using the multiple of G (x) as Equation (6).

At this time, since the C (x) is the multiple of G (x), it is thereby root of G (x) are both satisfied with the C (x) = 0, S j = R (α j) = C (α j) + E (? ^j ) = E (? ^j ).

Therefore, it can be seen that the syndrome polynomial S (x) is independent of R (x) and depends on the error pattern (Dependent).

Then, the root of G (x) in the GA HDTV standard is ^{α 0, α 1, ...,} α 18, α 19 , so the coefficients of S (x) are the received data to ^{α 0 ~ α 19 R (x} ) And can be obtained by the following equation (7).

In Equation (7), the coefficients S _j of the syndrome can be expressed by the following Equation (8).

As shown in Equation (8), the coefficients of each syndrome can be calculated by repeating Galois field addition and multiplication.

Accordingly, the syndrome generator 101 can be implemented as shown in FIG. 3, and is composed of N (i.e., twenty) syndrome blocks.

A first multiplexer for selectively outputting an output of the adder or an input data symbol according to a block edge signal, a second multiplexer for selectively outputting the data symbol, A constant Galois field multiplier for multiplying the output of the first register by an a-exponent value of a corresponding order, that is, α ¹ (1 ≦ i ≦ 2t) and feeding back the result to the adder, a first register for temporarily storing the output of the first multiplexer, A second multiplexer for selectively outputting a syndrome coefficient fed back from a final output stage (S ₀ ) or an output of the first register according to the block edge signal, and a second multiplexer for outputting the output of the second multiplexer And a second register for storing the data.

Here, the first syndrome block, the third syndrome block, and the Nth syndrome block are the same as those of the second syndrome block.

3, assuming that the data input symbols are the coefficients of the most significant order, i.e., (N, K, t) RS codes, the coefficients of the X ^N-1 terms are sequentially supplied to the adders of the respective syndrome blocks of the syndrome generator 101 Are input simultaneously. Here, N is the number of symbols of one code block, t is the number of correctable errors, 2t is the parity symbol to be added, and K is N-2t, which is the number of message symbols actually to be sent. Therefore, N = K + 2t symbols.

The adder adds the input symbol and the output of the constant Galois field multiplier to output to the first multiplexer. The first multiplexer selects an input data symbol because there is no accumulated data in a first symbol input cycle when a block code is input according to a block edge signal and selects an addition result of the adder in a remaining interval And outputs it to the first register. At this time, the constant Galois field multiplier multiplies the output of the first register by? ¹ if the value of? Of the corresponding order, for example, S ₁ block, is fed back to the adder. That is, the output of the first register is fed back to the adder only for the cell calculating S ₁ , and the remaining cells are used as inputs to the constant Galois field multiplier.

Meanwhile, the output of the first register is input to the second multiplexer. The second multiplexer selects a final output to be fed back in the first symbol input cycle according to the block edge signal, that is, when one block code is input And selects the output of the first register and outputs it to the second register in the remaining period. The second register outputs a syndrome obtained when data input of one block is completed.

That is, when data input of one block is completed by serial, N syndromes (S ₀ to S ₁₉ ) are output in parallel from N syndrome blocks at the same time.

If, second syndrome block is just around the loop for a cycle 2t, syndrome S ₁ is obtained as shown in Equation 9 below.

Since the syndrome generator 101 uses a constant multiplier that is much smaller in size than a normal multiplier, the number of gates can be reduced by about one tenth compared to the conventional one. Therefore, when integrated into a VLSI, the design is easy and the chip size can be reduced. Cost can also be reduced.

The Euclidean divider 102 receiving the syndromes S ₀ to S ₁₉ output in parallel from the syndrome generator 101 obtains the coefficients of the error evaluation polynomial Ω (x) and outputs the coefficients of the Euclidean multiplier 103 obtains the coefficient of the error locator polynomial Λ (x).

As shown in FIG. 4, each of the cells of the Euclidean divider 102 is connected to each of the multiplexers from a low-order coefficient of the syndrome polynomial S (x), and when the load enable signal is high, Is inputted to the multiplexer, and when the cell is low, the cell output of the previous stage of each cell is inputted to the multiplexer. At this time, the load enable signal is made high by using the edge detection signal only for one clock cycle. Therefore, S (x) is loaded in parallel for one clock cycle in the register of each cell connected to the output terminal of the multiplexer of each cell. The above-described FIG. 4 is performed until the degree of the error evaluation polynomial? (X) becomes smaller than t. Other than the above, the same as the conventional technique, and therefore, detailed description of the operation will be omitted.

Since the above-described Euclidean divider loads S (x) into the registers of each cell at a time in parallel, only a total of 2t clock cycles are required, thereby shortening the Euclidean divide operation time by about half the conventional technique .

The error position generator 105 receives the coefficients of the error locator polynomial Λ (x) output from the Euclidean multiplier 103 as shown in FIG. Finding α ⁱ satisfying _{x = α} ⁱ = 0 and Λ '(x) | and calculates the value of _{x = alpha} ⁱ .

That is, Figure 5 is t + 1 of the output of the register cell (51-0~51-t) and each cell (51-0~51-t) to the sum total of the rings exclusive Iowa Λ (α ⁱ⁾ (Total (X) of the error locator polynomial Λ (x) by extracting only the coefficients of the odd term of the outputs of the registers of the respective cells and obtaining an output of the exclusive OR gate 56 And a zero detection unit 57 for determining whether the output of the exclusive OR gate 56 is 0 and estimating an error position.

The t-th cell of the (t + 1) th cell is taken as an example. In accordance with the selection signal (MUX_SEL), the t-th value Λ _t input in parallel is selectively output. A first multiplexer 52 selectively outputs a ^{(255-N + 1) t} at the beginning according to the selection signal MUX_SEL and selectively outputs a value of α ^t thereafter, A multiplier 54 for multiplying the output of the second multiplexer 52 and 53 and a multiplier 54 for temporarily storing the output of the multiplier 54 and outputting the same to the exclusive OR gate 56 and feeding back the result to the first multiplexer 52 And a register 55 as shown in Fig. The configuration of the remaining cells is the same as that of the t-th cell. At this time, the multiplier 54 can improve the integration degree when integrated into a VLSI by using a constant Galois field multiplier.

If the error location generator 105 receives the coefficients of the error locator polynomial Λ (x) in parallel, the selection signal MUX_SEL becomes low in the initial clock cycle. By this selection signal MUX_SEL, in the first multiplexer _t Λ, Λ _t-1, ..., Λ ₁ is selected and the second multiplexers constant ^{α (255-N + 1)} t is selected from each other from the constant multiplying Galois field multiplier, respectively And stored in each register. From the next clock cycle, the selection signal MUX_SEL goes high, and the output of the register of each cell is output to the exclusive OR gate 56 and fed back to the first multiplexer. Therefore, a value fed back from each register is selected by the selection signal MUX_SEL in the first multiplexer of each cell, and in the second multiplexer, the selection signal? ^T is selected and multiplied by the constant Galois field multiplier, Lt; / RTI >

This process is performed for N cycles. Where N is the number of data symbols in the block.

That is, in the above-described manner, it is possible to obtain a value calculated every time the index is sequentially incremented from? ^{-N + 1} to? ⁰ in? (X). The output of the register of each cell 51-0 to 51-t output every clock is exclusive-ORed by the exclusive OR gate 56 and is output to the zero detecting section 57. The zero detecting section 57 outputs Determines whether the value is zero or not. At this time, if the output of the exclusive OR gate 56, that is, the root of the error locator polynomial Λ (x) is 0, the position is the place where the error occurred. If the error locator polynomial Λ (x) = 0 at α ^p , the p-th error position is obtained.

On the other hand, the value of Λ '(x) that differentiates Λ (x) differs only from the odd term of the output of each register, ie, the coefficients of the first, third, fifth, 56). For example, if Λ (x) = α⁵X³+ alpha²X²+ αX + alpha⁷If you say that, Λ '(x) = 3 · α⁵X²+ 2.alpha.²X^One+ (x), and the even term of Λ (x) is multiplied by an even number when it is differentiated, so that it is lost due to the characteristic of the Galois field addition, so that Λ '(x) = α⁵X²+ < / RTI >

At this time, if only the coefficients of the odd term are extracted from the exclusive OR gate 56, the values of Λ '(α ⁱ ) are not calculated and output but α ⁱ Λ' (α ⁱ ) is outputted. However, when the error magnitude is calculated by the error polynomial generation unit 106, since the value of α ⁱ Λ '(α ⁱ ) is required, this value is output as it is.

6 is a detailed block diagram of the error evaluation generation unit 104. It is assumed that coefficients of the error evaluation polynomial Ω (x) output from the Euclidian divider 102 are input in parallel instead of coefficients of the error locator polynomial Λ (x) Except that the zero detecting section is not necessary, and operates in the same manner as the error position generating section of FIG. 5 described above. That is, the error evaluation generation unit 104 receives the coefficients of the error evaluation polynomial Ω (x) output from the Euclidean divider 102 in parallel and outputs Ω (α ⁱ ), α ⁱ = α ^{255-N + 1} ,? ^{255-N + 2} , ...,? ^-1 ,? ⁰ .

7 is a detailed block diagram of an error polynomial generating unit 106 for calculating an error polynomial E (x). The error polynomial generating unit 106 performs error correction corresponding to the error position obtained by the error position generating unit 105 by a Forney algorithm. Value.

7 shows an inverse ROM 71 for inverting the value of Λ '(α ⁱ ) · α ⁱ output from the exclusive OR gate 56 of the error position generator 105, an output of the inverse ROM 71 And a Galois field multiplier 72 for multiplying the output of the Galois field multiplier 72 by? (? ^I ) output from the error evaluation generator 104 and a zero or the multiplier 72 ), And outputs the result as an error polynomial E (x).

7, which is constructed as described above, can be obtained by calculating Ω (α ⁱ ) calculated by the error evaluation generation unit 104 and the error position signal calculated by the error position generation unit 105 and the value Λ '(α ⁱ ) · α ⁱ The size of the error is calculated by the following Pony algorithm as shown in Equation (10).

Where h is the offset and GA HDTV standard is -1.

That is, when the value of Λ '(α ⁱ ) · α ⁱ output from the exclusive OR gate 56 of the error location generator 105 passes through the inverse ROM 71 . The Galois field multiplier 72 multiplies the output of the inverse ROM 71 ) Is multiplied by the value of? (? ^I ) calculated by the error evaluation generating unit 104, the coefficient of the error polynomial E (x), that is, the error value is calculated. At this time, the multiplexer 73 selects the coefficient of the error polynomial E (x) obtained by the multiplier 72 at the position where the error has occurred according to the error position signal calculated by the error position generator 105, And outputs the selected zero signal to the error correction unit 108. [

The error correction unit 108 is an exclusive OR gate and exclusively processes the error value output from the error polynomial generation unit 106 and the original data stored in the FIFO RAM 107 to correct an error, And outputs it to the confirmation and data output unit 109.

8 is a detailed block diagram of the error checking and data output unit 109. The first FIFO 81 stores original data output from the FIFO RAM 107, A syndrome calculation unit 83 for calculating a syndrome using the correction data output from the error correction unit 108, a syndrome calculation unit 83 for calculating a syndrome calculated by the syndrome calculation unit 83, And a correcting data stored in the first FIFO 81 or the second FIFO 82 according to the discrimination result of the zero detecting unit 84 And a multiplexer 85 for outputting the data as final data.

Here, the syndrome calculation unit 83 has the same structure as the syndrome calculation unit 101 of FIG. 3 described above.

The error checking and data output unit 109 of FIG. 8 configured as described above calculates syndromes on the corrected data to check whether the corrected data is correctly corrected or not by the error correction unit 108, and outputs S (x) = 0 Or not.

That is, the first FIFO 81 stores the original data output from the FIFO RAM 107 and the second FIFO 82 stores the correction data output from the error correction unit 108. Then, the syndrome calculation section 83 calculates the syndrome S (x) in the same manner as in Fig. 3 using the correction data.

The zero detection unit 84 determines whether the syndrome S (x) calculated by the syndrome calculation unit 83 is 0 or not and outputs the result as a selection signal of the multiplexer 85. That is, if the syndrome S (x) = 0 of the corrected data means that the data is corrected correctly, the multiplexer 85 selectively outputs the correction data stored in the second FIFO 82 as final data, If the syndrome S (x)? 0 indicates that more than t errors have occurred on the transmission channel, the multiplexer 85 selects and outputs the uncorrected original data stored in the first FIFO 81 as final data .

Therefore, when more than t errors occur on the channel, it is possible to prevent an error caused by a malfunction of the R-S decoder.

Meanwhile, the structure of the R-S decoder used in the present invention can be applied to all (N, K) R-S codes.

As described above, according to the error correcting apparatus of the digital TV according to the present invention, since the syndrome polynomial of the correction data is calculated and the syndrome polynomial of the correction data is 0, it means that the data is corrected correctly, If the syndrome polynomial of the data is not 0, it means that there are more than t errors on the transmission channel. Therefore, if more than t errors are generated on the channel by outputting uncorrected original data as final data, This can prevent errors.

In addition, a syndrome generator, an error location generator, an error evaluation generator, and an error polynomial generator use a constant Galois field multiplier instead of a general ordinary multiplier, and a similar cell basis structure to the error location generator and the error evaluation generator It is possible to easily design the integrated circuit in the VLSI, improve the integration degree, reduce the chip size, and reduce the cost.

The syndrome generator outputs the syndrome polynomials in parallel, and the Eclipse divider loads them in parallel, thereby shortening the execution time of the divide operation, thereby reducing the size of the FIFO RAM, and shortening the pipeline structure The size of the FIFO RAM can be further reduced.

Claims (14)

An error correction apparatus for a digital TV that corrects an error by receiving an RS code word polynomial C (x) generated by adding 2t (t is the number of correctable errors) parity bits to a message polynomial M (x) , A syndrome generator for generating a syndrome polynomial S (x) from the received polynomial R (x) and outputting it in parallel; An Euclidean divider that loads the syndrome polynomial S (x) generated in the syndrome generator in parallel to obtain a coefficient of the error evaluation polynomial Ω (x); An Euclidean multiplier receiving a syndrome generated by the syndrome generator and obtaining a coefficient of an error locator polynomial Λ (x); An error evaluation generator for calculating a root of a coefficient of the error evaluation polynomial Ω (x) generated in the Euclidean divider to estimate an error magnitude; Obtaining the roots of the error locator polynomial by Euclidean while the error locator polynomial in the multipliers Λ (x) increase in the indices from ^{-N +} α ¹ to α ⁰ Sikkim assigned sequentially Λ (x) Λ (α ⁱ ) = 0 generates a position of x = α ⁱ satisfying and the error locator polynomial Λ (x) 1-order differential function Λ '(error position generating and outputting a x) of the unit; (X) of the error evaluation polynomial Ω (x) of the error evaluation generating unit and the error position calculated by the error position generating unit and the first order differential function Λ '(x) of the error locator polynomial Λ (x) x), < / RTI > A memory for storing the received polynomial R (x); An error corrector for correcting an error by logically combining the error polynomial E (x) of the error polynomial generator and original data stored in the memory; A syndrome calculation unit for calculating a syndrome of the corrected data by the error correction unit, discriminating whether the correction data has been corrected correctly, checking whether the original data stored in the memory or the corrected data by the error correction unit is selected and output as final data, And a data output unit for outputting the error correction code. 2. The apparatus of claim 1, wherein the syndrome generator The error correction unit is designed to satisfy the following equation. Here, N is the number of data symbols of one code block, and S _j is the jth syndrome coefficient. 2. The apparatus of claim 1, wherein the syndrome generator An adder for adding the data symbols input in series and the cumulative value fed back, A first multiplexer for selecting an input data symbol in a first symbol input cycle of one block code and selecting and outputting an addition result of the adder in a remaining interval, A first register for temporarily storing the output of the first multiplexer, A constant Galois field multiplier for multiplying an output of the first register by an exponent of a corresponding order and feeding back the result to the adder; A second multiplexer for selecting a syndrome coefficient to be fed back at a final output stage in a first symbol input cycle of one block code and selecting and outputting an output of the first register in a remaining interval, And a syndrome block composed of a second register for storing a syndrome coefficient output from the second multiplexer is provided in the order of the syndrome polynomial S (x). 4. The apparatus of claim 3, wherein the syndrome generator The data input symbols are input to the adder of each syndrome block in serial from the coefficient of the most significant order, and when the data input of one block is completed, the respective syndrome coefficients are output simultaneously through the second register of each syndrome block An error correction device for a TV. 2. The method of claim 1, wherein in the Euclidian divider Each cell is connected to a respective multiplexer from a coefficient of a syndrome polynomial S (x) having a low coefficient, and a coefficient of S (x) is input to the multiplexer if the load enable signal that is high only for one clock cycle is high And a cell output of a previous stage of each cell is input to the multiplexer if low, to obtain a coefficient of the error evaluation polynomial Ω (x). 2. The apparatus of claim 1, wherein the error location generator If the Euclidean coefficient multiplier from the error location polynomial Λ (x) are input in parallel in the initial clock cycle _{Λ t, Λ t-1,} ..., Λ ₁ respectively select the initial index value α ^{(α (255 -N + 1) i; 1 ≤} i ≤ 2t) and then multiplied by each other and stored in the respective registers, in the next clock cycle by each select a value that is fed back from each of the registers and multiplied by the respective index values (α ⁱ⁾ of the order (N is a number of data symbols of one code block) cycle, An exclusive OR gate that logically combines the values output from the respective registers of the cell block every clock to obtain a total sum of? (? ¹ ) And a zero detection unit for determining whether a sum of? (? ¹ ) output from the exclusive OR gate is 0 or not. 7. The apparatus of claim 6, wherein the error location generator Wherein multiplication is performed using a constant Galois field multiplier in each cell block. 7. The apparatus of claim 6, wherein the error location generator (X) obtained by first differentiating the error-locator polynomial Λ (x) is obtained by extracting only the odd-term coefficients of the output of each register from the exclusive OR gate (α ⁱ Λ '(α ⁱ )) Wherein the error correction unit comprises: The apparatus of claim 1, wherein the error evaluation generator When the oil cleaners coefficients of the error evaluation polynomial Ω (x) from Meridian divider are input in parallel in the initial clock cycle _{Ω t, Ω t-1,} ..., select Ω ₁ α respectively to the initial index value ^{(α (255 -N + 1) i; 1 ≤} i ≤ 2t) and then multiplied by each other and stored in the respective registers, in the next clock cycle by each select a value that is fed back from each of the registers and multiplied by the respective index values (α ⁱ⁾ of the order (N is a number of data symbols of one code block) cycle, And an exclusive OR gate for logically combining the values output from the respective registers of the cell block every clock to obtain a total sum of? (? ¹ ). The apparatus of claim 1, wherein the error polynomial generator By applying the Ω (α ⁱ⁾ and the error position The error position signal calculated in the generator and, a primary differential function ^{Λ '(α i) · α} i for pony algorithm calculated by the error evaluation generating unit of the error position occurs And an error value corresponding to the error position obtained by the error correction unit. The apparatus of claim 1, wherein the error polynomial generator An inverse ROM for inverting a first-order differential function Λ '(α ⁱ ) · α ^{i of} the error locator polynomial Λ (X) output from the error position generator, The output of the inverse ROM ) And the output (? (? ^I ) of the error evaluation generation unit) And a multiplexer for selecting a result of the multiplication by zero or the multiplier according to the error position value calculated by the error position generator and outputting the selected result as an error polynomial E (x). 12. The apparatus of claim 11, wherein the multiplexer Selects a coefficient of the error polynomial E (x) obtained by the multiplier at a position where an error occurs, and selects a zero signal at a position where no error has occurred. The apparatus of claim 1, wherein the error checking and data outputting unit A first first-in-first-out memory for storing original data output from the memory; A second first-in-first-out memory for storing correction data output from the error correcting unit; A syndrome calculation unit for calculating a syndrome of correction data output from the error correction unit; A zero detection unit for determining whether the syndrome calculated by the syndrome calculation unit is 0, And a multiplexer for selecting the original data stored in the first first-in-first-out memory or the correction data stored in the second first-in-first-out memory according to the discrimination result of the zero detection unit and outputting the selected data as final data. . 14. The apparatus of claim 13, wherein the multiplexer If the syndrome S (x) of the correction data is 0, the correction data stored in the second first-in-first-out memory is selected and outputted as final data, and if the syndrome S (x) And outputs the selected data as final data.