KR100335482B1 - Error correcting system - Google Patents

Abstract

PURPOSE: An error correcting system is provided to realize a circuit to calculate an error position by a syndrome calculating circuit, thereby simplifying the circuit arrangement and the chip realization. CONSTITUTION: An error correcting system includes a data buffer(80) for storing received data, a syndrome and error position calculator(81) for calculating a syndrome in response to the received data and calculating an error position multinominal expression, an operation part(82) for calculating a coefficient of the error position multinominal expression and an error value, and an adder(85) for correcting an error calculated in the error position calculated in response to the output signal from the data buffer, an output signal from the syndrome and error position calculator and an output signal from the operation part.

Description

Error Correction System

The present invention relates to an error correction system, and more particularly, to an error correction system used in a digital audio reproducing apparatus such as a compact disc player (CDP), a digital audio tape (DAT), or the like.

Digital audio playback devices such as CDT, DAT, etc. apply random Solomon (RS) code, which is a block code BCH code, to "Cross Interleaving" -processed data, so that random and burst errors Use "Cross Insertion RS Code (CIRC)" to correct

Error correction encoding the CIRC used in the digital audio system is 2 and the block sequence of the finite field GF (2 ⁿ⁾ having ⁿ elements, each element is m bits made up (this is referred to as symbols) and t of error correction capability If you have,

Code length: n = 2 ⁿ -1 (symbols) = m (2 ⁿ -1) (bits);

Information length: k = n-2t (symbols) = m (n-2t) (bits);

Parity-check length: n-k = 2t (symbols) = m (2t) (bits);

Minimum length: d _min = 2t + 1 (symbols).

That is, the CIRC consists of k data symbols, n-k parity symbols, and n code symbols, and is decoded in the following manner.

Each of the n symbols is an m-bit element on the finite field GF ( ²ⁿ ), and is generated by one codeword by the generated polynomial G (x), and α is a finite field source. The generated polynomial is defined as

The codeword C (x) generated by G (x) is transmitted, and the received vector R (x) has an error E (x) generated during transmission.

R (x) = C (x) + E (x) = Σα _i χ ⁱ ------------ Equation <2>

The received vector first obtains the quintet S (i) for decoding. When α is a finite source, α ¹ (O ≦ i ≦ 2t−1) becomes the root of the generated polynomial G ( χ ), and substituting this into equation <2> gives the following expression <3>.

S (i) = R (α ⁱ ) = C (α ⁱ ) + E (α ⁱ ) where O ≦ ⁱ ≦ 2t-1 ------------ Formula <3>

In this case, C (α ⁱ ) becomes '0', and the i th fifth S (i) becomes a parameter including only an error component. This miscalculation circuit is easily implemented with finite field operators, i.e., loops of adders, flip-flops, and multipliers. In other words, the quintet circuit is a division circuit for dividing the received data R (x) by the least polynomial x + α ⁱ .

If q (0≤q≤t) errors occur in E (x)

In addition, according to equations <3> and <4>, each testimony S ₁ is represented by the following formula <5>.

In Equation <5>, e _im (1 ≦ m ≦) is called an error value and is represented by Y _j . Α ^jn (1 ≦ n ≦ q, 1 ≦ _j ≦ q) is referred to as an error position and denoted by Z _j .

therefore,

The error position polynomial σ (x) is

Where e is the number of errors and σ ₁ to σ _e for the positive S (i)

Therefore, when sigma ₁ to sigma _e , which are coefficients of the error position polynomials, are found in equation < 7 _> , and root x _i of equation < 6 > is the error position.

For example, when e = 1 and e = 2, sigma ₁ to sigma _e can be obtained as follows according to equation < 7 &gt;.

When 1 error (e = 1);

When 2 errors (e = 2);

As described above, when σ ₁ σ _2, which is a coefficient of the error position polynomial, is obtained according to the number of errors, respectively, the equation is as follows. Only when e = 1 and e = 2 errors.

After obtaining the error position from the above formulas <10> and <11>,

The error value is obtained as follows.

The error is corrected using the error position data and the error value thus obtained.

The above process is summarized as follows.

1. The false positive S (i) is obtained from the received data R (x).

2. Use the error to find the coefficients and roots of the error-position polynomial, which is the error position.

3. Find the error value from the error and error location.

4. Correct the data at the error location using the error value.

In the above-described flow, the operation on the finite field is required in the process of obtaining the error position and the error value, and a typical conventional method of implementing the ALU on the finite field will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a conventional error correction system. The error correction system includes a data buffer 10, a syndrome generator 11, an error position polynomial coefficient calculator 12, an error position calculator 13, an error value calculator 14, and an adder 15.

The data buffer 10 receives and stores the received data R from the input terminal, and the syndrome generator 11 calculates a false positive S from the received data R. The error position polynomial coefficient calculator 12 calculates the coefficient of the error position polynomial from the error, and the error position calculator 13 calculates the error position from the determined error position polynomial. The error value calculator 14 calculates the error value after the error position is calculated. The adder 15 corrects the error by adding the output of the data buffer 10 and the output of the error value calculator 14.

FIG. 2 is a detailed block diagram showing an example of the polynomial coefficient calculator shown in FIG.

In FIG. 2, the polynomial coefficient calculator 12 includes a syndrome buffer 21, a control buffer 22, a jump buffer 23, an A register 24, an address register 25, a B register 26, and a C register. Register 27, adder 28, F register 29, logarithmic buffer 30, D register 31, E register 32, compensator 33, G register 34, complement address register 35 ), A launch buffer 36 and an H register 37.

The jump control 23 and the control buffer 22 are for the system, the A register 24, the D register 31, the E register 32, the launch buffer 36, the logarithmic buffer 30, and the complementary device 33. ) Is for multiplication and division. The above method is disclosed in US Patent No. 4,142,174. In this system, a large number of algebraic buffers and launch buffers are required, and due to these ROM configurations, there is a problem in that the chip size is increased and the speed is slowed.

3 is another example of a conventional error correction system, which does not use a large number of algebraic and decimal buffers during operation of the error position polynomial calculator, and solves the error position polynomial only by addition and multiplication and generates an error position. This is a method for solving this problem due to the complicated structure of the multiplier on the finite body, has been disclosed in Korean Patent Publication No. 86-903 (July 16, 1986).

In FIG. 3, the error correction system includes the syndrome generator 43, the first register 47, the calculator 46, the second register 44, the third register 45, the RAM 48, and the error position calculator ( 70) and buses 40, 41, 42 connecting them. In addition, the error position interpolator 70 includes latches 49, 50, 51, 52, 59, 61, 62, 63, registers 53, 54, 60, adders 55, 56, and zero detectors 57. And a gate 58.

After receiving the reception data R through the data bus 40, the syndrome generator 43 calculates syndromes S ₀ to S ₃ . The syndromes S ₀ to S ₃ are stored in the memory 48 via the transmission bus 42. Therefore, syndromes S ₀ to S ₃ are read from memory 48 whenever necessary. In addition, the syndrome S ₀ -S _{3 is} supplied to the operation unit ALU 46, the first register 47, the second register 44, and the third register 45 through a transmission bus. Sa, Sb, and Sc are expressed as

Sa = S ₁ ² + S ₀ S ₂

Sb = S ₀ S ₃ + S ₁ S ₂

Sc = S ₁ S ₃ + S ₂ ² --- Equation <14>

The calculating unit 70 adds and multiplies the elements of the galois body. The calculating unit 70 includes a multiplier to be described below.

Sa, Sb, and Sc are supplied to the latch circuits 51, 50, and 49, respectively, via the transmission bus.

At the same time, "1" is supplied to the register 6o. The multiplication register 53 receives the clock pulse CP and multiplies the contents of this register by α. Similarly, the α ² multiplication register 54 receives a clock pulse CP and multiplies the contents of the register by α ² . The register 60 is initially set to "1" and the contents are multiplied by α each time a clock pulse (CP) is received. In this embodiment, registers occur from α ⁰ to α ³¹ .

After Sc, Sb, Sa and " 1 " are stored in the latch circuit, the α multiplication register, the α ² multiplication register and the register, respectively, 31 clock pulses are sequentially applied to the latch circuit and the register to solve the quadratic equation.

More specifically, the output of the latch circuit 52 and the output Sb of the? Multiplication register 50 are applied to the adder circuit 55 and merged with each other. Furthermore, the output Saα ² of the α ² multiplication register 54 and the output of the addition circuit 55 are summed in the addition circuit 56. The result is that the quadratic equation x is replaced by α ⁰ to α ³¹ when the clock pulse CP is applied. The addition circuit 56 generates "0". When the "0" detector 57 detects "0" twice, it means that the root of the quadratic equation has been determined. When the zero detector 57 detects "0", an output signal is generated. The contents of the register are stored in the latch circuits 61, 62, and 63 to obtain α ¹ and α ⁱ² which determine the error position. Data representing α ⁱ and α ^j is transmitted to the calculating unit via the transmission bus. Computing unit multiplies the α ⁱ by α ^j, α adds the α ^{i j.} Therefore, the coefficients σ ₁ and σ ₂ of the error correction coefficient position polynomial are found from the syndrome values.

In the conventional error correction arithmetic unit (ALU), due to the characteristics of the finite field calculation, the error position and size are performed by multiplying and dividing the received data in the form of a polynomial form by the power of α, which is a primitive source, and the opposite ROM. However, as described above, according to the publication No. 86-903, it was designed to obtain the error position by multiplication only without the need for division during the finite field calculation.

However, in the example of '903, a latch and an addition circuit for solving the error position polynomial are additionally required in addition to the basic ALU for addition and multiplication, which causes a complicated circuit and a large chip size.

Accordingly, an object of the present invention is to provide an error correction system having improved circuit configuration by using a generator of a syndrome generator for calculating a polynomial coefficient in order to solve the conventional problems as described above.

In order to achieve the above object, the apparatus of the present invention is a lead solo decoder that can correct single and double errors included in received data which is an element on a galloid body.

A data buffer for storing the received data;

A syndrome and error position calculator for calculating a syndrome by inputting the received data and calculating an error position polynomial;

An operation unit configured to calculate coefficients and error values of an error position polynomial by inputting the output of the syndrome and the error position calculator:

And an adder configured to input an output of the data buffer and correct an error according to the extracted error value at the calculated error position.

Next, the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram showing an error correction system according to the present invention.

The error correction system according to the present invention includes a data buffer 80, a syndrome & error position calculator 81, a finite field calculation unit 82, and an adder 85, and the calculation unit 82 is an error position polynomial coefficient calculator 83. ) And an error value calculator 84.

That is, in a lead solo decoder capable of correcting single and double errors included in reception data, which is an element on a galloid body, a syndrome is calculated by inputting a data buffer 80 and reception data which store the reception data. Inputs of the syndrome and error position calculator 81 and the output of the syndrome and error position calculator 81 for calculating the error position polynomial of the calculation unit 82 and the data buffer 80 for calculating the coefficients and error values of the error position polynomial And an adder 85 for inputting an output and correcting the error in accordance with the extracted error value at the calculated error position.

Comparing the error correction system according to the present invention and the conventional error correction system, it can be seen that a part of the calculation of the error position polynomial for solving the error position polynomial is included in the syndrome calculator. That is, in general, the process of calculating the syndrome from the received data and the circuit are well known, and the present invention is also used to solve the error position polynomial. In this way, the circuit configuration can be simplified by using the multiplier of the syndrome calculation circuit as an additional part for solving the error position polynomial.

In addition, the calculation unit 82 calculates the coefficients and error values of the error position polynomials only through multiplication and addition without using the decimal and logarithmic buffers.

5 is an embodiment of the present invention, which includes a syndrome & error position calculation unit 81, a calculation unit 82, and a RAM 86 connected through a data bus 87.

The syndrome and error position calculator 81 includes first, second, second and fourth adders 94, 93, 92, 91 for adding the received data R with the feedback data, and the first, second, First, second, third, and fourth registers 98, 97, 96, and 95 for storing the outputs of the second and fourth adders 94, 93, 92, and 91, and the second register 97, respectively. The first multiplier 101 to multiply the output of and the second multiplier 100 to multiply the output of the third register 96 and α ² , and the third multiplied by the output of the fourth register 95 and α ³ . A multiplier 99, a zero detector 102 for detecting zero by adding the outputs of the first, second and third registers 98, 97 and 96, and a pulse for generating a cell pulse CP A latch 104 is provided to latch the output of the pulse counter 103 in accordance with the output of the counter 103 and the zero detector 102.

In addition, the calculating unit 82 selects one of the inverse generator 110 for obtaining the inverse of the output of the syndrome and the error position calculator 81, the output of the syndrome and the error position calculator 81, and the output of the inverse generator 110. The sixth and seventh registers 113 for storing the output of the multiplexer 111, the fifth register 112 for storing the output of the multiplexer 111, and the output of the syndrome and error position calculator 81, respectively. 115, the fourth multiplier 114 multiplying the output of the fifth register 112 and the output of the sixth register 113, the output of the fourth multiplier 114 and the output of the seventh register 115 And a fifth adder 116 to be combined.

Looking at the operation of the device of such a configuration as follows. The received data R coming through the data bus 87 first calculates the syndromes SO to S3 in the syndrome and error position calculator 81. The calculating unit 82 obtains coefficients of the polynomial according to equations <8, 9> by addition and multiplication, and stores them in the RAM 86 together with the syndrome values.

Subsequently, the multiplication circuits 99, 100, and 101 of the syndrome register are used as they are to solve the error position polynomial. In this case, 0 ₂ is provided to the first register 98,? ₁ is provided to the second register 97, and “1” is provided to the third register 96.

The pulse counter 103 generates a cell pulse CP to supply the cell pulse CP to the syndrome registers 95 to 98, and the zero detector 102 is provided with the first, second and third registers 98 and 97. , Sum the outputs of 96) and detect that it is zero. When zero is detected, latch 104 latches the output of pulse counter 103, which is an error position. Accordingly, the calculation unit 82 calculates an error value so that the error can be corrected.

As described above, the present invention has the effect of reducing the manufacturing cost and facilitating chip implementation by simplifying the circuit configuration by using the circuit implemented in the syndrome calculation circuit for solving the error position polynomial in the error correction system. .

1 is a block diagram showing a conventional error correction system,

2 is a block diagram of the error position polynomial coefficient calculator of FIG.

3 is another example of a conventional error correction system,

4 is a block diagram showing an error correction system according to the present invention;

5 is an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

80 ... Data buffer 81 ... Syndrome & error position calculator

82 ... Galois calculator 83 ... error-position polynomial coefficient calculator

84 ... Error calculator 85 ... Adder

Claims (3)

In the reed solo only decoder capable of correcting single and double errors contained in the received data which is an element on the galois body, A data buffer for storing the received data: A syndrome and error position calculator for calculating a syndrome in response to the received data and calculating an error position polynomial: An operation unit for calculating a coefficient and an error value of an error position polynomial in response to an output signal of the syndrome and error position calculator: And an adder for correcting an error according to an error value calculated at an error position calculated in response to an output signal of the data buffer, an output signal of a syndrome and an error position calculator, and an output signal of the calculator. Nem. 2. The apparatus of claim 1, wherein the syndrome and error position calculator adds the received data and the returned data: first, second, third and fourth adders: First, second, third and fourth registers for storing the outputs of the first, second, third and fourth adders, respectively: A first multiplier that multiplies the output of the second register by a; A second multiplier that multiplies the output of the third register by α ² A third multiplier that multiplies the output of the fourth register by α ^3; A zero detector for detecting zero by adding outputs of the first, second, and third registers: A pulse counter that generates a click pulse: and And a latch for latching the output of the pulse counter in accordance with the output of the zero detector. The apparatus of claim 1, wherein the calculating unit obtains an inverse of the output of the syndrome and error position calculator. A multiplexer for selecting one of the output of the syndrome and error locator and the output of the inverse generator; A fifth register for storing the output of the multiplexer: Sixth and seventh registers for storing the outputs of the syndrome and error position calculator, respectively: A fourth multiplier that multiplies the output of the fifth register by the output of the sixth register; and And a fifth adder for adding the output of the fourth multiplier and the output of the seventh register.