JP2001044853A - Chain search circuit, error correction device and disk driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chain search circuit that shourtens the time required for chain search without having to increase the number of gates of a multiplication result storage circuit, when conducting pipeline processing for quickening chain search. SOLUTION: A chain search circuit 55 is provided with flip-flop circuits(FF) 101a to 101c, that are provided corresponding to each term of an error location polynomial, store each coefficient of the error location polynomial for an initial value and store a multiplication result of multiplying an element of a Galois field with each coefficient, high-order fixed multipliers 103a to 103c that multiply the powers (αn) of the highest order αrespectively in parallel corresponding to the flip-flop circuits(FF) 101a to 101c, and low order fixed multipliers 104a to 104c that respectively multiply the powers (αn-1) of the lower order α, and the flip-flop circuits (FF) 101a to 101c latch only the result of products of the high-order fixed multipliers 103a to 103c that multiply the powers (αn) of the highest order α.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Chien search circuit, an error correction device, and a disk drive device, and more particularly, to decoding of a Reed-Solomon code on a Galois field GF (2 ⁿ ) using a Chien search. The present invention relates to a Chien search circuit that calculates a root of a position polynomial and obtains an error position, an error correction device, and a disk drive device.

[0002]

2. Description of the Related Art In recent small-sized HDDs, as a means of improving performance by reducing command overhead, an HDD for processing around a host interface is used.
There is a tendency to adopt a technique in which the intervention of a microprocessor of D (hereinafter referred to as a local MPU) is reduced as much as possible, and the processing is performed by a host interface controller (HIC) by hardware as much as possible.

As one of them, data transfer between the host and the cache memory can be performed under the control of the HIC without the intervention of the local MPU, while data transfer between the medium and the cache memory is performed by the local MPU.
Is a hard disk controller
r: Local MP that controls HDC and performs data transfer
It is conceivable to use a system that requires the intervention of U.

On the other hand, in digital signal recording / reproducing devices such as the above HDD and magnetic tapes and optical disks,
2. Description of the Related Art An error correction device using an error correction code is used to correct a data error caused by dropout or the like on a recording medium.

In recent years, a Reed-Solomon code (Reed-Solomon cod
e) Signs are used. The Reed-Solomon code is a correction code defined on a Galois field (Galois field) GF (2 ⁿ ). The Galois field is a set created based on an exclusive OR operation and in which addition, subtraction, multiplication and division operations are defined, and the elements of the Galois field are associated with data in word units and used for error correction. For example, a primitive polynomial p (X) in the Galois field GF (2 ⁸ ) is represented by the following equation (1), and a generator polynomial Gr (X) of the Reed-Solomon code is represented by the following equation (2).

[0006]

(Equation 1)

[0007] A polynomial of any order is represented by the Galois field GF
Since a method of solving algebraically on (2 ⁿ ) is not known, generally, Chien search for checking whether or not all elements on the Galois field GF (2 ⁿ ) are solutions of algebraic equations is performed. ) To find the solution of the polynomial. The Chien search algorithm uses a finite number of elements of the Galois field to sequentially substitute these into a polynomial, and determines whether or not the element is a solution based on whether or not the value of the polynomial is 0, This is performed for all the elements to solve the polynomial.

Further, an error locator polynomial (error locator po
lynomial) indicates the information corresponding to the error position of the data, and the error position of the data can be detected by solving this according to the Chien search algorithm. However, in the Reed-Solomon code, since there are 2 ⁿ -1 kinds of error magnitudes, it is necessary to find not only the error position but also the corresponding error magnitude. The value of the error is determined by an error evaluator polynomial. In general, the error locator polynomial S (z) is expressed by the following equation (3), and the error evaluation polynomial ω (z) is an equation that is one order smaller than S (z).

[0009]

(Equation 2)

FIG. 8 is a block diagram showing a configuration of a conventional error correction device.

In FIG. 8, 11 is an input terminal, 12 is a buffer memory, 13 is a syndrome calculation circuit, 14 is a position polynomial / numerical polynomial calculation circuit, 15 is a Chien search circuit, 16 is an error numerical calculation circuit, and 17 is error correction. Circuit, 1
8 is an output terminal.

From input terminal 11, received signals Y0, Y1,.
, Yn-1 are input, and the syndrome calculation circuit 13 calculates the syndrome from the received signal. Syndrome is
It is supplied to the position polynomial / numerical polynomial calculation circuit 14, where the coefficients of the error position polynomial and the error numerical polynomial are calculated. The Chien search circuit 15 derives the error position by finding the root of the error position polynomial. Further, the error value calculation circuit 16 obtains the magnitude of the error at the error position from the error position polynomial and the coefficients of the error value polynomial.

The error correction circuit 17 includes a buffer memory 12
, And corrects the error having the magnitude calculated at the error numerical value calculation circuit 16 at the error position determined by the Chien search circuit 15, and outputs the decoding result from the output terminal 18.

FIG. 9 is a flow chart showing the error correction processing of the error correction apparatus, and (1) to (5) show the steps of the processing. (1) First, the syndrome calculation circuit 13 outputs the received signal Y
A syndrome is generated from 0, Y1,..., Yn-1, and the generated syndrome is calculated by the position polynomial / numerical polynomial calculation circuit 14.
Transfer to Here, all the generated syndromes are 0
If so, it is determined that there is no error. (2) The position polynomial / numerical polynomial calculation circuit 14 calculates an error position polynomial and an error evaluation polynomial (coefficients of the error numerical polynomial) using the generated syndrome. (3) The Chien search circuit 15 finds the root of the error locator polynomial to find the error location. (4) The error value calculation circuit 16 obtains an error value at the error position from the error position polynomial and the error evaluation polynomial. (5) The error correction circuit 17 corrects the error data using the detection result of the error position.

Hereinafter, a Chien search circuit used in a conventional error correction device will be described.

Normally, since it is difficult to directly find the root of a fourth-order or higher-order equation, when finding the root of an error locator polynomial of a linear cyclic code, elements on the field of the code are substituted into X one by one. Then, a root is obtained by checking whether or not the error locator polynomial S (z) becomes 0. The root search by this method is called a Chien search.

For example, when the Galois field GF (2 ⁸ ) is used, since 255 elements exist, 255 clocks are required at least until all the elements have been substituted into the Chien search circuit.

However, in a device such as an HDD having a high transfer rate, the time available for the chain search is limited.
The Chien search circuit is divided into a plurality of circuit units for processing by pipelining, and the time for Chien search is shortened by operating each circuit unit in parallel.

FIG. 10 is a diagram showing the configuration of a Chien search circuit used in a device having a high transfer rate such as an HDD, and is an example of a two-stage pipeline.

In FIG. 10, reference numeral 20a denotes a first-stage Chien search circuit having a pipeline configuration, 20b denotes a second-stage Chien search circuit, and 21a to 21f denote the coefficients of the error locator polynomial or the Galois field Flip-flops (FF) constituting an 8-bit register for holding the product of multiplication of the elements, 22a to 22f convert coefficients S1 to Si of the error locator polynomial into flip-flops (FF) 21a to
Input terminals for input to 21f, 23a to 23c are 2
Fixed multipliers 24a to 24c to multiply the coefficients S1 to Si related to X of the error locator polynomial shown in the above equation (3) by α ⁿ in the Chien search circuit 20b and output the result to flip-flops (FF) 21d to 21f. 24f is each input S
A fixed multiplier that multiplies, as coefficients, exponentially displayed elements of a continuous Galois field, which is a solution of a code generation polynomial of a Reed-Solomon code, by multiplying ¹ to Si, S1 to Si by α ^n, and a flip-flop 25a (FF) 21a-21c
Exclusive OR (EOR) circuit that performs an exclusive OR operation on the output of each bit, and a flip-flop (FF) 25b
An exclusive OR (EOR) circuit that performs an exclusive OR operation on the outputs of 21d to 21f for each bit.

The output of the EOR circuit 25a or the EOR circuit 2
When the output of 5b is 0, the position at that time becomes an error locator. Note that the error locator is obtained in the form of α ⁻¹ , and usually converts this index expression into a vector position having a bit width expressed by a Galois field GF (2 ⁿ ) using an index-vector conversion circuit (not shown). And used in the next correction step.

Flip-flops (FF) 21d to 21f
Constitutes a multiplication result holding circuit for holding the multiplication result.

In the drawing, n is an arbitrary constant indicating a power of α. In the case of a Galois field GF (2 ⁸ ) and a two-stage pipeline, it is 128.

In the above configuration, the first-stage Chien search circuit 20a converts the coefficients S1 to Si of the respective degrees of the error locator polynomial input from the input terminals 22a to 22c into the corresponding flip-flops (FF) 21a to 21c. To load. In the fixed multipliers 24a to 24c, each input S
A product obtained by multiplying 1 to Si by an element of a continuous Galois field expressed as an exponent which is a solution of a code generation polynomial of a Reed-Solomon code and multiplying the element of a Galois field by a flip-flop (F
F) Hold at 21a-21c. The power of α is repeated by the corresponding order of the error locator polynomial to check α ^{0 to} α ⁿ⁻¹ among the coefficients of the error locator polynomial.

The second-stage Chien search circuit 20b is fixed.
The input terminals 22d to 22f are determined by the multipliers 24a to 24f.
Coefficients S1 to Si of each order of the error locator polynomial input from
To α ⁿAnd S1 to Si are converted to αⁿMultiplied by the error position
Flip-flop corresponding as the second half coefficient of polynomial
(FF) Load to 21d to 21f. Fixed multiplier 24
For d to 24f, α is assigned to each of S1 to Si.ⁿMultiplied by
What is the solution of the code generation polynomial of the Reed-Solomon code
Multiplies successive Galois fields in exponential notation, and
The result of multiplying the element of the field is flip-flop (FF) 2
It is held at 1d to 21f. The power of α is calculated as the error position
Error location polynomial by repeating the corresponding order of the polynomial
Α among the coefficients of the equationⁿ~ Α²⁵⁵Inspect up to.

Thus, the two-stage pipelined Chien search circuit has half the clock (128 clocks) compared to the non-pipelined Chien search circuit.
Makes it possible to make all the original substitutions. That is,
The first-stage Chien search circuit 20a starts by substituting α ⁰ , and the second-stage Chien search circuit 20b generates α ¹²⁸
, All the original substitutions are completed in 128 clocks. Therefore, the time for the chain search can be reduced to about half.

[0027]

However, such a conventional Chien search circuit has the following problems.

In a device having a high transfer rate such as an HDD,
Since the time available for the chain search is limited, the time for the chain search is shortened by using a pipeline as described above. However, it is necessary to prepare as many Chien search circuits as the number of pipelines for pipelining, which has led to a significant increase in gate circuits. For example, in a two-stage pipelined Chien search circuit, 2i flip-flops (FFs), which are multiplication result holding circuits, are required twice that before the pipeline processing.

A specific description will be given. For example, two ⁸ in the body,
An erasure correction (Erasure Co.) that uses a Reed-Solomon code using a twelfth-order generator polynomial and decodes a random error (Random Error) and a burst error (Burst Error) using a flag (pointer) indicating an error position.
rrection) using the Euclid's algorit method
hm). If this is realized by hardware, the number of 8-bit flip-flops (FF) used in one Chien search circuit in FIG. 10 is 29, which is about 3500 gates. In FIG. 10, 2
Since it is a pipeline of stages, the sum of the two Chien search circuits is about 7000 gates. That is, 2
Pipelining reduces the Chien search time to half the speed (128 clocks), but doubles the flip-flop (FF) in the Chien search circuit from about 3500 gates to about 7000 gates.

The present invention provides a chain search circuit capable of reducing the time required for a chain search without increasing the number of gates of a multiplication result holding circuit when performing pipeline processing for speeding up the chain search. , An error correction device and a disk drive device.

[0031]

SUMMARY OF THE INVENTION A Chien search circuit according to the present invention provides an element in the field of a linear cyclic code for each coefficient of an error locator polynomial indicating the position of an error occurring in the linear cyclic code. In a Chien search circuit that determines the root by substituting whether or not the error locator polynomial becomes 0, the Chien search circuit is provided corresponding to each term of the error locator polynomial, and holds each coefficient of the error locator polynomial as an initial value. A multiplication result holding means for holding a multiplication result obtained by multiplying each coefficient of the position polynomial by an element of the field; and a field having a different degree in the holding result held in the multiplication result holding means and arranged in parallel with the multiplication result holding means. And a plurality of fixed multiplier groups for multiplying the element of, wherein the multiplication result of the highest-order fixed multiplier group among the plurality of fixed multiplier groups is held in the multiplication result holding means. Features.

When decoding the Reed-Solomon code on the Galois field GF (2 ⁿ ), the Chien search circuit according to the present invention calculates the root of the error locator polynomial using the Chien search and finds the error position. In the circuit, multiplication is provided corresponding to each term of the error locator polynomial, holds each coefficient of the error locator polynomial as an initial value, and holds a multiplication result obtained by multiplying each coefficient of the error locator polynomial by an element of a Galois field. A plurality of fixed multiplier groups arranged in parallel with the result holding means and the multiplication result holding means for multiplying the held results held by the multiplication result holding means by elements of Galois fields of different orders; Exclusive OR means for performing an exclusive OR operation for each bit component of the output of the group of units, and multiplying the multiplication result of the highest-order fixed multiplier group among a plurality of fixed multiplier groups Retention Characterized by being configured to hold the stage.

In the Chien search circuit according to the present invention, the multiplication in each fixed multiplier group may be executed simultaneously by the same clock.

The Chien search circuit according to the present invention performs a Chien search in which the element of the Galois field corresponding to the minimum code length is substituted into an error locator polynomial of order i (where i is an arbitrary positive integer).
When the number of pipelines is n (n is an arbitrary positive integer) and the time required for Chien search is code length / n, the number of fixed multiplier groups is n, and the multiplication result holding means is:
The number may be i-1.

[0035] The error correction device according to the present invention comprises: syndrome generation means for generating a syndrome from input data;
Calculating means for calculating an error locator polynomial and an error evaluation polynomial using a syndrome; chien search means for finding a root of the error locator polynomial by a chien search; and correction for correcting an error in data using an error position and an error value And an error correction device comprising: a chain search circuit according to any one of claims 1 to 4;

A disk drive device according to the present invention includes a recording / reproducing means for reproducing a servo sector on a disk-shaped recording medium and recording or reproducing a data sector, and at least controlling input / output of data to / from an external device or recording / reproducing. A disk drive device comprising: a control unit that controls recording or reproduction of a data sector by a unit; and an error correction unit that realizes decoding of data based on an error correction code by a hardware structure having a Chien search circuit structure. The Chien search circuit uses the Chien search circuit according to any one of claims 1 to 4.

[0037]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 is a block diagram showing a configuration of a disk drive device according to a first embodiment of the present invention. This embodiment is an example in which a Chien search circuit and an error correction device are applied to an HDD that requires a high transfer rate.

In FIG. 1, a magnetic disk drive (HD
D) 30 is a magnetic disk 31 as a data recording medium
(Disk-shaped storage medium) and
A magnetic head 32 for performing reproduction, a head arm 33 to which the magnetic head 32 is attached, a head amplifier (AE) 34 disposed close to the magnetic head 32 and amplifying a reproduction signal of the magnetic head 32, Servo pattern from reproduction output supplied via AE34, cylinder I
A channel 35 for extracting D (CYLID) and the like, converting an encoding method, and the like, and a hard disk controller (Hard Disk) for controlling operations such as reading / writing data from / to a magnetic disk and decoding an error correction code.
Controller: HDC) 36, an MPU 37 for controlling the operation of the entire HDD including control of the HDC 36, and a sector buffer 38 composed of a DRAM for temporarily storing supplied data and for caching recorded / reproduced data. It is comprised including.

The HDC 36 includes a head arm 33.
VCM including a voice coil motor (VCM) for moving the magnetic disk 31 and a spindle motor for rotating the magnetic disk 31.
A VCM drive unit (all not shown) for driving a CM is provided. The HDC 36, the MPU 37, and the sector buffer 38 are configured as, for example, a single semiconductor element as an HDC-MPU integrated chip.

The channel 35 is a read / write channel module in which a waveform shaping circuit, an analog / digital converter (ADC), a digital / analog converter (DAC) and the like are modularized. The channel 35 supplies an analog voltage corresponding to the reproduction level of the servo pattern or a digital value corresponding thereto to the HDC 36.

The MPU 37 is a microprocessor for executing a control program, and includes a memory for storing the control program and data. The MPU 37 executes the control program to control commands with external devices, input / output control of data, It executes write / read control for the disk 31 and the like.

The HDC 36 generates a control signal for the channel 35, searches for a servo pattern, generates a CYLID from a gray code reproduced output, and the like, and outputs a drive signal for outputting these signals and the sector data shown in FIG. And an ECC control unit (error correction device) 42 that implements decoding of servo data based on an ECC (error correcting code) by a hardware structure having a Chien search circuit structure, and holds a sector buffer segment. A memory controller 43 for controlling the sector buffer 38 and a host controller 44 comprising an interface (I / F) for connecting to an external host device via a bidirectional line are provided.

FIG. 2 is a diagram showing the structure of sector data used in the HDD 30.

As shown in FIG. 2, one sector data is 5
It consists of 12 bytes of user data and ECC.

The HDC 36 operates according to a preset hardware sequence while the MPU 37 operates according to a program. For this reason, the operation can be performed at a higher speed than that of the MPU 37 although the operation is specialized for the servo control. After the predetermined parameters are set by the MPU 37 or the like, the operation can be performed independently, and the processing load of the MPU 37 or the like is not increased so much.

The ECC controller 42 is mounted as a part of the HDC 36, and the HDC 36 is provided on the same element as the MPU 37 as described above. Therefore, the number of terminals for inputting and outputting signals to and from the outside of the device can be reduced while maintaining the number of wires between the HDC 36 and the MPU 37. This can contribute to downsizing of the package size and downsizing of the device.

The ECC controller 42 is specifically configured as shown in FIG.

FIG. 3 is a block diagram showing the configuration of the ECC controller 42. The block configuration itself is the same as in FIG.

In FIG. 3, 51 is an input terminal, 52 is a buffer memory, 53 is a syndrome calculation circuit (syndrome generation means), 54 is a position polynomial / numeric polynomial calculation circuit (arithmetic means), and 55 is a Chien search circuit (Chen search circuit). Means, 56 is an error value calculation circuit, 57 is an error correction circuit (correction means), and 58 is an output terminal.

From input terminal 51, received signals Y0, Y1,.
, Yn-1 are input, and the syndrome calculation circuit 53 calculates the syndrome from the received signal. Syndrome is
It is supplied to the position polynomial / numerical polynomial calculation circuit 54, and the coefficients of the error position polynomial and the error numerical polynomial are calculated. The Chien search circuit 55 derives the error position by finding the root of the error position polynomial. Further, the error value calculation circuit 56 obtains the magnitude of the error at the error position from the error position polynomial and the coefficients of the error value polynomial.

The error correction circuit 57 includes a buffer memory 52
Receives the received signal, corrects the error having the magnitude calculated at the error value calculation circuit 56 at the error position determined by the Chien search circuit 55, and outputs the decoding result from the output terminal 58.

The configuration of the disk drive device according to the present embodiment has been described above. The feature of the present embodiment lies in the structure of the Chien search circuit realized by the ECC controller 42 using hardware logic.

That is, the ECC control unit 42 according to the present embodiment has not only hardware logic for performing error correction but also a Chien search circuit structure described below. As long as it has, the type of the disk drive device and the position control method of the actuator can be applied to any type.

FIG. 4 is a block diagram showing the configuration of the Chien search circuit 55, and is a diagram showing the configuration of a Chien search circuit used for an HDD having a high transfer rate. This embodiment is an example in the case where the number of pipelines is set to two when performing pipeline processing for speeding up the Chien search.

In FIG. 4, the chain search circuit 55
Flip-flops (FF) 101a to 101c (multiplication result holding means) constituting an 8-bit register for holding the result of multiplying the coefficient of the error locator polynomial by the element of the Galois field; Coefficients S1 to Si related to the polynomial Z are flip-flop (FF) 101a to
Input terminals 102a to 102c for inputting to 101c
Are arranged in parallel with the flip-flops (FF) 101a to 101c, and multiply the coefficients S1 to Si of the error locator polynomial by a higher-order power of α (α ⁿ ) of the order of the error locator polynomial, thereby obtaining a flip-flop (FF ) The high-order fixed multipliers 103a to 103c that output to the 101a to 101c and the flip-flops (FF) 101a to 101c are arranged in parallel, and the multiplication results held in the flip-flops (FF) 101a to 101c are added to the error position polynomial. Low-order fixed multipliers 104a to 104c for multiplying and outputting a lower-order power of α (α ^n-1 ) among the orders and a higher-order fixed multiplier 103a
Flip-flop (F
F) An exclusive OR (EOR) circuit 105 (exclusive OR means) for performing an exclusive OR operation on the outputs of 101a to 101c for each bit, and low-order fixed multipliers 104a to 104
An exclusive OR (EOR) circuit 106 (exclusive OR means) for performing an exclusive OR operation on the multiplication result of c for each bit.

The high-order fixed multipliers 103a to 103c
A high-order fixed multiplier group 103 (a plurality of fixed multiplier groups) is configured as a whole, and low-order fixed multipliers 104a to 104c are formed.
Constitute a low-order fixed multiplier group 104 (a plurality of fixed multiplier groups) as a whole.

Output of EOR circuit 105 or EOR circuit 1
When the output of 06 is 0, the position at that time becomes an error locator. Note that the error locator is obtained in the form of α ⁻¹ , and usually converts this index expression into a vector position having a bit width expressed by a Galois field GF (2 ⁿ ) using an index-vector conversion circuit (not shown). And used in the next correction step.

Flip-flops (FF) 101a to 101
1c is a higher-order fixed multiplier 103a-103 that multiplies a higher-order power of α (α ⁿ ) among the degrees of the error locator polynomial.
Only the multiplication result of c is held.

The high-order fixed multipliers 103a to 103c
Flip-flops (FF) 101a to 101c are arranged in parallel, and multiply coefficients S1 to Si of the error locator polynomial by the highest power of α (α ⁿ ) of the order of the error locator polynomial, and are pipelined. In the present embodiment in which the number of is 2, the powers of α are α ⁻² , α ⁻⁴ ,..., Α ⁻²ⁱ , respectively.

The low-order fixed multipliers 104a to 104c are
The flip-flops (FF) 101a to 101c are arranged in parallel with the flip-flops (FF) 101a to 101c.
Is multiplied by a low-order power of α (α ^n-1 ) of the order of the error locator polynomial and output.
In the present embodiment, the powers of α are α ⁻¹ , α ⁻² ,
…, Α ^-i .

Here, high-order fixed multipliers 103a to 103a
The arrangement of 3c (high-order fixed multiplier group 103) and low-order fixed multipliers 104a to 104c (low-order fixed multiplier group 104) will be described more specifically.

The chain search circuit 55 is provided in parallel with each flip-flop (FF) 101a to 101c,
Higher-order fixed multipliers 103a to 103c for multiplying the highest order powers of α (α ⁿ ), and lower-order αs
Powers (α ^n-1) to multiply respectively disposed a low following the fixed multiplier 104 a to 104 c, high-order fixed multiplier for multiplying the power of most higher α (α ⁿ⁾ 103a~10
Only the multiplication result of 3c is flip-flop (FF) 101
a to 101c and a high-order fixed multiplier 1
03a to 103c are multiplied by an EOR circuit 105, and the multiplication results of the low-order fixed multipliers 104a to 104c are multiplied by an EOR circuit.
Each of the circuits 106 performs an EOR to search for a result of the error locator polynomial calculation of 0.

Focusing on such a configuration in each of the flip-flops (FF) 101a to 101c, for example, the flip-flop (FF1) 101a multiplies α ⁻² in parallel with the flip-flop (FF1) 101a. A high-order fixed multiplier 103a and a low-order fixed multiplier 104a that multiplies by α ^{−1 in} which the order of the error locator polynomial is one lower than the fixed multiplier 103a are arranged. Only multiplication result is flip-flop (FF1)
It is held at 101a. Also, a high-order fixed multiplier 103
The multiplication result of a is EORed by the EOR circuit 105, and the multiplication result of the low-order fixed multiplier 104 a is EORed by the EOR circuit 106. That is, the flip-flop (FF1) 101
a, high-order fixed multiplier 103a and low-order fixed multiplier 1
In the circuit unit 04a, × α ⁻² and × α ⁻¹ are calculated in parallel by the coefficient S1 related to Z of the error locator polynomial shown in the above equation (3).

Similarly, a flip-flop (FF1) 10
1b, in parallel with the flip-flop (FF2) 101b, a high-order fixed multiplier 103b for multiplying by α ^-4 and a low-order multiplier for multiplying the fixed multiplier 103b by α ^-3 whose order of the error locator polynomial is one less. The next fixed multiplier 104b is arranged, and only the multiplication result of the higher-order fixed multiplier 103b is held in the flip-flop (FF2) 101b. The multiplication result of the higher-order fixed multiplier 103b is an EOR circuit 105, and the multiplication result of the lower-order fixed multiplier 104b is an EOR circuit 106.
And the flip-flop (FF2) 101
b, high-order fixed multiplier 103b and low-order fixed multiplier 1
In the circuit section composed of 04b, × α ^-4 and × α ^-3 are calculated in parallel by the coefficient S2 related to Z of the error locator polynomial.

Further, a flip-flop (FFi) 10
In 1c, in parallel with the flip-flop (FFi) 101c, a high-order fixed multiplier 103c that multiplies by α ⁻²ⁱ and a low-order that multiplies α ^{−i by} which the order of the error locator polynomial is one less than the fixed multiplier 103c. The next fixed multiplier 104c is arranged, and only the multiplication result of the higher-order fixed multiplier 103c is held in the flip-flop (FFi) 101c. The multiplication result of the higher-order fixed multiplier 103c is output from the EOR circuit 105,
The multiplication result of the low-order fixed multiplier 104c is output from the EOR circuit 10
6 and the flip-flop (FFi) 10
1c, a high-order fixed multiplier 103c and a low-order fixed multiplier 104c have a Z
X α ^-2i and × α ^-i are calculated in parallel by the coefficient Si according to the above.

Therefore, in the entire Chien search circuit 55, two multiplication operations are performed in which the multiplication of a higher-order coefficient and the multiplication of a lower-order coefficient corresponding to each flip-flop (FF) 101a to 101c constitute one set. Are executed in parallel.

The coefficient Si related to Z of the error locator polynomial
In the multiplication, the exponent part is minus and division is performed.
The division may be performed by multiplying the reciprocal of the coefficient using the reciprocal table. When the polynomial is calculated by multiplication using the reciprocal table as described above, the configuration of the polynomial calculation unit can be simplified, and the linear cyclic code can be decoded with a small amount of hardware. See Japanese Patent Application No. 10-184827, which has already filed an application.

The operation of the Chien search circuit of the disk drive configured as described above will be described below.

First, the basic concept of the present invention will be described.

The Chien search circuit used in the error correction device of the conventional disk drive device performs the Chien search by sequentially substituting the elements of the Galois field of the minimum code length into the error locator polynomial. It was taking time. In a device having a high transfer rate, such as an HDD, the time available for chien search is limited. Therefore, the chien search circuit is divided into a plurality of circuit units and processed by pipelining. In addition, the order of the error locator polynomial is also increased to further improve the correction capability (for example,
12th).

When the number of pipelines is n and the time required for Chien search is code length / n,
The number of fixed multipliers for the Chien search circuit is multiplied by n, and the result of multiplying the coefficient of the error locator polynomial by a flip-flop (FF) is held. In this case, the flip-flop (F
F) requires (degree i−1 of the error locator polynomial) × n.

In the present invention, a circuit for multiplying by a power of α is parallelized, and only the operation result of the highest-order fixed multiplier group is held by a flip-flop (FF).
The time required for Chien search is reduced to 1 / n without increasing the number of gates of the flip-flop (FF).

Next, the operation of the chain search circuit 55 of the disk drive will be described in detail based on the above basic concept.

Now, for the sake of simplicity, the Galois field GF
In (2 ⁸ ), consider a Chien search circuit for finding the root of the ith-order error locator polynomial. Further, a high-order fixed multiplier group 103
Is called a fixed multiplier group A, and the low-order fixed multiplier group 104 is called a fixed multiplier group B.

First, the coefficients S1 to Z1 of the error locator polynomial shown in the above equation (3) are applied to flip-flops (FF1) 101a to (FFi) 101c, which are a group of multiplication result holding circuits.
Load Si.

Then, the fixed multiplier group A calculates the value when α ⁻² is substituted for Z, and the fixed multiplier group B calculates the value when α ⁻¹ is substituted for Z. . At this time, the flip-flop (FF1) 101a holds a multiplication result when α- ² is substituted for Z.

Next, the flip-flop (FF1) 10
Since 1a holds the value when α ⁻² is substituted, the fixed multiplier group A calculates the value when α ⁻⁴ is substituted for Z, and the fixed multiplier group B calculates the value when Z ⁻² is substituted. Is calculated when α ^-3 is substituted for. And flip-flop (FF1) 1
01a holds the multiplication result when α- ⁴ is substituted for Z.

The power of α is repeated for each clock by the corresponding order of the error locator polynomial. As for the fixed multiplier group A, flip-flops (FF1) 101a to
(FFi) 101c has a fixed multiplier group A for each clock.
Is held as the square of the result of multiplication.

Here, by performing the above operation for 128 clocks, that is, 128 times, all 255 elements can be inspected. In this case, as in the conventional example, 2
Since the stage is not pipelined, the flip-flop (FF1) 101a which is a multiplication result holding circuit
All the original substitutions are completed without increasing the number of (FFi) 101c and in the time required for the Chien search in 128 clocks, which is equivalent to the case of performing two-stage pipelining. That is, the Chien search time can be reduced to about half (128 clocks) without increasing the number of multiplication result holding circuits.

The reason why the Chien search time is reduced by half will be described more specifically.

FIG. 5A is a block diagram for explaining the operation of the Chien search circuit in relation to the error locator polynomial, and is the same as FIG. However, in order to clarify the operation, a polynomial of degree shown in FIG. 5B is taken as an example, and the exponent part is minus, and the coefficients are C1 to C4.

First, the coefficient C1 related to Z of the error locator polynomial of the order shown in FIG. 5B is loaded into the flip-flop (FF1), which is a group of multiplication result holding circuits.

The fixed multiplier group A calculates the value when α ² is substituted for Z, and the fixed multiplier group B calculates the value when α ¹ is substituted for Z. At this time, the fixed multiplier 1 of the fixed multiplier group A in the flip-flop (FF1)
03a, the multiplication result C1α when α ² is substituted for Z
² is output from the fixed multiplier 104a of the fixed multipliers B, the multiplication result C1arufa ¹ when substituting alpha ¹ to Z is outputted. Flip-flop (FF1) 101a holds the multiplication result C1arufa ² from the fixed multiplier 103a when substituting alpha ² to Z.

Similarly, the flip-flop (FF2) has
The coefficient C2 relating to Z of the error locator polynomial of the order shown in FIG. 5B is loaded. At this time, the flip-flop (FF
From the fixed multiplier 103b of the fixed multipliers A in 2), is multiplied result C2arufa ⁴ is output when substituting (alpha ^{2) 2} to Z, from the fixed multiplier 104b of the fixed multipliers B,
Multiplication result C2arufa ² when substituting (alpha ^{1) 2} in Z is outputted. Flip-flop (FF2) 101b holds the multiplication result C2arufa ⁴ from the fixed multiplier 103a when substituting (alpha ^{2) 2} to Z.

The flip-flop (FFi) has a coefficient C according to Z of the error locator polynomial of the order shown in FIG.
Load 3 At this time, flip-flop (FFi)
From the fixed multiplier 103c of the fixed multiplier group A at
Z in (alpha ^{2) 3} outputs the multiplication result C3arufa ⁶ when substituting, from the fixed multiplier 104c of the fixed multipliers B, and the multiplication result C3arufa ³ when substituting (alpha ^{1) 3} to Z Is output. Flip-flop (FFi) 101c holds the multiplication result C3arufa ⁶ from the fixed multiplier 103a when substituting (alpha ^{2) 3} to Z.

The power of α is repeated for each clock. As for the fixed multiplier group A, the flip-flops (FF1) to (FFi) hold the values obtained by squaring the multiplication result of the fixed multiplier group A for each clock.
That is, the fixed multiplier group A is squared at one clock, and the fixed multiplier group B is one square at one clock.
The coefficients are multiplied by the power.

The operation up to this point is shown by the equation in FIG. The upper equation in FIG. 5C shows the EOR of the multiplication result of the fixed multiplier group B, and the lower equation in FIG. 5C shows the fixed multiplication held in the flip-flops (FF1) to (FFi). It represents the EOR of the multiplication result of the group A.

As a characteristic operation, the upper and lower equations in FIG. 5C are calculated at the same time, that is, in one clock.

As described above, the high-order fixed multiplier group 103
The multiplication in the (fixed multiplier group A) and the operation of holding the flip-flops (FF1) to (FFi) of the values and the multiplication operation in the low-order fixed multiplier group 104 (fixed multiplier group B) are simultaneously executed. Therefore, all of the 255 elements can be inspected at 128 clocks. Therefore, without increasing the multiplication result holding circuit,
The chain search time can be reduced by about half.

Attention is paid to the fact that the multiplication operation in the high-order fixed multiplier group 103 and the multiplication operation in the low-order fixed multiplier group 104 operate in parallel. It can be said that this is a new pipeline method without increasing the number of result holding circuits.

The operation of the Chien search circuit, which is a feature of the present invention, has been described above. However, the present Chien search circuit can be directly applied to the Chien search circuit 55 of the ECC control unit 42 shown in FIG. Control unit 42
The overall circuit scale can be reduced. The operation of the ECC control unit 42 is the same as that of the conventional example shown in FIG.

As described above, the Chien search circuit 55 according to the first embodiment is provided corresponding to each term of the error locator polynomial, holds each coefficient of the error locator polynomial as an initial value, and sets the error locator polynomial as an initial value. Flip-flops (FF) 101a to 101c that hold multiplication results obtained by multiplying each coefficient of the position polynomial by an element of the Galois field, and the highest order α in parallel with each flip-flop (FF) 101a to 101c. Higher-order fixed multipliers 103a to 103c for multiplying by powers of (α ⁿ ), respectively, and lower-order fixed multipliers 10 for multiplying lower-order powers of α (α ^n-1 ), respectively.
4a to 104c, and the highest power of α (α
ⁿ ), only the multiplication results of the higher-order fixed multipliers 103a to 103c are flip-flop (FF) 101a to 1
01c and a high-order fixed multiplier 103a
The EOR circuit 105 calculates the multiplication result of the low-order fixed multipliers 104a to 104c.
At the time of performing EOR at 06 and searching for the result of the operation of the error locator polynomial being 0, the flip-flops (FFs) 101a to 101c are used when performing pipeline processing for speeding up the Chien search. The time required for the Chien search can be reduced without increasing the number of.

In this embodiment, when performing a Chien search for substituting into the i-th order error locator polynomial in the Galois field GF (2 ⁸ ) of the minimum code length, the number of pipelines is set to n = 2 and the Chien search is required. Since the time is the code length / 2, the flip-flops (FF1) 101a to (FFi)
101c is i−1, and a plurality of fixed multiplier groups are a high-order fixed multiplier group 103 and a low-order fixed multiplier group 104. Therefore, fixed multipliers 103a-103
Although the numbers of c and 104a to 104c are the same as those of the conventional Chien search circuit shown in FIG. 10, the flip-flops (FF1) 101a to 101f which are multiplication result holding circuits are provided.
The number of (FFi) 101c can be reduced to half.

In addition, when the present chain search circuit is configured, there is no need to add components or change the method of introducing coefficients.

Further, since the hardware amount of the chain search circuit 55 is reduced, the ECC control unit 42 and the HDD 30
The overall circuit scale can be reduced. Second Embodiment In the above embodiment, the case where two pipelines are used is described. However, by increasing the number of pipelines in the same way, the time of the Chien search can be reduced without increasing the number of multiplication result holding circuits. Can be reduced. Hereinafter, an example in which the number of pipelines is increased will be described.

FIG. 6 is a block diagram showing a configuration of a Chien search circuit, and is a diagram showing a configuration of a Chien search circuit used for an HDD having a high transfer rate. In this embodiment, when performing pipeline processing for speeding up the chain search,
This is an example where the number of pipelines is three. This chain search circuit can be used for the chain search circuit of the ECC control unit 42 in FIG.

Referring to FIG. 6, Chien search circuit 200
Are the flip-flops (FF) 201a to 201c forming an 8-bit register for holding a result obtained by multiplying the coefficient of the error locator polynomial by the element of the Galois field, and Z of the error locator polynomial shown in the equation (3). Such coefficients S1 to Si
Input terminals 202a to 202c for inputting to the flip-flops (FF) 201a to 201c and the flip-flops (FF) 201a to 201c, and the coefficients S1 to Si of the error locator polynomial, Among them, high-order fixed multipliers 203a to 203c that multiply by the highest power of α (α ⁿ ) and output to flip-flops (FF) 201a to 201c, and are arranged in parallel to flip-flops (FF) 201a to 201c. A high-order fixed multiplier that multiplies the coefficients S1 to Si of the error locator polynomial by a higher-order power of α (α ⁿ ) of the order of the error locator polynomial and outputs the result to flip-flops (FF) 201a to 201c. 204a to 204c and a flip-flop (F
F) The multiplication results arranged in parallel to 201a to 201c and held in the flip-flops (FF) 201a to 201c have lower powers of α (α) among the degrees of the error locator polynomial.
^n-1 ) to output a low-order fixed multiplier 205a-
205c and the highest-order fixed multipliers 203a to 203c
(FF) 201 holding the multiplication result of
Exclusive OR (EOR) circuit 206 that performs an exclusive OR operation on the outputs of a to 201c for each bit, and performs an exclusive OR operation on the multiplication results of higher-order fixed multipliers 204a to 204c for each bit. Exclusive OR (EOR) circuit 207
And an exclusive OR (EO) for performing an exclusive OR operation on the multiplication results of the low-order fixed multipliers 205a to 205c for each bit.
R) circuit 208 and EOR for each bit of EOR circuit 206
A first 0 determination circuit (Zero Detect 1) 209 for determining that the OR output is 0, and a second 0 for determining that the EOR output of each bit of the EOR circuit 207 is 0
Judgment circuit (Zero Detect 2) 210 and EOR circuit 20
And a third zero determination circuit (Zero Detect 3) 211 for determining that the EOR output of each of the 8 bits is 0.

The highest-order fixed multipliers 203a to 203c
Constitutes a highest-order fixed multiplier group 203 (a plurality of fixed multiplier groups) as a whole, and includes higher-order fixed multipliers 204a to 204d.
204c constitutes a higher-order fixed multiplier group 204 (a plurality of fixed multiplier groups) as a whole, and a lower-order fixed multiplier 205
a to 205c are low-order fixed multiplier groups 205 as a whole.
(A plurality of fixed multiplier groups).

Each of the 0 determination circuits 209 to 211 determines that the operation result of the error locator polynomial obtained by the EOR circuits 206 to 208 is 0, and if it determines 0, the position at that time is used as an error locator. Output. The indexed error locator is converted to a Galois field GF (2 ⁿ ) using an index-vector conversion circuit (not shown).
Is converted into a vector position having a bit width represented by the following formula, and is supplied to the next correction step.

Flip-flops (FF) 201a to 201
1c is the highest-order fixed multiplier 203a that multiplies the highest order power of α (α ⁿ ) among the degrees of the error locator polynomial.
Only the multiplication results of .about.203c are held.

Highest fixed multipliers 203a to 203c
Are arranged in parallel with flip-flops (FF) 201a to 201c, and the coefficients S1 to Si of the error locator polynomial have the highest power of α (α ⁿ ) among the degrees of the error locator polynomial.
In the present embodiment where the number of pipelines is 3, the powers of α are α ³ , α ⁶ ,..., Α ³ⁱ , respectively.

The high-order fixed multipliers 204a to 204c
Flip-flops (FF) 201a to 201c are arranged in parallel, and coefficients S1 to Si of the error locator polynomial are added to the highest-order fixed multiplier 203 of the order of the error locator polynomial.
a to 203c are multiplied by a higher order power of α (α ^n-1 ). In the present embodiment, the powers of α are α
² , α ⁴ ,..., Α ²ⁱ .

The low-order fixed multipliers 205a to 205c
The flip-flops (FF) 201a to 201c are arranged in parallel with the flip-flops (FF) 201a to 201c.
Is multiplied by the low-order power of α (α ⁿ⁻² ) of the order of the error locator polynomial and output.
In the present embodiment, the powers of α are α ¹ , α ² ,.
α ⁱ .

Incidentally, the coefficient Si relating to Z of the error locator polynomial
Is a normal multiplication operation in which the exponent part is positive, but may be a division operation using a reciprocal table in which the exponent part is negative and the reciprocals of the coefficients are tabulated as in the first embodiment.

Here, the highest-order fixed multipliers 203a to 203a
203c (highest-order fixed multiplier group 203), high-order fixed multipliers 204a to 204c (high-order fixed multiplier group 20)
4) and the arrangement of low-order fixed multipliers 205a to 205c (low-order fixed multiplier group 205) will be described more specifically.

In this embodiment, the basic configuration is the same as that of the first embodiment, and it is determined how many times the basic clock required for the Chien search is to be reduced.
Since there are three clocks (the number of pipelines is three), three fixed multiplier groups 203 to 205 are connected to the flip-flop (F
F) It is arranged in parallel with 201a to 201c, and only the multiplication result of the fixed multiplier group 203 having the highest order is stored in the flip-flops (FF) 201a to 201c.

That is, the present chain search circuit 200
The highest-order fixed multipliers 203a to 203c which multiply by the highest-order powers of α (α ⁿ ) in parallel with the flip-flops (FF) 201a to 201c, respectively;
Higher ^- order fixed multipliers 204a to 204c that respectively multiply by the next higher powers of α (α ⁿ⁻¹ ), and lower-order fixed multipliers that multiply by lower powers of α (α ^n-2 ), respectively. Fixed multipliers 205a to 205c are arranged, and the highest-order fixed multiplier 2 for multiplying the highest-order power of α (α ⁿ )
03a to 203c are held in flip-flops (FF) 201a to 201c, and the multiplication results of the highest-order fixed multipliers 203a to 203c are stored in EO.
In the R circuit 206, high-order fixed multipliers 204a to 204c
Is multiplied by an EOR circuit 207 to a low-order fixed multiplier 2
The EOR circuits 208 perform EOR on the multiplication results of 05a to 205c, and output 0 from the outputs of the EOR circuits 206 to 208, respectively.
The determination circuits 209 to 211 are configured to search for an error result polynomial operation result of 0.

[0108] High this arrangement, for multiplying Looking focusing on each flip-flop (FF) 201 a to 201 c, the example flip-flop (FF1) 201a, in parallel with flip-flop (FF1) 201a, the alpha ³ A next fixed multiplier 203a, a higher-order fixed multiplier 204a that multiplies α ² whose degree of the error locator polynomial is one less than the fixed multiplier 203a, and a fixed multiplier 204a
A low-order fixed multiplier 205a for multiplying α ^{1 in} which the order of the error locator polynomial is lower by ^one is arranged, and only the multiplication result of the highest-order fixed multiplier 203a is a flip-flop (F
F1) is held at 201a. The multiplication result of the highest-order fixed multiplier 203a is an EOR circuit 206, and the multiplication result of the high-order fixed multiplier 203a is an EOR circuit 207.
The multiplication result of the low-order fixed multiplier 205a is
EOR at 8. That is, the flip-flop (FF1) 201a, the highest-order fixed multiplier 203a,
High order fixed multiplier 204a and low order fixed multiplier 205
In the circuit section consisting of a, xα ³ , × α ^2, and × α ^{1 are} calculated by the coefficient S1 relating to Z of the error locator polynomial shown in the above equation (3).
Are calculated in parallel.

Similarly, a flip-flop (FF2) 20
1b, the highest-order fixed multiplier 203b, the higher-order fixed multiplier 204b, and the lower-order fixed multiplier 205b have a circuit section of × α ⁶ , × α by the coefficient S2 related to Z of the error locator polynomial. ⁴ and × α ² are calculated in parallel. In the flip-flop (FFi) 201c, a circuit unit including the highest-order fixed multiplier 203c, the higher-order fixed multiplier 204c, and the lower-order fixed multiplier 205c has a coefficient related to Z of the error locator polynomial. × α ³ⁱ , × α by Si
²ⁱ and ^{xα i} are calculated in parallel.

Therefore, in the entire Chien search circuit 200, each flip-flop (FF) 201a to 201c
Accordingly, three multiplication operations are performed in parallel, in which multiplication of the highest-order coefficient, multiplication of the higher-order coefficient, and multiplication of lower-order coefficients are a set. .

Hereinafter, the operation of the Chien search circuit 200 configured as described above will be described. The basic operation is
This is the same as the embodiment.

Now, for the sake of simplicity, the Galois field GF
In (2 ⁸ ), consider a Chien search circuit for finding the root of the ith-order error locator polynomial. The highest-order fixed multiplier group 2
03 is referred to as a fixed multiplier group A, the higher-order fixed multiplier group 204 is referred to as a fixed multiplier group B, and the lower-order fixed multiplier group 205 is referred to as a fixed multiplier group C.

First, the coefficients S1 to Z of the error locator polynomial shown in the above equation (3) are applied to flip-flops (FF1) 201a to (FFi) 201c, which are a group of multiplication result holding circuits.
Load Si.

Then, the fixed multiplier group A calculates the value when α ³ is substituted for Z, and the fixed multiplier group B calculates the value when α ² is substituted for Z. Multiplier group C
Calculates the value when α ¹ is substituted for Z. At this time, the flip-flop (FF1) 201a holds only the multiplication result when α ³ is substituted for Z.

Next, the flip-flop (FF1) 20
Since 1a holds the value when α ³ is substituted, the fixed multiplier group A calculates the value when α ⁶ is substituted for Z, and the fixed multiplier group B calculates α when α is substituted for Z. The value when ⁴ is substituted is calculated, and the fixed multiplier group C calculates the value when α ² is substituted for Z. And flip-flop (FF)
1) 201a holds the multiplication result when α ⁶ is substituted for Z.

The above exponentiation of α is repeated for each clock at the corresponding order of the error locator polynomial. As for the fixed multiplier group A, flip-flops (FF1) 201a to
(FFi) 201c includes a fixed multiplier group A for each clock.
Is held as the third power of the result of multiplication.

By performing the above operation 85 times, that is, 85 times, all 255 elements can be inspected. In this case, the number of flip-flops (FF1) 201a to (FFi) 201c, which are the multiplication result holding circuit groups, is not increased, and the time required for the Chien search is all 85 clocks equivalent to the case of performing three stages of pipeline processing. The original assignment of is terminated. This reduces the Chien search time by 1/3 without increasing the number of multiplication result holding circuits.
(85 clocks).

The reason why the Chien search time is reduced to 1/3 will be described more specifically.

FIG. 7A is a block diagram for explaining the operation of the Chien search circuit in relation to the error locator polynomial, and is the same as FIG. However, in order to clarify the operation, an order polynomial shown in FIG.
Let the coefficients of the polynomial be C1 to C4.

First, the coefficient C1 relating to the Z of the error locator polynomial of the order shown in FIG. 7B is loaded into the flip-flop (FF1) which is a multiplication result holding circuit group.

The fixed multiplier group A calculates the value when α ³ is substituted for Z, and the fixed multiplier group B calculates the value when α ² is substituted for Z. The group C calculates a value when α ¹ is substituted for Z.

At this time, the flip-flop (FF1)
From the fixed multiplier 203a of the fixed multiplier group A in FIG.
To α^ThreeIs multiplied by substituting^ThreeIs output
From the fixed multiplier 204b of the constant multiplier group B, Z is α^TwoTo
Multiplication result C1α when substituted ^TwoIs output to the fixed multiplier
From the fixed multiplier 205a of the group C,¹Was assigned
Multiplication result C1α¹Is output. flip flop
(FF1) 201a is α for Z^ThreeThe highest when substituting
Multiplication result C1α from the next fixed multiplier 203a^ThreeOnly keep
Carry.

Similarly, the flip-flop (FF2) has
The coefficient C2 related to Z of the error locator polynomial of the order shown in FIG. 7B is loaded. At this time, the flip-flop (FF
From the fixed multiplier 203b of the fixed multipliers A in 2), is multiplied result C2α output ⁶ when substituting (alpha ^{3) 2} to Z, from the fixed multiplier 204b of the fixed multipliers B,
Z in (alpha ²⁾ is multiplied result C2arufa ⁴ is output ² when substituting, from the fixed multiplier 205b of the fixed multipliers C, and the multiplication result C2arufa ² when substituting (alpha ^{1) 2} to Z Is output. Flip-flop (FF2) 201b holds only multiplication result C2arufa ⁶ from the fixed multiplier 203a when substituting (alpha ^{3) 2} in Z.

The coefficient C according to Z of the error locator polynomial of the order shown in FIG. 7B is added to the flip-flop (FFi).
Load 3 At this time, flip-flop (FFi)
From the fixed multiplier 203c of the fixed multiplier group A at
Z in (alpha ³⁾ is multiplied result C3arufa ⁹ is output ³ when substituting, from the fixed multiplier 204c of the fixed multipliers B, and the multiplication result C3arufa ⁶ when substituting (alpha ^{3) 2} to Z Output
From the fixed multiplier 205c of the fixed multiplier group C, Z is given by (α
^{3) 1} multiplication results when substituting C3arufa ³ is output. The flip-flop (FFi) 201c outputs the multiplication result C3 from the fixed multiplier 203a when (α ³ ) ³ is substituted for Z.
to hold the only α ^6.

The power of α is repeated for each clock in each circuit section.

The result of the multiplication after the arrow (→) in FIG.
The result of multiplication by the next clock after the above operation is shown.
As described above, with respect to the fixed multiplier group A, the flip-flops (FF1) to (FFi) hold a value obtained by cubing the multiplication result of the fixed multiplier group A for each clock. That is, the fixed multiplier group A is multiplied by the cube of one clock, the fixed multiplier group B is multiplied by the square of one clock, and the fixed multiplier group C is multiplied by the square of one clock. Become.

The operation up to this point is shown by the equation in FIG. 7C represents the EOR of the multiplication result of the fixed multiplier group C, and the middle equation of FIG. 7C represents the EOR of the multiplication result of the fixed multiplier group B. The lower equation in (c) represents the EOR of the multiplication result of the fixed multiplier group A held in the flip-flops (FF1) to (FFi).

As a characteristic operation, the upper, middle, and lower equations in FIG. 7C are calculated simultaneously, that is, in one clock.

As described above, the highest-order fixed multiplier group 20
3 (fixed multiplier group A) and the operation of holding the flip-flops (FF1) to (FFi) of the value, the multiplication operation in the higher-order fixed multiplier group 204 (fixed multiplier group B), and the lower-order Since the multiplication operations in the fixed multiplier group 205 (fixed multiplier group C) are performed simultaneously,
With five clocks, all 255 elements can be checked. Therefore, the Chien search time can be reduced to about 1/3 without increasing the multiplication result holding circuit.

The operation of the chien search circuit, which is a feature of the present invention, has been described above. The chien search circuit 200 can be applied to the chien search circuit 55 of the ECC controller 42 shown in FIG. , The overall circuit size of the ECC control unit 42 can be reduced.

As described above, the Chien search circuit 200 according to the second embodiment holds each coefficient of the error locator polynomial as an initial value, and multiplies each coefficient of the error locator polynomial by a Galois field element. Flip-flops (FF) 201a to 201c holding the multiplication results and high-order α powers (α ⁿ ) multiplying the highest order powers of α (α ⁿ ) in parallel with the flip-flops (FF) 102a to 201c, respectively. Fixed multipliers 203a to 203c, higher-order fixed multipliers 204a to 204c for multiplying the next higher powers of α (α ^n-1 ), and lower-order powers of α (α ^n-2) ), Each of which is a low-order fixed multiplier 2
05a-205c, and the highest-order fixed multiplier 203a-2 that multiplies the highest-order power of α (α ⁿ ).
Only the multiplication result of 03c is flip-flop (FF) 20
1a to 201c, the time required for the Chien search can be reduced without increasing the number of flip-flops (FF) 201a to 201c when performing pipeline processing for speeding up the Chien search. 1/3
Can be shortened.

That is, in this embodiment, three pipelines are used to shorten the Chien search time to 1/3 (85 clocks). However, the number of flip-flops (FFs) 201a to 201c in the Chien search circuit is reduced. Is
The number of the gate circuits in this part remains i-1 which is the number before the pipeline is formed, and the increase in the number of gate circuits in this part can be prevented.

In particular, in an apparatus having a high transfer rate such as an HDD, the time available for the Chien search is limited.
If it is necessary to increase the order of the error locator polynomial (for example, 12th order) in order to further improve the correction capability, the access time of the sector data of the disk drive device is substantially determined by the Chien search time. I will. In the present embodiment, the time required for the Chien search can be reduced to 1/3 without increasing the number of flip-flops (FFs) by using three pipelines, and this corresponds to an increase in the speed of the disk drive device. be able to. Third Embodiment In each of the above-described embodiments, the case where two pipelines or three pipelines are used is described. However, by increasing the number of pipelines based on the same concept, the number of multiplication result holding circuits can be increased. It can reduce the time for chain search. Hereinafter, an example of increasing the number of pipelines will be shown by a general formula.

To solve the i-th order error locator polynomial, to use k pipelines, a group of fixed multipliers arranged in parallel with the multiplication result holding circuit is prepared as shown in Table 1.

[0135]

[Table 1]

In the fixed multiplier groups 1 to k shown in this table, only the multiplied output of the fixed multiplier group k which is the highest-order fixed multiplier is held in the multiplication result holding circuit.

The circuit configuration of the Chien search circuit can be configured in the same manner as in the second embodiment. Fixed multiplier groups 1 to k are arranged in parallel in a multiplication result holding circuit, and the highest order fixed The configuration is such that only the multiplication result of the multiplier group k is stored in the multiplication result holding circuit.

Therefore, in the present embodiment, the root of the error locator polynomial can be obtained with a clock of 1 / k.

When the Chien search circuit having such features is applied to a disk drive device having a high transfer rate such as an HDD, the error correction capability can be improved while reducing the amount of hardware, and high-speed operation can be performed.

In each of the above embodiments, the present invention is applied to the HD.
Although an example in which the present invention is applied to the D error correction device has been described, any type of disk drive device or error correction device can be applied as long as it has the present Chien search circuit structure. For example, the present invention can be applied to a Chien search circuit and an error correction device such as an optical disk device and a DVD device which need to correct a data error.

In each of the above embodiments, the Galois field GF
The Chien search for decoding the Reed-Solomon code on (2 ⁿ ) has been described. Each coefficient of the error locator polynomial indicating the position of an error generated in the linear cyclic code is added to the coefficient of the linear cyclic code. It can be applied to any Chien search algorithm that finds a root by substituting elements one by one.

In each of the above embodiments, the Galois field is G
The case of F (2 ⁸ ) has been described as an example, but the Galois field is G
It can be applied to the case of F (2 ⁿ ), and the same effect can be obtained.

Further, the type and number of flip-flops (FFs) and fixed multipliers constituting the Chien search circuit, and the MP constituting the disk drive device are described.
The type and number of U and HDC are not limited to the above-described embodiment.

[0144]

The Chien search circuit according to the present invention is provided for each term of the error locator polynomial, holds each coefficient of the error locator polynomial as an initial value, and adds a coefficient to each coefficient of the error locator polynomial. A multiplication result holding means for holding the multiplication result obtained by multiplying the element; and a plurality of fixed means arranged in parallel with the multiplication result holding means for multiplying the holding result held by the multiplication result holding means by elements of different degrees. A multiplier group is provided, and the multiplication result of the highest-order fixed multiplier group among the plurality of fixed multiplier groups is held in the multiplication result holding means. When performing pipeline processing, the time required for Chien search can be reduced without increasing the number of gates of the multiplication result holding means.

Therefore, by performing error correction using such a Chien search circuit, the error correction capability can be improved while reducing the amount of hardware in the error correction device, and the disk drive device can operate at high speed. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a disk drive device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a structure of sector data used in the disk drive device.

FIG. 3 is a block diagram illustrating a configuration of an ECC control unit of the disk drive device.

FIG. 4 is a block diagram showing a configuration of a Chien search circuit of an ECC control unit of the disk drive device.

FIG. 5 is a block diagram for explaining the operation of the Chien search circuit in relation to an error locator polynomial.

FIG. 6 is a block diagram illustrating a configuration of a Chien search circuit of an ECC control unit of a disk drive according to a second embodiment of the present invention.

FIG. 7 is a block diagram for explaining the operation of the Chien search circuit in relation to an error locator polynomial.

FIG. 8 is a block diagram illustrating a configuration of a conventional error correction device.

FIG. 9 is a flowchart showing an error correction process of a conventional error correction device.

FIG. 10 is a diagram showing a configuration of a Chien search circuit used in a conventional device having a high transfer rate.

[Explanation of symbols]

Reference Signs List 30 magnetic disk drive (HDD), 31 magnetic disk (disk-shaped storage medium), 32 magnetic head, 33
Head arm, 34 head amplifier (AE), 35 channels, 36 hard disk controller (HD
C), 37 MPU, 38 sector buffer, 41 drive control unit, 42 ECC control unit (error correction device),
43 memory control unit, 44 host control unit, 51 input terminal, 52 buffer memory, 53 syndrome calculation circuit (syndrome generation means), 54 position polynomial / numerical polynomial calculation circuit (calculation means), 55, 200 Chien search circuit (Chen search circuit) Means), 56 error value calculation circuit, 57 error correction circuit (correction means), 58 output terminals, 101a to 101c, 201a to 201c flip-flop (FF) (multiplication result holding means), 102a to
102c, 202a to 202c input terminals, 103, 2
03 Highest-order fixed multiplier group (plural fixed multiplier groups), 103a to 103c, 203a to 203c Highest-order fixed multiplier group, 104, 205 Low-order fixed multiplier group (plural fixed multipliers) Instrument group), 104a to 104c, 20
5a-205c Low-order fixed multipliers, 105, 106,
206-208 Exclusive OR (EOR) circuit, 204
High-order fixed multiplier group (a plurality of fixed multiplier groups), 204a
204c Higher-order fixed multiplier, 209 First 0 decision circuit (Zero Detect 1), 210 Second 0 decision circuit (Z
ero Detect 2), 211 Third zero judgment circuit (Zero Det
ect3)

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Akio Nakamura 1623-14 Shimotsuruma, Yamato-shi, Kanagawa Japan Inside the Yamato Office of IBM Japan, Ltd. (72) Tetsuya Tamura 1623 Shimotsuruma, Yamato-shi, Kanagawa Prefecture 14 F-term (reference) at Daiwa Office, IBM Japan, Ltd. 5B001 AA04 AA08 AA11 AB02 AC01 AD04 AE02 5J065 AA01 AB01 AC03 AD03 AD04 AD11 AE06 AF01 AF03 AG01 AG02 AH04 AH06

Claims (6)

[Claims] 1. An error locator polynomial that indicates a position of an error occurring in a linear cyclic code is substituted with one element on the field of the linear cyclic code one by one to determine whether the error locator polynomial becomes zero. In a Chien search circuit that finds a root based on whether or not, it is provided corresponding to each term of the error location polynomial, holds each coefficient of the error location polynomial as an initial value, and multiplies each coefficient of the error location polynomial by a field element And a plurality of fixed multiplications arranged in parallel to the multiplication result holding means and multiplying the holding results held by the multiplication result holding means by elements of different degrees. And a multiplier group, wherein the multiplication result of the highest-order fixed multiplier group among the plurality of fixed multiplier groups is held in the multiplication result holding means. 2. When decoding a Reed-Solomon code on a Galois field GF (2 ⁿ ), a root of an error locator polynomial is calculated using a Chien search, and a Chien search circuit for finding an error position includes: Multiplication result holding means provided corresponding to each term, holding each coefficient of the error locator polynomial as an initial value, and holding a multiplication result obtained by multiplying each coefficient of the error locator polynomial by an element of a Galois field; A plurality of fixed multiplier groups which are arranged in parallel with the result holding means and multiply the holding result held by the multiplication result holding means by an element of a Galois field having a different degree; and an output of the plurality of fixed multiplier groups Exclusive OR means for performing an exclusive OR operation for each bit component of the plurality of fixed multiplier groups, wherein the multiplication result of the highest-order fixed multiplier group among the plurality of fixed multiplier groups is the multiplication result holding means. Keep Chien search circuit being characterized in that configured to. 3. The Chien search circuit according to claim 1, wherein the multiplication in each of the fixed multiplier groups is performed simultaneously with the same clock. 4. An element of a Galois field for the minimum code length is represented by i (i
Is a positive integer) When performing a Chien search to substitute into the next error locator polynomial, when the number of pipelines is n (n is any positive integer) and the time required for the Chien search is code length / n The number of the plurality of fixed multiplier groups is n, and the number of the multiplication result holding means is i-1.
The described Chien search circuit. 5. Syndrome generation means for generating a syndrome from input data, calculation means for calculating an error locator polynomial and an error evaluation polynomial using the syndrome, and Chien search means for finding a root of the error locator polynomial by a Chien search. An error correction device comprising: a correction unit that corrects an error in data by using the error position and the value of the error; wherein the Chien search unit includes the Chien search circuit according to any one of claims 1 to 4. An error correction device characterized in that it is used. 6. A recording / reproducing unit for reproducing a servo sector on a disk-shaped recording medium and recording or reproducing a data sector, at least input / output control of data to / from an external device, or recording of a data sector by the recording / reproducing unit. Or, a disk drive device comprising: control means for controlling reproduction; and error correction means for realizing data decoding based on an error correction code using a hardware structure having a Chien search circuit structure. A disk drive device using the chain search circuit according to any one of claims 1 to 4.