JP3139499B2 - Error correction processor - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Outline Industrial application field Conventional technology (FIGS. 4 to 14) Problems to be solved by the invention Means for solving the problem Actions Embodiment One embodiment of the present invention ( (Figs. 1 to 3) Effects of the Invention [Outline] Regarding the error correction processing device, it is possible to check the error position and numerical value at the same time as the error position and the numerical value are obtained without increasing the amount of hardware, so that the processing time can be significantly reduced. In order to provide an error correction processing device that can be shortened, the data sequence is divided into a plurality of interleaves having the same data length, and an error correction code for performing error correction for each of the plurality of interleaves, An error correction processor for data provided with a CRC for verifying a result, which operates at each clock, detects an error position and an error value by an error correction code, and outputs the error. It is input and the circuit operates at each clock the error value from the error detection circuit for each clock, CR
A correction result verification syndrome generation circuit for sequentially generating correction result syndromes used for the C calculation, and by simultaneously providing clocks to the error detection circuit and the correction result verification syndrome generation circuit, an error position and an error value can be calculated. The detection processing and the generation processing of the correction result verification syndrome are performed simultaneously.

[Industrial applications]

The present invention relates to an error correction processing device, and more particularly, to an error correction processing device that speeds up a CRC check device during an optical disk read process.

The bit error rate of the optical disk is 2% of the magnetic disk.
It is 10 ^-3 to 10 ^-5, which is up to 3 digits, and the nature of the error is also different, so a new scheme needs to be designed. A magnetic disk has many reading errors due to poor S / N, and it is effective to repeat the reproduction again to recover the error. On the other hand, in the case of an optical disk, a defect on a recording medium is a main cause of an error, so that means for re-reproduction is not used. Error correction by signal processing and the status of reproduction error immediately after recording are checked. If there is a problem, replacement processing to record at another location (or, just before recording, check the medium for defects using a reproduction light beam. Changes the recording location).

BACKGROUND ART In an optical disc, both random errors and burst errors occur. Further, since the error rate of the optical disk medium is relatively high, a strong correction code is required. Therefore, the optical disc employs a method in which a large amount of coding is performed by the Reed-Solomon code in combination with an interleaving method (interleave method). Error correction code ECC (e
The rror correction code (hereinafter simply referred to as ECC) is called a Reed-Solomon code and has a very high error correction capability although it is complicated and requires a long error correction processing time. Because of the processing time, usually when reading one sector of data,
The read data is temporarily stored in a data buffer, and at the same time, a syndrome showing a symptom of an error is created based on the data read by the ECC processor, and based on the syndrome, it is detected where and how it is wrong. The process takes a very long time.

The ECC commonly used for magnetic disks and the like is a bit correction code, whereas the read / write
Solomon codes are byte correction codes. The bit correction code treats one bit of data as a codeword element and detects which bit is wrong. Then, if it is known which bit is wrong, the value of the bit may be inverted. On the other hand, the byte correction code is 8-bit data,
That is, one byte is treated as an element of a code word, and which byte is detected and how wrong is detected. Reed-Solomon code of the optical disc is to realize a byte corrected by treating each element of the code word as the original Galois field (finite) GF (2 ^8).

The Galois field GF (2 ^r ) is a Galois field having 2 ^r elements, and α is used to represent an element of the Galois field. For example, the element of the Galois field GF (2 ⁸ ) has 2 ⁸ = 256, and 1 (=
α ⁰ = α ²⁵⁵ ), α ¹ , α ² , α ³ ,..., α ²⁵⁴ . The element of the Galois field GF (2 ⁸ ) is an 8-dimensional binary vector,
That is, since it can be considered as 1-byte data,
This is used for byte error correction. In the Galois field, all four arithmetic operations including multiplication and division are completed. For example, The result of the calculation is always the source of the Galois field.

In the case of error correction of an optical disk, one byte of data is treated as an element of the Galois field GF (2 ⁸ ), and a certain element,
Detects how bad the byte data is.
For example, incorrectly data that would otherwise α ² is written α ⁵
Α ² + α ^X = α ⁵ , and α ^X is an error value. Addition of element of Galois field
More specifically, the subtraction can be performed by EOR (exclusive or) of the original vector expression.

Figure 4 (a) is read using a Galois field GF (2 ⁸⁾
It is an example of a code word of a Solomon code. Code length (codeword length) of Reed-Solomon code using Galois field GF (2 ⁸ )
Is 2 ^r -1. In this example a code length = 2 ⁸ -1 = 255 bytes.

The number of check symbols (the length of the ECC part) is determined by the ECC generator polynomial. In this example, it is assumed that the generator polynomial is such that the number of check symbols is 16 bytes.
From 15 to position 0 is the ECC part. Excluding the ECC part, 239 bytes (position 254 to position 16) are the data part. The length of the data portion is called the number of information symbols.

The narration correction capability of the ECC is also determined by the generator polynomial, and in the example of FIG. 4A, the error correction capability is 8 bytes. That is, an error of up to 8 bytes out of 255 bytes can be corrected.

FIG. 4B shows an example of a code word used in the optical disc, in which the number of information symbols of the code word in FIG. 4A is set to 104 bytes. The error detection procedure of the code word of FIG. 4A and the code word of FIG. 4B are the same. A procedure for correcting the error of this code will be described.

First, a syndrome is obtained from the entire codeword. The syndrome is also a polynomial (syndrome polynomial).
If there are no errors, the syndrome will be zero. next,
An error position polynomial and a numerical polynomial are obtained based on the syndrome. In this case, the Euclidean algorithm is generally used.

Next, based on the error locator polynomial and the error numerical polynomial,
Find the error location and error value. In other words, what number byte is wrong and how is it determined. As a method at this time, a Chen algorithm (Chen search) is generally used.

FIG. 5 (a) is a diagram showing an array of data for one sector of the optical disk, in which ten codewords of FIG. 4 (b) are arranged. One row of the array, that is, one codeword is called one interleave. The error correction processing is performed for each interleave. The data portion of the array is 104 bytes x 10 = 1040 bytes, but the position 16 of interleave 6 to 9 contains a CRC (Cyclic Redundancy Check) code, so that 1036 bytes can be used as actual data. It is. This CRC is an element of the code word shown in FIG. 5 (b). First, an array consisting only of the data portion shown in FIG. 5A is created, and 0 is inserted in the CRC portion of the array. Next, the elements of each column of the array are EORed to make the elements of the information polynomial for CRC generation. For example, positions 119 of interleaves 0-9
The data, obtained by EOR all the D _119. Then, the remainder polynomial obtained by dividing the information polynomial composed of D _{119 to} D ₁₆ by the CRC generation polynomial is CRC (C3 to C0).

The CRC is incorporated in the data array as shown in FIG. This CRC is not used for error correction but for verifying the result of error correction based on the ECC. That is, after error correction based on the ECC is completed, a CRC for verifying the correction result is obtained from the 108-byte code words D _{119 to} D _{0 in} FIG. If so, it is determined that the error correction result is correct. If the CRC for verifying the correction result is not 0, the error correction result is incorrect. Thereby, the correction (miscorrection) can be prevented.

In the process of reading from an optical disk, in error correction based on ECC, CRC is also used as a part of data to perform error correction, and then a correction result verification syndrome is obtained.

[Conventional technology]

◆ Principle The Chien search finds an error position jl and an error value e _jl from an error position polynomial σ _(X) and an error value polynomial ω _(X) .

σ _(X) and ω _(X) are represented by the following equations.

σ _(X) = σ ₀ + σ ₁ x + σ ₂ X ² +… σ _l x ^l … ω _(X) = ω ₀ + ω ₁ x + ω ₂ x ² … + ω _l-1 x ^l-1 …, where l : Number of error data σ _i , ω _j (0 ≦ i ≦ l, 0 ≦ j ≦ l ₋₁ ): Galois field GF (2 ⁸ )
Here, the Galois field GF (2 ⁸ ) is a finite set of 0,1 (= β ⁰ = β ²⁵⁵ ), β ¹ ,..., Β ^254. Have.

・ If G _(X) is a polynomial (G _(X) is a primitive polynomial), All values can be represented by an 8-dimensional binary vector.

For example, β ¹ = HEX (02).

EOR product / quotient exponentiation of sum / difference vector (β ^m × β ⁿ = β ^{(m + n) mod 255} where the element of Galois field used is α = β
I'm using ⁸⁸ .

The times of σ _(X) = 0 indicate an error position. Position jl (0 ≦ jl ≦ 2
When the data of 54) is incorrect, σ (α ^−jl ) = 0. For example, if there is an error at position 19 in FIG.
Since jl = 19, σ (α ^-19 ) = 0.

Then the error value e _jl is Is determined by However, α _'(X) is sigma format derivative of _(X), for example, _{σ (X) = σ 0 +} σ 1 when ^{_{x + σ 2 x 2 + σ}} 2 x 3 + σ 4 x 4 + σ 5 x 5 ......, α' _(X) = σ ₁ + σ ₃ x ³ + σ ₅ x ⁴ .

Operation The basic circuit is shown in FIG. 6, and the operation of this circuit is as follows. In the figure Is a multiplication circuit using an EOR matrix for multiplying the input value by α ⁿ , Is a flip-flop.

The circuit 1 of the error locator polynomial σ _(X) is as shown in FIG. Multiplication circuits 11 to 18 represented by FFs (hereinafter abbreviated as FFs) 20 to 28 and an EOR circuit 19.
The solid line in the figure shows the calculation route, and the broken line shows the initial value setting route. The operation of the circuit 1 is as follows.

(Initial value of FF ₎ Enter the coefficient of σ _(X) as shown. For example, FF , The coefficient of the eighth-order term of σ _(x) is set.

(The value of the output of the EOR circuit after t clock) (the value of FF after t ^{_{clock) σ i × σ i × t}} σ 0 σ 1 × α 1 × t σ 2 × α 2 × t σ 3 α 3 × ^t σ ₈ × α ^{8 × t} = σ ₀ σ ₁ × (α ^t ) ¹ σ ₂ × (α ^t ) ² σ ₃ × (α ^t ) ³ …… σ ₈ × (α ^t ) ⁸ = σ ( α ^t ) An error position jl is obtained from t when the output of the EOR circuit becomes 0. That is, when σ (α ^t ) = 0, σ (α ^-jl ) = 0, and therefore α ^t = α ^-jl = α ^{255- jl,} so that t = 255- ^{jl and jl} = 255-t For example, When t = 236, jl = 255−236 = 19, which means that the data at position 19 is incorrect.

When performing the initial setting of FF, select the initial value setting route with the selector, Are connected as shift registers. Then, when the byte is set one byte at a time from the initial setting input, this shifts more and more and finally ends up with FF28. When all the initial settings are completed, the operation route is switched to the operation route that goes around the selector. The initial setting route functions as a simple shift register, and the data set first shifts downward every time one byte is set. Once all the coefficients have been set, there is no need to set anything from the processor,
Only this circuit runs every clock.

Similarly, the circuit 31 of the error numerical polynomial ω _(X) , as shown in FIG. Multiplication circuits 32-39 represented by FFs 40 to 47 of 8 bits and an EOR circuit 48. The operation of this circuit 31 is as follows.

(Output of EOR circuit after t clock) ω ₀ × α ^{119 × t} ω ₁ × α ^{120 × t} ω ₂ × α
^{121 × t} ω ₃ × α ^{122 × t} ... Ω ₇ × α ^{126 × t} = α ^{119 × t} × (ω ₀ ω ₁ × α ^t ω ₂ × α ^2t ω ₃ × α ^3t ……… ω × α ^7t ) = α ^{119 × t} × ω (α ^t ) This is the value of the numerator of the expression of _ejl .

The circuit 53 of sigma _(x) form a differential sigma of _(x), as shown in FIG. 9, Multiplication circuits 62 to 64 represented by And an EOR circuit 69. The circuit 53 outputs the formal differential σ ′ of σ (α ^t ) from the EOR circuit 69 t clocks after the operation starts.
(Α ^t ) is output. σ ′ (α ^t ) is the denominator of the expression of e _jl .

Therefore, the value obtained by dividing the output value of the circuit 31 of ω _(x) by the output value of the circuit 53 of σ ′ _(x) is the error value e _jl .

Thus, if these circuits are operated until t = 255, that is, for 255 clocks, the positions 254 to 0
Can be detected. However, in the example of the code word shown in FIG. 4 (b), since the positions 254 to 120 do not exist, if the positions 254 to 120 are detected as error positions, the code word cannot be corrected.

The operation of the Chien search has been described above, and a specific error position / numeric value detection circuit using the Chien search will be described below. FIG. 14 is a diagram showing an error position / numeric value detection circuit using Chien search. The same components as those in the circuits shown in FIGS. I do. In FIG. 14, reference numeral 51 denotes an error position / numerical value detection circuit. The error position / numerical value detection circuit 51 includes an error position detection circuit 52 including the circuit 1 of the error position polynomial σ _(X) , and an error numerical value polynomial. the circuit 31 of the omega _(X), the form differential sigma 'circuit 53 _(x) of the sigma _(x), and error value calculating circuit 58 is constituted by an error detection result storage circuit 70,. The error position detection circuit 52 is a circuit for the error position polynomial σ _(X) 1 and Z
An ero detection circuit 57 is provided. Error value calculation circuit 58 is Galois field reciprocal ROM (256 bytes) 59, Galois field multiplier
It is composed of 60.

In such a configuration, first, the coefficient of the position polynomial σ _(x) is set to FF20 to FF28, the coefficient of σ ′ _(x) is set to FF56 to 68, and ω _(x)
Are set to FF40 to 47, respectively. Then, after switching to the selector and the operation route, one clock is sequentially applied to the entire circuit 51. For example, the in FF 23, alpha ¹⁰ is set as the coefficients of the third order terms of the sigma _(x). And 1
Given a clock, the alpha ³ in alpha ¹⁰ multiplied values, i.e. alpha ¹³ is set to the FF 23. Further, when the second clock is given, α ^{13 + 3} = α ¹⁶ is set to FF23. Similarly, when the t-th clock is given, α10 ^{+ 3 × t} is set in FF23. Thus, giving t clocks to the entire circuit means that α ^t is substituted for each polynomial. At the same time as applying a clock to the entire circuit, σ _(x) = 0
Is detected. To that end, the values of all orders of σ _(x) are added. That is, all of the outputs of FF20 to FF28
EOR is performed, and it is checked whether or not the result (the output of the EOR circuit 19) becomes 0. The result where all the bits are "0" is the solution of σ _(x) = 0, that is, the position where the error position is obtained.

The position of the error can be known from the number of repeated multiplications up to that point when "0" is detected, that is, the number of given clocks. As described above, given a single clock, the alpha ¹ is substituted into the polynomial, the same as the two multipliers alpha number of given clock is substituted as that given a clock alpha ² is substituted , The substituted multiplier of α indicates the position of the error. Therefore, if a counter is provided which has an initial value of 0 and counts up by one each time a clock is applied, the value of the counter when σ _(x) = 0 is detected indicates the position of the error. . Location counter 55 is for this purpose.

The Zero detection circuit 57 is a circuit that detects σ _(x) = 0. Z
When the Zero detection signal is output from the ero detection circuit 57, the value of the Location counter 55 at that time is stored in the register file 56. However, since the number of errors is eight at the maximum, the register file 56 has 8 words. Have the capacity.

In the circuit 51, also at the same time substituting the alpha ^t because it gives at the same time the clock throughout the circuit to _{σ (x) σ '(x} ) and ω _(x) α
^This means that ^t is substituted. Therefore, when detecting an error position has been issued expression of the numerator of e _jl from the circuit 31 of omega _(x), sigma 'denominator from the circuit 53 of the formula e _jl of _(x) is output. The output of the circuit 31 of ω _(x) at this time is σ ′
_By dividing by the output of the circuit _(x) , the error value e _jl can be obtained. The error value calculation circuit 58 is a circuit that performs the division. The error value calculation circuit 58 realizes division by multiplying the output of the circuit 31 of ω _(x) by the reciprocal of the output of the circuit 53 of σ ′ _(x) . For that purpose, Galois field GF
And a multiplier 60 for reciprocal ROM59 and the Galois field GF (2 ⁸⁾ (2 ^8).

For example, the alpha ^200-30 becomes the case of alpha ²⁰⁰ ÷ alpha ^30, the in order to obtain in this way division, it is necessary to fix it to the multiplication, if α ²⁰⁰ × α ^255-30, α
The ^{200 + 255-30} = ^{α 170.} When α ³⁰ is input to the Galois field reciprocal ROM 59, α ^255-30 = α ²²⁵ from the Galois field reciprocal ROM 59
Is output. When the error position is detected, the output e _jl of the error value calculation circuit 58 is stored in the register file 56 together with the value of the counter 55.

This concludes the description of the error position / numeric value detection circuit (FIG. 14) using the Chien search.

Next, a method of the CRC check will be described. First,
As a premise, the concept of the syndrome and the operating principle of the syndrome generator will be described.

Syndrome concept As shown in Fig. 10 (a),
Considering polynomial A (x), CRC generating polynomial G (x)
It is assumed that G (x) = (X-α ¹³⁶ ) (X-α ¹³⁷ ) (X-α ¹³⁸ ) (X-α ¹³⁹ )

The syndrome of the polynomial A (x) at this time is represented by a polynomial in which α ¹³⁶ , α ¹³⁷ , α ¹³⁸ , and α ¹³⁹ are substituted for the polynomial A (x). That is, A (α ⁱ ) (however,
i = 136, 137, 138, 139).

Because it is _{A (x) = A 107 ·} X 107 + A 106 · X 106 + ...... + A 2 · X 2 + A 1 · X + A 0 ......, and substituting example alpha ¹³⁶ to A (x), A (α 136 ) = A ₁₀₇ · α ^{136 × 107} + A ₁₀₆ · α ^{136 × 106} +... + A ₂ · α ^{136 × 2} + A ₁ · α ¹³⁶ + A ₀ .

 Assuming that A (x) contains an error, A (x) = I (x) + E (x).

 Here, I (x): a polynomial composed of correct data E (x): a polynomial composed of error components (error numerical values).

The syndrome obtained from the correct data is 0. That is, if I (α ⁱ ), it is determined that A (x) has no error. If A (x) contains an error, A
(Α ⁱ ) = I (α ⁱ ) + E (α ⁱ )
Since (α ⁱ ) = 0, A (α ⁱ ) = E (α ⁱ ), and it can be seen that the syndrome of A (x) is determined by the polynomial E (x) including the error value. Fig. 10 (a)
Is a polynomial E (x) as an error component.
If (x) is included, A (α ⁱ ) = E (α ⁱ ) = E ₁₃₀ · α ^{i × 103} + E ₆ · α ^{i × 6} + E ₁ · α ⁱ ...

FIG. 11 is a diagram showing the operation principle of the syndrome generator. In the figure Is a multiplication circuit by an EOR matrix for multiplying the input value by α ⁱ , Is an 8-bit flip-flop.

(Initial value of FF) 0 (Input value) An ₁ , _{An 2} ,.
A ₁ and A ₀ are input in order from _An-1 .

(The value of the FF after one clock) A _n-1 (The value of the FF after two clocks) A _n-1 × α ^{i An} _n-2 (The value of the FF after three clocks) (A _n-1 × α ⁱ A _n−2 ) × α ⁱ _{An −3} = A _n−1 × (α ⁱ ) ^{2 An} ₋₂ × (α ⁱ ) A _n−3 (FF value after 4 clocks) ｛A _n−1 × (α ⁱ ) ^{2 An} ₋₂ × (α ⁱ ) A _n−3 ｝ × α ^{i An} ₋₄ = A _n−1 × (α ⁱ ) ^{3 An} ₋₂ × (α ⁱ ) ² _{An −3} × (α ⁱ ) A _n−4 (value of FF after n clocks) A _n−1 × (α ⁱ ) ⁿ⁻¹ A _n−2 × (α ⁱ ) ⁿ⁻² ... A ₁ (α ⁱ ) If _A0 input data is given by polynomial A (x), A (x) = A _n-1 X ^n-1 A _n-2 X ^n-2 ... A ₁ XA ₀ . the value of FF is, those obtained by substituting α ⁱ to a (x), that is, become the a (α ⁱ⁾ .......

As described above, A (α ⁱ ) is a syndrome.

CRC Check Method When processing one sector of the optical disk as shown in FIG. 5 (a), first, error correction by ECC is performed for each of the interleaves 0-9. Next, based on the data obtained by removing the ECC part from the data for which error correction has been completed, a fifth
A data string A (x) shown in FIG. Each byte of A (x) is obtained by EORing all 10 data in each column of the data array. For example, _A107 is obtained by EORing all the data at positions 119 of interleaves 0 to 9. However, CRC
(A ₃ ~A ₀₎ is used as a C3~C0 in the data array. Then, the syndrome A (α ⁱ ) of A (x) is calculated. If A (α ⁱ ) = 0, it is determined that the error correction has been correctly performed.

However, in this method, the correction result cannot be verified until all error corrections for one sector have been completed. Therefore, the processing time for one sector is lengthened, and data is required for verification of the correction result. In addition, an operation of reading data after error correction from the data buffer is required, which is troublesome. Therefore, in general, using the fact that the syndrome is determined only by the error component, the syndrome created based on the data before error correction is compared with the syndrome created only from the error component obtained by the error correction processing. If they match, a method of determining that error correction has been correctly performed is used. Specifically, the following procedure is performed.

First, a data string A (x) shown in FIG. 5 (b) is created based on the data before error correction, and the syndrome A of A (x) is created.
(Α ⁱ ) is calculated and stored. The calculation of A (α ⁱ ) may be performed simultaneously with the calculation of the error correction syndrome based on the data and the ECC. Next, error correction processing of each interleave is performed, and an error position and an error value are obtained.

Here, consider a data string as shown in FIG. The data sequences E0 (x) to E9 (x) in FIG. 12 are composed of error components of the data portions of interleaves 0 to 9 in FIG. 5 (a). For example, E0 (x) Of the data part of The value of the position without error is 0.
Since the CRC is not included in the data portion of interleaving 0-5, the CRC portion of E0 (x) -E5 (x) is always 0. In interleave 6, CRC (C3) is included at position 16, but as shown in A (x) of FIG.
Because corresponds to the coefficient A ₃ of the polynomial A (x), when there is an error in the position 16 must be assumed that there is an error in E6 (x) at the position C3. Instead, the value at position 16 is always 0. Since interleaves 7-9 also include a CRC at position 16, E
The same operation is required for 7 (x) to E9 (x). E
(X) is obtained by EORing all of E0 (x) to E9 (x), which is the same as the error component of A (x) in FIG. 5 (b).

As a result of the error correction processing of interleave 0, the position
It is assumed that an error position 19 where α ^E is added to the data of 19, and an error value α ^E ) is detected. Position 19 is 7 of E0 (x)
Corresponds to the next section, because its coefficient is α ^E, E0 (x)
The syndrome E0 (α ⁱ ) obtained from the above equation is expressed as follows: E0 (α ⁱ ) = α ^E × (α ⁱ ) ⁷ ... In this way, if the error position and error value of the interleave 0 are obtained, the software ( E0 in the program)
(Α ⁱ ) is calculated, and at the same time, an error position and a numerical value of interleave 1 are detected. The error position and error value are obtained by the aforementioned Chien search circuit. This is similarly repeated until interleave 9, and when syndromes E0 (α ⁱ ) to E9 (α ⁱ ) of interleaves 0 to 9 are obtained, E0 (α
ⁱ ) to E9 (α ⁱ ) are all EOR (added), then E
The syndrome E (α ⁱ ) of (x) is obtained. This E (α ⁱ ) is compared with the previously obtained and stored A (α ⁱ ), and if they match, it is determined that error correction has been correctly performed.

Further, a data sequence as shown in FIG. 13 can be used by applying FIG. Data string EC (x) in FIG.
Is a data sequence obtained by adding only the CRC portions of E6 (x) to E9 (x) in FIG. 12, and assuming that the data portion has no error. Therefore, for example, if there is an error at the position 16 of the interleave 6, it is assumed that there is an error at the position C3 of EC (x). Similarly, the position of interleave 7
16 is at position C2 of EC (x), position 16 of interleave 8 is at EC
In position C1 of (x), position 16 of interleave 9 is EC (x)
Respectively correspond to the position C0.

As a result of providing EC (x), E6 (x) to E9 (x) in FIG.
Are all zero. Also, Syndrome E
(Α ⁱ ) is obtained by adding (EOR) E0 (α ⁱ ) to E9 (α ⁱ ) and EC (α ⁱ ).

[Problems to be solved by the invention]

However, in such a conventional error correction code processing apparatus, a CRC check (verification of an error correction result) is performed.
Is calculated by software based on the error position and numerical value of the error detection circuit (determined by the Chien search), which takes time because of the serial processing procedure, and the software burden is heavy. The problem that it became.

For example, in order to use software, it is necessary to perform a Galois field exponentiation calculation.
^When calculating 10 × 136, first, 10 × 136 is calculated, and the result is 1360. However, since there is no α ¹³⁶⁰ (that is, (α ⁿ ) ^m is α ^{(n × m) mod 255} ), 1360 is 25
The modulo 5 calculates, the result is 85, and the last alpha ⁸⁵ is determined. Furthermore, error position and numbers determined by the Chien search circuit is the original vector representation of the Galois field, rather than indicating the value of n in alpha ⁿ represents the value itself of alpha ^n. Since the calculation of n from the value of α ⁿ or vice versa is very complicated, usually this conversion
Use a conversion table using In any case, many memories and tables are required, and the calculation is complicated and time-consuming. In addition, if there are eight errors per interleave, the calculation must be performed up to eight times for each interleave processing. This means that a considerable amount of time is required from when the position and numerical value of the error are obtained to when the syndrome is obtained. take time. When a memory or the like is provided, there is a problem in that the hardware increases.

Therefore, the present invention does not increase the amount of hardware,
An object of the present invention is to provide an error correction processing device that can verify an error correction result in a very short time after an error position and a numerical value are obtained, and can significantly reduce processing time.

[Means for solving the problem]

In order to achieve the above object, an error correction processing device according to the present invention divides a data string into a plurality of interleaves having the same data length, and verifies an error correction code for performing error correction for each of the plurality of interleaves and a correction result. CRC to do
An error correction processing device for data comprising: an error detection circuit that operates at each clock, detects an error position and an error value by an error correction code, and outputs the error position and an error. An error value input from the error detection circuit, a correction result verification syndrome generation circuit for sequentially generating a correction result syndrome used for CRC calculation, and a clock for the error detection circuit and the correction result verification syndrome generation circuit simultaneously. , The error position and error value detection processing and the correction result verification syndrome generation processing are performed simultaneously.

[Action]

In the present invention, there is provided a syndrome generation circuit to which an output of an error position / numerical value detection circuit for obtaining a solution while substituting a value into an error position polynomial and a numerical value polynomial is provided. Operate synchronously.

Therefore, the CRC check (verification of the error correction result) is completed almost at the same time when the detection of the error position and the numerical value is completed.
The processing time can be greatly reduced.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

1 to 3 show an embodiment of an error correction processing device according to the present invention, in which the present invention is applied to an optical disk control LSI in an optical disk control device used for information processing and the like.

First, the configuration will be described. FIG. 1 is a diagram showing an example of the overall configuration of an optical disk control device. In the figure, reference numeral 111 denotes an optical disk control device; 112, an optical disk control device 111 and an interface SCSI (Small Computer System Interface);
e) Computers connected via 113), 114, 114 are interfaces ModifiedESDI (Enhanced Small Drive Inter
The optical disk device 111 is connected via an optical disk controller 115 and an ECC processor 116 as an optical disk control LSI, a microprocessor 117, and a data buffer 118 composed of DRAM.
, A SCSI control LSI 119, and a driver receiver 120, and the optical disk controller 115 composed of two chips and the ECC processor 116 perform the following processing.

-Sending commands to optical disk devices 113 and 114 and receiving status-Formatting data to be written to optical disk-Decoding data read from optical disk and correcting errors-Data transfer between optical disk devices 113 and 114 and data buffer 118-SCSI control LSI 119 Is used as an interface between the computer 112 and peripheral devices, and a computer system is connected to the optical disk control device 111 through the SCSI. Also,
The optical disk control device 111 controls the optical disk device 1 via ESDI.
The optical disc control device 111 controls the optical disc.

FIG. 2 is a block diagram of the optical disk control LSI, and a portion surrounded by a broken line in the figure shows the optical disk control LSI. In the figure, the optical disk controller 11
Reference numeral 5 denotes an MPU interface circuit 121 for transmitting and receiving commands and the like to and from a host MPU (microprocessor 117) via an MPU interface, and a SCSI control LSI 119 and a DMA control circuit 122 for controlling DMA transfer via a DMA interface.
A data buffer / ECCP control circuit 123 for controlling data transmission / reception via a data buffer / ECCP interface with the data buffer 118 and the ECC processor 116; a data encoding / decoding circuit 124;
25, an internal processor 126, and FIFO memories 127 and 128, which are connected by a predetermined internal bus.

The MPU interface circuit 121 transmits and receives commands and processing results to and from the host MPU (microprocessor 117), has a built-in memory for storing parameters required for executing commands, and reads / writes a data buffer from the host MPU. In this case, the data is transferred via the interface circuit 121. The DMA control circuit 122 performs a handshake control and a byte count control of the DMA transfer as a DMA bus master. Data buffer / ECC
The P control circuit 123 controls the read / write and refresh of the data buffer DRAM and controls the data transmission / reception with the ECC processor 116.
122, arbitrates data buffer / ECC processor access requests from the format encode / decode circuit 124 and the internal processor 126, and controls time division of the data buffer bus. When writing to the optical disc, the format encode / decode circuit 124
It performs parallel-serial conversion of write data and modulates it into RLL (2.7) code, adds a synchronization pattern such as Sync.Resync, and sends it out to ESDI. When reading from the optical disk, the data pattern is decoded to separate the synchronization pattern from the data, to demodulate the data, and to perform serial-parallel conversion. The ESDI control circuit 125 sends an ESDI control signal,
The internal processor 126 includes a reception register and an interface abnormality detection circuit, and controls transmission of codes to the optical disk device and reception of status and the like via the control circuit 125. The internal processor 126 decodes a command given from the host MPU, reports a processing result, and controls continuous processing of a plurality of sectors and single processing. It also issues commands to the ECC processor 116, receives and analyzes processing results, and performs error correction of data in the data buffer.

On the other hand, the ECC processor 116
5, a data transfer control circuit 131 for transmitting and receiving commands and the like via the optical disk controller interface,
ECC / syndrome generation circuit 132 for generating CC and syndrome, and EC generated by ECC / syndrome generation circuit 132
An ECC / syndrome buffer 133 for temporarily storing C / syndromes, and an error location /
Numerical value detection circuit 134, internal processor 135, FIFO memory
136, and these are connected by a predetermined internal bus. The data transfer control circuit 131 performs transmission and reception of commands and processing results between the optical disk controllers, and controls data transfer between the ECC / syndrome generation circuit 132 and an external data buffer. The ECC / syndrome generation circuit 132 uses a CRC
(Cyclic Redundancy Check), ECC generation, error syndrome generation when reading from optical disc, CR
Generate C check data. The ECC / syndrome buffer 133 is a buffer memory that temporarily stores the ECC / syndrome generated by the ECC / syndrome generation circuit 132,
ECC or syndrome for two sectors can be stored. The error position / numerical value detection circuit 134 detects an error position and an error value on the basis of the syndrome at the time of reading from the optical disk, and calculates a polynomial coefficient for calculating a polynomial of an error position and a coefficient of a numerical polynomial based on the Euclidean algorithm. It comprises a circuit 134a and an error position / numerical value detection circuit 134b. The internal processor 135 is an optical disk controller 115
In addition to decoding the command given from, and reporting the processing result, the processing data is moved inside the ECC processor.

In such a configuration, when data to be written to the optical disk is sent from the computer 112 to the optical disk controller 115 via the SCSI control LSI 119, the data is temporarily stored in the data buffer 118, and the necessary data is taken out and the optical disk The data is written in the optical disk devices 113 and 114 while being processed by the controller 115. At the time of reading, the data read from the optical disk devices 113 and 114 is temporarily stored in the data buffer 118, and is sent to the SCSI control LSI 119 at once when the data is accumulated to some extent. Since the optical disk has a very high error rate, the ECC processor 116 uses an error check code ECC so that errors can be corrected later when writing.
When reading, the position of the error and how it is erroneous are detected based on the ECC, and the error portion is corrected on the data buffer 118. As shown in FIG. 2, the optical disk controller 115 and the ECC processor
Both 116 have processors 126 and 135 inside, all of which operate under program control. The entire optical disk control device 111 including the optical disk controller 115 and the ECC processor 116 is program-controlled by the microprocessor 117. Therefore, an MPU interface circuit 121 is provided for notifying an instruction or a processing result with the microprocessor 117, and the internal processor 126 is connected to the MPU interface 121.
When the instruction is received from the CPU, the instruction is decoded and, for example, the data buffer / ECCP control circuit 123 is operated or the ECC processor 116 is activated. Also, ECC processor 11
6 operates according to a command from the optical disk controller 115, and the ECC processor 116 intercepts data transferred on the bus connecting the data buffer / ECCP control circuit 123 and the data buffer 118 and generates an ECC based on the data. When reading or reading, a syndrome for calculating the error position and numerical value is generated.

Next, a description will be given of an error position / numerical value detection circuit which is a point of the present invention. The present invention is based on the following basic concept. Since the circuit is already operating while finding the position and numerical value of the error by the Chien search, the circuit for generating the correction result verification syndrome may be operated together therewith. For example, if an error is detected at the position 19 while the error position / numerical value detection circuit is performing the digital error position / numerical value detection processing of FIG. 4B, the error position jl = 19. At this time, the error value
e _jl = e _{19 is} also known at the same time. Errors detected here, when fitted to E0 (x) of FIG. 13, so that the position 19 there is a error value e ₁₉ = alpha ^E.

In order to calculate the syndrome E0 (α ⁱ ), α ^E is input to the syndrome generator and a clock is given. If there is no error in the positions 18 to 16, the clock is input seven times while inputting 0 continuously. Just give it.

Further, the error position / numerical value detection circuit continues the Chien search until the position 0, that is, jl = 0, so that the clock must be supplied 19 more times. Assuming that a clock is simultaneously supplied to the syndrome generator and the error position / numerical value detection circuit, the calculation of E0 (α ⁱ ) is completed when jl = 11.

From this, when the error value output of the error position / numerical value detection circuit is input to the correction result verification syndrome generation circuit while a clock is simultaneously applied to both circuits and jl = 11, the correction result verification syndrome generation is performed. If the application of the clock to the circuit is stopped, when the detection of the error position and the numerical value is completed, the calculation of the correction result verification syndrome is also completed. However, positions 15 to 0 in FIG. 4 (b) are the ECC part, and the ECC is not included in the CRC calculation as shown in FIG. 5 (b). Also, E0 in FIG.
Since the positions C3 to C0 are always 0 in (x) to E9 (x),
When jl <16, 0 is input to the correction result verification syndrome generation circuit instead of the error value e _jl . E6
Since the position 16 is always 0 in (x) to E9 (x), 0 is similarly input when jl <17 in the processing of interleaving 6 to 9.

Thus, for example, when the calculation of E0 (α ⁱ ) is completed, the internal processor reads and stores the result. next
When the calculation of E1 (α ⁱ ) is completed, the E0 (α ⁱ ) is read out and added (EOR) to the stored E0 (α ⁱ ), and the result of the addition is stored. Even when the calculation of E2 (α ⁱ ) to E9 (α ⁱ ) is completed, the same is added and stored.

Next, EC (α ⁱ ) is calculated. When an error is detected at the position 16 in the error position / numerical value detection processing of the interleaving 6 to 9, the internal error value is stored in the internal processor. Then, after the processing of the interleave 9 is completed, the stored error value at the position 16 is sequentially input from the interleave 6 and a clock is applied to the correction result verification syndrome generation circuit. This operation is performed by the internal processor. Since the positions 119 to 16 of EC (x) are 0, there is no need to calculate them, and the calculation of EC (α ⁱ ) is completed only by giving four clocks. When the calculation of EC (α ⁱ ) is completed, EC (α ⁱ ) to E9 (α ⁱ ) are added to the result obtained by adding E0 (α ⁱ ) to E9 (α ⁱ ).
If (α ⁱ ) is added, the result is E (α ⁱ ).
Then, E (α ⁱ ) is compared with the syndrome A (α ⁱ ) calculated and stored from the data before error correction, and if they match, it is determined that the error correction result is correct. That is, if correct ^{E (α i) = E0 (} α i) + E1 (α i) + ...... + E9 (α i) + EC (α i) correction result is the ^{E (α i) = A (} α i) .

In addition, since A (α ⁱ ) −E (α ⁱ ) = 0, A (α ⁱ ) −E0 (α ⁱ ) −E1 (α ⁱ ) −... −E9 (α ⁱ ) −EC (α ⁱ ) = 0 Therefore, every time the calculation of E0 (α ⁱ ) to EC (α ⁱ ) is completed, subtraction (EOR) is sequentially performed from A (α ⁱ ) to obtain EC
It is also possible to determine that the result of subtraction to (α ⁱ ) is 0.

After the detection of the error positions and numerical values of all the interleaves is completed, the verification of the correction result is completed by performing a very small amount of processing. In addition, there is no need to handle multiplication / division and exponentiation in Galois fields in the internal processor, so that the internal processor (software) is hardly burdened.

In the interleave that does not perform the chain search, that is, in the interleave in which the error correction syndrome created from the data and the ECC is 0 and there is no error, the error value is all 0, so the correction result verification syndrome of the interleave is also set to 0. deal with. Since the addition of 0 is meaningless, the interleaving does not perform the syndrome addition processing.

Similarly, when there is no error in the position 16 of the interleaves 6 to 9, the calculation of EC (α ⁱ ) is not performed.

Hereinafter, a specific configuration of the error position / numerical value detection circuit will be described in accordance with the above basic concept. FIG. 3 is a diagram showing an error position / numeric value detection circuit using Chien search;
The same components as those of the conventional example shown in FIG. 14 are denoted by the same reference numerals and symbols, and the description will not be repeated. In FIG. 3, 151
Is an error position / numerical value detection circuit (error correction processing device).
2. A circuit 31 of the error locator polynomial ω (x), a circuit of σ ′ (x) (formal differentiation circuit) 53, an error value calculation circuit 58, an error detection result storage circuit 70, and a correction result verification syndrome generation circuit 152 It is configured. Correction result verification syndrome generation circuit 152 Multiplication circuits 153 to 156, 8-bit flip-flops FF157 to 160, and EOR (Galois field addition) circuits 161 to 16
4, a selector 165, and an AND circuit 166,
Error values e _jl output from the error value calculation circuit 58 is input to the EOR circuit 161 to 164 through the AND circuit 166 and the selector 165.

When performing processing of one sector, first, the output of the selector 165 and the AND circuit 166 are selected, and then a clock is applied to the entire circuit.
Perform the first interleaved chain search. As described above, when the error position is not at the error position, the input of the syndrome generator must be set to 0, but the output e _jl of the error value calculation circuit 58 outputs a meaningless value at this time. Therefore, in a cycle in which the output of the Zero detection circuit 57 is not “1” (that is, no 0 is found or an error position is not found), the output of the AND circuit 166 becomes 0.
I am trying to be. Although not shown, AND
The output of circuit 166 is j in the processing of interleaves 0-5.
When l <16 and in the processing of interleaves 6 to 9, j
It is also set to 0 when l <17. Therefore,
Only when an error position is found, the error value e _jl is
Is input to In this way, a Chien search is performed while inputting an error value to the correction result verification syndrome generation circuit 152. Then, when jl = 11, the supply of the clock to the correction result verification syndrome generation circuit 152 is stopped, and only the chien search is performed until jl = 0. jl
It can be seen from the output of the location counter 55. The location counter 55 counts and outputs the number t of clocks applied to the circuit. As described above, since t = 255−jl, for example, when jl = 11, the output value of the location counter 55 is t = 255−jl = 255−11 = 244. Therefore, the output value of the location counter 55 is 244. At this point, the correction result verification syndrome generation circuit 15
I try to stop giving the clock to 2. The flip-flops 157 to 160 are reset to 0 before processing one interleave. When the chain search of one interleave is completed, that is, when the output value of the location counter becomes 255 (jl = 0), the internal processor reads the contents of the error number counter 54, the register file 56, and the flip-flops 157 to 160.

After completing interleave 9, the internal processor
It is determined whether or not there is an error at the position 16 of the interleave 6 to 9.
(X) After selecting the input and resetting the flip-flops 157 to 160, the error values at the positions 16 of the interleaves 6 to 9 are sequentially input from the EC (x) input, and the clock is sent to the correction result verification syndrome generation circuit 152. give. After entering all four error values, flip-flop 157
Read the contents of ~ 160. Thus, all syndrome calculations are completed.

In contrast to the conventional example, if software was used to perform the syndrome calculation, a conversion ROM would be required or complicated calculations would be required. If the syndrome generation circuit 152 for verifying the correction result is operated together with the operation of the hardware, the detection of the error position and the numerical value is almost completed at the same time.
The CRC check (verification of the correction result) ends.

As described above, in this embodiment, the CRC check is completed almost at the same time when the calculation of the error position and the numerical value is completed by adding the correction result verification syndrome generating circuit 152 to the conventional error position and numerical value detecting circuit. , Processing time is greatly reduced. In other words, what used to be software and it took a long time to process with large hardware, but since the position and numerical value of the error were found by the Chien search, if it was operated there, it would be very fast with a small number of circuits, and Thus, the apparent processing time of the CRC check can be realized with almost zero.

Note that the number of interleaves for one sector of data is not necessarily
It does not need to be 10 and the length of one interleave is 12
It may be other than 0 bytes.

〔The invention's effect〕

According to the present invention, a correction result can be verified at the same time when an error position and a numerical value are obtained without significantly increasing the amount of hardware, and processing time can be significantly reduced.

[Brief description of the drawings]

1 to 3 are diagrams showing an embodiment of an error correction processing device according to the present invention, FIG. 1 is an overall configuration diagram of the optical disk control device, FIG. 2 is a block configuration diagram of the optical disk control LSI, FIG. 3 is a circuit diagram showing the error position / numerical value detection circuit, FIGS. 4 to 14 are diagrams showing a conventional error correction processing device, FIG. 4 is a diagram of a code word of the Reed-Solomon code, FIG. FIG. 5 is a diagram for explaining the data arrangement, FIG. 6 is a basic circuit diagram of the error locator polynomial and the error numerical polynomial, FIG. 7 is a circuit diagram showing a circuit of the error locator polynomial, and FIG. A circuit diagram showing a circuit of an error numerical polynomial, FIG. 9 is a circuit diagram showing a circuit of the formal differentiation, FIG. 10 is a diagram showing a data sequence including the CRC, and FIG. 11 explains an operation principle of the syndrome generator. Figure 12 shows the error values and errors Fig. 13 is a diagram for explaining the syndrome calculation based on the error position, Fig. 13 is a diagram for explaining the application of the syndrome calculation based on the error value and the error position, and Fig. 14 is the error position / value detection circuit. FIG. 1 ... Error locator polynomial σ _(X) circuit, 11-18, 32-39, 62-64, 153-156… Multiplication circuit, 20-28, 40-47, 65-68, 157-160… Flip-flop, 19, 48, 69… EOR circuit, 31… Circuit of error numerical polynomial ω _(X) , 51… Error position / numerical value detection circuit, 52… Error position detection circuit, 53… Formal differentiation Circuit, 54: Error number taunter, 55: Location counter, 56: Register file, 57: Zero detection circuit, 58: Error value calculation circuit, 59: Galois field reciprocal ROM, 60: Galois field multiplication 61, register, 70, error detection result storage circuit, 111 optical disk control device, 112 computer, 113, 114 optical disk device, 115 optical disk controller, 116 ELL processor, 117 … Microprocessor, 118… Data buffer, 119… SCSI control LSI, 120… Driver receiver, 121: MPU interface, 122: DAM control circuit, 123: Data buffer ECCP control circuit, 124: Format encode / decode circuit, 125: ESDI control circuit, 126: Internal processor, 127, 128, 136 ... … FIFO memory, 131… Data transfer control circuit, 132 …… ECC / syndrome generation circuit, 133 …… ECC / syndrome buffer, 134 …… Error position / numerical value detection circuit, 134a …… Polynomial coefficient calculation circuit, 134b …… Error position / numerical value detection circuit, 135: Internal processor, 151: Error position / numerical value detection circuit (error correction processor), 152: Correction result verification syndrome generation circuit, 161 to 164: EOR (Galois field addition) ) Circuit, 165: Selector, 166: AND circuit.

Continuation of front page (72) Inventor Masayuki Ishiguro 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Fujitsu VSI Co., Ltd. (56) References JP-A-63-257966 (JP, A) JP-A-62-117424 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 13/00-13/53

Claims (1)

(57) [Claims] 1. A data sequence comprising: dividing a data string into a plurality of interleaves having the same data length; providing an error correction code for performing error correction for each of the plurality of interleaves; and a CRC for verifying a correction result. An error correction processing device comprising: an error detection circuit that operates for each clock to detect an error position and an error value by an error correction code and outputs the error position; and an error detection circuit that operates for each clock and outputs from the error detection circuit for each clock. An error value is input, and a correction result syndrome generation circuit for sequentially generating a correction result syndrome used for CRC calculation is provided.By simultaneously providing a clock to the error detection circuit and the correction result verification syndrome generation circuit, An error characterized by simultaneous detection of an error position and error value and generation of a correction result verification syndrome Positive processing apparatus.