JP3281938B2 - Error correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction device for correcting an error occurring in information encoded by an error correction code, and more particularly to a compact disk player (hereinafter referred to as a compact disk player).
CD), digital audio player (hereinafter, referred to as CD)
DAT), a digital video signal recording / reproducing apparatus (hereinafter, referred to as a digital VTR), and the like, and an error correcting apparatus for correcting an error occurring in a reproduced or received digital signal at a high speed.

[0002]

2. Description of the Related Art CDs,
PCM (Pu) represented by DAT, digital VTR, etc.
lse Code Modulation) An error correction process using an error correction code is used for recording and reproduction. Hereinafter, the above CD,
An error correction device that performs an error correction process using a Reed-Solomon code defined on GF (q) as an error correction code actually used for a DAT and a digital VTR will be described.

In order to perform error correction of a large number of words using a Reed-Solomon code, it is necessary to generate a syndrome from received data and obtain coefficients of an error position polynomial and an error numerical polynomial. As one method for obtaining such a polynomial coefficient, a Euclidean algorithm, a Berlekamp algorithm, or the like is known. For example, the above-mentioned Euclidean algorithm is an algorithm for finding the greatest common divisor of two given polynomials, and performs division between polynomials whose coefficients are elements of the Galois field GF (q) to obtain an error locator polynomial and an error. Find a numerical polynomial. A detailed description of the Euclidean algorithm will be described later.

[0004] A decoding procedure for error correction of a large number of words using Reed-Solomon codes will be described below. In general, the procedure for decoding a Reed-Solomon code is as follows. (1) obtaining the syndromes S _i from the received data. (Generation of Syndrome) (2) Error locator polynomial σ from the found syndrome Si
(Z) and the error numerical polynomial ω (z) are obtained. (Euclidean or Berlekamp algorithm, etc.) (3) The error position is obtained from the error position polynomial σ (z).
(Chen search) (4) An error value is obtained from the error position and the error value polynomial ω (z). (5) The error of the received data is corrected from the error position and the error value. (Error correction)

A method for decoding a Reed-Solomon code defined by Galois field GF (2 ⁸ ) will be described below.

The syndrome _Si is given by the following equation. The reception polynomial X (z), the generator polynomial and G (z), the S (z) = X (z ) mod G (z) = S 0 + S 1 × z + ··· + S k × z k. In this conventional example, a case where a Reed-Solomon code having a code length n is decoded will be described.

Next, an error position polynomial σ (z) and an error numerical polynomial ω (z) are obtained from the syndrome S _i (S (z)). Hereinafter, a method of calculating the error locator polynomial and the error numerical polynomial using the Euclidean algorithm will be briefly described. The Euclidean algorithm is a repetition of division between polynomials defined on a Galois field, and is represented as follows. That is, the Euclidean algorithm is defined as two polynomials defined on the Galois field as A (z),
Assuming B (z), A (z) / B (z) = Q ₀ (z) (quotient)... R ₀
(Z) _{(remainder) B (z) / R 0} (z) = Q 1 (z) ( quotient) ··· R ₁
(Z) (remainder) R ₀ (z) / R ₁ (z) = Q ₂ (z) (quotient)... R ₂
(Z) (Remainder) The division between polynomials defined on the Galois field is repeated until a certain condition is satisfied.

For example, in the case of an error correction code used for an optical disk, a Reed-Solomon code having a minimum Hamming distance of 17 is used, so that A (z) = z ¹⁶ B (z) = S (z) = expressed as _{S 0 + S 1 × z +} ··· + S 15 × z 15, the order of the division is less of a polynomial is repeated until the 7 or less. (In this example, erasure is not considered.)

FIG. 25 shows a flowchart for obtaining the solution of the basic equation (error locator polynomial and error numerical polynomial) by the Euclidean algorithm. First, initial values are set in S1. The calculations shown in S2 and S3 are executed, and if NO in S4, each polynomial is set as shown in S5, and the process returns to S2 again. If YES in S4, S
6, the error locator polynomial σ (z) and the error numerical polynomial ω
Find (z). In the figures, <> indicates a Gaussian symbol.

Therefore, the calculation of the error locator polynomial σ (z) and the error numerical polynomial ω (z) by the Euclidean algorithm is performed in the case of a Reed-Solomon code having a minimum Hamming distance of 17 by dividing the polynomials on the Galois field by a maximum of eight. It will be good if you go around.

An error position is obtained from an error position polynomial σ (z) obtained by the Euclidean algorithm.
For this, a method called Chien search is generally used.
In this method, the error locator polynomial σ (z) is a power of α (α is an element on the Galois field GF (2 ⁸ )) α ⁱ (i = 0,
1, 2,..., N−1) are successively substituted to obtain σ (α ⁱ )
Is found to be the root α ⁱ (corresponding to an error position) of σ (z) at which is zero. Here, n is the code length.

According to the above-described method, in order to calculate an error position, n elements (α ^{0 to} α ^n-1 ) on GF (2 ⁸ ) corresponding to the code length are sequentially converted to an error position polynomial σ (z ) To calculate α ⁱ (corresponding to an error position) where σ (z) = 0, so that the number of operation steps is n (code length) steps.

Hereinafter, a conventional error correction device will be described. FIG. 26 is a block diagram showing a schematic configuration of a conventional error correction device for decoding a Reed-Solomon code. In the figure, 1 is a RAM in which data to be corrected is stored, 2 is a syndrome generation circuit that generates a syndrome from a received word, and 3 is an error correction based on the reception syndrome output from the syndrome generation circuit 2. Is an error correction device control circuit for controlling the entire error correction device.

FIG. 27 shows a specific circuit configuration diagram of the syndrome generation circuit 2. Reference numeral 10 denotes a register for temporarily storing input data, reference numeral 11 denotes a multiplication circuit using each coefficient of a Reed-Solomon code generator polynomial as a multiplier, and reference numeral 12 denotes an addition circuit. As described above, the syndrome generation circuit 2 includes the register 10, the multiplication circuit 11, and the addition circuit 12.

FIG. 28 shows a specific circuit configuration example of the error correction operation circuit 3. Reference numeral 20 denotes a Euclidean arithmetic circuit that calculates an error locator polynomial σ (z) and an error numerical polynomial ω (z) according to the Euclidean algorithm shown in FIG. 25, and 21 denotes an error locator polynomial σ output from the Euclidean arithmetic circuit 20
A Chien search circuit 22 for calculating an error position from the coefficient data of (z), based on the coefficient data of the error numerical polynomial ω (z) output from the Euclidean arithmetic circuit 20 and the error position information output from the Chien search circuit 21 An error correction circuit that calculates an error value and performs error correction. Above, Euclidean arithmetic circuit 20, Chien search circuit
The error correction operation circuit 3 is composed of the error correction circuit 21 and the error correction circuit 22.

FIG. 29 is a block diagram showing a division circuit portion of the Euclidean arithmetic circuit 20 for dividing a polynomial on the Galois field. 50 and 51 are input terminals, 52a and 52b are divisors,
A register for storing the coefficient data of the dividend polynomial, 53
Is a selector, 54 is a multiplication circuit, and 55 is an addition circuit. As described above, the registers 52a and 52b, the selector 53, the multiplication circuit 54, and the addition circuit 55 constitute a polynomial division circuit portion on the Galois field of the Euclidean operation circuit 20.

FIG. 30 shows a specific circuit configuration example of the Chien search circuit 21. 31 is a feedback register for setting the coefficient data of the error locator polynomial σ (z) at the start of the Chien search, and thereafter setting the output of the successive multiplication circuit 32; 32, a multiplication circuit; 33, an addition circuit; A judgment circuit for judging whether the output is 0, 35 is a coefficient counter for counting the number of feedbacks of the feedback register 31, and 36 is a register for storing the count value of the coefficient counter 35 based on the 0 judgment result output from the judgment circuit 34. It is. As described above, the Chien search circuit 21 includes the feedback register 31, the multiplication circuit 32, the addition circuit 33, the determination circuit 34, the coefficient counter 35, and the register 36.

Next, the operation of the error correction device will be described with reference to FIGS. 26, 27, 28, 29 and 30. RAM1
The received or reproduced data including an error generated during reception or reproduction stored in the RAM 1 is read from the RAM 1 to generate a syndrome in the syndrome generation circuit 2 when the error correction processing is started. The syndrome generation circuit 2 divides the data (reception polynomial format) read from the RAM 1 by a generation polynomial to generate a syndrome. Note that a read address for reading the reproduction data from the RAM 1 and a read control signal are output from the error correction device control circuit 4.

The syndrome generation circuit 2 whose circuit configuration is shown in FIG. 27 includes a register 10 arranged in a shift register format,
It comprises a multiplying circuit 11 for multiplying input data (feedback data) by coefficient data corresponding to each term of the generator polynomial, and an adding circuit 12. The syndrome generation circuit 2 performs division of a polynomial on a Galois field by shifting the input data while sequentially calculating the data in the operation circuit. Therefore, the number of steps corresponding to the code length (n steps) is required to execute the operation. The details of the syndrome generation circuit 2 are described in “Code Theory” by Hideki Imai, published by the Institute of Electronics, Information and Communication Engineers, pp. 115-118.

In the manner described above, the syndrome generated by the syndrome generation circuit 2 is output to the error correction operation circuit 3 and the error correction device control circuit 4 together with the syndrome generation end signal. The error correction device control circuit 4 outputs a Euclidean operation start signal to the error correction operation circuit 3 based on the syndrome generation end signal. When the Euclidean operation start signal is input to the error correction operation circuit 3, the Euclidean operation circuit 20 uses the error position polynomial σ based on the syndrome output from the syndrome generation circuit 2.
(Z) and the error numerical polynomial ω (z) are calculated.

The Euclidean operation circuit 20 shown in FIG.
The circuit operation of the division part will be described. When the syndrome generation end signal is input, each register 52 is set to an initial value. Specifically, Z ^2t is set in the upper group of registers 52a, and the coefficients of the syndrome polynomial calculated by the syndrome generation circuit 2 are set in the lower group of registers 52b. The data set is the dividend side (Z
The polynomial division on the Galois field is executed by shifting the data of the upper register 52a group in which ^2t data is set. The division is repeated until the degree of the polynomial on the dividend side becomes smaller than the degree of the polynomial on the divisor side. In FIG. 29, a selector 53 connected to a group of registers 52 on the dividend side is connected to select an output of the adder circuit 55,
The selector 53 connected to the group of registers 52 on the divisor side is configured to select the output of the register 52. As a result, the data in the register 52 on the dividend side is shifted and division is executed.

As a result of the division, the remainder of the division is stored in the register group on the dividend side. Next, division is performed using the polynomial stored in the divisor register group as a dividend and the remainder of the division result as a divisor. This switches the divisor and the dividend by switching the output of the selector 53. This operation is repeated until the end condition of the algorithm shown in FIG. 25 is satisfied. When the above condition is satisfied, the Euclidean arithmetic circuit 20 calculates the error position polynomial and the coefficient data of the error numerical polynomial, and outputs them to the Chien search circuit 21 and the error correction control circuit 4 together with the Euclidean arithmetic end signal. The description of the division circuit portion of the Euclidean arithmetic circuit 20 is described in Japanese Patent Application Laid-Open No. 1-276825.

The error correction device control circuit 4 outputs a Chien search start signal for starting the operation of the Chien search circuit 21 based on the Euclidean arithmetic end signal output from the Euclidean arithmetic circuit 20. In the chain search circuit 21,
When a Chien search start signal is input, an error position is calculated based on each coefficient of the error position polynomial σ (z) calculated by the Euclidean arithmetic circuit 20. The specific operation of the Chien search circuit 21 will be described with reference to FIG. Chain search circuit 21
When the chain search start signal is input, the coefficient counter
35 is set to 0, and the error locator polynomial σ calculated by the Euclidean arithmetic circuit 20 is stored in the feedback register 31.
Each coefficient data of (z) is set. Then, the output of the feedback register 31 is multiplied by a multiplier set in the multiplication circuit 32 in advance, and latched by the feedback register 31 again.

The addition circuit 33 adds the outputs of the feedback registers 31. The determination circuit 34 determines whether the result of the addition is 0, and if it is 0, writes the count value of the coefficient counter 35 to the register 36. (This count value corresponds to the error position.) It takes n steps to end the chain search. The details of the Chien search circuit 21 are described in the aforementioned “Code Theory”, pp. 165 to 166.

In the error correction circuit 22, first, based on the error position information output from the Chien search circuit 21, RA
The erroneous data stored in M1 is read out. At the same time, the Euclidean arithmetic circuit
An error value is obtained from the error value polynomial ω (z) output from 20 and the error position information output from the Chien search circuit 21. The erroneous data read from the RAM 1 is added to the above-mentioned error numerical value and subjected to error correction. The error-corrected data is rewritten as erroneous data in the RAM 1.

FIG. 31 shows a simple flow of coding and decoding of the error correction device when the above-described error correction device is applied to, for example, a digital VTR. In FIG. 31, the data input to the error correction device is divided into a plurality of unit information blocks. Generally, the error correction code is often double-coded. In this case, a plurality of unit information blocks divided into a plurality of pieces are collected and arranged two-dimensionally as shown in FIG. Then, after the error correction coding apparatus adds the vertical error correction code (C2 code), the recording direction error correction code (C1 code) is added. In addition,
The code configuration shown in FIG. 32 is based on the document "AN EXPERIMENTAL HOME-US
E VCR WITH THREE DIMENSIONAL DCT ANDSUPERIMPOSED C
ORRECTION CODING ”IEEE TRANSACTIONS ON CONSUMER EL
ECTRONICS AUG.1991 VOL.37 NUMBER3 is one of the error correction codes used for home digital VTR.
It is a structural example. FIG. 33 shows one of the recording directions shown in FIG.
The code configuration of the line is shown. The data to which the error correction code is added is recorded on a recording medium in the case of a digital VTR, and is sent out on a communication path in the case of communication. The data reproduced from the recording medium is subjected to an error correction process in order to correct an error occurring during the reproduction process. In the error correction process, errors included in the reproduced data are corrected or detected. The error-corrected reproduction data is output to the next step.

Next, FIG.
The signal processing timing of each unit when decoding line data will be described with reference to the timing chart shown in FIG. FIG. 34 shows various control signals (a syndrome generation start signal, a Euclidean operation start signal, a Chien search start signal, and an error correction start signal) output from the error correction device control circuit 4, and the operation timing of each circuit (the syndrome generation circuit 2). , The operation timing of the Euclidean operation circuit 20, the operation timing of the Chien search circuit 21, and the error correction timing of the error correction circuit 22, and the data access state of the RAM 1. When error correction is started, the error correction device control circuit 4 outputs a syndrome generation start signal to the syndrome generation circuit 2 and a read address for reading reproduction data stored in the RAM 1 and containing an error generated during reproduction. , And a control signal. Syndrome generation circuit 2
Then, the value in the register 10 is set to 0 based on the syndrome generation start signal, and a predetermined operation (division) is performed on the data read from the RAM 1. As described above, the generation of the syndrome requires 241 steps corresponding to the code length until the operation is completed. This calculation time is shown in the SY section of FIG.

When the syndrome generation ends, the syndrome generation circuit 2 outputs a syndrome generation end signal. The error correction device control circuit 4 outputs a Euclidean operation start signal based on the syndrome generation end signal. The Euclidean arithmetic circuit 20 divides the polynomial on GF (2 ⁸ ) based on the Euclidean arithmetic start signal in the manner described above, and calculates an error position polynomial σ (z) and an error numerical polynomial ω (z). When decoding the Reed-Solomon code of the minimum distance 17 shown in the conventional example (calculation of the error locator polynomial and the error numerical polynomial) using the Euclidean algorithm, the above-described division between the polynomials is performed at a maximum of eight.
It can be calculated by repeating it twice. This calculation time is shown in FIG.
It is shown in the EU section in the middle. The number of steps at this time depends on the entire circuit configuration of the Euclidean arithmetic circuit 20, but the Reed-Solomon code of the minimum distance 17 shown in FIG. 33 is converted to an error position polynomial σ (z) and an error numerical polynomial using the Euclidean algorithm. The number of steps required to calculate ω (z) is 12
It can be realized in about 0 steps. Although the description of the detailed operation of the circuit is omitted, the division operation in the above-mentioned division circuit, data setting, generation of a control signal, calculation of error position polynomial σ (z) and error value polynomial ω (z), or Approximately 120 steps of the Euclidean arithmetic circuit for calculating the correction syndrome when an erasure occurs, but omitted in the example
20 decoding time is required.

When the Euclidean operation is completed, the Euclidean operation circuit 20 outputs a Euclidean operation end signal. The error correction device control circuit 4 outputs a Chien search start signal based on the Euclidean end signal. In the Chien search circuit 21, 0 is set in the coefficient counter 35 based on the Chien search start signal, and each coefficient data of the error locator polynomial calculated in the Euclidean arithmetic circuit 20 is set in each feedback register 31. Then, the output of the feedback register 31 is multiplied by a multiplier set in the multiplication circuit 32 in advance, and latched by the feedback register 31 again.
The coefficient counter 35 counts the number of feedbacks of the feedback counter 31. The addition circuit 33 adds the outputs of the feedback registers 31. The determination circuit 34 determines whether the addition result is 0, and if it is 0, writes the count value of the coefficient counter 35 to the register 36. As described above, the Chien search circuit 21 requires a maximum number of steps of the code length, that is, 241 steps, to calculate the error position. This calculation time is shown in the CH section in FIG.

When the chain search ends, a chain search end signal is output from the chain search circuit 21. The error correction device control circuit 4 outputs an error correction start signal based on the Chien search end signal. FIG. 35 shows a detailed timing chart of the error correction circuit 22. The error correction circuit 22 calculates an error value using the error value polynomial ω (z) based on the error correction start signal and the error position information output from the Chien search circuit 21. On the other hand, the error correction device control circuit 4 reads erroneous data from the RAM 1 based on the above-described error position information. The erroneous data read from the RAM 1 is added to the error value at the timing of the next clock, and error correction is performed. The error-corrected data is written to the RAM 1 again at the next clock. Therefore, in order to execute the error correction of one symbol in the error correction circuit 22, a period of three clocks is required at a minimum. Therefore, at least 24 steps are required to perform error correction of 8 symbols.

The error correction device is an indispensable device for reproducing errors in a CD, DAT, digital VTR, or the like, or correcting an error occurring in a received signal, but the conventional error correction device has the following problems. Having. One of the problems is that the conventional error correction apparatus requires a very long decoding time to perform one-line error correction, as shown in FIG. In the case of the conventional example, although the circuit architecture for high-speed operation is adopted in the division circuit portion of the Euclidean arithmetic circuit 20 to increase the speed, it is difficult to decode the one-line C1 block shown in FIG. The decoding time of step (241 + 120 + 241 + 24 = 626) is required. A Euclidean arithmetic circuit as shown in FIG.
Several circuit architectures for increasing the speed of 20 are introduced in published patent publications and the like. However, even if the operation time in the Euclidean operation circuit 20 is shortened, the processing time such as syndrome generation or Chien search is not shortened. In some cases, a high processing speed cannot be maintained.

A circuit configuration relating to speeding up of the error correction device is introduced in Japanese Patent Laid-Open Publication No. Hei 3-63973. This is shown in Figure 28
Syndrome generation circuit 2 and error correction operation circuit 3 shown in FIG.
Are operated in parallel. The circuit operation of this error correction device will be described with reference to the timing chart shown in FIG. Syndrome generation circuit 2 based on the parallel operation start signal
Starts syndrome generation. At the same time, the Euclidean operation circuit 20 in the error correction operation circuit 3 executes the error locator polynomial σ according to the Euclidean algorithm in the manner described above.
(Z) and the error numerical polynomial ω (z) are calculated. When the operation in the Euclidean operation circuit 20 is completed, the error position is calculated in the Chien search circuit 21 based on the coefficient data of the error position polynomial. When the Chien search circuit 21 calculates the error position, the error correction circuit 22 corrects the error. Note that the syndrome generation circuit 2 and the Euclidean arithmetic circuit 2
0, the operations of the Chien search circuit 21 and the error correction circuit 22 are the same as those of the above-described conventional example, and the detailed operation is omitted. FIG. 36 shows the number of operation steps in each circuit. The figure
Reference numeral 36 shows the output timing of various control signals output from the error correction device control circuit 4, the operation timing of each circuit, and the data access state of the RAM 1 as in the conventional example. Syndrome generation circuit 2 and error correction operation circuit 3
Are operated in parallel, so that C in one line shown in FIG.
The number of steps required to perform error correction for one block requires at least 385 steps.

However, even in this conventional example, when decoding the product code type Reed-Solomon code as shown in FIG. 32, the error correction by the C2 code is performed after the error correction by the C1 code is completed, so that the number of decoding steps is very large. It becomes so large that it cannot be decoded in real time. Also, C
Since 2 decoding is performed on the data subjected to C1 decoding, data must be read from the same RAM again. As a result, it is necessary to take measures such as arranging the error correction devices in parallel and performing parallel processing.

As shown in FIG. 27 and FIG. 30, the syndrome generation circuit 2 and the Chien search circuit 21 are provided with a multiplication circuit for multiplying a register output by a constant value on a Galois field and an addition circuit in series or parallel. Have been. At this time, it passes through a maximum of four stages of EX-OR gates on hardware. On the other hand, on the Euclidean arithmetic circuit 20, although depending on the hardware configuration, the number of EX-OR gates is about seven, and it is difficult to increase the speed as compared with the syndrome generation circuit 2 and the Chien search circuit 21 because it passes through several selectors. There was a problem that it is. Further, there is a problem that the circuit scale of the Euclidean arithmetic circuit 20 shown in FIG. 29 is unnecessarily large. In addition, at least three steps are required for error correction of one symbol in the error correction circuit 22, and there is a problem in speeding up.

Recently, the development of digital VTRs has been promoted by various companies, and increasing the speed of the error correction device has become an important issue. FIG. 37 shows a block configuration diagram of a division circuit unit (hereinafter, referred to as a core circuit) between polynomials defined on a Galois field when performing a conventional Euclidean operation described in JP-A-3-72027. Show. The description of the addition circuit, the multiplication circuit, and the division circuit described below is based on the assumption that they perform addition, multiplication, and division operations on a Galois field.

In the figure, reference numerals 81a and 81b denote registers for storing coefficient data of the polynomial to be divided and divisor polynomials, reference numerals 82 and 83 denote selectors for selecting one of the outputs of the registers 81a and 81b, reference numeral 84 denotes a division circuit, and reference numeral 85 denotes a division circuit. Is a multiplication circuit, 86 is an addition circuit,
95 is an input terminal, 87 and 88 are order detection circuits, registers 81a and 8
Detect the degree of the polynomial stored in 1b. 89 is a Euclidean arithmetic control circuit for controlling the entire operation,
Controls the selectors 82 and 83, and the order detection circuit 87,
The end condition of the Euclidean algorithm is determined based on the order determination result output from 88. Register 81
a, 81b, selectors 82, 83, division circuit 84, multiplication circuit 85, addition circuit 86, degree detection circuits 87, 88, and Euclidean operation control circuit 89, for dividing the polynomials on the Galois field in the Euclidean operation circuit. The unit (core circuit) is configured. In the conventional example, the register arranged on the right side is configured to store higher-order coefficients of each polynomial.

Next, the principle of operation of the division circuit when performing division with the above circuit configuration will be briefly described. Now, the dividend polynomial, respectively the dividend polynomial and divisor _{polynomial: M1 (Z) = A n} Z n + A n-1 Z n-1 + ·
.. + A ₁ Z ¹ + A ₀ division polynomial: M2 (Z) = B _m Z ^m + B _m-1 Z ^m-1 + ··
・ Set to + B ₁ Z ¹ + B ₀ . Note that n> m. Hereinafter, the calculation procedure when the above division is performed by handwriting is shown in Equation 1.

[0038]

(Equation 1)

As shown in Equation 1, the calculation is repeated until the degree of the remainder of the polynomial to be reduced becomes smaller than the degree of the polynomial. In Equation 1, each coefficient data of the final remainder polynomial is represented by C _i (i = 0, 1, 2,..., M−1).

According to the Euclidean algorithm shown in FIG. 25, a remainder polynomial: R (Z) = C _m-1 Z ^m-1 + C _m-2 Z ^m-2 +... + C ₁
When the order of Z + C ₀ does not satisfy the predetermined condition, the division is repeated by setting the divisor polynomial M2 (Z) as the polynomial to be divided and the remainder polynomial R (Z) as the divisor polynomial. At this time, the details will be described later, but in the division circuit shown in FIG. 37, the selectors 82 and 83 are switched to exchange the divisor polynomial and the polynomial to be deleted.

Similarly, a calculation procedure in the case where M2 (Z) is divided by R (Z) in Equation 2 is shown.

[0042]

(Equation 2)

In this calculation, for convenience, it is assumed that the maximum degree C _m-1 of the remainder polynomial R (Z) is not zero. (Generally, when it is 0, the order detection circuits 87, 88 shown in FIG. 37
In the above-mentioned dividend polynomial, and after determining the order of the divisor polynomial, and shifting the coefficient data of the dividend polynomial, and the divisor polynomial until the maximum order of the divisor polynomial and the divisor polynomial is not 0,
Performs division. Also, when the maximum degree of the remainder polynomial during the division operation becomes 0, the division operation is similarly performed after shifting the coefficient data of the remainder polynomial until the maximum degree of the remainder polynomial does not become 0. 1) Similar to Equation 1, the division operation is repeated until the coefficient of the remainder of the polynomial to be divided is smaller than the degree of the polynomial.

[0044] As a result of the remainder polynomial of the coefficient data (R '(Z) and _{to) D i (i = 0,1,2,} ···,
m-2). When the degree of R '(Z) does not satisfy the condition shown in FIG. 25, the division is repeated with R (Z) as a polynomial to be divided and R' (Z) as a polynomial. At this time, the division circuit of FIG. 37 switches the selectors 82 and 83 in the same manner as described above to exchange the divisor polynomial and the polynomial to be deleted. Then, this operation is executed until the end condition of the Euclidean algorithm is satisfied.

FIGS. 38 and 39 are principle diagrams for explaining the operation of a conventional circuit for dividing a polynomial between Galois fields. In FIGS. 38 and 39, 90 is a register for storing coefficient data of a polynomial to be deleted, 91 is a register for storing coefficient data of a polynomial, 92 is a division circuit, 93 is a multiplication circuit, 94 is an addition circuit, and 95 is an input terminal. is there. As described above, the registers 90 and 91, the division circuit 92, the multiplication circuit 93, and the addition circuit 94 constitute a division circuit between polynomials on the Galois field. Figures 38 and 39
Is a diagram for explaining the operation of division between polynomials on a Galois field, so that exchange means and the like by the Euclidean algorithm are omitted. In addition, the order detection circuit is omitted for the sake of simplicity.

The circuit operation in the case of performing division between polynomials on a Galois field with the shift register configuration shown in FIGS. 38 and 39 will be described below. In construction of the divider circuit shown in FIG. 38, 39, the dividend ^{polynomial: A (Z) = Z 8} + Z 7 + Z 5 + Z 2 +1 divisor ^{polynomial: B (Z) = Z 6} + Z 3 + if Z ² performs a +1 division Will be described.

In this conventional example, each coefficient of the polynomial A (Z) to be removed is set in the register 90, and each coefficient data of the polynomial B (Z) is set in the register 91. The division between the polynomials in the Galois field is executed by sequentially shifting the contents of a register 90, which is arranged in a shift register and storing the coefficient data of the polynomial A (Z) to be divided, to the right side.
FIGS. 38 and 39 show the above polynomial A (Z) and the polynomial B
The contents of coefficient data in each register when dividing by (Z) are shown.

First, as shown in FIG. 38 (a), the coefficient of the polynomial A (Z) is set in the register 10, and the coefficient data of the polynomial B (Z) is set in the register 91. In this conventional example, it is assumed that the coefficient of a higher-order term is set from the rightmost register. In the figure, the numbers written in the registers indicate the coefficient data set in each register. From the state shown in FIG. 38 (a), the division circuit 92 and the multiplication circuit 93
When the coefficient of the polynomial to be shifted is shifted right by one while performing the operation for each coefficient by the adder circuit 94, the result is 14 (b).
It becomes as shown in. The division circuit 92 is configured to divide the highest-order coefficient on the polynomial side by the highest-order coefficient on the polynomial side.

The state of each coefficient is indicated by a number in the register.
That is, the remainder when the degree of the dividend polynomial is reduced by one by performing the division of the dividend polynomial by the divisor polynomial is automatically set in the register 90 for storing each coefficient data of the dividend polynomial, This becomes the dividend polynomial in the next division.
Similarly, when the second division is performed, the remainder is set in the register 90 as shown in FIG. Similarly, the result of the third division is shown in FIG. 39 (b). This division operation is repeated until the degree of the dividend polynomial becomes smaller than the degree of the division polynomial. In this conventional example, since the order difference between the polynomial A (Z) and the polynomial B (Z) is quadratic, the above division operation may be repeated three times.

The above processing is confirmed by hand calculation. The division of polynomials on Galois field by writing to Equation 3 (A (Z) /
(B (Z)) is shown.

[0051]

(Equation 3)

The remainder at each stage is shown in FIG.
(b), which corresponds to the state of FIGS. 39 (a) and (b).
At this time, the data stored in the register 90 stores the coefficient data of the remainder polynomial obtained by dividing the polynomial to be divided by the polynomial. Therefore, the division between the polynomials on the Galois field can be performed for each polynomial by using a division circuit having a shift register configuration as shown in FIGS.

The operation of the Euclidean operation division circuit of the error correction apparatus for decoding a Reed-Solomon code in accordance with the Euclidean algorithm shown in FIG. 25 will be described below with reference to FIG. In this conventional example, a case will be described in which a Reed-Solomon code with a minimum Hamming distance of 17 used for an optical disk or the like is decoded. Now, the syndrome polynomial S generated from the reproduction signal (Z) S (Z) = S 15 Z 15 + S 14 Z 14 + S 13 Z 13 + ··· S 1
And Z + S _0.

First, when the Euclidean operation is started, first, based on the Euclidean operation start signal output from the Euclidean operation control circuit 89, the register 81a stores the initial value of the subject polynomial Z ^2t (in this conventional example, the minimum distance is Since the code is 17, the coefficient of Z ¹⁶ ) is stored and the register
81b stores coefficient data of a syndrome polynomial S (Z), which is a divisor polynomial. In addition, the counters of the order detection circuits 87 and 88 are set to 16 and 15, which are the initial values of the orders, respectively. The counters in the order detection circuits 87 and 88 are configured such that the count value decreases by one each time the registers 81a and 81b storing the coefficient data of the polynomial to be deleted are shifted once.

In the conventional example, higher-order coefficient data is stored in a register arranged on the right side. At the same time, a syndrome polynomial, which is a divisor polynomial, is determined by the order detection circuit 88 to determine whether the coefficient data of the highest order is zero. In the Euclidean arithmetic control circuit 89, the order detection circuit 88
If the value of the coefficient data of the maximum order of the divisor polynomial (syndrome polynomial) detected in step is 0, the contents of the register 81b storing the coefficient data of the divisor polynomial are shifted until the data of the maximum order is no longer 0. Repeat the operation.
At that time, the count value of the order counter in the order detection circuit 88 is reduced. When this operation ends, the selector 82
Is controlled to select the output of the register 81a, and the selector 83 is controlled to select the output of the register 81b.

The register 81a storing the coefficient data of the polynomial to be removed is added to the adder circuit when a clock is input.
The output of the register 86 is latched, and the register 81b storing the coefficient data of the divisor polynomial is configured to hold the coefficient data. Although a specific control circuit is omitted in FIG. 37, the clocks 1 and 2 input to the registers 81a and 81b are not supplied only to the registers in which the coefficient data on the divisor side is stored. The configuration is such that coefficient data is held in a register. Alternatively, a selector may be provided before the registers 81a and 81b so that the output of the adder circuit 86 is selected for the register in which the dividend coefficient is stored, and the selector is provided for the register in which the divisor coefficient is stored. It can also be realized by a configuration that latches its own output. Note that each operation circuit (the division circuit 84, the multiplication circuit 85, and the addition circuit 86) shown in the figure performs each operation defined on the Galois field.

The circuit operation of the division circuit in the conventional Euclidean operation circuit will be described below with reference to FIGS. Figure
This shows a state in which the initial value Z ¹⁶ is set in the register 81a as the polynomial to be removed in 40 (a), and the syndrome polynomial S (Z) is set in the register 81b as the polynomial to be removed. The numbers and symbols described in the registers indicate coefficient data stored in the registers. In this conventional example, it is assumed that the highest order coefficient of the syndrome polynomial is not 0 for the sake of simplicity. Also, the coefficient data of the higher order of each polynomial stored in the register is arranged at the right end. In this figure, to explain the operation, the output of each register 81a, 81b is connected to a selector 82,
Division circuit 84, multiplication circuit 85 and addition circuit selected by 83
Connected directly to 86.

The division circuits shown in FIGS. 40 and 41 have the same configuration as the division circuits shown in FIGS. 38 and 39, and shift operation is performed until the order of the remainder of the polynomial to be divided becomes smaller than the order of the polynomial. Is performed by repeating. The end of division is determined by the Euclidean arithmetic control circuit 89 based on the order information output from the order detection circuits 87 and 88. Figure 40
(b) shows the state of the coefficient data stored in each of the registers 81a and 81b when the above division is completed. Incidentally, H ₁₄ to H ₀ stored in the register 81a is a coefficient data of the remainder polynomial.

Next, in the Euclidean arithmetic control circuit 89,
Based on the degree of the remainder polynomial output from the degree detection circuit 87 (or 88), the Euclidean operation is terminated if the order of the remainder satisfies the Euclidean operation termination condition (the order is 7 or less in the conventional example). If the termination condition is not satisfied, the calculation is executed with the polynomial that was the divisor polynomial in the previous operation as the polynomial to be removed and the remainder polynomial as the divisor polynomial. At this time, the division unit circuit (core circuit) in the Euclidean arithmetic circuit shown in FIG. 37 determines whether the maximum degree of the divisor polynomial (remainder polynomial) is 0, and if it is 0, the divisor polynomial (remainder polynomial). After the contents of the register 81a are shifted until the maximum order of the register 81 is no longer 0, the selection outputs of the selectors 82 and 83 are switched so that the selector 82 selects the output of the register 81b and the selector 83 selects the output of the register 81a. Outputs control signal.

FIG. 41A shows the above connection state. As shown in the figure, the selectors 82 and 83 switch the connection to each arithmetic circuit, thereby exchanging the polynomial to be deleted and the polynomial. (Note that the circuit configuration is the same as that of the division circuits shown in FIGS. 38 and 39.) The division is performed until the degree of the remainder of the polynomial is smaller than the degree of the polynomial, as in the above example. The division is performed by repeating the shift operation while calculating the contents of the register storing the polynomial coefficient data. FIG. 41B shows the state of the coefficient data stored in each of the registers 81a and 81b when the above division is completed. Note that I _{13 to} I ₀ stored in the register 81b are used.
Is the coefficient data of the remainder polynomial.

Then, the degree of the remainder polynomial is determined, and if the predetermined condition is not satisfied, the connections of the selectors 82 and 83 are switched to perform the division operation based on the Euclidean algorithm again. This division operation is repeated until the degree of the remainder polynomial becomes 7 or less. Thus, when decoding a Reed-Solomon code, division between polynomials on a Galois field based on the Euclidean algorithm can be performed for each polynomial, and the error correction processing speed can be improved.

The division unit circuit (core circuit) between the polynomials on the Galois field in the Euclidean operation circuit of the conventional error correction device is configured as described above to speed up the Euclidean operation, but performs the Euclidean operation. In order to exchange polynomials, the output of each register is connected to a selector. For example, the minimum Hamming distance employed as an error correction code of an optical disc shown in the above-described conventional example is
When decoding 17 codes, a selector is required for each register, and control of the selector is also required. For this reason, the circuit scale becomes unnecessarily large, and a selector control circuit and a control signal bus are required to control these selectors. That is, JP-A-3-720
The division circuit (core circuit) of the polynomial on the Galois field in the Euclidean operation process introduced in Japanese Patent Publication No. 27 can perform the division of the above polynomial at high speed, but the circuit scale becomes unnecessarily large, and There was a problem that also became complicated.

The present invention has been made in view of such circumstances, and one object of the present invention is to provide an error correction device capable of operating at high speed.

Another object of the present invention is to provide an error correction device capable of high-speed operation without increasing the circuit scale.

It is still another object of the present invention to provide an error correction device that does not require unnecessary control.

[0066]

An error correction apparatus according to a first aspect of the present invention is an error correction apparatus for performing error correction using an error correction code that is a linear code added to an input signal, the error correction apparatus comprising: A syndrome generating means for generating a syndrome from a signal, and an error location polynomial σ (z) and an error numerical polynomial ω based on the generated syndrome.
Error position / numerical polynomial calculating means for calculating (z), error position calculating means for calculating an error position based on the calculated error position polynomial σ (z), and calculated error numerical polynomial ω
(Z) and error correction means for performing error correction of erroneous data stored in the RAM based on the error position information.
The three processing operations of the error position / numerical polynomial calculation means and the error position calculation means are performed in parallel.

The error correction device according to the second invention of the present application is the error correction device according to the first invention, wherein the clock for driving the syndrome generation means and the error position calculation means has a higher frequency than the clock for driving the error position / numerical polynomial calculation means. Clock.

The error correction device according to the third invention of the present application is the error correction device according to the first invention, wherein the number of decoding steps of the error position / numerical polynomial arithmetic means whose circuit scale is substantially determined by the number of steps at the time of decoding is determined by the syndrome generation means and The number of decoding steps of the error position calculating means is increased so as to be substantially equal to the number of decoding steps.

The error correction device according to the fourth invention of the present application
When error correction is performed on the data in the RAM by the error correction means, at least two or more erroneous data based on the error position information output from the error position calculation means are continuously read from the RAM.
And then read the error-corrected data
The data is rewritten with erroneous data in the AM, and this operation is repeated until all the data whose error positions have been detected are corrected.

The error correcting apparatus according to the fifth invention of the present application divides a predetermined polynomial to be divided by a polynomial, further divides the remainder as a polynomial, and divides the polynomial as a polynomial to be divided to obtain a polynomial of the remainder. An error correction device that performs an error correction process using a Reed-Solomon code including a process of Euclidean mutual repetition that repeats the above operation until an order satisfies a certain condition, and stores each coefficient data of a polynomial to be deleted and a polynomial to be deleted. The registers are arranged in the form of a shift register, and a division circuit that divides the coefficients of the maximum degree of the two polynomials with each other, and multiplies the coefficient data of the polynomial set on the divisor side of the division circuit by the output of the division circuit Multiplying circuit,
An addition circuit for adding the output of the multiplication circuit and the coefficient data of the polynomial set on the dividend side of the division circuit is arranged, and the coefficient data of the dividend polynomial is stored when performing the division on the Galois field. By sequentially shifting the contents of the register, division based on the Euclidean mutual division process is performed.

The error correction device according to the sixth invention of the present application is configured such that, in the fifth invention, the multiplication circuit is arranged in a group of registers for setting an initial value Z ^2t in the Euclidean mutual division process.

The error correction device according to the seventh aspect of the present invention is the error correction device according to the fifth or sixth aspect, wherein in the division circuit, when the coefficient of the maximum degree of the polynomial input as the divisor is 0, the output of the division circuit is output. It is configured to output as 1.

The error correction device according to the eighth invention of the present application is the error correction device according to the fifth, sixth, or seventh invention, which calculates the error position polynomial σ (Z) using the division result output from the division circuit. The calculation method is switched between a case where coefficient data of the highest degree of the dividend polynomial input to the circuit is treated as a divisor and a case where the coefficient data is treated as a dividend.

The error correction device according to the ninth invention of the present application is the error correction device according to the fifth, seventh, or eighth invention, wherein the first selection means selects the output of the division circuit and the error position information; A second selecting means for selecting an output of the storage means for storing the coefficient of the polynomial of the division circuit and an output of the storage means for storing coefficient data of the polynomial on the dividend side of the division circuit; Selecting means for selecting the coefficient of the polynomial of the formula (1) and the coefficient of the polynomial on the divisor side of the divider circuit having a higher first order, and multiplying the output of the first selecting means and the output of the third selecting means. Multiplying means, and adding means for adding the output of the multiplying means and the output of the second selecting means. When calculating the modified syndrome polynomial at the time of erasure correction, the first, second and third selections are made. Error position information and divisor of division circuit by means Constructed as coefficient data and 1 Tsugiji polynomial selects the coefficients of the high polynomial.

[0075]

The error correcting apparatus according to the first aspect of the present invention operates, when correcting an error in a reproduced or received signal, three processing means, a syndrome generating means, an error position / numerical polynomial calculating means, and an error position calculating means in parallel. Figure
The decoding time when performing error correction on one error correction block shown in 33 can be reduced to half or less. In addition, since the data is always accessed between the error correction device and the RAM, which is a bottleneck for speeding up during decoding, an error correction device capable of decoding in the shortest decoding time can be obtained. (This is because, as described above, when decoding an error correction code in the product code format as shown in FIG. 32, first, the received data is written in the RAM, and C1 and C2
Error correction using codes is performed. At this time, in the RAM, it is necessary to read data for generating a syndrome, to read data in which an error has been detected for error correction, and to write data having been subjected to error correction. When considering the speed-up of the error correction device, data access between the RAM and the error correction device has become a serious problem. )

The error correction device according to the second aspect of the present invention increases the clock frequency of the syndrome generation means and the error position calculation means, which can achieve relatively high speed, as compared with the clock frequency of the error position / numerical polynomial operation means. The decoding time required to decode one error correction block can be reduced, and the processing speed can be increased.

The error correction device according to the third invention is arranged such that the number of decoding steps of the error position / numerical polynomial operation means is substantially equal to the number of decoding steps of the syndrome generation means or error position calculation means and the number of decoding steps of the error correction circuit. By increasing, the circuit size of the error position / numerical polynomial operation means is reduced, and the number of decoding steps of the error position / numerical polynomial operation means increases, but the number of decoding steps of the error correction device does not change. Higher speed can be realized.

The error correction device according to the fourth aspect of the present invention controls the processing operation of the error correction circuit by sequentially reading erroneous data in the RAM based on the error position information and then writing the error-corrected data to the RAM. When performing error correction for one symbol, data reading from the RAM, error correction, R
The operation of writing data to the AM and taking at least three steps is replaced by the operation of reading data from the RAM, correcting errors, and writing data to the RAM in parallel.
This can be performed in steps, and the speed of the error correction device can be increased. In particular, when the access time to the RAM becomes a problem, the access time to the RAM is reduced, so that the speed can be increased.

The error correcting apparatus according to the fifth aspect of the present invention does not have a selector for exchanging coefficient data of each polynomial when performing division between polynomials on the Galois field in the Euclidean mutual division process. By performing the division, the circuit scale can be reduced, and the selector control is not required, thereby simplifying the circuit.

In the error correction device according to the sixth aspect of the present invention, the multiplication circuit is arranged in a group of registers for setting the initial value Z ^2t in the Euclidean mutual division process to perform the division operation. It is possible to reduce the circuit scale by reducing the number.

The error correction device according to the seventh aspect of the present invention is configured such that when a coefficient of the maximum degree of a polynomial input as a divisor is 0, the output of the division circuit arranged in the division circuit when performing the Euclidean operation is 0. Therefore, even if the maximum degree of the polynomial to be divided or the polynomial in the Euclidean arithmetic control circuit is 0, the polynomials on the Galois field in the Euclidean algorithm are not increased without increasing the circuit scale. Perform operations.

When calculating the error locator polynomial σ (Z) using the output of the division circuit, the error correction device of the eighth invention treats the coefficient data of the maximum degree of the dividend polynomial input to the division circuit as a divisor. Since the calculation method is switched between the case where it is used and the case where it is treated as the dividend, the error locator polynomial is accurately calculated and the number of decoding steps can be reduced.

The error correction apparatus according to the ninth aspect of the present invention can be configured by simply adding a selector circuit to calculate the corrected syndrome polynomial to be calculated at the time of performing erasure correction. it can.

[0084]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments.

First Embodiment FIG. 1 shows a block diagram of an error correction apparatus according to a first embodiment of the present invention. In the figure, 1, 2, and 20 to 22 are the same as those shown in FIGS. 40 is Euclidean arithmetic circuit 20
A register 41 stores the coefficient data of the error locator polynomial and the error numerical polynomial output from the controller 41. The register 41 controls the syndrome generation circuit 2, the Euclidean operation circuit 20, the register 40, the Chien search circuit 21, and the error correction circuit 22,
An error correction device control circuit that also performs write and read control of the RAM 1. The circuit configuration of the syndrome generation circuit 2, the polynomial division circuit on the Galois field of the Euclidean arithmetic circuit 20, and the circuit configuration of the Chien search circuit 21 are shown in FIGS.
The configuration is the same as that shown in FIG. 30 and the description is omitted.

Next, the operation of the error correction device according to the first embodiment of the present invention will be described. In this embodiment, a case where the C1 code in the recording direction at the minimum distance 17 shown in FIG. 33 is decoded as in the conventional example will be described. When error correction processing is started, reproduced or received data stored in the RAM 1 including an error generated during reproduction or reception is read from the RAM 1 in units of C1 blocks (unit information blocks). Reading of the reproduction data from the RAM 1 is performed based on a reading address generated in synchronization with a system start signal output from the error correction device control circuit 41 and a reading control signal. The data read from the RAM 1 is output to the syndrome generation circuit 2. The syndrome generation circuit 2 sets 0 to each register 10 arranged in a shift register format based on the system start signal output from the error correction device control circuit 41. Then, the data read from the RAM 1 is shifted while performing the sequential operation in the same manner as in the conventional example, thereby executing the division operation. Syndrome generation requires 241 steps equivalent to the code length as in the conventional example. The syndrome generated by the syndrome generation circuit 2 is output to the Euclidean arithmetic circuit 20 together with a syndrome generation end signal. Syndrome generation end signal is an error correction device control circuit
Also output to 41. The Euclidean arithmetic circuit 20 sets an initial value of the arithmetic processing in the Euclidean arithmetic circuit 20 based on the syndrome generation end signal output from the syndrome generation circuit 2. If the operation of the Euclidean operation circuit 20 is not completed, the initial value of the operation process is set at the same time when the Euclidean operation is completed.

On the other hand, the Euclidean arithmetic circuit 20 starts Euclidean arithmetic based on an initial value set in advance at the end of syndrome generation based on a system start signal output from the error correction device control circuit 41. The Euclidean arithmetic circuit 20 calculates the error position polynomial σ (z) and the error numerical polynomial ω (z) by repeatedly performing the division of the polynomial on the Galois field in accordance with the algorithm shown in FIG. The circuit operation of the Euclidean arithmetic circuit 20 will be described with reference to FIG. When the syndrome generation end signal is input, an initial value is set in each of the registers 52a and 52b. Specifically, Z in the upper register group 52a
^2t is set, and the coefficient data of the syndrome polynomial calculated by the syndrome generation circuit ² is set in the lower register group 52b. The set data shifts the data on the dividend side (the first group of upper registers 52a in which the data of ^Z2t is set) based on the system start signal, thereby executing the polynomial division on the Galois field. The division is repeated until the degree of the polynomial on the dividend side becomes smaller than the degree of the polynomial on the divisor side. The division operation is specifically described as follows. In FIG. 29, a selector 53 connected to a group of registers 52 on the dividend side includes an adder 55.
Is connected to select the output of the divisor side register 52
The selector 53 connected to the group is configured to select the output of the register 52. As a result, the data on the divisor side is maintained in the register 52, and the data in the register 52 on the dividend side is shifted and division is executed.

As a result of the division, the remainder of the division is stored in the register group on the dividend side. Next, division is performed using the polynomial stored in the divisor register group as a dividend and the remainder of the division result as a divisor. This switches the divisor and the dividend by switching the output of the selector 53. This operation is repeated until the end condition of the Euclidean algorithm shown in FIG. 25 is satisfied.
When the above condition is satisfied, the Euclidean arithmetic circuit 20 calculates each coefficient data of the error locator polynomial and the error numerical polynomial. Each calculated coefficient data is temporarily stored in the register 40. Note that the Euclidean operation circuit 20 outputs a Euclidean operation end signal to the error correction device control circuit 41 when the Euclidean operation is completed.

Similarly, the Chien search circuit 21 sets the coefficient data of the error locator polynomial stored in the register 40 in the feedback register 31 based on the system start signal output from the error correction device control circuit 41, The count value of the counter 35 is set to 0. And
As in the conventional example, the output of the feedback register 31 is multiplied by a multiplier preset in the multiplier 32 and latched by the feedback register 31 again. The coefficient counter 35 counts the number of times of feedback of the feedback register 31.

The output of the feedback register 31 is added by the adding circuit 33. The determination circuit 34 determines whether the addition result is 0. If the addition result is 0, the value of the coefficient counter 35 is stored in a register.
Write to 36. This count value corresponds to the error position as in the conventional example. In the Chien search, the feedback register 31 is operated 241 times corresponding to the code length to calculate an error position. When the chain search ends, a chain search end signal is output to the error correction device control circuit 41. The error correction device control circuit 41 outputs an error correction start signal to the error correction circuit 22 based on the Chien search end signal, the Euclidean operation end signal, and the syndrome generation end signal.

The error correction device control circuit 41 outputs an error correction start signal and simultaneously reads out erroneous data stored in the RAM 1 based on error position information output from the Chien search circuit 21. And outputs a read address and a read control signal. For example, in the case of eight error correction, eight pieces of erroneous information corresponding to eight pieces of error position information are read from the RAM 1. On the other hand, the error correction circuit 22 starts error correction based on the input error correction start signal. First, in the error correction circuit 22, the error numerical polynomial ω output from the Euclidean arithmetic circuit 20
(Z) and an error value is obtained from the error position information output from the Chien search circuit 21. The erroneous data read from the RAM 1 is added to an error value and error correction is sequentially performed. When the reading of the erroneous information from the RAM 1 ends, the error-corrected data is sequentially rewritten with the erroneous data in the RAM 1. FIG. 9 shows a timing chart of the error correction circuit 22.

Next, the signal processing timing of each circuit unit when error correction is performed using the first embodiment will be described with reference to FIG. FIG. 2 shows the output timing of various control signals output from the error correction device control circuit 41, the operation timing of each circuit, and the data access state of the RAM 1. When the error correction is started, the error correction device control circuit 41 outputs a system start signal to the syndrome generation circuit 2, the Euclidean operation circuit 20, and the Chien search circuit 21 and reads the reproduction data stored in the RAM 1. It outputs a read address and a control signal.

The syndrome generation circuit 2 sets the value in the register 10 to 0 based on the system start signal and performs a predetermined operation (division) on the data read from the RAM 1. Note that, as described above, when generating a syndrome, the code length is equivalent to the code length until the operation is completed.
It takes 241 steps. This calculation time is shown in the SY section in FIG.

When the syndrome generation ends, a syndrome generation end signal is output together with the syndrome data generated by the syndrome generation circuit 2. The Euclidean operation circuit 20 sets an initial value for the Euclidean operation based on the syndrome generation end signal. If the operation of the Euclidean arithmetic circuit 20 is not completed, an initial value is set as soon as the Euclidean arithmetic is completed.

The Euclidean arithmetic circuit 20 divides the polynomial on GF (2 ⁸ ) based on the system start signal in the above-described manner, and calculates an error position polynomial σ (z) and an error numerical polynomial ω (z). When the Euclidean arithmetic circuit 20 decodes the Reed-Solomon code of the minimum distance 17 shown in FIG. 33, about 120 steps are required as in the conventional example. This calculation time is shown in the EU section in FIG.

The error locator polynomial σ (z) and the error numerical polynomial ω (z) calculated by the Euclidean arithmetic circuit 20
Are temporarily stored in the register 40. In addition,
When the Euclidean operation is completed, the Euclidean operation circuit 20
Thus, a Euclidean operation end signal is output.

In the chain search circuit 21, 0 is set in the coefficient counter 35 based on the system start signal, and each coefficient data of the error locator polynomial calculated by the Euclidean arithmetic circuit 20 is set in each feedback register 31.
Then, the output of the feedback register 31 is multiplied by a multiplier preset in the multiplication circuit 32, and again the feedback register 31
Latched. The coefficient counter 35 counts the number of feedbacks of the feedback counter 31. In the adder circuit 33, each feedback register 31
Add the outputs of The determination circuit 34 determines whether the addition result is 0, and if it is 0, writes the count value of the coefficient counter 35 to the register 36. As described above, the Chien search circuit 21 requires a maximum number of steps of the code length, that is, 241 steps, to calculate the error position. This calculation time is shown in the CH section in FIG.

When the chain search ends, a chain search end signal is output from the chain search circuit 21. The error correction device control circuit 41 outputs an error correction start signal based on the Chien search end signal, the Euclidean operation end signal, and the syndrome generation end signal. The error correction circuit 22 calculates an error value using the error value polynomial ω (z) based on the error correction start signal and the error position information output from the Chien search circuit 21. Then, error correction is performed by adding an error value to the data calculated for the error position read from the RAM 1. The error-corrected data is written to the RAM 1 at the same time when the reading of the erroneous data from the RAM 1 ends. Figure 9 shows the error correction circuit
22 shows a timing chart. In this embodiment, 16 steps are required to correct an error of 8 symbols. In addition,
A detailed description of the timing chart of the error correction circuit shown in FIG. 9 will be described later.

In the error correction device control circuit 41, RAM1,
The above operations of the syndrome generation circuit 2, the Euclidean operation circuit 20, the register 40, the Chien search circuit 21, and the error correction circuit 22 are controlled. At that time, the syndrome generation circuit 2
In order to manage the parallel operation of the three circuits of the Euclidean arithmetic circuit 20 and the Chien search circuit 21, the error correction device control circuit 41 sets an operation flag of each circuit by a system start signal, and outputs the operation flag from each circuit. An operation flag generation circuit for resetting the operation flag based on the operation end signal is provided therein, and each circuit is controlled by the state of the flag. Specifically, a signal for controlling the address of the RAM 1, transferring the data calculated by each circuit, or setting the initial value of each circuit is output to each circuit according to the state of the operation flag. I do. This operation flag is also output to each circuit.

The error correction start signal is output at the same time when the access between the syndrome generation circuit 2 and the RAM 1 and the calculation of the error position in the Chien search circuit 21 are completed. At the same time, based on the error position information calculated by the chain search circuit 21, a read address and a read control signal for reading erroneous data from the RAM 1 are generated.

As shown in this embodiment, in the error correction device, the syndrome generation circuit 2, the Euclidean operation circuit 20
By operating the three circuits of the chain search circuit 21 in parallel, the number of steps for decoding one error correction block can be 257 steps as shown in FIG. It is possible to increase the decoding speed by a factor of (626/257). Also, the decoding speed can be increased to 1.5 times (386/257) as compared with the case where the syndrome generation circuit 2 and the error correction operation circuit 3 are operated in parallel. Therefore, the speed of the circuit can be increased without arranging the error correction devices in parallel, and the circuit scale can be significantly reduced as compared with the case where the error correction devices are arranged in parallel.

In the error correction device that performs parallel processing as in this embodiment, the data access time of the RAM 1 determines the operation speed of the error correction device. In particular, when decoding the error correction code in the product code format shown in FIG. 32, the data including the reproduced error is temporarily stored in the RAM 1 and then subjected to error correction. Generally, decoding of an error correction code in a product code format is performed by correcting an error in a recording direction by a C1 code and then correcting an error in a vertical direction by a C2 code.
For data for which an error could not be corrected by one code,
Error correction is performed using two codes. (In the case of performing error correction using the C1 code added in the recording direction, it is possible to generate a syndrome directly from reproduced data and perform error correction without temporarily storing data in the RAM 1, When performing the correction, it is necessary to read out the data of the error correction block shown in Fig. 32 in the vertical direction.
The error correction of the reproduced data by the C2 code is performed on the data once stored in the RAM 1. )

The reproduced data once stored in the RAM 1 is stored in the RAM 1 for error correction using an error correction code.
Is read out. The data read from the RAM 1 is subjected to syndrome generation, error position calculation, and error value calculation by the error correction device as described above. And
The data at the address corresponding to the calculated error position is RA
It is read from M1, added to the error value, and subjected to error correction. The error-corrected data is written to the RAM 1 at an address corresponding to the error position.

The RAM 1 used at this time is an SRAM or DRAM which can randomly access data at high speed.
Are used. Generally, in the above-described RAM, a data input / output I / O port and a write / read address port are not provided separately. Therefore, in order to realize the highest speed processing in the error correction device, the syndrome generation circuit 2 and the error correction circuit 22 having data access to the RAM 1 are operated independently of each other,
The Euclidean operation circuit 20 and the Chien search circuit 21 that do not have access to the RAM 1 may be operated in parallel with the syndrome generation circuit 2. That is, the syndrome generation circuit 2
In addition, while the error correction circuit 22 is operating, the error correction device may be operated so that the operations of the Euclidean operation circuit 20 and the Chien search circuit 21 are completed. By operating the error correction device in this manner, the RAM 1 is always in an access state with the syndrome generation circuit 2 or the error correction circuit 22 when the error correction operation is started, and can perform error correction with a minimum decoding time. . FIG. 2 shows a RAM access signal indicating the operation state of the RAM 1 in this embodiment. Therefore, the error correction device having the configuration of the first embodiment (that is, the configuration in which the three circuits of the syndrome generation circuit 2, the Euclidean operation circuit 20, and the Chien search circuit 21 are operated in parallel) has the highest decoding speed. Become.

Second Embodiment Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram of an error correction device according to a second embodiment. In the figure, 1, 2, 20-22,
Reference numerals 40 and 41 are the same as those shown in the first embodiment, and a description thereof will be omitted. In the present embodiment, as shown in the figure, the syndrome generation circuit 2, Chien search circuit 21, and error correction circuit 22 are configured to be driven by the clock 1.
Further, the Euclidean arithmetic circuit 20 is configured to be driven by a clock 2 having a frequency different from the clock 1. The error correction device control circuit 41 uses the clock 1 and the clock 2 to store the RAM 1, the syndrome generation circuit 2,
It controls the Euclidean operation circuit 20, the register 40, the Chien search circuit 21, and the error correction circuit 22. Also, the circuit configuration of the syndrome generation circuit 2, the polynomial division circuit on the Galois field of the Euclidean operation circuit 20, and the circuit configuration of the Chien search circuit 21 are the same as those shown in FIGS. Omitted.

Next, the operation of the error correction device according to the second embodiment of the present invention will be described. In this embodiment, a case where the frequency of the clock 1 is controlled at twice the frequency of the clock 2 will be described. This is because, as shown in FIG. 27 and FIG. 30, the syndrome generation circuit 2 and the Chien search circuit 21 multiply the output of the register by a constant value on the Galois field,
Adder circuits are arranged in series or in parallel. On this occasion,
Up to 4 stages of EX-O between registers on hardware
It will pass through the R gate. On the other hand, on the Euclidean arithmetic circuit 20, although it depends on the hardware configuration, since it is composed of a multiplication circuit of variables and an adder, the EX-O
With about seven stages of R gates, data is latched in the next register through several selectors. Therefore, it is relatively easy to increase the speed of the syndrome generation circuit 2 and the Chien search circuit 21 as compared with the Euclidean arithmetic circuit 20. In addition,
Clock 2 frequency is above for clarity
It is assumed that the frequency is the same as the clock that drives the circuit in the first embodiment . Also, in the present embodiment, as in the first embodiment, FIG.
The case of decoding the C1 code in the recording direction at the minimum distance 17 shown in 33 will be described.

When the error correction processing is started, the reproduced or received data stored in the RAM 1 is read from the RAM 1 in units of C1 blocks (unit information blocks). The reading of data from the RAM 1 is performed based on a system start signal output from the error correction device control circuit 41 and a read address generated in synchronization with a clock 1 for driving the syndrome generation circuit 2 and a read control. This is performed based on a signal. The data read from the RAM 1 is output to the syndrome generation circuit 2.

The syndrome generation circuit 2 generates a syndrome in the same manner as in the first embodiment, but the operation at this time is the same as in the first embodiment, and a description thereof will be omitted. In generating the syndrome, the same as the first embodiment,
241 steps are required, but the syndrome generation circuit 2
Is driven by a clock having a frequency twice as high as that of the first embodiment, so that the generation of the syndrome is completed in half the time of the first embodiment. The Euclidean operation circuit 20 starts the Euclidean operation in synchronization with the clock 2 based on an initial value set in advance at the end of the syndrome operation based on the system start signal output from the error correction device control circuit 41. The operation of the Euclidean arithmetic circuit 20 is the same as in the first embodiment, and a description thereof will be omitted. Thereafter, as in the first embodiment, the Chien search circuit 21 calculates an error position. Since the clock for driving the Chien search circuit 21 is driven by a clock having a frequency twice as high as that of the first embodiment, the calculation of the error position can be performed in half the time of the first embodiment. finish. Thereafter, similarly to the first embodiment, an error value is obtained by the error correction circuit 22, error correction is sequentially performed, and the error-corrected data is sequentially rewritten with erroneous data in the RAM 1.

Next, FIG. 4 shows the signal processing timing of each circuit unit when decoding one line of data shown in FIG. 33 using the second embodiment. 4, the same parts as those in FIG. 2 are denoted by the same reference numerals.

In generating the syndrome, 241 steps corresponding to the code length are required until the operation is completed. However, in the generation of the syndrome, the frequency of the clock 1 is twice as large as that in the first embodiment. Time (SY part in FIG. 4) is halved (241/2)
Steps). Since the clock frequency of the Euclidean operation part is the same as that of the first embodiment, the operation time (EU part in FIG. 4) is the same as that of the first embodiment (about 120 steps). On the other hand, the frequency of the clock for driving the Chien search circuit 21 is the first as in the case of the syndrome generation.
Since the time is twice as long as that of the first embodiment, the operation time (CH part in FIG. 4) in the Chien search circuit 21 is half of the time of the first embodiment (about 241/2 steps). In the second embodiment, since the error correction circuit 22 is driven by the clock 1, the operation is completed in about half the processing time of the first embodiment (about eight steps).

In the second embodiment, the parallel operation of the three circuits of the syndrome generation circuit 2, the Euclidean operation circuit 20 and the Chien search circuit 21 is controlled by two systems of the clock 1 and the clock 2, and the syndrome generation circuit 2 and the frequency of the clock driving the Chien search circuit 21 is set to twice the frequency of the clock driving the Euclidean arithmetic circuit 20. Therefore, as shown in FIG. 4, the number of steps for decoding one error correction block is 128.
The number of steps can be increased to 5 steps, which is about 4.8 times (626 / 128.5) compared to the conventional error correction device. In addition, it is about three times (386/12) that the syndrome generation circuit 2 and the error correction operation circuit 3 are operated in parallel.
8.5) It is possible to increase the decoding speed. Therefore,
The speed of the circuit can be increased without arranging the error correction devices in parallel, and the circuit scale can be significantly reduced as compared with the case where the error correction devices are arranged in parallel.

Also, as in the first embodiment, in this embodiment,
The Euclidean arithmetic circuit 20 and the Chien search circuit 21 that do not have data access to the RAM 1 are operated in parallel with the syndrome generation circuit 2, and the Euclidean arithmetic circuit is operated while the syndrome generation circuit 2 and the error correction circuit 22 are operating.
Since operation is performed such that the operations of 20 and the Chien search circuit 21 are completed, error correction can be performed with a minimum decoding time. Further, in the error correction device of the present embodiment, the clock for driving the syndrome generation circuit 2 and the Chien search circuit 21 which can be relatively operated at a high frequency is twice as high as that of the first embodiment. The error correction operation per block can be performed in about half the decoding time as compared with the embodiment.

In the second embodiment, the frequency of clock 1 is set to twice the frequency of clock 2;
However, the present invention is not limited to this, and is, for example, an integral multiple such as three times or four times,
The same effect can be obtained by selecting a non-integer multiple such as 1.5 times or 3.2 times. Further, the syndrome generation circuit 2 and the Chien search circuit 21 are driven by a clock having the same frequency. However, the present invention is not limited thereto. The frequency of the clock for driving and the frequency of the clock for driving the Chien search circuit 21 may be different. Further, the clock 1 is used as a clock for driving the error correction circuit 22.
Alternatively, a clock of another frequency may be used.

Third embodiment. Next, a third embodiment will be described. The block configuration of the error correction device according to the third embodiment of the present invention is the same as that of the first embodiment (FIG. 1). FIG. 5 is a block diagram of a division circuit for performing division of a polynomial on a Galois field of the Euclidean arithmetic circuit 20 in the third embodiment.

In FIG. 5, reference numerals 50 and 51 are the same as those shown in FIG. Reference numerals 60, 65 and 66 denote registers, reference numerals 61 and 62 denote selectors, reference numeral 64 denotes an adder, and reference numeral 63 denotes a multiplication circuit. As described above, the registers 60, 65 and 66, the selector 61 and
Euclidean operation circuit with 62, adder 64, and multiplication circuit 63
20 are made up. It should be noted that the present embodiment is different from the conventional Euclidean operation circuit 20 shown in FIG.
In the division circuit of the Euclidean arithmetic circuit 20 shown in (1), one multiplication circuit connected to each register is connected to every two registers, thereby reducing the circuit scale. More specifically, although the number of selectors 62 and registers 66 is increased, for example, when decoding a Reed-Solomon code with a minimum distance of 17 as in the present embodiment, 16 multiplication circuits (400 × 16 = 6400 gates) are omitted. The number of registers 66 can be increased by 8 (8 × 56 = 448 gates) and 16 selectors 62 (24 × 16 = 384 gates)
The circuit scale of about 5500 gates can be reduced.

Next, the operation of the error correction device according to the third embodiment will be described. In the present embodiment, the case of decoding the C1 code in the recording direction at the minimum distance 17 shown in FIG. 33 as in the first embodiment will be described. In the third embodiment, the syndrome generation circuit 2, the Chien search circuit 21, and the error correction circuit 22
The operation of this embodiment is the same as that of the first embodiment, and the description thereof is omitted.
Only the operation of will be described in detail with reference to FIG.

When the syndrome generation end signal is input, initial values are set in the registers 60 and 65. Specifically, Z ^2t is set in the upper two columns of register groups 60a and 60b shown in FIG. 5, and the coefficients of the syndrome polynomial calculated by the syndrome generation circuit 2 are set in the lower two columns of register groups 65a and 65b. Set. Based on the system start signal, the set data shifts the data on the dividend side (the first two upper rows of registers 60 in which the data of Z ^2t is set) to execute the division of the polynomial on the Galois field. . The division is repeated until the degree of the polynomial on the dividend side becomes smaller than the degree of the polynomial on the divisor side.

The division operation is specifically described as follows. In FIG. 5, a selector 61 connected to a group of registers 60 on the dividend side is connected so as to select an output of the register 66, and a selector 61 connected to a group of registers 65 on the divisor side selects the output of the register 65. It is constituted so that.
As a result, the data on the divisor side is maintained in the register 65,
The data in the register 60 on the dividend side is shifted and division is performed.

At this time, the division circuit of the Euclidean arithmetic circuit 20 shown in the present embodiment performs the division by sequentially switching the selector 62 because one multiplication circuit 63 is arranged in two registers as shown in FIG. Execute. Specifically, while the data of one register on the dividend side is performing division, the other register holds the data so as to hold the data.
Control 61. FIG. 6 is a timing chart showing the operation of each register 60 on the dividend side, each register 65, register 66 on the divisor side, and the operation of the multiplication circuit 63. This timing chart is for the case where the dividend is stored in the register 60 and the divisor is stored in the register 65. Note that even if the divisor and the dividend are exchanged, the control timing (the calculation order or the number of steps) does not change. Control of each register and selector is executed according to the timing chart shown in FIG. As shown in the figure, in performing the division on the Galois field, the order of the dividend is reduced by two in four steps. (In the conventional example, the order of the dividend is reduced by two in two steps.) Therefore, in this embodiment, the number of decoding steps in the Euclidean arithmetic circuit 20 is about 240 steps.

As a result of the division, the remainder of the division is stored in the register group on the dividend side. Next, division is performed using the polynomial stored in the divisor register group as a dividend and the remainder of the division result as a divisor. This switches the divisor and the dividend by switching the control of the selector group 61. This operation is repeated until the end condition of the Euclidean algorithm shown in FIG. 25 is satisfied. When the above conditions are satisfied, the Euclidean arithmetic circuit 20
Calculates the error position polynomial and the coefficient data of the error numerical polynomial. Each calculated coefficient data is temporarily stored in a register.
Stored in 40. Note that the Euclidean operation circuit 20 outputs a Euclidean operation end signal to the error correction device control circuit 41 when the Euclidean operation is completed.

Next, FIG. 7 shows the signal processing timing of each circuit unit when decoding one line of data shown in FIG. 33 using the third embodiment. 7, the same parts as those in FIG. 2 are denoted by the same reference numerals. In the present embodiment, when decoding the Reed-Solomon code of the minimum distance 17 shown in FIG.
Approximately 240 steps are required for the calculation time at 20 (EU part in FIG. 7). Other parts are the same as in the first embodiment.

In this embodiment, as in the first embodiment, the decoding speed can be increased as compared with the conventional example. In addition, the number of decoding steps of the Euclidean arithmetic circuit 20 is increased to about the number of steps necessary for operating the syndrome generation circuit 2 and the error correction circuit 22 (at this time, the number of steps required for syndrome generation and error correction is reduced). By determining the number of steps so that they are substantially equal), the circuit size can be reduced without delaying the decoding time of the error correction device. In this embodiment, the circuit scale of about 5500 gates can be reduced as compared with the conventional example. Therefore, the speed of the circuit can be increased without arranging the error correction devices in parallel, and the circuit scale can be significantly reduced as compared with the case where the error correction devices are arranged in parallel.

In this embodiment, the Euclidean arithmetic circuit
The circuit size of 20 was determined so that the maximum number of decoding steps was almost the same as the chain search or syndrome generation, but this is not a limitation.If there is enough decoding time, the circuit size can be further reduced. Needless to say, it may be used for In addition, by operating the Euclidean arithmetic circuit 20 and the Chien search circuit 21 that do not access data with the RAM 1 in parallel with the syndrome generation circuit 2, error correction can be performed with a minimum decoding time. This is the same as the second embodiment.

Fourth Embodiment Next, a fourth embodiment will be described. The fourth embodiment relates to a modification of the division circuit for performing the polynomial division on the Galois field of the Euclidean operation circuit 20 in the error correction device according to the third embodiment. FIG. 8 shows a Euclidean arithmetic circuit 20 according to the fourth embodiment.
FIG. 2 is a block diagram showing a division circuit portion of FIG. The basic configuration of the present embodiment is as shown in FIG.

In FIG. 8, reference numerals 50 and 51 are the same as those shown in FIG. 70 and 71 are registers, 72, 73 and 74 are selectors, 75 is a multiplication circuit, 76 is an adder, 77 is a register, and 78 is a division circuit. As described above, the registers 70 and 71, the selectors 72, 73 and 74, the multiplication circuit 75, and the adder 7
6, the register 77, and the division circuit 78 constitute a polynomial division circuit on the Galois field of the Euclidean operation circuit 20. In this embodiment, the coefficient of the maximum order of the dividend is
The division is performed by multiplying the result of the division by the coefficient of the maximum order of the divisor by the coefficient of each divisor. The divider circuit of the Euclidean arithmetic circuit 20 shown in FIG.
After selecting the divisor and the divisor, multiplication of the polynomial on the Galois field is performed by multiplying each coefficient data on the divisor side by the output of the above-described division circuit 78 and adding each coefficient data on the dividend side.

Therefore, in the fourth embodiment, all the multiplier circuits connected to the dividend side are deleted, and one multiplier circuit connected to the register on the divisor side is connected for every two registers. As with the third embodiment, the circuit scale is reduced. Specifically, compared to the third embodiment,
Although the number of selectors 74 and division circuits 78 are increased, the minimum distance 17
When decoding the Reed-Solomon code of
(400 × 7 = 2800 gates) can be omitted, and the number of selectors 74 to be increased is 16 (24 × 16 = 384 gates) and the division circuit 78 is one (about 2000 gates), and the circuit scale is about 400 gates. Reduction can be achieved.

Next, the operation of the error correction device according to the fourth embodiment of the present invention will be described. In the present embodiment, the case of decoding the C1 code in the recording direction at the minimum distance 17 shown in FIG. 33 as in the first embodiment will be described. The operations of the syndrome generation circuit 2, the Chien search circuit 21, and the error correction circuit 22 in the fourth embodiment are the same as those in the first embodiment, and therefore the description thereof will be omitted, and the Euclidean arithmetic circuit which is a feature of this embodiment will be described. Only the operation 20 will be described in detail with reference to FIG.

When the syndrome generation end signal is input, the initial values are set in the registers 70 and 71. Specifically, Z ^2t is set in the register groups 70a and 70b in the upper two columns shown in FIG. 8, and the coefficients of the syndrome polynomial calculated by the syndrome generation circuit 2 are set in the register groups 71a and 71b in the lower two columns. Set. Set data is dividend side based on the system start signal (first Z register group 70 of the upper two rows of data is a set of ^2t) performing polynomial division over a Galois field by shifts the data of the . The division is repeated until the degree of the polynomial on the dividend side becomes smaller than the degree of the polynomial on the divisor side.

The division operation is specifically described as follows. In FIG. 8, the selector 72a connected to the group of registers 70 on the dividend side is connected to select the output of the register 77, and the selector 72b connected to the group of registers 71 on the divisor side selects the output of the register 71. It is constituted so that. As a result, the data on the divisor side is maintained in the register 71, the data in the register 70 on the dividend side is sequentially shifted, and the division is executed.

At this time, the division circuit of the Euclidean arithmetic circuit 20 shown in this embodiment multiplies each coefficient of the divisor by the output data of the division circuit 78. As shown in the figure, the multiplication circuit 75 has one register for every two registers. The division is performed by sequentially switching the selectors 73 since the two are arranged. In particular,
While the data of one register on the dividend side is performing division, the other register controls the selector 72 so as to hold the data. The control of the entire circuit is performed in the same manner as in the third embodiment (see FIG. 6). This timing chart is for the case where the dividend is stored in the register 70 and the divisor is stored in the register 71.

In the fourth embodiment, the circuit scale can be reduced without delaying the decoding time of the error correction device.
Other operations, effects, and the like in this embodiment are the same as those in the third embodiment described above, and a description thereof will be omitted.

In the third embodiment (fourth embodiment), selectors 61 (72) are provided in all stages of registers 60, 65 (70, 71) in order to hold the data in registers 60, 65 (70, 71). ) Is provided, but the present invention is not limited to this. For example, the same effect can be obtained by performing processing such as stopping the clock input to the registers 60, 65 (70, 71) for holding data. Further, a first-stage multiplication circuit 63 connected to the output of the input terminal 50
It is needless to say that (75) and the register 66 (77) can be omitted because the data input from the input terminal 50 is 0. In addition, the circuit configuration in the case where the number of decoding steps of the polynomial on the Galois field of the Euclidean arithmetic circuit 20 is doubled has been described. However, the present invention is not limited to this, and when operating the syndrome generation circuit 2 and the error correction circuit 22, As long as the number of decoding steps is substantially equal to the required number of steps, a circuit capable of decoding with three or four times the number of steps may be used. Further, the number of decoding steps of the Euclidean arithmetic circuit 20 is set to be substantially equal to the number of steps required for operating the syndrome generation circuit 2 and the error correction circuit 22. However, the number of decoding steps is limited to this if there is enough decoding time. The same effect can be obtained even if the number of decoding steps is increased more than the above.

Next, the circuit operation of the error correction circuit 22, which is common to the above embodiments, will be described with reference to FIGS. The error correction circuit 22 calculates RA based on the error position information output from the Chien search circuit 21 and the error numerical polynomial calculated by the Euclidean arithmetic circuit 20 as described above.
Error correction is performed on the data in which the error position in M1 is calculated. The circuit operation of the error correction circuit 22 will be described based on the timing chart shown in FIG. Error correction device control circuit 41 based on error position information output from Chien search circuit 21
Outputs a read address and a control signal for reading the data at the error position calculated in the RAM 1. At this time, erroneous data in the RAM 1 is sequentially read out eight times as shown in FIG.

The erroneous data continuously read from the RAM 1 is obtained by combining the error value calculated by the error correction circuit 22 with the error data shown in FIG.
Are sequentially added at the error correction timing shown in FIG. The error-corrected data is sequentially written to the address where the erroneous data is stored at the same time when reading of all data calculated from the RAM 1 at the error position is completed. In the case of eight error corrections, the number of steps of the circuit operation of the error correction circuit 22 is 16, and the operation can be speeded up by eight clocks, which is conventionally required at least 24 steps.

Similarly, another operation of the error correction circuit 22 will be described with reference to the timing chart of FIG. In this example, based on the error position information output from the Chien search circuit 21, the error correction device control circuit 41 outputs a read address and a control signal for reading data in the RAM 1 in which the error position is calculated. At this time, two erroneous data in the RAM 1 are continuously read as shown in FIG.

The erroneous data two consecutively read from the RAM 1 are sequentially added to the error value calculated by the error correction circuit 22 at the error correction timing shown in FIG. The error-corrected data is written to the address where the data for which the error position has been calculated two consecutive times is stored at the timing shown in FIG. Hereinafter, error correction is performed by repeating this operation for the number of data for which errors are to be corrected. In the case of eight error corrections as shown in FIG. 10, the number of steps of the circuit operation of the error correction circuit 22 is 16, and the speed can be increased by eight clocks as compared with the conventional case requiring at least 24 steps.

In general, when speeding up the error correction apparatus, the data access time to the RAM 1 becomes the most bottleneck as described in the above embodiment. This is because the decoding time can be shortened by parallelizing the operation of each circuit in the other parts as shown in the above embodiment, but the data access to the RAM 1 cannot be performed in parallel, so that the speeding up is realized. At this time, the keyword is how to reduce the number of calculation steps of the syndrome generation circuit 2 and the error correction circuit 22 that have access to the RAM 1. When the error correction circuit 22 shown in this embodiment is employed, the minimum number of steps required to correct the error of the C1 code having the minimum distance 17 shown in FIG.
41 + 16) It is about steps. In the present embodiment, the operation for correcting an error of eight symbols has been described, but the present invention is not limited to this. Further, all or two of the erroneous data are continuously read from the RAM 1, but the present invention is not limited to this.
Needless to say, the same effect can be obtained if the number of data to be continuously read, such as writing to 1, is two or more.

In the first to fourth embodiments, the case where the Euclidean algorithm is used as a method for obtaining an error position polynomial and an error numerical polynomial from the syndrome obtained by the syndrome generation circuit 2 has been described. Instead, even if the error locator polynomial and the error numerical polynomial are obtained by another method such as the Berlekamp algorithm, the error correction can be performed at high speed by operating the syndrome generation circuit 2, the Euclidean operation circuit 20 and the Chien search circuit 21 in parallel. It goes without saying that the code can be decoded.

Although the Reed-Solomon code is used as the error correction code, the present invention is not limited to this, and may be used in an error correction device that decodes another linear error correction code such as a BCH code.

Although the decoding of the C1 code shown in FIG. 33 has been described, the present invention is not limited to this, and it goes without saying that the same effect can be obtained by decoding the C2 code with a similar circuit configuration. The configuration of the error correction code is not limited to those shown in FIGS. 32 and 33, and the same effect can be obtained when decoding an error correction code of a double or more product code format. Further, even with a code combining Reed-Solomon code and BCH code as an error correction code of the product code format, the speed of the decoding circuit can be increased by the above configuration.

In addition, although the three circuits of the syndrome generation circuit 2, the Euclidean operation circuit 20 and the Chien search circuit 21 are controlled to operate simultaneously based on the system start signal, the timing for performing the parallel operation is not limited to this. For example, the initial value of the Euclidean arithmetic circuit 20 may be set immediately after the syndrome is generated, and the Euclidean arithmetic circuit 20 may be operated. Alternatively, the Chien search circuit 21 may be operated immediately after the Euclidean operation is completed. The output timing of the syndrome data output from the syndrome generation circuit 2, the initial value set timing in the Euclidean arithmetic circuit 20, the output timing of the coefficient data of the error position polynomial and the error numerical polynomial to the register 41, and the initial value of the Chien search circuit 21 Set timing, error correction circuit
The control timing at 22 is not limited to the timing described above, and the same effect can be obtained by operating the three circuits of the syndrome generation circuit 2, the Euclidean operation circuit 20, and the Chien search circuit 21 in parallel.

The circuit configurations of the syndrome generation circuit 2, the division circuit on the Galois field of the Euclidean arithmetic circuit 20, and the Chien search circuit 21 are shown in FIGS. 27, 29 and 30, but are not limited thereto. The arithmetic circuit portion may be configured with an arithmetic processing circuit such as a microcomputer or a large-capacity ROM.

The three circuits of the syndrome generation circuit 2, the Euclidean operation circuit 20 and the Chien search circuit 21 are operated in parallel. However, the present invention is not limited to this. For example, an error correction circuit 22 is included in addition to these three circuits. The same effect can be obtained by operating the four circuits in parallel.

The circuit operation of the error correction circuit 22 is not limited to this. For example, if there is a margin in the decoding time, erroneous data based on the error position detected by the Chien search circuit 21 as shown in the conventional example. May be read out from the RAM 1, error correction is performed, and writing to the RAM 1 is repeated.

Although the output of the Euclidean arithmetic circuit 20 is temporarily stored in the register 40, the register for storing the coefficients of the error locator polynomial and the error numerical polynomial is not necessarily required, and may be omitted depending on the control method.

The circuit operations of the syndrome generation circuit 2, the Euclidean operation circuit 20 and the Chien search circuit 21 have been started simultaneously. However, the present invention is not limited to this, and the start timing may be different even if the above three circuits are different. A similar effect is achieved.

Next, other embodiments (fifth to ninth embodiments) of the present invention, which are characterized by the configuration of the division circuit between polynomials defined on the Galois field, will be described.

Fifth embodiment. FIG. 11 is a block diagram of a division circuit for dividing polynomials defined on a Galois field of an error correction apparatus according to a fifth embodiment of the present invention. In the figure, 81a,
81b, 85 to 88 and 95 are the same as those shown in FIG. Reference numeral 100 denotes a division circuit that performs division by using the output of the register 81a as a dividend and the output of the register 81b as a divisor, and 101 denotes a Euclidean operation control circuit that controls a division circuit unit of the Euclidean operation.

Next, the principle of operation of the division circuit when performing division with the circuit configuration shown in FIG. 11 will be briefly described. Now, the dividend polynomial, respectively as in the example the dividend polynomial, and a divisor polynomial _{conventional: M1 (Z) = A n} Z n + A n-1 Z n-1 + ·
·· A ₁ Z + A ₀ dividend _{polynomial: M2 (Z) = B m} Z m + B m-1 Z m-1 + ··
・ Set to B ₁ Z + B ₀ . Note that n> m. Hereinafter, the calculation procedure when the above division is performed by handwriting is shown in Equation 4. In this embodiment, as initial values, each coefficient data of the polynomial to be removed is stored in the register 81a, and each coefficient data of the polynomial is stored in the register 81a.
It shall be stored in b. First, as shown in Equation 4, the coefficient data of the maximum degree of the divisor polynomial is the same as the coefficient data of the maximum degree of the polynomial to be divided by multiplying each coefficient data of the divisor polynomial by the division result output from the division circuit 100. (The operation of reducing the order of the polynomial to be reduced by one order). This division is repeated until the degree of the remainder of the dividend polynomial becomes smaller than the degree of the division polynomial, as in the conventional example. In Equation 4, each coefficient data of the final remainder polynomial is represented by C _i (i = 0, 1, 2,..., M−1).

[0150]

(Equation 4)

According to the Euclidean algorithm shown in FIG. 25, the above-mentioned remainder polynomial: R (Z) = C _m−1 Z ^m−1 + C _m−2 Z ^m−2 +
... If the degree of + C ₁ Z + C ₀ does not satisfy the predetermined condition, the division is repeated with the divisor polynomial M2 (Z) as the polynomial to be divided and the remainder polynomial R (Z) as the divisor polynomial.

Equation 5 shows a calculation procedure when M2 (Z) is divided by R (Z). In this calculation, for convenience, it is assumed that the maximum degree C _m-1 of the remainder polynomial R (Z) is not zero. In general, when it is 0, the order polynomials and divisor polynomials are determined by the order detection circuits 87 and 88 shown in FIG. Performs division by shifting coefficient data of a polynomial. Also, when the maximum degree of the remainder polynomial during the division operation becomes zero, the division is performed by shifting the coefficient data of the remainder polynomial until the maximum degree of the remainder polynomial no longer becomes zero.

[0153]

(Equation 5)

Note that these controls are performed by the Euclidean arithmetic control circuit 101. In the present embodiment shown in FIG. 11, a selector for exchanging coefficient data of a polynomial to be removed and coefficient data of a divisor polynomial as shown in the conventional example is not provided. Therefore, when performing the division, the coefficient data of the maximum degree of the polynomial to be divided is multiplied by the coefficient data of the polynomial to be divided to the maximum value of the polynomial by multiplying each coefficient data of the polynomial by the multiplier as shown in Expression 5. Division (operation of reducing the order of the polynomial to be reduced by one) is performed in the same manner as the coefficient data of the order. This division is repeated until the degree of the remainder of the dividend polynomial becomes smaller than the degree of the division polynomial, as in the conventional example. As a result, each coefficient data of the remainder polynomial (referred to as R ″ (Z)) is represented by E _i (i = 0, 1, 2,..., M−2).

Then, the remainder polynomial R ″ (Z) (R ″
_{(Z) = E m-2} Z m-2 + E m-3 Z m-3 + ··· + E 1 Z
When the order of + E ₀ ) does not satisfy the condition shown in FIG. 25, the division is repeated with the above R (Z) as the polynomial to be divided and R ″ (Z) as the polynomial. The writing procedure is shown in Equation 6. In this case, too, for the sake of simplicity, it is assumed that the coefficient of the maximum degree of the remainder polynomial, E _m−2, is not 0. As described above, it is necessary to exchange the coefficient data of the subject polynomial and the division polynomial. No selector is placed.

[0156]

(Equation 6)

Therefore, when performing division in the same manner as in Equation 4, the coefficient data of the maximum order of the divisor polynomial is multiplied by the coefficient data of the divisor polynomial by multiplying each coefficient data of the divisor polynomial by the multiplier output from the division circuit 100. The division (operation of reducing the order of the polynomial to be divided by 1) is performed in the same manner as the coefficient data of the maximum order.

This division is repeated until the degree of the remainder of the dividend polynomial becomes smaller than the degree of the divisor polynomial as in the conventional example. As a result, each coefficient data of the remainder polynomial (R ■■■ (Z)) is replaced by F _i (i = 0, 1, 2,..., M−
Expressed in 3). Then, this operation is executed until the end condition of the Euclidean algorithm is satisfied. The reason why the error numerical value polynomial ω (Z) and the error position polynomial σ (Z) are calculated by repeating this operation is that when calculating the error position or the error numerical value, the above polynomial is expressed by the maximum degree of each polynomial. This is for normalization. (For details, see “Coding Theory”, pp.169-175)

The operation of the Euclidean operation division circuit of the error correction device for decoding a Reed-Solomon code according to the Euclidean algorithm shown in FIG. 25 will be described below with reference to FIG. In this embodiment, a case will be described in which a Reed-Solomon code having a minimum Hamming distance of 17 employed in an optical disc or the like is decoded in the same manner as in the conventional example. Now, the syndrome polynomial S generated from the reproduction signal (Z) S (Z) = S 15 Z 15 + S 14 Z 14 + S 13 Z 13 + ··· + S
And ₁ Z + S _0.

First, when the Euclidean operation is started, based on the Euclidean operation start signal output from the Euclidean operation control circuit 101, the coefficient of the polynomial Z ^{2t to} be initialized is stored in the register 81a. Register 81b has a syndrome polynomial S (Z) which is a divisor polynomial.
Are stored. In addition, the order detection circuits 87 and 8
The counters of 8 are set with the initial values of the orders 16 and 15, respectively. The counters in the order detection circuits 87 and 88 store 1 in the register 81 which stores the coefficient data of the polynomial to be removed.
Each time the shift is performed, the count value is decreased by one. In this embodiment, similarly to the conventional example, higher-order coefficient data is stored in the register arranged on the right side.

At the same time, for the syndrome polynomial, which is a divisor polynomial, the order detection circuit 88 determines whether the coefficient data of the highest order is zero. When the coefficient of the maximum degree of the divisor polynomial (syndrome polynomial) detected by the degree detector 88 is 0, the Euclidean arithmetic control circuit 101 shifts the contents of the register 81b storing the coefficient data of the divisor polynomial (note that In this case, the contents of the register 81b are shifted as they are without performing the adding operation in the adding circuit 86.) The shifting operation is repeated until the data of the maximum order is no longer 0. At this time, the counter in the order detection circuit 88 is decremented by one every time the shift operation is performed.

The register 81a storing the coefficient data of the polynomial to be removed is added to an adder circuit when a clock is input.
The output of the register 86 is latched, and the register 81b storing the coefficient data of the divisor polynomial is configured to hold the coefficient data. (In Figure 11,
Although the specific control circuit is omitted, the clocks (clock 1 and clock 2) input to the registers 81a and 81b are not supplied to the registers storing the divisor-side coefficient data, so that the coefficient data of the divisor polynomial is not supplied. Is held in a register. Note that each operation circuit (division circuit 100, multiplication circuit 85, and addition circuit 86) shown in the figure
Performs each operation defined on the Galois field.

The circuit operation of the division circuit in the Euclidean operation circuit of this embodiment will be described below with reference to FIGS. Figure
12 (a) shows a state in which an initial value Z ¹⁶ is set as a polynomial to be removed in a register 81a, and a syndrome polynomial S (Z) is set as a polynomial in 81b. Note that the numbers and symbols described in the registers indicate coefficient data stored in the registers. In this embodiment, for the sake of simplicity, the highest order coefficient of the syndrome polynomial is 0.
Not. Also, the coefficient data of the higher order of each polynomial stored in the register is arranged at the right end. The division circuit 100 divides the output of the register 81a as a dividend and the output of the register 81b as a divisor, and outputs the result. At this time, the clock 1 is supplied to the register 81a in which the coefficient data of the dividend is stored.

The division circuits shown in FIGS. 12 and 13 have the same configuration as the division circuit described in FIGS. 38 and 39, and shift operation is performed until the degree of the remainder of the dividend polynomial becomes smaller than the degree of the division polynomial. Is performed by repeating. The end of division is determined by the Euclidean arithmetic control circuit 101 based on the order information output from the order detection circuits 87 and 88. When the maximum degree of the remainder polynomial is detected as 0 by the degree detection circuit 87 (or 88) during the division operation, the Euclidean arithmetic control circuit 101 stores the coefficient data of the remainder polynomial in the register 81a (or 81b). Is shifted by one as it is. At this time, the count value of the counter in the order detection circuit 87 (or 88) is reduced by one.

FIG. 12B shows the state of the coefficient data stored in each register 81 when the division is completed. Incidentally, H ₁₄ to H ₀ stored in the register 81a is a coefficient data of the remainder polynomial when performing the division. When the division operation is completed, the order detection circuit 87 (or 88) detects the maximum order of the remainder polynomial, and if the maximum order is 0,
Based on the control signal output from the Euclidean arithmetic control circuit 101, the coefficient of the remainder polynomial is shifted by one. This operation is performed when the coefficient data of the maximum order of the remainder polynomial is 0.
Repeat until no more. At this time, as described above, the count value of the counter in the order detection circuit 87 (or 88) is 1
It is reduced one by one.

In the Euclidean arithmetic operation control circuit 101, the order of the remainder is determined based on the order of the remainder polynomial output from the order detection circuit 87 (or 88). ) Is satisfied, the Euclidean operation is terminated, and if the termination condition is not satisfied, the operation is executed with the polynomial that was the divisor polynomial in the previous operation as the polynomial to be deleted and the remainder polynomial as the divisor polynomial. At this time, the coefficient data stored in the register 81 is shown in FIG. Since there is no exchange means as in the conventional example, the connection state of the circuit does not change, but the register 81a
Is stopped, and the clock 2 is supplied to the register 81b. Therefore, register
The contents of 81a are held, and the coefficients of the remainder polynomial are sequentially stored in the register 81b.

At this time, in the division circuit in the Euclidean arithmetic circuit, the order detection circuit 88 determines whether the maximum degree of the dividend polynomial (remainder polynomial) is 0, and if it is 0, the result is stored in the register 81b. A control signal is output so that the contents of the polynomial to be deleted (remainder polynomial) are shifted by one. This is because when the register for storing the divisor and the dividend to be output to the division circuit 100 is determined and the coefficient data of the dividend polynomial is used as the divisor, the dividend when the coefficient of the highest degree of the dividend polynomial becomes zero is used. This is because (the maximum coefficient of the divisor polynomial) is divided by 0, and the solution (output) may become indefinite.

The division is performed by repeating the shift operation while calculating the contents of the register storing the coefficient data of the polynomial to be divided until the degree of the remainder of the polynomial to be divided becomes smaller than the degree of the polynomial to be divided, as in the above example. Performs division by.
FIG. 13 (b) shows that each of the registers 81a and 81
The state of the coefficient data stored in 1b is shown. In addition,
J _{13 to} J ₀ stored in the register 81b are coefficient data of the remainder polynomial.

The order of the remainder polynomial is determined, and if the predetermined condition is not satisfied, the clock supplied to the registers 81a and 81b is switched and the division operation based on the Euclidean algorithm is performed again. This division operation is repeated until the degree of the remainder polynomial becomes 7 or less. Thus, when decoding a Reed-Solomon code, division between polynomials on a Galois field based on the Euclidean algorithm can be performed for each polynomial, so that the error correction processing speed can be improved and the switching means (selector) can be improved. ), The circuit scale can be reduced, and selector control is not required.

Sixth embodiment. FIG. 14 shows a sixth embodiment of the present invention. In FIG. 14, the circuit configuration is the same as that of the fifth embodiment (FIG. 11), and a detailed description thereof will be omitted. In the sixth embodiment, the position of the multiplication circuit 85 connected to the register is set to the fifth position.
Different from the embodiment. The difference from the fifth embodiment is that the multiplier 85 is connected to the register where the initial value Z ^2t is set at the start of the Euclidean operation. With this configuration, the fifth
As compared with the embodiment, one multiplication circuit 85 can be omitted, and the circuit scale can be reduced (about 400 gates can be reduced).

The operation of the Euclidean division circuit of the error correction device for decoding a Reed-Solomon code according to the Euclidean algorithm shown in FIG. 25 will be described below with reference to FIG. 14, similarly to the fifth embodiment. In the sixth embodiment, the fifth
A case of decoding a Reed-Solomon code having a minimum Hamming distance of 17 employed in an optical disk or the like as in the embodiment will be described. Now, the syndrome polynomial S generated from the reproduction signal (Z) S (Z) = S 15 Z 15 + S 14 Z 14 + S 13 Z 13 + ··· + S
And ₁ Z + S _0.

First, when the Euclidean arithmetic operation is started, based on the Euclidean arithmetic operation start signal output from the Euclidean arithmetic operation control circuit 101, the initial value of the coefficient of the polynomial Z ^{2t to} be removed is stored in the register 81a. Register 81b has a syndrome polynomial S (Z) which is a divisor polynomial.
Are stored. In addition, the order detection circuits 87 and 8
In the counters 8, the initial values of the orders 15 and 16 are set, respectively. Counters in the order detection circuits 87 and 88 are registers 81a and 81b storing coefficient data of the polynomial to be removed.
Each time is shifted once, the count value is decreased by one.

At the same time, the syndrome polynomial, which is a divisor polynomial, has a coefficient data of the highest order of 0 in the order detection circuit 88.
Is determined. When the coefficient data of the maximum degree of the divisor polynomial (syndrome polynomial) detected by the degree detector 88 is 0, the Euclidean arithmetic control circuit 101 shifts the contents of the register 81b storing the coefficient data of the divisor polynomial ( At this time, the content of the register 81b is shifted as it is without performing the adding operation in the adding circuit 86.) The shifting operation is repeated until the data of the maximum order is no longer 0. At this time, the counter in the order detection circuit 88 decreases the count value by one.

The register 81a storing the coefficient data of the polynomial to be removed is added to the adder circuit when a clock is input.
The output of the register 86 is latched, and the register 81b storing the coefficient data of the divisor polynomial is configured to hold the coefficient data. Although a specific control circuit is omitted in FIG. 14, a configuration in which clock data 1 and 2 input to the registers 81a and 81b are controlled to hold coefficient data of a polynomial in the registers as in the fifth embodiment. Is taking. It is assumed that each operation circuit shown in the figure performs each operation defined on the Galois field.

The circuit operation of the division circuit in the Euclidean operation circuit of the present embodiment will be described below with reference to FIGS.
FIG. 15A shows a state in which the initial value Z ¹⁶ is set in the register 81a as a polynomial to be removed, and the syndrome polynomial S (Z) is set in the register 81b as a polynomial to be removed.
Note that the numbers and symbols described in the registers indicate coefficient data stored in the registers. In this embodiment, it is assumed that the highest order coefficient of the syndrome polynomial is not 0 for the sake of simplicity. Also, the coefficient data of the higher order of each polynomial stored in the register is arranged at the right end. The division circuit 100 divides the output of the register 81a as a divisor and the output of the register 81b as a dividend, and outputs the result. At this time, the clock 1 is supplied to the register 81a in which the coefficient data of the divisor is stored.

FIG. 15 (b) shows a state where the register 81a is shifted once from the state shown in FIG. 15 (a). Since the initial value on the dividend side is Z ¹⁶ as shown in the Euclidean algorithm shown in FIG. 25, the coefficient of the minimum degree of the dividend polynomial becomes 0. Therefore, in the case of the circuit configuration shown in FIG. 14, the coefficient data of the minimum degree of the remainder polynomial on the dividend polynomial side obtained by the first division is S ₀ + 0 × S ₁₅ = S ₀ , and the multiplication circuit 85 can be omitted. I understand. Fig. 15 (b)
Shows each coefficient data stored in the registers 81a and 81b after the first division. K _{14 to} K ₁ and S ₀ shown in the figure are each coefficient data of the remainder polynomial.

As in the fifth embodiment, division is performed by repeating the shift operation until the degree of the remainder of the polynomial to be reduced becomes smaller than the degree of the polynomial. The end of division is determined by the Euclidean arithmetic control circuit 101 based on the order information output from the order detection circuits 87 and 88. In addition,
The maximum degree of the remainder polynomial during execution of the division operation is the degree detection circuit.
When 0 is detected by 87 (or 88), the Euclidean arithmetic control circuit 101 changes the contents of the register 81a (or 81b) storing the coefficient data of the remainder polynomial to 1 as it is.
Is configured to shift by one. At this time, the count value of the order counter in the order detection circuit 87 (or 88) is 1
Reduced. This is because when the register for storing the divisor and the dividend to be output to the division circuit 100 is determined and the coefficient data of the dividend polynomial is used as the divisor, the dividend when the coefficient of the highest degree of the dividend polynomial becomes zero is used. This is because (the maximum coefficient of the divisor polynomial) is divided by 0, and the solution (output) may become indefinite.

FIG. 16A shows the state of the coefficient data stored in each of the registers 81a and 81b when the above division is completed. Note that L _{14 to} L ₀ stored in the register 81a are coefficient data of the remainder polynomial when the above division is performed.
In the present embodiment, L ₀ = S ₀ . When the division operation is completed, the order detection circuit 87 (or 88) detects the maximum order of the remainder polynomial, and if the maximum order is 0, based on the control signal output from the Euclidean arithmetic control circuit 101, the remainder polynomial Is shifted by one as it is. This operation is repeated until the coefficient data of the maximum order of the remainder polynomial is no longer 0. At this time, as described above, the order detection circuit
The count value of the order counter in 87 (or 88) is decremented by one.

In the Euclidean arithmetic control circuit 101, based on the degree of the remainder polynomial output from the degree detection circuit 87 (or 88), the order of the remainder is changed to the end condition of the Euclidean operation (in this embodiment, the order is 7 or less). ) Is satisfied, the Euclidean operation is terminated, and if the termination condition is not satisfied, the operation is executed with the polynomial that was the divisor polynomial in the previous operation as the polynomial to be deleted and the remainder polynomial as the divisor polynomial. At this time, the coefficient data stored in the registers 81a and 81b is shown in FIG. As in the fifth embodiment, since there is no exchange means, the connection state of the circuit does not change, but the clock 1 supplied to the register 81a is stopped.
Conversely, clock 2 is supplied to register 81b. Therefore, the contents of the register 81a are held, and the coefficients of the remainder polynomial are sequentially stored in the register 81b.

At this time, in the division circuit in the Euclidean arithmetic circuit, the degree detection circuit 88 determines whether the maximum degree of the dividend polynomial (remainder polynomial) is 0, and if it is 0, the result is stored in the register 81b. A control signal is output so that the contents of the polynomial to be deleted (remainder polynomial) are shifted by one.

In the division, the shift operation is performed while calculating the contents of the register storing the coefficient data of the dividend polynomial until the degree of the remainder of the dividend polynomial becomes smaller than the degree of the divisor polynomial, as in the fifth embodiment. Perform division by repeating. In FIG. 17, when the above division is completed, each register 81a, 8a
This shows the state of the coefficient data stored in 1b. Incidentally, M ₁₃ ~M ₀ stored in the register 81b is the coefficient data of the remainder polynomial.

Then, the order of the remainder polynomial is determined, and if the predetermined condition is not satisfied, the clock supplied to the registers 81a and 81b is switched and the division operation based on the Euclidean algorithm is performed again. This division operation is repeated until the degree of the remainder polynomial becomes 7 or less. Thus, when decoding a Reed-Solomon code, division between polynomials on a Galois field based on the Euclidean algorithm can be performed for each polynomial, so that the error correction processing speed can be improved and the switching means (selector) can be improved. ), The circuit scale can be reduced, and selector control is not required. Further, compared with the fifth embodiment, one multiplication circuit 85 can be omitted, and the circuit scale can be reduced.

Seventh embodiment. The seventh embodiment of the present invention is based on the adder 86 and the divider 10 used in the fifth and sixth embodiments.
The configuration of 0 is different from the control method of the Euclidean arithmetic circuit 101. Therefore, the seventh embodiment will be described using the Euclidean division circuit shown in FIG. FIG. 18 shows a specific configuration diagram of the division circuit 100. 110 is an inverse ROM for outputting the reciprocal of the input coefficient, 111 is a multiplication circuit, and 112 is an OR gate. The inverse element ROM 110 is configured to output the reciprocal of the original element on the Galois field. FIG. 19 shows the configuration of the adder 86. In the figure, 113 is an AND gate, and 114 is an EXOR gate. Table 1 shows the contents of the inverse ROM 110 of this embodiment. Note that α described in the table is an element on the Galois field of the primitive polynomial G (Z). As shown in the table, the inverse ROM 110 in this embodiment is configured to output 0 when 0 is input. Further, α described in Table 1 is an element on the Galois field defined by GF (2 ⁸ ).

[0184]

[Table 1]

The operation of the circuit according to the seventh embodiment will be described below with reference to FIG. Similar to the fifth embodiment, the syndrome polynomial S generated from the reproduction signal (Z) S (Z) = S 15 Z 15 + S 14 Z 14 + S 13 Z 13 + ··· + S
And ₁ Z + S _0.

First, when the Euclidean operation is started, based on the Euclidean operation start signal output from the Euclidean operation control circuit 101, the initial value of the coefficient of the polynomial Z ^{2t to} be removed is stored in the register 81a. Register 81b has a syndrome polynomial S (Z) which is a divisor polynomial.
Is stored. Also, the order detection circuits 87, 88
Are set to the initial values of the orders, 16 and 15, respectively.

At the same time, the highest order coefficient data of the syndrome polynomial, which is the divisor polynomial, is detected by the order detection circuit 88. In the Euclidean arithmetic control circuit 101, the divisor polynomial (syndrome polynomial) detected by the order detector 88
If the coefficient data of the maximum order is 0 , the contents of the register 81b storing the coefficient data of the divisor polynomial are shifted, and the shift operation is repeated until the data of the maximum order is no longer 0. At this time, the count value of the order counter in the order detection circuit 88 is reduced by one.

At this time, the division circuit 100 inputs 0 as the data on the divisor side. In the inverse element ROM 110, as shown in Table 1, when 0 is input, 0 is output. The data output by the inverse ROM 110 is a multiplication circuit
The dividend is multiplied by 111 and output. In this case, the inverse R
Since the output data from the OM 110 is 0, the multiplication circuit 111
Is 0. The OR gate 112 receives the LSB data output from the multiplication circuit 111 and the Euclidean operation control circuit 10
The logical sum with the control signal output from 1 is calculated. The Euclidean arithmetic control circuit 101 sets “H” when the coefficient data of the maximum order of the polynomial detected by the order detection circuit 88 is 0.
Is output. Therefore, 1 is output from the division circuit 100.

Each bit of the coefficient data output from the register 81a of the divider circuit 100 in which the dividend coefficient data is stored is input to one input terminal of the AND gate 113 in the adder circuit 86. It is configured as
A control signal output from the Euclidean arithmetic control circuit 101 is input to the other input. This control signal is configured to output “L” when the coefficient data on the divisor side of the division circuit 100 is detected as 0 by the degree detection circuit 88. With this configuration, the coefficient data on the divisor side (register 81b side) input to the division circuit 100 is 1 × S _j + 0 = S _j (j = 0, 1,..., 1
5) is performed and the shift operation is repeated.
The shift operation is repeated until the coefficient data of the maximum order of the divisor polynomial is not 0. Thus, when shifting the coefficient data, the Euclidean arithmetic control circuit 101 does not need any special control, and only needs to be aware of the register for performing the coefficient shift.

When the maximum degree of the syndrome polynomial is detected, division based on the Euclidean algorithm is started. Similarly to the fifth embodiment, the register 81a storing the coefficient data of the polynomial to be deleted is configured so that the output of the adder 86 is latched when a clock is input.
The register 81b storing the coefficient data of the divisor polynomial is configured to hold the coefficient data.

In the division operation, the degree of the remainder of the polynomial to be divided is
The process is repeated until the order of the divisor polynomial becomes smaller. The end of division is determined by the Euclidean arithmetic control circuit 101 based on the order information output from the order detection circuits 87 and 88. Note that even when the maximum degree of the remainder polynomial is detected as 0 by the degree detection circuit 87 during the execution of the division operation, the division circuit 10
Since 0 is output from 0, the multiplication circuit 85 and the addition circuit 86 calculate 0 × S _i + X _i = X _i , and the register 81a stores X _i (X _i is a register
The coefficient data stored in 81a is shifted and stored as it is. Therefore, the Euclidean arithmetic control circuit 101 may repeat the shift operation without changing the control.

When the division operation is completed, the order detection circuit 87
In (or 88), the maximum degree of the remainder polynomial is detected, and if the maximum degree is 0, the contents of the register 81a are shifted as it is. At this time, as described above, the count value of the counter in the order detection circuit 87 (or 88) is reduced by one.

In the Euclidean arithmetic control circuit 101, based on the degree of the remainder polynomial output from the degree detection circuit 87 (or 88), the order of the remainder is changed to the end condition of the Euclidean operation (in this embodiment, the order is 7 or less). ) Is satisfied, the Euclidean operation is terminated, and if the termination condition is not satisfied, the operation is executed with the polynomial that was the divisor polynomial in the previous operation as the polynomial to be deleted and the remainder polynomial as the divisor polynomial. At this time, the connection state of the circuit does not change because there is no exchange means as in the conventional example, but the clock 1 supplied to the register 81a is stopped, and
Clock 2 is supplied to 81b. Therefore, register 81a
Are held, and the coefficients of the remainder polynomial are sequentially stored in the register 81b.

At this time, in the division circuit in the Euclidean operation circuit, even when the maximum order (output of the register 81b) of the dividend polynomial (remainder polynomial) is 0 by the order detection circuit 88, as described above, the Euclidean operation is performed. Control circuit 101
In this configuration, the contents of the register 81b are shifted only by outputting "L" and "H" control signals to each of the adding circuits 86 and the dividing circuits 100, respectively. Good. That is, when the order detection circuit 88 determines that the maximum order coefficient data of the polynomial stored in the register 81b is 0, the division circuit 100 outputs 1 as the division result. On the other hand, in the adder circuit 86, the control signal output from the Euclidean arithmetic control circuit 101
The output of the D gate 113 becomes "L". (That is, 0 is input to the addition circuit 86.) Therefore, the multiplication circuit 85 and the addition circuit 86 execute the operation of 1 × Y _i + 0 = Y _i . Therefore, Y is stored in the register 81b.
_i (Y _i is the coefficient data stored in the register 81b)
Is shifted and stored as it is.

In the division, as in the above example, the shift operation is repeated while calculating the contents of the register storing the coefficient data of the polynomial to be divided until the degree of the remainder of the polynomial to be divided becomes smaller than the degree of the polynomial to be divided. Performs division by.
Then, the order of the remainder polynomial is determined, and if the predetermined condition is not satisfied, the clock supplied to the registers 81a and 81b is switched and the division operation based on the Euclidean algorithm is performed again. This division operation is repeated until the degree of the remainder polynomial becomes 7 or less. Thus, when decoding a Reed-Solomon code, division between polynomials on a Galois field based on the Euclidean algorithm can be performed for each polynomial, so that the error correction processing speed can be improved and the Euclidean operation control circuit can be improved. The control in 101 is also very simple, and the circuit scale can be reduced.

In the seventh embodiment, the division circuit 100 is composed of the inverse ROM 110 and the multiplication circuit 111. However, the present invention is not limited to this. If the input divisor is 0, the division circuit 100
If the division circuit 100 is configured so that the output of 0 is output as 1, the same effect can be obtained even if it is configured by a logic gate or a microcomputer. In the seventh embodiment, a ROM is used to determine the inverse of the input data. However, it is needless to say that a RAM may be used, and the inverse may be determined by a logic gate. Further, the configuration of the adder circuit 86 is not limited to the configuration shown in FIG. 19, and the same effect can be obtained if the output of the register 81b is directly output based on the control signal output from the Euclidean arithmetic circuit 101. In addition, the case where it is defined by GF (2 ⁸ ) has been described, but the present invention is not limited to this. G
An operation on a Galois field defined by F (q) (q is a prime number or an exponent of a prime number) has the same effect. Furthermore,
Although the case of the division circuit shown in FIG. 11 has been described, a similar effect can be obtained with the circuit configuration shown in FIG. Also, it goes without saying that the control of the Euclidean operation control circuit 89 can be simplified similarly when the seventh embodiment is applied to the division circuit 84 and the addition circuit 86 shown in the conventional example. If the maximum order coefficient data of the syndrome polynomial is 0 when the initial value is set, the circuit configuration and control when shifting the data in the register 81b until the maximum order coefficient data is not 0 can be simplified. .

Eighth embodiment. Hereinafter, an eighth embodiment of the present invention will be described. In the present embodiment, a case will be described in which the error correction device shown in FIG. 11 uses the configuration of the division circuit 100 having the configuration shown in FIG. FIG. 20 shows a part of an error position calculation circuit that calculates an error position polynomial using the division results output from the division circuit 100 and the Euclidean operation control circuit 101 and a control signal. In the figure, 120 is an inverse ROM,
121 is a multiplication circuit, and 122 is a selector. In the eighth embodiment, for the sake of simplicity, a description will be given of a case where the degree difference between the polynomial to be divided and the polynomial is 1 when performing division on a Galois field.

When division between polynomials is performed by the error correction device shown in FIG. 11, data output from the division circuit 100 as a quotient has the following two patterns. One is when the coefficient data of the polynomial to be deleted is stored in the register 81a, and the other is when the coefficient data of the polynomial to be deleted is stored in the register 81a.
b. Now, each of the the dividend polynomial and divisor polynomial, the dividend _{polynomial: M1 (Z) = A n} Z n + A n-1 Z n-1 + ·
.. + A ₁ Z + A ₀ divisor polynomial: M2 (Z) = B _n-1 Z ^n-1 + B _n-2 Z ^n-2 +
.. + B ₁ Z + B ₀ . In Equation 7, the coefficient data of the polynomial to be removed is stored in the register 81a
Equation 8 shows the division result when the coefficient data of the polynomial to be divided is stored in the register 81b.

[0199]

(Equation 7)

[0200]

(Equation 8)

When the coefficient data of the polynomial to be deleted is stored in the register 81a, the division is performed as shown in Expression 7, and when calculating the coefficient data of the error locator polynomial, the zero-order term is normalized (normalized). After that, coefficient data of the error locator polynomial is obtained according to the algorithm shown in FIG. In this case, the division result output from the division circuit 100 matches the coefficient data of the quotient polynomial as it is. The quotient polynomial in the case where the result is normalized is shown in the lowermost expression of Expression 7.
Similarly, a case where coefficient data of a polynomial to be deleted is stored in the register 81b will be described using Expression 8. Equation 8 shows the calculation process in each step. The right side shows the output of the division circuit 100 in each step. In this case, the coefficient data output from the division circuit 100 does not match the coefficient data of the quotient polynomial. However, in the case of the calculation method shown in Equation 8, when a normalized expression for calculating the coefficient data of the error locator polynomial is obtained, when the quotient polynomial is a first-order polynomial, the output of the division circuit 100 in Step 2 is used as it is. It can be seen from the comparison with Equation 7 that the coefficient is a first-order coefficient of the polynomial. The operation of the circuit shown in FIG. 20 will be described based on this.

Referring to FIG. 20, the inverse ROM 120 stores FIG.
The coefficient of the zero-order quotient polynomial output from the division circuit 100 shown in FIG. One input of the multiplication circuit 121 is provided with the output of the inverse ROM 121, and the other input is provided with a division circuit.
The coefficient of the first-order quotient polynomial output from 100 is input. In the selector 122, the Euclidean arithmetic control circuit 101
Based on the output control signal, the output of the multiplier 121 is selected when the coefficient of the polynomial to be stored is stored in the register 81a, and 0 when the coefficient data of the polynomial to be stored is stored in the register 81b. It is configured to output coefficient data of the following quotient polynomial.

According to this configuration, when the register 81a stores the coefficient data of the polynomial to be divided (corresponding to equation 7), the result of the division is the first order of the quotient polynomial used in calculating the error locator polynomial. When the coefficient data of the polynomial to be divided is stored in the register 81b (corresponding to Equation 8), the 0th-order coefficient data output from the division circuit 100 is the first-order coefficient data of the quotient polynomial. Is output as As a result, the quotient polynomial is normalized, and when calculating the error locator polynomial, the error locator polynomial can be calculated with a simple circuit configuration only by adding the selector 122. Further, as shown in Equation 8, when coefficient data of the polynomial to be deleted is stored in the register 81b, the coefficient data is calculated without performing the division operation, so that the number of decoding steps can be reduced.

Although the first embodiment deals with the first-order quotient polynomial in the present embodiment, the circuit configuration is slightly complicated in the case of the second-order or third-order, but can be realized with a simple circuit configuration. Hereinafter, the case of second order or higher will be briefly described. Respectively Hijo polynomial and divisor polynomial in Table 2, the dividend _{polynomial: M1 (Z) = A n} Z n + A n-1 Z n-1 + ·
.. + A ₁ Z + A ₀ division polynomial: M2 (Z) = B _n−2 Z ⁿ⁻² + B _n−3 Z ⁿ⁻³ +
.. + B ₁ Z + B ₀ , the coefficient data of the polynomial to be deleted is stored in the register 81a.
(The coefficient data of the maximum degree of the divisor polynomial is treated as a divisor in the division circuit 100, the normal division shown in the conventional example) and the coefficient data of the polynomial to be divided are stored. When the data is stored in the register 81b (the coefficient data of the maximum degree of the divisor polynomial is
Here, the calculation result is shown. Note that, also in the present embodiment, the configuration of the division circuit unit when performing the Euclidean operation adopts the circuit configuration shown in FIG.

[0205]

[Table 2]

Equation 9 shows coefficient data obtained by normalizing the quotient polynomial that has been subjected to the ordinary division. Thus, when the coefficient data of the dividend polynomial is stored in the register 81b (when the coefficient data of the maximum order of the divisor polynomial is treated as the dividend in the division circuit 100), the normalized quotient polynomial is obtained. In this case, the quotient data output from the division circuit 100 is P _i (i = 0, 1,..., K; k is the order of the quotient polynomial), and the coefficient data of the quotient polynomial is Q _i (i =
0, 1,..., K; k is the order of the quotient polynomial), and Q ₀ = 1 Q ₁ = Q ₀ × P ₀ Q ₂ = Q ₁ × P ₁ ··· Q _k = Q _k−1 × P _k−1 . Equation 10 shows the result of calculating the data of the maximum order when the quotient polynomial is quadratic. (When the coefficient data of the maximum degree of the divisor polynomial is treated as the dividend in the division circuit 100)

[0207]

(Equation 9)

[0208]

(Equation 10)

FIG. 21 shows a part of an error position calculation circuit for calculating an error position polynomial in which the case where the quotient polynomial is quadratic or higher is considered. 20 to 122 are the same as those shown in FIG. Reference numeral 123 denotes a shift register in which coefficient data (division results) of the quotient polynomial output from the division circuit 100 are stored in ascending order. 124 is a selector, and 125 is a register. The inverse ROM 120, the multiplication circuit 121, the selectors 122 and 124, the shift register 123, and the register 125 constitute a part of the error position calculation circuit.

Next, the operation will be described. In FIG. 21, a coefficient of a zero-order quotient polynomial output from the division circuit 100 shown in FIG. Also,
In the shift register 123, coefficient data of the first-order or higher-order quotient polynomial output from the division circuit 100 shown in FIG. 11 is sequentially stored in ascending order. The selector 124 outputs the output of the inverse ROM 120 and the output of the register 125 to the Euclidean arithmetic circuit 101.
The switching is performed based on the control signal output from the controller. Multiplication circuit
At 121, the output of the shift register 123 and the output of the selector 124 are multiplied. Note that the shift register 123 is
Each time multiplication is performed by 1, data is sequentially shifted.

In the selector 122, the Euclidean arithmetic circuit
If the coefficient of the polynomial to be removed is stored in the register 81a based on the control signal output from the multiplication circuit 121,
Is selected and the coefficient data of the polynomial to be
If the coefficient is stored in b, the coefficient data of the zero-order quotient polynomial is output as it is, and control is performed so as to select the output of the multiplication circuit 121 when calculating the second and subsequent coefficients of the quotient polynomial. It is configured as follows. The output of the selector 122 is stored in the register 125. The selector 124 selects the output of the inverse ROM 120 when the register 81a shown in FIG. 11 is treated as a polynomial to be removed, and selects the output of the register 125 when the register 81b is treated as a polynomial to be removed. Is configured.

According to this configuration, when the register 81a stores the coefficient data of the polynomial to be divided, the division circuit 100
The division result obtained by normalizing the coefficient data of each quotient polynomial output by the coefficient data of the 0th order is the coefficient data of the quotient polynomial used when calculating the error locator polynomial, and the coefficient of the polynomial to be deleted is stored in the register 81b. When the data is stored, the above-described calculation is executed by controlling the selectors 122 and 124 as described above, so that the coefficient data of the quotient polynomial can be calculated. Therefore, the error locator polynomial can be calculated with a simple circuit configuration in which only the selectors 122 and 124 are added.

In the above embodiment, the case where the quotient polynomial is quadratic or tertiary is described, but in this case, 0 may be included in each coefficient data of the quotient polynomial. Although the description is slightly complicated in such a case, it can be realized with a simple circuit configuration. Hereinafter, the case where the first-order term in the second-order quotient polynomial is 0 will be briefly described. Hijo polynomial Table 3, and the divisor polynomial, respectively, the dividend _{polynomial: M1 (Z) = A n} Z n + A n-1 Z n-1 + ·
.. + A ₁ Z + A ₀ division polynomial: M2 (Z) = B _n−2 Z ⁿ⁻² + B _n−3 Z ⁿ⁻³ +
.. + B ₁ Z + B ₀ , the coefficient data of the polynomial to be deleted is stored in the register 81a.
(The coefficient data of the maximum degree of the divisor polynomial is treated as a divisor in the division circuit 100, the normal division shown in the conventional example) and the coefficient data of the polynomial to be divided are stored. When the data is stored in the register 81b (the coefficient data of the maximum degree of the divisor polynomial is
In the case where the dividend is treated as a dividend). In the present embodiment, the circuit configuration shown in FIG. 11 is adopted as the configuration of the division circuit unit when performing the Euclidean operation. In order to explain the present embodiment, the first-order term of the quotient polynomial is set to 0.

[0214]

[Table 3]

Equation 11 shows coefficient data obtained by normalizing the quotient polynomial subjected to the ordinary division.

[0216]

[Equation 11]

Thus, when the coefficient data of the dividend polynomial is stored in the register 81b (when the coefficient data of the maximum degree of the divisor polynomial is treated as the dividend in the division circuit 100), the normalized quotient is calculated. When obtaining the polynomial, the quotient data output from the division circuit 100 is represented by P _i (i =
, K; k is the degree of the quotient polynomial, and the coefficient data of the quotient polynomial is Q _i (i = 0, 1,..., K; k).
Is the degree of the quotient polynomial), and P _{j to} P _m (0 <j ≦ m
Assuming that the data of <k) is 0, Q ₀ = 1 Q ₁ = Q ₀ × P ₀ Q ₂ = Q ₁ × P _{1 ···} Q _j = 0 _··· Q _{m + 1} = Q _j−1 × P _{j −1 ··} Q _k = Q _k−1 × P _k−1

FIG. 22 shows a circuit configuration of a part of an error position calculating circuit that calculates an error position polynomial that can cope with the case where 0 exists in the coefficients of the quotient polynomial. Fig. 21 for 120 to 125
Are omitted since they are the same as those shown in FIG. 126 is a shift register for storing flag data for identifying whether the maximum order coefficient data detected by the degree detection circuit 88 is 0 when the coefficient data stored in the register 81b is a polynomial to be removed, and 128 is a shift register. A register for latching the output of the register 126 to match the timing with the data, and a selector 127 for selecting the output of the register 125 and 0 based on the signal output from the register 128. Inverse ROM 120
, The multiplying circuit 121, the selectors 122, 124, 127, the shift registers 123, 126, and the registers 125, 128 constitute a part of the error position calculating circuit. Note that the configuration of the division circuit 100 shown in FIG. 11 used in the description of the present embodiment has the configuration shown in FIG. That is, when 0 is input to the data on the divisor side of the division circuit 100, 1 is output from the division circuit 100.

Next, the operation will be described. In FIG. 22, a coefficient of a zero-order quotient polynomial output from the division circuit 100 shown in FIG. Also,
In the shift register 123, coefficient data of the first-order or higher-order quotient polynomial output from the division circuit 100 shown in FIG. 11 is sequentially stored in ascending order. At the same time, when the register 81b is treated as a polynomial in the shift register 126,
The 0 detection flag detected by the order detection circuit 88 (in this embodiment, it is set to “H” when 0 is detected) is stored. Note that the 0 detection flag data is output when the coefficient data stored in the register 81b is used as a polynomial to be deleted or when the coefficient of the maximum degree of the polynomial to be deleted is 0. The selector 124 switches between the output of the inverse ROM 120 and the output of the register 125 based on the control signal output from the Euclidean arithmetic control circuit 101. Multiplication circuit 12
At 1, the output of the shift register 123 and the output of the selector 124 are multiplied.

The shift registers 123 and 126 are multiplication circuits.
Each time the multiplication is performed at 121, the data is sequentially shifted. The selector 122 selects the output of the multiplication circuit 121 based on the control signal output from the Euclidean arithmetic control circuit 101 when the coefficient data of the polynomial to be deleted is stored in the register 81a. In the case of being stored in the register 81b, first, the coefficient data of the zero-order quotient polynomial is output as it is, and when calculating the second and subsequent coefficients of the quotient polynomial, control is performed so that the output of the multiplication circuit 121 is selected. It is configured as follows. The output of the selector 122 is stored in the register 125. The selector 124 selects the output of the inverse ROM 120 when the register 81a shown in FIG. 11 is treated as a polynomial to be removed, and selects the output of the register 125 when the register 81b is treated as a polynomial to be removed. Is configured. Also,
The 0 flag data output from the shift register 126 is output by the register 128 in synchronization with the coefficient data of the quotient polynomial.

Now, the coefficient data of the polynomial to be deleted is stored in the register.
The case stored in 81a will be described. Division circuit
If the quotient data output from 100 is 0th order, the inverse ROM
The quotient data of the first order or higher inputted to the selector 120 and the selector 122 is stored in the shift register 123. It is assumed that "L" is stored in the shift register 126. If the data input to the inverse ROM 120 is 0, control is performed in this embodiment to treat the data as error detection. (Note that the same applies to the above embodiment.) The selector 124 is configured to select the output of the inverse ROM 120, the selector 122 selects the output of the multiplier 121, and the selector 127 selects the output of the register 125. ing. In this case, even when 0 is stored in the coefficient data of the quotient polynomial, 0 / (output of the inverse element ROM 120) is executed, and normalization is executed without any particular operation. As a result, normalization of the quotient polynomial when the coefficient data of the polynomial to be deleted is stored in the register 81a is executed.

Similarly, a case where the coefficient data of the polynomial to be deleted is stored in the register 81b will be described. If the quotient data output from the division circuit 100 is 0th order, the inverse RO
M120 and the quotient data of the first or higher order inputted to the selector 122 are stored in the shift register 123. At this time, the shift register 126 stores the 0 flag data detected by the order detection circuit 88. In this embodiment, the register 81b
Is output when the coefficient data of the maximum degree of the polynomial of the stored polynomial is 0. When the coefficient data of the 0th order of the quotient polynomial is 0, the error correction device is controlled so as to be treated as error detection in this embodiment. The selector 124 is controlled to select the output of the register 125. In the selector 122, based on the control signal output from the Euclidean arithmetic control circuit 101, first, coefficient data of the zero-order quotient polynomial is output as it is, and when calculating the coefficients of the quotient polynomial thereafter, the multiplication circuit 121 is used. Is controlled so as to select the output.
The output of the selector 122 is stored in the register 125. Thus, after the primary coefficient data of the quotient polynomial is output from the selector 122 as an initial value, Q _i × P _i is executed by the successive multiplication circuit 121 to obtain a quotient polynomial.

On the other hand, when the coefficient data of the quotient polynomial is 0 (that is, when the coefficient data of the dividend polynomial input as a divisor to the division circuit 100 is 0), the division circuit 100 calculates the division calculation power as described above. 1 is output, and at the same time, the 0 detection flag is output from the order detection circuit 88.
Therefore, when obtaining coefficient data of the quotient polynomial,
At 121, Q _i × 1 is executed, and Q _i is stored in the register 125. The 0 flag data output from the shift register 126 is output to the selector 127 by the register 128 at the same timing as the coefficient data of the quotient polynomial. The shift register 126 outputs 0 flag data, and the selector 127 selects 0. Then, when calculating the next quotient polynomial, Q _i × P _{i + 1} is executed.

According to this configuration, by controlling the shift register 126 for storing the 0 flag and the selectors 122, 124 and 127 as described above, it is possible to execute the above-described calculation and calculate coefficient data of the quotient polynomial. Therefore, the error locator polynomial can be calculated with a simple circuit configuration in which only the shift register 126 and the selectors 122, 124, 127 are added.

In the eighth embodiment, the configuration of the circuit for normalizing the quotient polynomial of the error locator polynomial calculation circuit when calculating the error locator polynomial is shown in FIGS.
The 0 and the multiplication circuit 121 may also be used as the division circuit 100 shown in FIG. 20 to reduce the circuit scale. Further, the shift register 123 may be used also as the registers 81a and 81b to reduce the circuit scale.

In the eighth embodiment, the circuit configuration of the error locator polynomial calculation circuit for calculating the error locator polynomial is shown in FIG.
Although the configurations shown in FIGS. 22 to 22 have been taken, the present invention is not limited to this configuration.In an error correction device having the circuit configuration shown in FIG. 11 or FIG. 14, the polynomial input to the division circuit 100 as the dividend is a divisor polynomial. The same effect can be obtained by a configuration in which the calculation method in the error position calculation circuit for calculating the error position polynomial is switched between the case where the error polynomial is used and the case where the error polynomial is used. For example, in the present embodiment, the coefficient data of the 0th order of the quotient polynomial is normalized to 1, but the coefficient of the maximum order of the quotient polynomial is set to 1
In the case of normalization to, the details of how to obtain the quotient polynomial are omitted, but the same can be obtained by switching the calculation method for obtaining the quotient polynomial in the error position calculating means as described above.

In the eighth embodiment, even when the quotient polynomial is quadratic or when the division result output from the division circuit 100 is 0, the quotient polynomial is calculated by the circuit configuration shown in FIG. 21 or FIG. However, if the quotient polynomial is of a certain order or higher, or if the coefficient data output from the division circuit 100 includes coefficient data of 0, the quotient polynomial is not calculated but is processed as error detection, thereby simplifying control and circuit scale. May be reduced.

Ninth embodiment. Hereinafter, a ninth embodiment of the present invention will be described. In this embodiment, the case where the error correction device shown in FIG. 11 is used will be described. FIG. 23 shows a block diagram of the ninth embodiment. This embodiment has a configuration in which a selector for calculating a correction syndrome required for performing erasure correction is added to the configuration of the core circuit of the error correction device shown in FIG. In the figure, 81a, 81b, 85-8
8, 95, 100 and 101 are the same as in FIG. 130, 131 and 132 are selectors, and 133 is an input terminal for inputting an erasure position. When the erasure correction is performed, the number of registers 81a and 81b for storing the above-described polynomial to be deleted and the polynomial to be divided is (maximum degree of the corrected syndrome + 1) because each coefficient data of the corrected syndrome is stored.
Registers are required for each dividend and divisor.

The erasure correction is a method used for error correction when the error position is known but the error value is not known. In short, the correction syndrome is calculated from the error position information, and this correction syndrome is also calculated. At this time, the Euclidean algorithm shown in FIG. 25 is executed to perform error correction. At that time, in the Euclidean algorithm, only the end condition is changed and the syndrome polynomial is replaced with the modified syndrome polynomial, and the others remain unchanged.
(For a detailed description of the Euclidean algorithm when there is an erasure, refer to pp.173-175 of "Coding Theory" above)

[0230] A method of calculating the above-mentioned modified syndrome will be briefly described below. Now, it was calculated from reproduced or received data syndrome polynomial S a (Z) S (Z) = S 15 Z 15 + S 14 Z 14 + S 13 Z 13 + ··· S 1
Z + S _0, and the position of the erasure is α ₀ ... Α _k .
At this time, the modified syndrome S (z) ′ is given by S (z) ′ = S (z) × ｛(Z + α ₀ ) × (Z + α ₁ )
× ... × (Z + α _k )｝

The modified syndrome S will be described below with reference to FIG.
The circuit operation for obtaining (Z) ′ will be described. When the syndrome generation is completed, each coefficient data of the syndrome polynomial is set in the register 81b in the core circuit of the Euclidean operation. At this time, the register position at which the coefficient of the maximum degree of the syndrome polynomial is stored changes depending on the number of erasures. When the coefficient data of the syndrome polynomial is set in the register 81b, the selector 130 outputs error position information by a control signal output from the Euclidean arithmetic control circuit 101.
The selector 131 is controlled so as to select the output of the register 81b, and the selector 132 is controlled so as to select the coefficient data of the syndrome polynomial having a high first order stored in the register 81b.
Then, by shifting the contents of the register 81b to the right, S (Z) × Z + S (Z) × α ₀ is executed. (Note that α ₀ indicates the position information of the erasure.) Equation 12 shows a specific handwriting result.

[0232]

(Equation 12)

[0233] Note that the maximum degree S ₁₅ is assumed to be configured to directly shift the coefficients for unchanged even if operation is performed. Also, the zero-order coefficient is configured to execute only S ₀ × α ₀ . Then, the correction syndrome is calculated by sequentially performing this operation. FIG. 24 shows the connection state of the selectors 131 and 132 when calculating the correction syndrome. This diagram shows a connection state of a part of the circuit shown in FIG. As shown in the figure, in the present embodiment, the register 81a does not operate when calculating the correction syndrome.

When the calculation of the modified syndrome is completed, FIG.
The selector 130 switches the selector 130 to select the output of the divider circuit 100 and the selector 131 to select the output of the register 81a. Further, the selector 132 is switched so as to select the output of the register 81b of the same order, and the connection of each component becomes the same as that shown in FIG. On the other hand, the Euclidean arithmetic control circuit 101 sets the end condition u shown in FIG. 25 from u = t to u = (2 × t + k) / 2 based on the number of erasures when obtaining the correction syndrome. Here, k is the number of symbols to be subjected to erasure correction.

First, when the Euclidean operation is started, based on the Euclidean operation start signal output from the Euclidean operation control circuit 101, the initial value of the coefficient of the polynomial Z ^{2t to} be removed is stored in the register 81a. The modified syndrome polynomial S, which is a divisor polynomial, is stored in the register 81b.
Each coefficient data of (Z) ′ is stored. In addition, the counters of the order detection circuits 87 and 88 each have the initial value of the order.
16 and 15 are set. The counters in the order detection circuits 87 and 88 are registers that store the coefficient data of the polynomial to be removed.
Each time the value 81 is shifted once, the count value is decreased by one. At the same time, the modified syndrome polynomial, which is a divisor polynomial, is determined by the order detection circuit 88 to determine whether the coefficient data of the highest order is zero. In the Euclidean arithmetic control circuit 101, when the coefficient of the maximum degree of the divisor polynomial (corrected syndrome polynomial) detected by the degree detector 88 is 0, a register 81 storing coefficient data of the divisor polynomial is stored.
The content of b is shifted (in this case, the content of the register 81b is shifted as it is without performing the addition operation in the addition circuit 86). The shift operation is repeated until the data of the maximum order is not 0. At this time, the counter in the order detection circuit 88 changes the count value by one each time the shift operation is performed.
It is reduced one by one.

Similarly to the fifth embodiment, the register 81a storing the coefficient data of the polynomial to be deleted is configured so that the output of the adder circuit 86 is latched when a clock is input. The register 81b in which the polynomial coefficient data is stored is configured to hold the coefficient data. This operation is repeated until the degree of the dividend polynomial becomes smaller than the degree of the divisor polynomial.

In the Euclidean arithmetic control circuit 101, based on the degree of the remainder polynomial output from the degree detection circuit 87 (or 88), the degree of the remainder is newly set when performing the erasure correction. If the end condition is not satisfied, the Euclidean operation is ended. If the end condition is not satisfied, the operation is executed with the polynomial that was the divisor polynomial in the previous operation as the polynomial to be removed and the remainder polynomial as the divisor. Since there is no switching means as in the conventional example, the connection state of the circuit does not change, but the clock 1 supplied to the register 81a is stopped and the clock 2 is supplied to the register 81b. Therefore, the contents of the register 81a are held, and the coefficients of the remainder polynomial are sequentially stored in the register 81b.

At this time, in the division circuit in the Euclidean arithmetic circuit, the order detection circuit 88 determines whether the maximum degree of the dividend polynomial (remainder polynomial) is 0, and if it is 0, the result is stored in the register 81b. A control signal is output so that the contents of the polynomial to be deleted (remainder polynomial) are shifted by one. This is because when the register for storing the divisor and the dividend to be output to the division circuit 100 is determined and the coefficient data of the dividend polynomial is used as the divisor, if the coefficient of the maximum degree of the dividend polynomial becomes 0, the dividend This is because (the largest coefficient of the divisor polynomial) is divided by 0, and the solution (output) may become indefinite. In this embodiment, since the configuration of the division circuit 100 is the configuration shown in FIG. 18, even when the coefficient data of the maximum order is 0, the division operation can be performed without much concern.

Similarly to the above example, the division is performed by repeating the shift operation while calculating the contents of the register storing the coefficient data of the polynomial to be divided until the degree of the remainder of the polynomial to be divided is smaller than the degree of the polynomial. Execute. And
The order of the remainder polynomial is determined, and if the predetermined condition is not satisfied, the clock supplied to the registers 81a and 81b is switched to perform the division operation based on the Euclidean algorithm again. Thus, when decoding a Reed-Solomon code, division between polynomials on a Galois field based on the Euclidean algorithm that also considers erasure correction can be performed for each polynomial, thereby improving the error correction processing speed. As much as possible, since there is no exchange means (selector), the circuit scale can be reduced, and selector control is not required.

In the fifth to ninth embodiments , the Reed-Solomon code having a minimum Hamming distance of 17 used for an optical disk or the like has been described. However, the present invention is not limited to this. To play. Further, with the circuit configuration shown in the above embodiment, two or more kinds of Reed-Solomon codes having different minimum Hamming distances can be decoded. For example, the Reed-Solomon code of the product code format can be decoded by changing the initial value and the end condition of the Euclidean algorithm with the same circuit.

In each embodiment, the case where the Reed-Solomon code is used as the error correction code has been described.
Similar effects can be obtained by decoding other linear error correction codes such as a CH code using the above-described division circuit.

In each of the embodiments, when performing the division operation, the register
Clocks 1 and 2 are used for shifting 81a and 81b and holding data.
However, the present invention is not limited to this. For example, a selector is provided at the input of the registers 81a and 81b,
The selector may control the register on the polynomial side to latch its own output and the register on the polynomial side to latch the output of the adder 86.

In addition, the exchange decision between the polynomial to be divided and the polynomial to be divided is not limited to the method of detecting the degree difference between the polynomials output from the degree detection circuits 87 and 88. For example, before starting the division, the difference between the degree of the dividend polynomial and the degree of the divisor polynomial is determined in advance, and based on this information, the number of shifts of the division circuit is uniquely determined, and division is performed without detecting the degree difference. May be used.

In each embodiment, when the order of a syndrome polynomial, a remainder polynomial, or the like is detected, the registers 81a, 8
Although the order detection circuits 87 and 88 are connected and detected only to the register in which the coefficient of the maximum order in 1b is stored, the present invention is not limited to this. For example, the coefficient determination circuit is stored in the register 81 that stores each coefficient data. (A circuit for determining whether or not the coefficient data is 0) may be provided to perform the order determination.

Although the details are omitted, it goes without saying that the above circuit configuration can also be applied to, for example, remainder decoding and the like other than the Euclidean algorithm.

[0246]

As described above, the error correction apparatus according to the first aspect of the present invention provides an error correction apparatus for correcting an error occurring in a signal encoded by an error correction code which is a linear code added to an input signal in advance. A syndrome generating means for generating a syndrome dependent only on an error contained in a reproduced or received signal from a unit information block to which an error correction code is added, and an error position based on the generated syndrome. Error position / numerical polynomial calculating means for calculating a polynomial σ (z) and an error numerical polynomial ω (z); error position calculating means for calculating an error position based on the calculated error position polynomial σ (z); Error correction means for performing error correction on the basis of the calculated error numerical polynomial ω (z) and error position information, wherein at least error correction means for error correction; Since the three processing operations of the position / numerical polynomial calculation means and the error position calculation means are operated in parallel, for example, when decoding processing is performed on one error correction block shown in FIG. Processing can be completed at a speed.

In the error correction device of the second invention, the clock for driving the syndrome generating means and the error position calculating means, which can achieve relatively high speed, is a clock having a higher frequency than the clock for driving the error position / numerical polynomial calculating means. Since it is configured to be driven, the decoding time required to decode one error correction block can be reduced, and the processing speed can be increased.

The error correcting apparatus according to the third aspect of the present invention increases the number of steps of the error position / numerical polynomial calculation means in accordance with the number of steps of the syndrome generation means and the error position calculation means which require a relatively large number of steps for calculation. Since the scale is increased, the circuit scale can be reduced without impairing the decoding speed of the entire error correction device.

Further, the error correction device according to the fourth invention reads out erroneous data based on the error position information output from the error position calculation means when the error correction means corrects the data in the RAM. Since the error-corrected data is configured to be sequentially written into the RAM, the
When performing error correction of a symbol, data reading from the RAM, error correction, and data writing to the RAM can be performed in at least three steps in two steps, thereby increasing the speed of the error correction device. . Therefore,
Since the configuration is such that data access to the RAM, which is a bottleneck in speeding up, is always performed, it is possible to configure the highest-speed error correction device while minimizing an increase in circuit scale.

The error correcting apparatus according to a fifth aspect of the present invention divides a given polynomial by a polynomial, further divides the remainder as a polynomial, and divides the polynomial as a polynomial to obtain the degree of the polynomial of the remainder. A register for storing each coefficient data of the polynomial and the polynomial in an error correction device that performs an error correction process using a Reed-Solomon code including a process of Euclidean mutual repetition that repeats the above operation until a certain condition is satisfied. Are arranged in the form of a shift register,
A division circuit for dividing the coefficients of the maximum degree of the two polynomials with each other; a multiplication circuit for multiplying the output of the division circuit by the polynomial coefficient data set on the divisor side of the division circuit; an output of the multiplication circuit and a division circuit And an adder circuit for adding coefficient data of the polynomial set on the dividend side, and sequentially shifting the contents of the register storing the coefficient data of the dividend polynomial when performing division on the Galois field. Is configured to execute division based on the Euclidean mutual division process, so when performing division between polynomials on the Galois field in the Euclidean mutual division process, there is no selector for exchanging coefficient data of each polynomial. In addition, since the division is performed during the Euclidean mutual division process, the circuit scale can be reduced, and the selector control becomes unnecessary, so that the circuit can be simplified.

In the error correction device according to the sixth invention, the multiplication circuit is arranged in a group of registers for setting the initial value Z ^2t in the Euclidean mutual division process so as to reduce the number of multiplication circuits. The number of multiplication circuits can be reduced by one, and the circuit scale can be reduced to about 400 gates as described above.

Further, the error correction device according to the seventh aspect of the present invention is configured such that when the coefficient of the maximum degree of the polynomial input as the divisor is 0, the output of the division circuit is output as 1 in the division circuit. Even when the maximum degree of a polynomial to be divided or a divisor polynomial is 0 in the Euclidean arithmetic control circuit, it is possible to execute an arithmetic operation between polynomials on a Galois field in the Euclidean algorithm without adding special control, thereby simplifying the control circuit. I can do it.

The error correcting apparatus according to the eighth invention calculates the error locator polynomial σ (Z) using the output of the division circuit.
Since the calculation method is switched between a case where coefficient data of the highest degree of the dividend polynomial input to the division circuit is treated as a divisor and a case where the coefficient data is treated as a dividend, an error locator polynomial is accurately calculated. At the same time, the number of decoding steps can be reduced.

The error correcting apparatus according to the ninth aspect of the present invention is characterized in that the output of the dividing means and the first selecting means for selecting the error position information, and the output of the storing means for storing the coefficients of the polynomial on the divisor side of the dividing means. A second selecting means for selecting an output of a storage means for storing coefficient data of a polynomial on the dividend side of the dividing means, and a dividing means having a higher order degree than the coefficient of the polynomial on the divisor side of the dividing means. Selecting means for selecting a coefficient of a polynomial on the divisor side, multiplying means for multiplying an output of the first selecting means and an output of the third selecting means, an output of the multiplying means and a second selecting means Adding means for adding the output of the dividing means to the corrected syndrome polynomial at the time of erasure correction, wherein the first, second and third selecting means respectively provide error position information and a polynomial on the divisor side of the dividing means. Coefficient data and polynomial with high first order Since the configuration is such that the coefficients are selected, the correction syndrome polynomial to be calculated when performing erasure correction can be calculated simply by adding a selector circuit. Can respond.

[Brief description of the drawings]

FIG. 1 is a block diagram of an error correction device according to the present invention.

FIG. 2 is a timing chart for explaining a circuit operation of the error correction device shown in FIG.

FIG. 3 is a block diagram of another error correction device of the present invention.

FIG. 4 is a timing chart for explaining a circuit operation of the error correction device shown in FIG. 3;

FIG. 5 is a block diagram of a polynomial division circuit on a Galois field of the Euclidean operation circuit.

6 is a timing chart for explaining a circuit operation of the division circuit shown in FIG.

FIG. 7 is a timing chart for explaining the operation of the entire error correction device.

FIG. 8 is a block diagram of another division circuit of the polynomial on the Galois field of the Euclidean operation circuit.

FIG. 9 is a timing chart for explaining a circuit operation of the error correction circuit.

FIG. 10 is another timing chart for explaining the circuit operation of the error correction circuit.

FIG. 11 is a block diagram of another division circuit that divides polynomials on a Galois field when performing Euclidean operation of the error correction device of the present invention.

12 is a diagram for explaining a circuit operation of the division circuit shown in FIG.

13 is a diagram for describing a circuit operation of the division circuit shown in FIG.

FIG. 14 is a block diagram of another division circuit that divides polynomials on a Galois field when performing the Euclidean operation of the error correction device of the present invention.

15 is a diagram for explaining a circuit operation of the division circuit shown in FIG.

16 is a diagram for explaining a circuit operation of the division circuit shown in FIG.

17 is a diagram for explaining a circuit operation of the division circuit shown in FIG.

FIG. 18 is a block diagram of a division circuit in the error correction device of the present invention.

FIG. 19 is a block diagram of an adder circuit in the error correction device of the present invention.

FIG. 20 is a circuit configuration diagram of an error position calculation unit in the error correction device of the present invention.

FIG. 21 is a circuit configuration diagram of another error position calculating means in the error correction device of the present invention.

FIG. 22 is a circuit configuration diagram of still another error position calculating means in the error correction device of the present invention.

FIG. 23 is a block diagram of a division circuit that divides polynomials on a Galois field when performing an Euclidean operation of the error correction device of the present invention in consideration of erasure correction.

FIG. 24 is a circuit connection diagram for explaining a circuit operation of the error correction device of the present invention.

FIG. 25 is a flowchart illustrating the operation of the Euclidean algorithm.

FIG. 26 is a block diagram of a conventional error correction device.

FIG. 27 is a block diagram of a syndrome generation circuit.

FIG. 28 is a block diagram of a conventional error correction operation circuit.

FIG. 29 is a block diagram of a polynomial division circuit on a Galois field of a conventional Euclidean operation circuit.

FIG. 30 is a block diagram of a Chien search circuit.

FIG. 31 is a flowchart showing a procedure of encoding and decoding using an error correction code.

FIG. 32 is a configuration diagram of an error correction code employed in a home digital VTR.

FIG. 33 is a configuration diagram of one line in a recording direction of the error correction code illustrated in FIG. 32;

FIG. 34 is a timing chart for explaining the operation of the conventional error correction device.

FIG. 35 is a timing chart for explaining a circuit operation of a conventional error correction device.

FIG. 36 is a timing chart for explaining the operation of the conventional error correction device .

FIG. 37 is a block diagram of a division circuit that divides polynomials on a Galois field when performing a Euclidean operation in a conventional error correction device.

FIG. 38 is a diagram for explaining the operation of a conventional division circuit for performing division between polynomials on a Galois field.

FIG. 39 is a diagram for explaining the operation of a conventional division circuit for performing division between polynomials on a Galois field.

FIG. 40 is a diagram for explaining the operation of a division circuit for performing division between polynomials on a Galois field when performing a Euclidean operation in a conventional error correction device.

FIG. 41 is a diagram for explaining the operation of a division circuit for performing division between polynomials on a Galois field when performing a Euclidean operation in a conventional error correction device.

[Explanation of symbols]

 1 RAM 2 syndrome generation circuit 20 Euclidean operation circuit 21 Chien search circuit 22 error correction circuit 41 error correction device control circuit 81a, 81b register 85 multiplication circuit 86 addition circuit 100 division circuit 101 Euclidean operation control circuit 130 selector 131 selector 132 selector

Continuation of the front page (72) Inventor Junko Ishimoto 1 Baba Zoshosho, Nagaokakyo City, Kyoto Prefecture Mitsubishi Electric Corporation Electronic Product Development Laboratory (56) References JP-A-1-236735 (JP, A) JP-A-1 Japanese Patent Application Laid-Open No. 63-16929 (JP, A1) JP-A-3-163973 (JP, A) JP-A-3-121627 (JP, A) JP-A-3-166826 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 13/00 G11B 20/00 H04L 1/00

Claims (7)

(57) [Claims] 1. An error correction device for performing error correction using an error correction code which is a linear code added to input data, a storage means for storing the input data, and an input read from the storage means. Syndrome generating means for generating a syndrome from the data, calculating means for calculating an error locator polynomial and an error numerical polynomial based on the output of the syndrome generating means, and calculating an error position from the error locating polynomial derived from the calculating means An error value is derived using an error position calculating means, an error position information output from the error position calculating means, and an error numerical polynomial output from the calculating means, and an error position in the input data is detected. Error correction means for performing error correction on erroneous data; data writing and data reading to the storage means; Control means for controlling the operations of the error generating means, the error position calculating means and the error correcting means, and when an error occurs in the input data, the calculating means
Necessary for calculating the error locator polynomial and the error numerical polynomial.
The required time is calculated by the syndrome generation means.
The time required to generate the system and the error correction means
Necessary for performing error correction on erroneous data in input data.
The arithmetic means is configured so that the sum is equal to or less than the required time.
When performing error correction on the input data stored in the storage means, the control means detects the end of the operations of the syndrome generation means, the calculation means, and the error position calculation means, An error correction device, wherein at least the syndrome generation means, the calculation means, and the error position calculation means are controlled to start at substantially the same time based on the detection result. 2. A linear code added to input data.
An error correction device that performs error correction using a certain error correction code
A storage means for storing the input data;
Syndrome from input data read from storage
Syndrome generation means for generating the syndrome
Error position polynomial and error numerical polynomial based on the output of the means
And an error derived from the arithmetic means
Error position calculating means for calculating an error position from a position polynomial
And error position information output from the error position calculation means.
Using the error numerical value polynomial output from the arithmetic means
Deriving the error value and detecting the error position in the input data
And error correcting means for performing error corrections to incorrect data, the
When the error correction means performs error correction on the input data,
All erroneous input data based on the error location information is
After the data has been read from the storage means,
Data with erroneous input data based on the error location information
Control means for controlling the error correction means to rewrite
DOO erroneous Ri correction device you comprising: a. 3. Generating a predetermined dividend polynomial from input data
The calculated syndrome polynomial is divided as a polynomial, and
After the remainder as a polynomial,
The operation of dividing a polynomial as a dividend polynomial is called the remainder polynomial.
Euclidean to repeat until degree of expression satisfies certain conditions
Error locations from syndrome polynomials using an algorithmic process
Calculate and calculate the coefficients of the set polynomial and the error numerical polynomial.
Error correction in the input data using the coefficients of each polynomial
In the error correction device, the coefficients of the predetermined polynomial
First storage means for storing in order from a higher order,
Increase the coefficient of the syndrome polynomial generated from the force data.
A second storage means for storing in order from the next order;
Coefficient of the maximum degree of the polynomial stored in the storage means of No. 1
Is the maximum order of the polynomial stored in the second storage means.
Division means for performing a division on a Galois field by a coefficient of a number;
The output of the stage and the output of said second storage means except for the maximum order;
Multiplication on the Galois field by
The output of the first storage means in which the coefficient is stored and the maximum
Before being connected to the output of said second storage means except for the order
The multiplication means is stored in the first and second storage means.
Pairing from higher order coefficients
The output of the first storage means and the output of the multiplication means
Adding means for adding on the Galois field, wherein the adding means is provided in the first storage means and the second storage means.
When performing division on the Galois field between polynomials
The first storage means in which each coefficient of the dividend polynomial is stored
Before the first-order lower coefficient is stored as the storage content on the column side
The adding means connected to the output of the first storage means;
Mis Ri correction device it said that you have no to control so as to store the output of. 4. The method according to claim 1, wherein said multiplying means uses an Euclidean algorithm.
When performing division between polynomials, Z ^2t is used as an initial value.
4. The error correction device according to claim 3, wherein the error correction device is arranged on the first storage means side to be set . 5. The division means inputs as a divisor.
If the coefficient of the maximum degree of the polynomial is 0,
Claim, characterized in that one output of the dividing means 3 or
Or the error correction device according to 4 . 6. An error locator polynomial from an output of said division means.
When calculating, the polynomial of the dividend input to the division means
Coefficients treated as divisors and dividends
Claims characterized in that the operation method is switched depending on the case.
The error correction device according to 3, 4 or 5. 7. An output of said division means and error location information are
First selecting means for selecting and an output of the first storage means
And the output of the second storage means are paired from the higher order.
Second selection means for performing selection by performing
Polynomial coefficients stored in the means and their first order
Of the polynomial stored in the second storage means, where
Third selecting means for selecting a number, and the first selecting means
Multiplying means for multiplying the output of the third selecting means by the output of
A stage, an output of the multiplying means and an output of the second selecting means.
And addition means for adding
When calculating the syndrome polynomial, the first, second and
3 are respectively selected from the error position information and the second
Select the output of the storage means and the coefficients of the polynomial with a high first order
7. The error correction device according to claim 3, wherein the error correction device is configured to be configured as follows .