CN107688506A - A kind of BCH decoding systems of flowing structure - Google Patents

Abstract

The invention discloses a BCH decoding system with a pipeline structure, which belongs to the technical field of computer storage error correction. The system of the present invention includes: a parallel syndrome calculation module, which is used to calculate the syndrome in parallel according to the received data; a key equation solving-parallel chien search module, which is used to calculate the key equation according to the syndrome, and find out the solution of the key equation ; The FIFO memory module is used to buffer the data read from the NAND Flash chip, and when calculating the solution of the key equation, gradually output the data in the FIFO memory module; the BCH decoding controller module is used to realize the BCH decoding two Parallel execution of stage pipelines. The system of the invention multiplexes hardware resources in different modules of the BCH decoder and adopts a parallel pipeline structure for BCH decoding, which can effectively increase the throughput rate of BCH decoding and reduce hardware overhead.

Description

A Pipeline Structured BCH Decoding System

technical field

The invention belongs to the field of computer storage error correction, and more specifically relates to a BCH decoding system with a pipeline structure.

Background technique

With the wide application of non-volatile storage devices using NAND Flash as the medium, single-layer NAND Flash can no longer meet the requirements of large-capacity and low-cost storage. The new generation of multi-layer memory has low unit cost, high storage density, and large storage capacity. It is increasingly used in non-volatile storage systems. However, due to the increasingly smaller distance between the chip process and adjacent programming levels, the raw bit error rate (RBER) of NAND Flash has increased sharply. Traditional error-correcting codes have Unable to meet reliability requirements. As a cyclic code, BCH (Bose, Ray-Chaudhuri, Hocquenghem) code has excellent performance and simple structure, and is an error correction code technology widely used in storage systems. When writing data to the NAND Flash chip, the original data passes through the 8-bit parallel BCH encoder, and after the data encoding is completed, it is written into the NAND Flash chip. When reading data from the NAND Flash chip, the 8-bit parallel read data is read from the chip. And input to the BCH decoder at the same time, if the number of stored data errors is less than the maximum number of errors that can be corrected by the BCH code, the correct original data will be output, and if the number of data errors is higher than the maximum number of errors that can be corrected by the BCH code, the decoding will be reported fail.

The encoding process of the BCH code is relatively simple, and it is realized by using a linear feedback shift register (LFSR). The decoding process of the BCH code is mainly divided into three steps, which are syndrome calculation, key equation solving and Chien search. Among them, the key equation solving process is complicated and consumes a lot of hardware logic resources. It is the core module in the BCH decoding circuit. The current research mainly focuses on reducing the implementation complexity of the key equation solving circuit and improving the decoding of the BCH decoder. The speed is mainly achieved through parallelization. By parallelizing the syndrome calculation and the Chien search algorithm in the decoding process, the decoding speed of BCH can be significantly improved. However, the separate research on each module of the BCH decoder does not consider the sharing of circuit resources in the BCH decoder as a whole, resulting in a large amount of hardware resource overhead. At present, a research team has proposed a syndrome-Qian search block circuit structure that shares hardware resources, which can reduce the overall hardware complexity of the BCH decoder, but it cannot implement the pipeline execution of the decoding process, which restricts the improvement of performance. .

Contents of the invention

In view of the above defects or improvement needs of the prior art, the present invention provides a BCH decoding system with a pipeline structure, the purpose of which is to consider the hardware design of the BCH decoder and the characteristics of data reading in SSD storage devices as a whole, By multiplexing the hardware resources in different modules in the BCH decoder, the parallel pipeline structure is used to decode the BCH, thereby reducing the hardware overhead of the BCH decoder and improving the decoding speed of the BCH decoder.

In order to achieve the above object, according to one aspect of the present invention, a BCH decoding system with a pipeline structure is provided, and the system includes:

Parallel syndrome calculation module, used for calculating the syndrome in parallel according to the received data;

Key equation solving-parallel Chien search module, used to calculate key equations based on syndromes, and find the solution of key equations by searching key equation roots, and reuse finite fields in the process of calculating key equations and searching key equation roots multiplier;

The FIFO memory module is used to cache the data read from the NAND Flash chip, and gradually output the data in the FIFO memory module when calculating the solution of the key equation;

The BCH decoding controller module is used to realize the parallel execution of the BCH decoding two-stage pipeline: at the first stage of the pipeline, data is read from the NAND Flash chip and simultaneously written into the parallel syndrome calculation module and the FIFO memory module; In the second stage of the pipeline, the syndrome obtained in the parallel syndrome calculation module is input into the key equation solving-parallel Chien search module, and the data in the FIFO memory module is gradually output, and the FIFO is corrected according to the obtained key equation solution Incorrect data output in the memory module.

Further, the parallel syndrome calculation module is specifically used for:

Accept the data read from the NAND Flash chip, calculate the remainder of the minimum polynomial corresponding to the data in parallel according to the read data, and calculate the value of the corresponding syndrome according to the remainder.

Further, the key equation solving-parallel Chien search module is specifically used to use the SIBM algorithm to calculate the key equation, and use the Chien search algorithm to search for the root of the key equation.

Generally speaking, compared with the prior art, the above technical solution conceived by the present invention has the following technical characteristics and beneficial effects:

(1) Reduce the hardware overhead of decoding by multiplexing the finite field multiplier in the process of calculating the key equation and searching for the root of the key equation;

(2) The parallel execution of the two-stage pipeline for BCH decoding is realized, which improves the decoding efficiency and throughput.

Description of drawings

Fig. 1 is the structural representation of the embodiment of technical scheme of the present invention;

Fig. 2 is a schematic circuit diagram of a parallel calibration sub-module in an embodiment of the present invention

Fig. 3 is the SIBM algorithm circuit schematic diagram of the embodiment of the present invention;

4 is a schematic diagram of a parallel chien search circuit according to an embodiment of the present invention;

Fig. 5 is the key equation solving-parallel chien search circuit schematic diagram of the embodiment of the present invention;

Figure 6 (a) is a schematic diagram of BCH decoding without pipeline according to an embodiment of the present invention;

Figure 6(b) is a schematic diagram of the BCH decoding pipeline according to the embodiment of the present invention;

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

First explain and illustrate the technical terms of the present invention, and make the following provisions in the follow-up description:

BCH (n, k, t) code: indicates that the code word length is n bits (n<=2 ^m -1, m is a positive integer, when n=2 ^m -1, the BCH code is a standard BCH code), information The bit length is k bits, and the redundant bit information bits are r bits (r=nk), and t represents the error correction capability of the error correction code, indicating that any errors less than t bits in the n bits of the codeword can be corrected .

BCH shortened code: For all BCH codewords with n<2 ^m -1, it is a shortened code of the standard BCH code. A shortened BCH code can be regarded as a standard BCH code with a high-order sequence of 0, so the shortened The error correction capability of the BCH code remains unchanged.

As shown in Figure 1, it is a structural schematic diagram of an embodiment of the present invention, including a parallel syndrome calculation module, a key equation solving-parallel Chien search module, a FIFO memory module and a BCH decoding controller module;

The parallel syndrome calculation module is used to calculate the encoding syndrome. For the BCH (n, k, t) code, the parallel syndrome calculation module calculates 2t syndromes defined as follows:

Among them, S _i represents the i-th syndrome; α ⁱ represents the i-th element in the finite field; R(α ⁱ ) represents the acceptance polynomial, N represents the maximum power exponent of the remainder polynomial, r(α ⁱ ) ^represents the corresponding The remainder of the minimum polynomial; r _j (α ⁱ ) represents the value of degree j in the remainder polynomial.

An 8-bit parallel syndrome calculation module circuit diagram is shown in Figure 2, the data is input in 8-bit parallel mode, and the parallel syndrome calculation module keeps the intermediate results in the register (Parity Reg), after completing the data input, the register ( The value in Parity Reg) is r(x), and α ⁱ is substituted into r(x) to get the required syndrome.

The key equation solving-parallel Chien search module is used to solve the key equations of BCH decoding and search for the roots of the key equations. The SIBM algorithm is used to solve the key equations of BCH decoding, and the Chien search algorithm is used to search for the roots of the key equations. The key equation solving-parallel chien search module uses 2t syndromes S _i , 0<i<2t as input, solves the key equation and judges whether a certain data bit is wrong by searching the form of the root of the key equation.

The schematic diagram of the SIBM algorithm circuit is shown in Figure 3. The syndrome S _i , 0<i<2t, is gradually shifted into the SIBM algorithm circuit in the form of a shift register. According to the SIBM algorithm, the circuit shown in Figure 3 needs to use 2t The general finite field multiplier can calculate the key equation after t iterations.

The schematic diagram of the 8-bit parallel chien search circuit is shown in Figure 4. The 8-bit parallel chien search circuit needs to use (8+1) t constant finite-field multipliers in total, and the parallel chien search circuit receives input from the SIBM algorithm circuit. The key equation, after the initialization is completed, the intermediate result is stored in the register D. The result of Chien_result marks whether the data bit is wrong, and the entire codeword (or information bit) can be searched after n (or k) iterations.

The key equation solving-parallel Qian’s search module circuit schematic diagram is shown in Figure 5. After the SIBM algorithm calculates the key equation, it directly calculates the value of the key equation after h iterations according to the number of digits h shortened by the BCH shortening code. To speed up the chien search, multiplex the general finite field multiplier in the SIBM circuit module in the chien search circuit module to complete the iterative calculation of the chien search. In this embodiment, the key equation solving-parallel chien search block A total of 2t general finite field multipliers and 6t constant finite field multipliers are used, which can reduce the use of 3t constant finite field multipliers compared with discrete SIBM algorithm circuits and 8-bit parallel Chien search circuits.

The FIFO memory module is used to cache the data read from the NAND Flash chip, and when executing the Chien's search iterative algorithm, gradually output the data in the FIFO memory module.

The BCH decoding controller module is used to control the data interaction between the parallel syndrome calculation module, the key equation solving-parallel Chien search module and the FIFO memory module. According to the characteristics of the NAND Flash page, there are usually multiple BCH code words in a NAND Flash page, and the BCH decoding controller module is used to realize the parallel execution of the two-stage pipeline of multiple BCH code words in one page. Among them, the parallel syndrome calculation is the first stage of the pipeline, and the key equation calculation-parallel Chien search is the second stage of the pipeline. The schematic diagram of BCH decoding without pipeline is shown in Figure 6(a), and the schematic diagram of pipeline is shown in Figure 6(b). When the NANDFlash chip reads data, the BCH decoding controller module writes the data into the parallel syndrome calculation module and the FIFO memory module at the same time, corresponding to the parallel syndrome calculation in Figure 6(b), the first codeword read After the output is completed, the syndrome obtained by the syndrome calculation module is input into the key equation solving-parallel Chien search block, and the subsequent read codewords are simultaneously written into the parallel syndrome calculation module and the FIFO memory module, and start For the decoding operation of the next code word, when the Qian's search module iterates, it outputs the data in the FIFO memory module and corrects the wrong data according to the search result.

It is easy for those skilled in the art to understand the above content. The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention etc., should be included within the protection scope of the present invention.

Claims (3)

1. a BCH decoding system of pipeline structure, is characterized in that, described system comprises: Parallel syndrome calculation module, used for calculating the syndrome in parallel according to the received data; Key equation solving-parallel Chien search module, used to calculate key equations based on syndromes, and find out the solutions of key equations by searching the roots of key equations, with limited reuse in the process of calculating key equations and searching for keys. domain multiplier; The FIFO memory module is used to cache the data read from the NAND Flash chip, and gradually output the data in the FIFO memory module when calculating the solution of the key equation; The BCH decoding controller module is used to realize the parallel execution of the BCH decoding two-stage pipeline: at the first stage of the pipeline, data is read from the NAND Flash chip and simultaneously written into the parallel syndrome calculation module and the FIFO memory module; In the second stage of the pipeline, the syndrome obtained in the parallel syndrome calculation module is input into the key equation solving-parallel Chien search module, and the data in the FIFO memory module is gradually output, and the FIFO is corrected according to the obtained key equation solution Incorrect data output in the memory module. 2. The BCH decoding system according to claim 1, wherein the parallel syndrome calculation module is specifically used for: Accept the data read from the NAND Flash chip, calculate the remainder of the minimum polynomial corresponding to the data in parallel according to the read data, and calculate the value of the corresponding syndrome according to the remainder. 3. The BCH decoding system according to claim 1, wherein the key equation solving-parallel Chien search module is specifically used to use the SIBM algorithm to calculate the key equation, and use the Chien search algorithm to search for the root of the key equation.