CN110875746A

CN110875746A - Hardware architecture of high-speed GII decoder

Info

Publication number: CN110875746A
Application number: CN201811016480.5A
Authority: CN
Inventors: 王中风; 李文杰; 林军
Original assignee: Nanjing University
Current assignee: Nanjing University
Priority date: 2018-08-29
Filing date: 2018-08-29
Publication date: 2020-03-10

Abstract

The invention discloses a hardware architecture of a high-speed Generalized Integrated Interleaved (GII) code decoder. The existing literature only stays in a software level for the research of the decoding algorithm of the GII, and the invention firstly proposes the hardware architecture of the GII decoder. The architecture fully utilizes the characteristics of the GII code and has extremely high speed. In order to meet the requirement of high throughput rate, full parallelism is adopted on an interlace level; and on the symbol level, the syndrome computing unit, the nested syndrome computing unit, the chien search unit and the numerical value computing unit all adopt partial parallelism. Aiming at two parts of calculation of nested syndromes and key equation coefficient updating in an algorithm, the invention designs a corresponding high-efficiency hardware architecture. In the inverse matrix multiplication module, complex matrix inversion is avoided, and a lookup table is used for realizing the inverse matrix multiplication. The framework can achieve extremely high throughput rate, and is very suitable for being applied to scenes requiring high-speed and low-power FEC schemes by considering extremely low decoding complexity of the GII code.

Description

Hardware architecture of high-speed GII decoder

Technical Field

The invention relates to the technical field of integrated circuits and communication, in particular to a hardware architecture of a high-speed GII decoder.

Background

The Generalized Integrated Interleaved (GII) code is a multilevel code that has been proposed to address error correction in distributed storage systems. The GII code is flexible in structure, and can be selected according to performance indexes regardless of code length, layer number or check bits. The most primitive GII code is ambiguous in coding algorithm and very complex in decoding algorithm, which has been ignored for a long time by academia. In recent years, a GII coding algorithm and a more efficient decoding algorithm have been proposed in succession, so that GII code re-emphasis has been brought to relevant researchers.

The decoding algorithm of the GII code is a layered decoding algorithm, and the characteristic enables the GII code to be decoded in the first layers when errors are few, so the corresponding decoding complexity is low, and the power consumption of the decoder is also at a lower level. On the other hand, the GII code adopting the BM correlation algorithm can multiplex the previous results in the decoding process, so that the iteration times of the BM are greatly reduced, and the GII decoder has extremely low decoding delay due to the characteristic.

At present, the GII code research only stays in the application of a storage system and in the software implementation stage, and various communication systems such as optical communication and the like all want to have an error correction code decoder with high throughput, low delay and low power consumption. Therefore, the GII code has great potential, becomes an error correction code scheme in communication standards such as Ethernet and the like, and has great significance for the research on the hardware architecture of the GII decoder.

Disclosure of Invention

The invention provides a hardware framework of a GII decoder for the first time, and the framework aims to meet the requirements of high-speed communication systems with throughput rates of more than or equal to 100Gbps such as Ethernet and the like on the decoder.

The corresponding GII decoding hardware architecture mainly comprises the following parts:

● syndrome calculation unit, for the whole GII code word, the syndrome parallel calculation of all interlaces; for a single interleaver, J symbols are computed in parallel. The syndrome calculation unit calculates only the low-order syndromes.

● key equation calculation units, using ribM algorithm, the number of ribM calculation units is equal to the number of interlaves, the number of basic units in each ribM unit is equal to three times of the maximum error correction capability.

● the searching and error value calculating module adopts all interlaves to be parallel, and the single interlave further adopts J symbols to be parallel. The error value calculation is only performed after the last iteration is completed and is used for error correction of the GII codeword.

● high-order nested syndrome calculation unit calculates error by calculatingDecoded higher order syndrome of interleave and correctly decoded r of interleave (α)^j) And multiplying the conversion matrix to obtain a high-order nested syndrome.

● the inverse matrix multiplication module converts the higher order nested syndromes to higher order syndromes.

● the key equation coefficient update unit updates the coefficients stored in the registers of the key equation computation unit before each iteration.

Drawings

FIG. 1 is a top level framework diagram of the GII decoder architecture proposed by the present invention;

FIG. 2 is a block diagram of a key equation calculation unit;

FIG. 3 is an architecture diagram of a decodable interleave high order syndrome computation module;

FIG. 4 shows r (α)^j) Calculating an architecture diagram of the unit;

FIG. 5 is a top level architecture diagram of a high order nested syndrome computation unit;

fig. 6 is an architecture diagram of a key equation coefficient update unit.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be further described with reference to the accompanying drawings. The embodiments described below by referring to the drawings are exemplary and intended to be illustrative of the present invention and are not to be construed as limiting the present invention.

The top level architecture of the GII decoder proposed by the present invention is shown in FIG. 1. The syndrome computing unit only computes low-order syndromes, and in order to achieve higher throughput, the syndrome computing unit adopts a partially parallel structure, and the parallelism J can be adjusted along with the parameter indexes. The received code word enters a syndrome calculation unit to perform syndrome calculation on one hand, and is stored in the RAM on the other hand.

The last clock cycle of the syndrome calculation initializes the registers of the key equation calculation unit of fig. 2 with the resulting syndromes. Then, the key equation calculation unit carries out the first calculation, and the required clock period is 2t_L-1Wherein t is_L-1Is the minimum value in the error correction capability. Key prescriptionThe polynomial expression (x) obtained by the program computing unit is sent to a chien searching unit for root searching, and the polynomial expression (x) and the trigonometric searching unit are simultaneously used for root searching

Sent to a high-order nested syndrome calculation unit for calculation.

The key equation in the framework adopts a ribM algorithm and four polynomials

The coefficients of Λ (x) and b (x) are updated iteratively. The critical path of the riBM architecture has only one galois field multiplication and one galois field addition.

The top-level architecture of a five-layer high-order nested syndrome computation unit of GII code with error correction capability of t ═ 28, 20, 16, 13, 12 is shown in fig. 5, e (α)^j) The calculation unit is used for calculating the higher order syndrome of the correctly decoded interleave, and the specific structure is shown in FIG. 3. to avoid extra clock cycles, the unit is synchronized with the Chien search, the value of the higher order syndrome is stored in the shift register, e (α) according to the parallelism of the Chien search and the distribution of the GII code body error correction capability^j) The computing units can be flexibly adjusted, e.g., serially e (α)^j) When the number of clock cycles required by the computing unit is greater than that of the chien search, the serial connection can be changed into partial parallel connection to realize the synchronization of the module and the chien search module. Such synchronization is intended to meet the high throughput requirements without introducing additional clock cycles. The order of the syndromes in the shift register goes from high to low from left to right.

On the other hand, the higher order r of all interlaves (α)^j) The decoding flag bit of the Qian search marks whether the corresponding interleaver is correctly decoded, and r is obtained (α)^j)-e(α^j) While an incorrectly decoded interleave only needs r (α)^j) The hardware architecture of the module in which this calculation process is performed is shown in FIG. 4. to obtain the higher-order nested syndrome, it is necessary to further obtain the previous e (α)^j) And r (α)^j) The conversion matrix is multiplied.

r(α^j) The computation unit is essentially similar to a partially parallel syndrome computation unit, which reads the interleave in RAM and computes r (α)^j). The cell in fig. 5 contains all syndrome orders from 24 th to 55 th. In each decoding stage, only the module with the corresponding order is executed. The module of matrix multiplication outputs the high order nested syndrome that gets, its input has the multiplexer, in order to choose the module of the corresponding order in different decoding stages.

And the high-order nested syndrome obtains a high-order syndrome through an inverse matrix multiplication unit. The inverse matrix multiplication unit does not adopt a Galois field matrix inversion module, but uses a lookup table to realize the inversion of the matrix, thereby greatly reducing the complexity of hardware.

The higher order syndromes obtained by the inverse matrix multiplication module are not arranged in the order of the undecodable interlaces, so a shift net is added to rearrange the order of the higher order syndromes.

Before the next key equation calculation, the key equation coefficient updating unit calculates to obtain the data to be updated

And

the specific structure of the unit is shown in fig. 6, and the structure only includes a simple multiply-add unit.

In subsequent iterations, the key equation computation unit does not perform all iterations. Updating the output pairs of the cells with the key equation coefficients at the beginning of each decoding phase

And

the coefficients of (a) are reinitialized. Reinitialized

And

the coefficients of (2) contain information of higher-order syndromes, so that only additional iteration is needed after the original iteration, and 2t iterations are not needed again.

Each decoding stage thereafter is similar to that analyzed above. But the value calculation module is only synchronous with the chien search in the last decoding stage to calculate the error value. And adding the error numerical value obtained by calculation with the original code word read out from the RAM to obtain the corrected code word.

Claims

1. A hardware architecture for a high-speed GII decoder comprising:

● syndrome calculation units with full parallelism at the Interleave level and partial parallelism at the symbol level, for receiving the code word from the channel and calculating all the low order syndromes.

● the key equation computation unit is still fully parallel at the interleave level. In each decoding stage, the partial registers in the key equation calculation units corresponding to the interlaves which cannot be decoded in the previous stage are assigned again.

● Qian search module with full parallelism at the level of interlave and partial parallelism at the level of sign, which is used to calculate the number of roots of the error location polynomial and determine whether each interlave can be translated.

● numerical computation module with complete parallelism of Interleave level and partial parallelism of symbol level, which is used to compute error numerical value.

● the high-order nested syndrome calculation unit comprises a high-order syndrome calculation module of interplay capable of decoding, r (α) of all interplay^j) A calculation module and a matrix multiplication module.

● the inverse matrix multiplication module is used to get the inverse matrix of the sub-matrix of the transformation matrix and multiply with the high order nested syndrome to get the high order syndrome.

● the shift network passes the higher order syndromes to the corresponding interlaces in the correct order.

● the key equation coefficient updating unit adopts the full parallelism of interlave to update the coefficients of KES part of the irresolvable interlave.

2. The syndrome computation unit as recited in claim 1, wherein full parallelism at an interleave level and partial parallelism at a symbol level are employed to achieve high throughput. The calculation unit calculates only the low order syndromes and initializes the key equation calculation unit with these syndromes without storing them in the storage unit.

3. The key equation computation unit of claim 1, being still fully parallel at the interleave level. With the riBM architecture, the number of basic computation units corresponds to the value of the maximum error correction capability of the GII code.

4. A chien search module as claimed in claim 1, the module having a degree of parallelism in accordance with the syndrome computation unit. At the end of each decoding stage, the chien search uses the error location polynomial to find the error location and outputs the flag bit whether the interleave is solvable or not.

5. The numerical computation module of claim 1, wherein the parallelism is consistent with the chien search, and the module computes the error value only at the end of the whole decoding process.

6. The higher order nested syndrome computation unit of claim 1 is divided into three parts, inter higher order syndrome computation module for decodable, r (α) for all inter^j) The unit can be designed to be serial or partially parallel according to the difference between the required number of clock cycles and the error correction capability of adjacent layers, r (α) of all interlaves^j) A calculation module is also performed concurrently with the chien search, which reads the codewords stored in the memory and calculates r (α) of the corresponding order^j). The moduleFull parallelism is adopted at an interlace level, and partial parallelism is adopted at a symbol level.

7. The inverse matrix multiplication module of claim 1 comprising a basic matrix multiplication unit and a look-up table. And the lookup table outputs the corresponding elements of the inverse matrix to the matrix multiplication calculating unit according to the serial number of the irresolvable interleaver.

8. The key equation coefficient update unit of claim 1, which performs the polynomial fitting by using a multiply-add calculation similar to a convolution calculation

And

and updating the key equation calculation unit using the updated terms.

9. A key equation coefficient update unit as claimed in claim 7, which unit uses the riBM algorithm

And

the coefficient updating rule of (2) only needs the multiplication and addition of the Galois field to complete the operation, and the key path is also the multiplication and addition of the Galois field.