CN107688506B - BCH decoding system with flow structure - Google Patents
BCH decoding system with flow structure Download PDFInfo
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- CN107688506B CN107688506B CN201710769471.2A CN201710769471A CN107688506B CN 107688506 B CN107688506 B CN 107688506B CN 201710769471 A CN201710769471 A CN 201710769471A CN 107688506 B CN107688506 B CN 107688506B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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Abstract
The invention discloses a BCH decoding system with a pipeline structure, and belongs to the technical field of computer storage error correction. The system of the invention comprises: the parallel syndrome computing module is used for computing syndromes in parallel according to the received data; the key equation solving-parallel Qian's search module is used for calculating a key equation according to the syndrome and finding out a solution of the key equation; the FIFO memory module is used for caching the data read out from the NAND Flash chip and gradually outputting the data in the FIFO memory module when calculating the solution of the key equation; and the BCH decoding controller module is used for realizing the parallel execution of the BCH decoding two-stage production line. The system of the invention multiplexes hardware resources in different modules in the BCH decoder, adopts a parallel flow structure to carry out BCH decoding, and can effectively increase the throughput rate of BCH decoding and reduce hardware overhead.
Description
Technical Field
The invention belongs to the field of computer storage error correction, and particularly relates to a BCH decoding system with a pipeline structure.
Background
With the wide application of the nonvolatile storage device using NAND Flash as a medium, single-layer NAND Flash cannot meet the requirements of a high-capacity and low-cost memory, a new-generation multilayer memory has low unit cost, high storage density and large storage capacity, and is increasingly applied to a nonvolatile storage system. BCH (Bose, Ray-Chaudhuri, Hocquenghem) code is used as a cyclic code, has excellent performance and simple structure, and is an error correcting code technology widely applied to a storage system. When data are written into the NAND Flash chip, original data are written into the NAND Flash chip after data coding is completed through the 8-bit parallel BCH encoder, when data are read from the NAND Flash chip, the 8-bit parallel data are read out from the chip and are simultaneously input into the BCH decoder, if the number of stored data errors is smaller than the maximum number of errors which can be corrected by the BCH code, correct original data are output, and if the number of data errors is larger than the maximum number of errors which can be corrected by the BCH code, decoding failure is reported.
The BCH code is simple in coding process and is realized by using a Linear Feedback Shift Register (LFSR). The BCH code decoding process mainly comprises three steps, namely syndrome calculation, key equation solution and Qian's search. The key equation solving process is complex, a large amount of hardware logic resources are consumed, the key equation solving process is a core module in the BCH decoding circuit, the current research mainly focuses on reducing the implementation complexity of the key equation solving circuit, the improvement of the decoding speed of the BCH decoder is mainly realized in a parallelization mode, and the decoding speed of the BCH can be obviously improved through syndrome calculation and a Qian's search algorithm in the parallelization decoding process. However, the separate research of each module of the BCH decoder does not consider the circuit resource sharing in the BCH decoder from the whole, which causes a large amount of hardware resource overhead. At present, a research team provides a syndrome-chien search block circuit structure sharing hardware resources, which can reduce the overall hardware complexity of a BCH decoder, but cannot realize the pipeline execution of the decoding process, thereby restricting the improvement of the performance.
Disclosure of Invention
In view of the above drawbacks or needs for improvement in the prior art, the present invention provides a BCH decoding system with a pipeline structure, which aims to perform BCH decoding by multiplexing hardware resources in different modules in a BCH decoder and using a parallel pipeline structure in consideration of the hardware design of the BCH decoder and the characteristics of data reading in SSD storage devices as a whole, thereby reducing the hardware overhead of the BCH decoder and increasing the decoding speed of the BCH decoder.
To achieve the above object, according to one aspect of the present invention, there is provided a pipelined BCH decoding system, including:
the parallel syndrome computing module is used for computing syndromes in parallel according to the received data;
the key equation solving-parallel Qian's searching module is used for calculating a key equation according to the syndrome, finding out the solution of the key equation by searching a key equation root, and multiplexing a finite field multiplier in the process of calculating the key equation and searching the key equation root;
the FIFO memory module is used for caching the data read out from the NAND Flash chip and gradually outputting the data in the FIFO memory module when calculating the solution of the key equation;
and the BCH decoding controller module is used for realizing the parallel execution of the BCH decoding two-stage production line: in the first stage of the pipeline, reading data from the NAND Flash chip and simultaneously writing the data into the parallel syndrome computing module and the FIFO memory module; in the second stage of the pipeline, the syndrome obtained in the parallel syndrome calculation module is input into a key equation solving-parallel Qian's search module, data in the FIFO memory module is output step by step, and error data output in the FIFO memory module is corrected according to the solution of the obtained key equation.
Further, the parallel syndrome computation module is specifically configured to:
and receiving data read from the NAND Flash chip, calculating a remainder of a minimum polynomial corresponding to the data in parallel according to the read data, and calculating a corresponding syndrome value according to the remainder.
Further, the key equation solving-parallel chien search module is specifically configured to calculate a key equation using the SIBM algorithm and search a key equation root using the chien search algorithm.
Generally, compared with the prior art, the technical scheme of the invention has the following technical characteristics and beneficial effects:
(1) the decoding hardware cost is reduced by multiplexing a finite field multiplier in the process of calculating a key equation and searching a key equation root;
(2) the parallel execution of the BCH decoding two-stage production line is realized, and the decoding efficiency and throughput rate are improved.
Drawings
FIG. 1 is a schematic structural diagram of an embodiment of the present invention;
FIG. 2 is a circuit diagram of parallel calibration sub-modules according to an embodiment of the present invention
FIG. 3 is a schematic circuit diagram of an SIBM algorithm according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a parallel chien search circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a key equation solving-parallel chien search circuit according to an embodiment of the present invention;
FIG. 6(a) is a schematic non-pipelined BCH decoding of an embodiment of the present invention;
FIG. 6(b) is a schematic diagram illustrating a BCH decoding flow according to an embodiment of the present invention;
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The technical terms of the present invention are explained and illustrated first, and the following definitions are made in the following description:
BCH (n, k, t) code: indicating a codeword length of n bits (n)<＝2m-1, m is a positive integer, when n is 2m1, the BCH code is a standard BCH code), the information bit length is k bits, the redundant bit information bits are r bits (r ═ n-k), t represents the error correction capability of the error correction code, and it represents that any error less than t bits occurring in n bits of the codeword can be corrected.
BCH shortening codes: for all n<2mBCH code words of-1 are all a shortened code of the standard BCH code, and a shortened BCH code can be regarded as aThe standard BCH code with a high order of 0, so the error correction capability of the shortened BCH code remains unchanged.
FIG. 1 is a schematic structural diagram of an embodiment of the present invention, which includes a parallel syndrome calculation module, a key equation solving-parallel chien search module, a FIFO memory module, and a BCH decoding controller module;
a parallel syndrome computation module for computing coded syndromes, for BCH (n, k, t) codes, the parallel syndrome computation module computes 2t syndromes defined as:
wherein S isiRepresents the ith syndrome; alpha is alphaiRepresents the ith element in a finite field; r (alpha)i) Denotes an acceptance polynomial, N denotes the maximum power exponent of the remainder polynomial, r (α)i) Denotes alphaiA residue corresponding to the minimum polynomial; r isj(αi) Representing the value of degree j in the remainder polynomial.
Fig. 2 shows a schematic circuit diagram of an 8-bit parallel syndrome calculation module, data is input in an 8-bit parallel manner, the parallel syndrome calculation module holds an intermediate result in a register (Parity Reg), after data input is completed, the value in the register (Parity Reg) is r (x), and α is calculatediSubstituting into r (x) to obtain the desired syndrome.
And the key equation solving-parallel chien searching module is used for solving the BCH decoding key equation and searching the root of the key equation, wherein the SIBM algorithm is used for solving the BCH decoding key equation, and the chien searching algorithm is used for searching the root of the key equation. Key equation solving-parallel chien search module uses 2t syndromes Si，0<i<2t as input, solving a key equation and judging whether a certain data bit has errors by searching the form of a key equation root.
The circuit diagram of the SIBM algorithm is shown in FIG. 3, the syndrome Si，0<i<2t are shifted step by step in a shift register into the SIBM algorithm circuit, according to the SIBM algorithm, as shown in fig. 3The key equation can be calculated by using 2t universal finite field multipliers and carrying out t iterations.
The schematic diagram of the 8-bit parallel Chien search circuit is shown in fig. 4, the 8-bit parallel Chien search circuit needs to use (8+1) t constant finite field multipliers in total, the parallel Chien search circuit receives a key equation from the SIBM algorithm circuit, after initialization is completed, an intermediate result is stored in a register D, a Chien _ result marks whether the data bit is erroneous, and a complete codeword (or information bit) can be searched through n (or k) iterations.
The schematic circuit diagram of the key equation solving-parallel chien search module is shown in fig. 5, after the SIBM algorithm calculates the key equation, the value of the key equation after iteration h is directly calculated according to the number h of bits shortened by the BCH shortening code. In the embodiment, a key equation solving-parallel Qian's search block totally uses 2t universal finite field multipliers and 6t constant finite field multipliers, and compared with a discrete SIBM algorithm circuit and an 8-bit parallel Qian's search circuit, the use of 3t constant finite field multipliers can be reduced.
And the FIFO memory module is used for caching the data read out from the NAND Flash chip and gradually outputting the data in the FIFO memory module when executing the chien search iterative algorithm.
And the BCH decoding controller module is used for controlling data interaction among the parallel syndrome computing module, the key equation solving-parallel Qian's search module and the FIFO memory module. According to the characteristics of a NAND Flash page, a plurality of BCH coding code words are usually generated in one NAND Flash page, the BCH decoding controller module is used for realizing the parallel execution of two-stage pipelining of the plurality of BCH code words in one page, wherein a parallel syndrome calculation is the first stage of the pipelining, a key equation calculation-parallel chien search is the second stage of the pipelining, a pipelining-free schematic diagram of BCH decoding is shown in FIG. 6(a), and a pipelining schematic diagram is shown in FIG. 6 (b). When the NANDFlash chip reads data, the BCH decoding controller module writes the data into the parallel syndrome calculation module and the FIFO memory module at the same time, corresponding to the parallel syndrome calculation as in fig. 6(b), after the first codeword is read out, the syndrome obtained by the syndrome calculation module is input into the key equation solving-parallel chien search block, and the subsequently read codewords are written into the parallel syndrome calculation module and the FIFO memory module at the same time, the decoding operation of the next codeword is started, and when the chien search module iterates, the data in the FIFO memory module is output and the error data is corrected according to the search result.
It will be appreciated by those skilled in the art that the foregoing is only a preferred embodiment of the invention, and is not intended to limit the invention, such that various modifications, equivalents and improvements may be made without departing from the spirit and scope of the invention.
Claims (3)
1. A pipelined BCH decoding system, the system comprising:
the parallel syndrome computing module is used for computing syndromes in parallel according to the received data;
the key equation solving and parallel chien search module is used for calculating a key equation according to the syndrome and finding out the solution of the key equation by searching the root of the key equation, wherein the key equation for solving the BCH decoding uses an SIBM algorithm, a finite field multiplier is multiplexed in the process of calculating the key equation and searching the root of the key equation, and a general finite field multiplier in the SIBM circuit module is multiplexed in the chien search circuit module to complete iterative calculation of chien search;
the FIFO memory module is used for caching the data read out from the NAND Flash chip and gradually outputting the data in the FIFO memory module when calculating the solution of the key equation;
and the BCH decoding controller module is used for realizing the parallel execution of the BCH decoding two-stage production line:
in the first stage of the pipeline, reading data from the NAND Flash chip and simultaneously writing the data into the parallel syndrome computing module and the FIFO memory module;
in the second stage of the pipeline, the syndrome obtained in the parallel syndrome calculation module is input into a key equation solving-parallel Qian's search module, data in the FIFO memory module is output step by step, and error data output in the FIFO memory module is corrected according to the solution of the obtained key equation.
2. The BCH decoding system of claim 1, wherein the parallel syndrome computation module is specifically configured to:
and receiving data read from the NAND Flash chip, calculating a remainder of a minimum polynomial corresponding to the data in parallel according to the read data, and calculating a corresponding syndrome value according to the remainder.
3. The BCH decoding system of claim 1 wherein the key equation solving-parallel chien search module is specifically configured to compute key equations using SIBM algorithm and search key equation roots using chien search algorithm.
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