CN101488369A - Interface circuit for BCH code controller - Google Patents
Interface circuit for BCH code controller Download PDFInfo
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- CN101488369A CN101488369A CNA2009100251719A CN200910025171A CN101488369A CN 101488369 A CN101488369 A CN 101488369A CN A2009100251719 A CNA2009100251719 A CN A2009100251719A CN 200910025171 A CN200910025171 A CN 200910025171A CN 101488369 A CN101488369 A CN 101488369A
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Abstract
The invention relates to a BCH code control unit interface circuit which is characterized in that a register set is arranged in an interface of a system bus arranged between an embedded CPU encoding and decoding circuit and a BCH encoding and decoding circuit, the register set is internally provided with a non-zero error testing control bit, a zero error testing control bit and a decoding completion times status bit. In testing and scanning of bad blocks of a Flash type memory device, the non-zero error testing control bit can put a faulty address search circuit out of work after enabling, the zero error testing control bit can put a wrong position multinomial iterative circuit and a faulty address search circuit out of work after enabling, thus improving speed to test the Flash bad blocks and reducing power consumption of the circuit. In the use of the Flash type memory device, the decoding completion times status bit is used as a counter for recording the decoding completion times of a flash sector, meanwhile, a status signal faster than an interrupt signal of a response decoding circuit is supplied to the CPU, so that the CPU directly reads the value of the counter to inform corresponding modules of reading the decoded data, thus improving reading speed by 10% (2MB/s).
Description
Technical field
The present invention relates to a kind of controller interface circuit, particularly relate to the interface circuit of a kind of BCH (Bose-Chaudhuri-Hocquenghem) code controller in Flash type memory device control chip.
Background technology
Storage arrangement is divided into volatile memory devices and non-volatile memory device usually.Non-volatile memory device keeps the data of being stored under powering-off state, and volatile memory devices discharges the data of being stored under powering-off state.Volatile memory devices comprises the storage arrangement of dynamic random access memory (DRAM).Non-volatile memory device comprises flash memory device, ROM (read-only memory) (ROM) device, EPROM device (EPROM) and electrically erasable read-only (EEPROM) storage arrangement.
Flash memory device has many useful features.For example, although fast unlike dynamic random access memory device (DRAM), also has reading speed faster.In addition, compare with hard disk, flash memory device can stand the stronger bump to himself.Although data be wiped and be made carbon copies to flash memory device can by electricity, and are different with EEPROM, flash memory device can be that data are wiped and write in unit with the piece.In addition, the flash memory device cost is lower than EEPROM.Because these characteristics, flash memory device can be widely used in high capacity, non-volatile, solid-state storage device.For example, flash memory device generally is used for cell phone, digital camera and digital recorder.SRAM (Static Random Access Memory) is a kind of internal memory with static access facility, does not need refresh circuit can preserve the data of its storage inside.Unlike the DRAM internal memory, need refresh circuit, at set intervals, fixing will be once to the DRAM refresh charge, otherwise inner data promptly can disappear, so SRAM has higher performance.
Along with the development of embedded system, NandFlash just is applied in the embedded system more and more.NandFlash has littler volume with it with respect to NorFlash, write faster and erasing speed, but thereby erasing times has obtained developing rapidly more frequently.Jumbo NandFlash is particularly suitable for the storage of big data quantity in the present digital equipment and carries, and can reduce cost, and improves performance.And NandFlash with need the interface support being connected of processor, it can be the interface of pure hardware, promptly design itself has a NandFlash hardware control among the SoC, as long as directly connect according to the concrete signal line; Also can be the pure software interface, promptly itself not have special NandFlash hardware control among the SoC, at this moment signal wire can be connected on GPIO mouth or the external storage interface, realize the various operations of NandFlash by software.Various model NandFlash order this problem of limitation that is not quite similar and makes its NandFlash that supports order though the pure software interface can solve well, expend very much the clock period, and read or write speed will descend greatly.
Dma controller is a kind of unique peripheral hardware at the internal system transferring data, it can be considered as a kind ofly can inside and outside storer and each being had the controller that the peripheral hardware of DMA ability couples together by one group of private bus.Why it belongs to peripheral hardware, is because it is to carry out transmission under the programming Control of processor.It should be noted that and have only the peripheral hardware of data traffic big (kBps or higher) just need support the DMA ability usually, the typical example of these application facet comprises video, audio frequency and network interface.
In the control chip of NandFlash type structure mass-memory unit, because factors such as the characteristics of NandFlash type structure and noise, it is inevitable that the data of transmission can be made mistakes, can carry out Error detection and correction when guaranteeing that data are read, usually all be when the data write storage unit, need write a part of redundant data artificially by certain rule, be used for Error Control.BCH code is to correct the sign indicating number of a plurality of random errors, and this routine with NandFlash memory device type of makeing mistakes conforms to.
BCH code is a kind of reflected code that can correct a plurality of random errors, between its generator polynomial and the minimum distance confidential relation is arranged, and can describe with the root of generator polynomial g (x).It has strict Algebraic Structure, and error correcting capability is strong, simple structure, and people can be easy to construct BCH code according to desired error correcting capability t, and its Code And Decode device is also realized easily than other sign indicating numbers, is to use a most general class sign indicating number in the linear block codes.
The realization approach of BCH code error correction has software to realize and hardware is realized two kinds.The software implementation method dirigibility realizes by force and more easily, but the operating rate of implementation method is not ideal enough, is difficult to satisfy the error correction requirement in the data communication of dynamic real-time.And the operating rate of hardware implementation method is fast, when high data rate and long frame application scenario, has advantage, but present realization performance also is not special outstanding, be mainly reflected in or hardware realizes that area is big, hardware realization speed is still waiting further raising, the design underaction of some hard-wired controller also, for example, the data bit width that the hardware handles data are supported is single, can not improve the repeat usage of hardware circuit implementation etc., also increase simultaneously the difficulty of software design and processing greatly, influenced the serviceability and the efficient of BCH code error correction on the whole.
Summary of the invention
The invention provides a kind of BCH code controller interface circuit, its objective is the performance that to improve interface circuit by the design of register controlled position, improve the processing speed and the performance of BCH code controller, satisfy the needs of different application environment.
For achieving the above object, the technical solution used in the present invention is: a kind of BCH code controller interface circuit, comprise a system bus interface, this system bus interface is connected between the BCH coding-decoding circuit in embedded type CPU and the BCH code controller, the BCH coding-decoding circuit is made up of BCH parallel encoding circuit and BCH parallel decoding circuit two parts, wherein BCH parallel decoding circuit is by syndrome syndrome computing circuit, error location polynomial iterative circuit and misaddress search circuit are formed, its innovation is: be provided with registers group in the described system bus interface, be provided with the wrong test of non-zero control bit in this registers group, the number of times mode bit is finished in zero wrong test control bit and decoding, wherein:
The wrong test of non-zero control bit obtains the first negate signal behind first phase inverter, the enable signal of the first negate signal and misaddress search circuit obtains first control signal through first with door, is used to control the misaddress search circuit; The wrong test of non-zero control bit is enabled when bad piece of Flash is tested by CPU, syndrome syndrome computing circuit in the bad piece test scan of Flash in the BCH parallel decoding circuit and the work of error location polynomial iterative circuit, obtain the number of bits that data are made mistakes in the Flash piece, be used for defining whether corresponding Flash piece is bad piece, and the wrong test of the non-zero after enabling control bit is not worked the misaddress search circuit;
Zero wrong test control bit obtains the second negate signal behind second phase inverter, the enable signal of the second negate signal and error location polynomial iterative circuit obtains second control signal through second with door, is used to control the error location polynomial iterative circuit; The enable signal of the second negate signal and misaddress search circuit obtains the 3rd control signal through the 3rd with door, is used to control the misaddress search circuit; Zero wrong test control bit is enabled when bad piece of Flash is tested by CPU, syndrome syndrome computing circuit work in the bad piece test scan of Flash in the BCH parallel decoding circuit, obtain the result that whether data make mistakes in the Flash piece, be used for defining whether corresponding Flash piece is bad piece, and zero wrong test control bit after enabling is not worked error location polynomial iterative circuit and misaddress search circuit;
It is a counter that the number of times mode bit is finished in decoding, this counter is used to write down BCH parallel decoding circuit and finishes the number of times of Flash sector, this counter provides a kind of than responding BCH parallel decoding circuit interruption signal status signal faster to CPU simultaneously, CPU directly reads the value of this counter, notifies corresponding module to read decoding and finishes later data.
Related content in the technique scheme is explained as follows:
1, in the such scheme, described first phase inverter, first and door, second phase inverter and second with a kind of sensu lato logical circuit that refers in the present invention, its equivalent electrical circuit also should be included within protection scope of the present invention.Such as, first phase inverter can be made of a phase inverter, also can be made of three phase inverter series connection, even can be made of the series connection of odd number phase inverter, consequently consistent, and circuit is equivalent.In a word, the circuit with equivalent effect that adopts other a plurality of logic elements to constitute according to prior art all should be included within protection scope of the present invention.
2, in the such scheme, described corresponding module is meant the module that need use correct data after the BCH decoding, such as the USB module etc.
3, in the such scheme, can also be provided with following control bit in the described registers group:
(1) Flash form control bit, this control bit becomes " 0 " or " 1 " two states by CPU according to Flash form assignment, wherein a kind of state makes the BCH parallel encoding circuit data that corresponding every sector is 528 bytes Flash forms in coding generate the data redundancy position of 13 bytes, another kind of state makes the BCH parallel encoding circuit data that corresponding every sector is 540 bytes Flash forms in coding generate the data redundancy position of 26 bytes, and the figure place of described data redundancy position determines the error correcting capability of BCH parallel decoding circuit.
(2) streamline control bit, this control bit is enabled by CPU, streamline control bit after enabling makes the syndrome syndrome computing circuit in the BCH parallel decoding circuit produce look-at-me after handling this sector Flash data, notice CPU reads next sector Flash data, and error location polynomial iterative circuit and misaddress search circuit be when handling this sector Flash data, and syndrome syndrome computing circuit is handled next sector Flash data simultaneously.
(3) exceptional reset control bit, according to enabling unusually that the BCH coding-decoding circuit occurs, the exceptional reset control bit after enabling makes BCH coding-decoding circuit forced resetting to this control bit by CPU.
Because the technique scheme utilization, the present invention compared with prior art has following advantage and effect:
1, improved the bad piece test speed of Flash.The present invention is provided with non-zero wrong test control bit and zero wrong test control bit in system bus interface.The wrong test of non-zero control bit is enabled when bad piece of Flash test by CPU, and the non-zero after enabling is wrong to be tested control bit the misaddress search circuit is not worked, and has improved the bad piece test speed of Flash, has reduced circuit power consumption.Zero wrong test control bit is enabled when bad piece of Flash is tested by CPU, the wrong test of after enabling zero control bit makes in the BCH coding-decoding circuit error location polynomial iterative circuit and misaddress search circuit not work, further improve the bad piece test speed of Flash, reduced circuit power consumption.Two kinds of selections are provided simultaneously, make things convenient for the application of software.
2, improved the decoding speed of system.First, the present invention is provided with decoding and finishes the number of times mode bit in system bus interface, this counter is used to write down BCH parallel decoding circuit and finishes the number of times of Flash sector, this counter provides a kind of than responding BCH parallel decoding circuit interruption signal status signal faster to CPU simultaneously, CPU directly reads the value of this counter, notify corresponding module to read decoding and finish later data, reduced the time that CPU carries out interrupt service routine, improved the decoding speed of system, the method has improved 10% (2MB/s) with respect to traditional method from the speed of Flash reading of data.Second, the present invention is provided with the streamline control bit in system bus interface, after enabling, this control bit can make the syndrome syndrome computing circuit in the BCH parallel decoding circuit after handling this sector Flash data, produce look-at-me, notice CPU reads next sector Flash data, and error location polynomial iterative circuit and misaddress search circuit be when handling this sector Flash data, and syndrome syndrome computing circuit is handled next sector Flash data simultaneously.This mode of handling different task has simultaneously improved the decoding speed of entire stream.If do not enable this control bit, then BCH controller interface circuit control parallel decoding circuit carries out serial arithmetic, and whether first judgment data is wrong, calculates the number of makeing mistakes again, and error correction again, error correction are finished and provided look-at-me again, and decoding speed is slower by contrast.
3, be applicable to multiple Flash data layout.The present invention is provided with Flash form control bit in system bus interface, this control bit becomes " 0 " or " 1 " two states by CPU according to Flash form assignment, wherein a kind of state makes the BCH parallel encoding circuit data that corresponding every sector is 528 bytes Flash forms in coding generate the data redundancy position of 13 bytes, another kind of state makes the BCH parallel encoding circuit data that corresponding every sector is 540 bytes Flash forms in coding generate the data redundancy position of 26 bytes, and the figure place of described data redundancy position determines the error correcting capability of BCH parallel decoding circuit.Applicable surface is more extensive.
4, the work of BCH coding-decoding circuit is more stable.The present invention is provided with the exceptional reset control bit in system bus interface, this control bit is by CPU enabling unusually according to the appearance of BCH coding-decoding circuit, exceptional reset control bit after enabling makes BCH coding-decoding circuit forced resetting, makes the work of BCH coding-decoding circuit more stable.
Description of drawings
Accompanying drawing 1 is Flash type memory device schematic diagram of the present invention;
Accompanying drawing 2 is BCH code controller principle figure of the present invention;
Accompanying drawing 3 provides the schematic diagram of six control bits or mode bit for system bus interface of the present invention;
Accompanying drawing 4 is SRAM interface principle figure of the present invention;
Accompanying drawing 5 is Flash transmission monitoring interface principle figure of the present invention;
Accompanying drawing 6 is the present invention's parallel pipelining process operation chart of decoding;
Accompanying drawing 7 is supported the conversion regime figure of several data bit wide for the present invention.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described:
Embodiment:
As shown in Figure 1, Flash type memory device is made up of USB interface, embedded type CPU, BCH code controller and Flash storer usually.Wherein, USB interface is the standard connecting interface, CPU is Embedded central processing unit, and the Flash storer is a data storage cell, and the BCH code controller is that Flash type memory device reads and writes data and adopts in the process BCH code algorithm to carry out the Code And Decode controller of (comprising error correction).
As shown in Figure 2, the BCH code controller is made up of BCH coding-decoding circuit, SRAM storer (StaticRandom Access Memory, static RAM), dma module (direct memory access modules) and interface circuit (referring to BCH code controller interface circuit of the present invention).The BCH coding-decoding circuit is made up of BCH parallel encoding circuit and BCH parallel decoding circuit two parts, wherein, BCH parallel encoding circuit is used for the data that write the Flash storer are encoded, and BCH parallel decoding circuit is used for the data of reading the Flash storer are decoded (comprising error correction).BCH parallel decoding circuit is made up of syndrome syndrome computing circuit, error location polynomial iterative circuit and misaddress search circuit, wherein, whether syndrome syndrome computing circuit is used for judgment data wrong, the error location polynomial iterative circuit is used for the actual number of makeing mistakes of computational data, and the misaddress search circuit is used for Search Error position and error correction.
As can be seen from Figure 2, invention BCH code controller interface circuit is made up of system bus interface, Flash transmission monitoring interface, SRAM interface, dma module interface and Flash interface.Wherein:
System bus interface is connected between embedded type CPU and the BCH coding-decoding circuit, realizes the visit of CPU to the BCH controller.
Flash transmission monitoring interface is connected between BCH coding-decoding circuit and the Flash interface, realize monitoring the Flash transmission signals, can support the operation of several data bit wide, comprise word (32 bit), half-word (16 bit), byte (8 bit) is delivered to the BCH coding-decoding circuit to corresponding data byte and is carried out encoding and decoding.
The SRAM interface is connected between BCH coding-decoding circuit and the SRAM storer, realizes taking out from the SRAM storer vicious data, and the error pattern processing that provides with the BCH coding-decoding circuit obtains correct data later, is written back to the process of SRAM storer again.
The dma module interface is connected between BCH coding-decoding circuit and the dma module, realizes that dma module directly reads the data redundancy position that the BCH coding-decoding circuit produces in cataloged procedure, is then written in the Flash storer, does not need CPU to visit, and has improved transmission speed.
The Flash interface is used to connect the Flash storer.
As shown in Figure 3, innovation of the present invention is: be provided with registers group in the system bus interface between embedded type CPU and BCH coding-decoding circuit, be provided with encoding and decoding speed, performance and functional reliability that six control bits or mode bit improve the BCH code controller in this registers group.Specify as follows:
(1) the wrong test of non-zero control bit
The wrong test of non-zero control bit obtains the first negate signal behind first phase inverter, the enable signal of the first negate signal and misaddress search circuit obtains first control signal through first with door, is used to control the misaddress search circuit; The wrong test of non-zero control bit is enabled when bad piece of Flash is tested by CPU, syndrome syndrome computing circuit in the bad piece test scan of Flash in the BCH parallel decoding circuit and the work of error location polynomial iterative circuit, obtain the number of bits that data are made mistakes in the Flash piece, be used for defining whether corresponding Flash piece is bad piece, and the wrong test of the non-zero after enabling control bit is not worked the misaddress search circuit.
(2) zero wrong test control bit
Zero wrong test control bit obtains the second negate signal behind second phase inverter, the enable signal of the second negate signal and error location polynomial iterative circuit obtains second control signal through second with door, is used to control the error location polynomial iterative circuit; The enable signal of the second negate signal and misaddress search circuit obtains the 3rd control signal through the 3rd with door, is used to control the misaddress search circuit; Zero wrong test control bit is enabled when bad piece of Flash is tested by CPU, syndrome syndrome computing circuit work in the bad piece test scan of Flash in the BCH parallel decoding circuit, obtain the result that whether data make mistakes in the Flash piece, be used for defining whether corresponding Flash piece is bad piece, and zero wrong test control bit after enabling is not worked error location polynomial iterative circuit and misaddress search circuit.
The bad piece test scan of Flash before the above non-zero wrong test control bit and zero wrong test control bit all are used for Flash type memory device and dispatch from the factory is used for testing the bad piece in the Flash storage unit.Conventional method is that a large amount of random data are stored among the Flash behind BCH parallel encoding circuit code, and then the error in data situation of preserving in the decoding detection Flash piece defines whether corresponding Flash piece is bad piece.Because it is relatively independent that the syndrome syndrome computing circuit in the BCH parallel decoding circuit, error location polynomial iterative circuit and misaddress search circuit are formed, whether and the decoding job order is: earlier wrong by syndrome syndrome computing circuit judgment data, come the actual number of makeing mistakes of computational data by the error location polynomial iterative circuit again, (such as error correcting capability is 8 during in the error correcting capability scope when the number of makeing mistakes, actual makeing mistakes≤8), at last by misaddress search circuit Search Error position and error correction.If in decode procedure data wrong be will pass through syndrome syndrome computing circuit, error location polynomial iterative circuit and misaddress search circuit successively to carry out error correction.In the bad piece test scan of Flash, after enabling, the wrong test of non-zero control bit is assumed to be " 1 ", be " 0 " through obtaining the first negate signal behind first phase inverter, the enable signal " 1 " of the first negate signal " 0 " and misaddress search circuit obtains first control signal through first with door and is " 0 ", the misaddress search circuit that is used for controlling BCH parallel decoding circuit does not need work, and syndrome syndrome computing circuit is used for judging whether the data that are stored in the Flash piece are wrong, the error location polynomial iterative circuit is used for the actual number of makeing mistakes of computational data, the error correcting capability of number and BCH coding-decoding circuit of then data being made mistakes compares, when the number of makeing mistakes of data in the detected Flash piece exceeds the error correcting capability scope, be bad piece then by this Flash piece of software mark, can not use, when the number of makeing mistakes does not exceed the error correcting capability scope, be piece then by this Flash piece of software mark, can use (in the above explanation, suppose that the wrong test of non-zero control bit enables the back and is " 1 ", the enable signal of supposing the misaddress search circuit is " 1 ", but suppose that in actual applications the wrong test of non-zero control bit enables the back and is " 0 ", the enable signal of supposing the misaddress search circuit also is fine for " 0 ", and its effect is constant).In the bad piece test scan of Flash, after enabling, zero wrong test control bit is assumed to be " 1 ", be " 0 " through obtaining the second negate signal behind second phase inverter, the enable signal " 1 " of the second negate signal " 0 " and error location polynomial iterative circuit obtains second control signal through second with door and is " 0 ", and being used to control the error location polynomial iterative circuit does not need work; The enable signal " 1 " of while second negate signal " 0 " and misaddress search circuit obtains the 3rd control signal through the 3rd with door and is " 0 ", and being used to control the misaddress search circuit does not need work.As long as syndrome syndrome computing circuit judges whether whether wrong this Flash piece that just can define is bad piece to the data that are stored in the Flash piece, if it is wrong then be bad piece by this Flash piece of software mark, otherwise be that piece is (in the above explanation, suppose that zero wrong test control bit enables the back and is " 1 ", the enable signal of supposing the misaddress search circuit is " 1 ", the enable signal of supposing the misaddress search circuit is " 1 ", but be " 0 " after hypothesis zero wrong test control bit enables in actual applications, the enable signal of supposing the misaddress search circuit is " 0 ", the enable signal of supposing the misaddress search circuit is " 0 ", also be fine, its effect is constant).
More than, as long as zero error test scan process is owing to know in the Flash piece whether whether wrong this Flash piece that just can define is bad piece to data, do not need to calculate actual make mistakes number and error correction, therefore the zero wrong test scan speed that can improve bad piece of Flash that is provided with of testing control bit by error location polynomial iterative circuit and misaddress search circuit.In like manner, as long as non-zero error checking scanning process knows in the Flash piece whether whether wrong data and the number of makeing mistakes just can define this Flash piece is bad piece, do not need to finish error correction, so the setting of the wrong test of non-zero control bit also can improve the test scan speed of bad piece of Flash by the misaddress search circuit.Zero wrong test control bit and the difference of the wrong test of non-zero control bit mainly be bad piece of definition Flash require different, zero wrong bad piece of test control bit definition Flash strict, non-zero is wrong, and to test control bit suitably loose.
(3) the number of times mode bit is finished in decoding
It is a counter that the number of times mode bit is finished in decoding, this counter is used to write down BCH parallel decoding circuit and finishes the number of times of Flash sector, this counter provides a kind of than responding BCH parallel decoding circuit interruption signal status signal faster to CPU simultaneously, CPU directly reads the value of this counter, notifies corresponding module to read decoding and finishes later data.
A kind of mode bit of application when to be that Flash type memory device is actual use that the number of times mode bit is finished in decoding, particularly from Flash type memory device during reading of data carrying recorded decoding finish the mode bit of number of times.The effect that the number of times mode bit is finished in decoding is normally write down BCH parallel decoding circuit and is finished the number of times of Flash sector, and BCH parallel decoding circuit is whenever finished decode procedure one time, and this mode bit increases progressively automatically.Software can dispose the initial value of this mode bit, allows this mode bit begin counting on this radix.Thereby CPU can read the value of this mode bit knows that BCH parallel decoding circuit finishes the number of times of decoding.But it is emphasized that in the present invention: this mode bit provides a kind of than responding BCH parallel decoding circuit interruption signal status signal faster to CPU, CPU can directly read the value of this mode bit, and do not need to wait for the generation of BCH parallel decoding circuit interruption signal, just can notify corresponding module to read decoding and finish later data, therefore, reduce the time that CPU need carry out interrupt service routine at every turn, improved execution efficient.Described corresponding module is meant the module that need use correct data after the BCH decoding, such as the USB module etc.
(4) Flash form control bit
Flash form control bit is used for the BCH code controller and selects different Flash forms when data is encoded, produce the figure place of data redundancy position ECC when promptly being used to control BCH parallel encoding circuit data being encoded, the figure place of data redundancy position ECC has determined the error correcting capability of BCH parallel decoding circuit.Flash form control bit becomes " 0 " or " 1 " two states by CPU according to Flash form assignment, wherein a kind of state makes the BCH parallel encoding circuit data that corresponding every sector is 528 bytes Flash forms in coding generate the data redundancy position of 13 bytes, another kind of state makes the BCH parallel encoding circuit data that corresponding every sector is 540 bytes Flash forms in coding generate the data redundancy position of 26 bytes, and the figure place of described data redundancy position determines the error correcting capability of BCH parallel decoding circuit.
(5) streamline control bit
The streamline control bit has been used for improving the decoding speed of entire stream.Its principle is to utilize syndrome syndrome computing circuit, error location polynomial iterative circuit and misaddress search circuit in the BCH parallel decoding circuit to form relatively independent characteristics, can make the different Flash sectors of data of the interior at one time processing of different circuit by the streamline control bit, make different Flash sectors of data overlapping on the processing time, to improve decoding speed.The streamline control bit is enabled by CPU, streamline control bit after enabling makes the syndrome syndrome computing circuit in the BCH parallel decoding circuit produce look-at-me after handling this sector Flash data, notice CPU reads next sector Flash data, and error location polynomial iterative circuit and misaddress search circuit be when handling this sector Flash data, and syndrome syndrome computing circuit is handled next sector Flash data simultaneously.Fig. 6 is decoding parallel pipelining process operation chart, a last row Codec represents the process of syndrome syndrome computing circuit deal with data among the figure, and next row Correct represents the process of error location polynomial iterative circuit and misaddress search circuit deal with data, 1., 2., 3., 4. represent the different sectors of data of Flash respectively, next row empty forms registration 3. is according to not makeing mistakes.Error location polynomial iterative circuit and misaddress search circuit are when handling this sector Flash data as can be seen from this figure, and syndrome syndrome computing circuit is handled next sector Flash data simultaneously.
If do not enable this control bit, BCH controller interface circuit control BCH parallel decoding circuit carries out serial arithmetic, whether elder generation's judgment data is wrong, calculate the number of makeing mistakes again, error correction again, error correction is finished and is provided look-at-me again, and decoding speed is slower by contrast, only is fit to software reads small number of sectors from Flash situation.
(6) exceptional reset control bit
The exceptional reset control bit is used for the BCH coding-decoding circuit is carried out exceptional reset, promptly when the BCH coding-decoding circuit abnormality or software occur and need remove once still uncompleted decode procedure, utilize the exceptional reset control bit that the BCH coding-decoding circuit is resetted, with each the register zero clearing in the BCH coding-decoding circuit.According to enabling unusually that the BCH coding-decoding circuit occurs, the exceptional reset control bit after enabling makes BCH coding-decoding circuit forced resetting to the exceptional reset control bit by CPU.
As shown in Figure 4, the SRAM interface is connected between BCH coding-decoding circuit and the SRAM storer, and each signal description is as follows among the figure:
Output signal
Sram_addr[12:0]: the address signal of misdata in SRAM, the error byte address offset amount that this signal is provided by the BCH coding-decoding circuit add and store that the start address of data obtains among the SRAM into.
Sram_wdata[7:0]: be written to the correct data among the SRAM, the error pattern that this signal is provided by misdata of taking out from SRAM and BCH coding-decoding circuit XOR mutually obtains later on.
Sram_wr[3:0]: the SRAM data are write enable signal, and low two decodings of the error byte address that this signal is provided by the BCH coding-decoding circuit obtain, and make that to be written among the SRAM respective byte effective.
The sram_rd:SRAM data read to select signal, and this signal is provided by the BCH coding-decoding circuit, and it is wrong to identify this byte, need to correct.
Input signal
Sram_rdata[31:0]: the SRAM data output signal, have the wrong data of byte in this data-signal at least, select it to carry out error correction for low two of the error byte address signal that provides by the BCH coding-decoding circuit.
Bch_addr[9:0]: the error byte address that the BCH coding-decoding circuit provides.
Bch_dout[7:0]: the error pattern that the BCH coding-decoding circuit provides.
Bch_wr: provided by the BCH coding-decoding circuit, it is wrong to identify this byte, and bch_dout[7:0] simultaneously effectively.
As shown in Figure 5, Flash transmission monitoring interface is connected between BCH coding-decoding circuit and the Flash interface, and each signal description is as follows among the figure:
Output signal:
Bch_din[7:0]: be input to the data that the BCH coding-decoding circuit need be encoded or decode.
Din_vlid: the data that are input to the BCH coding-decoding circuit effectively identify, the BCH coding-decoding circuit this signal for high level time sampling bch_din.
Encode: be input to BCH coding-decoding circuit coding or decoding control signal, this level during for high level control BCH coding-decoding circuit enter coding mode, control BCH coding-decoding circuit enters decoding schema during for low level.
Input signal:
The io_rw_b:Flash read-write control signal, high level is read operation, data stream is for to be delivered to on-chip SRAM from Flash; Low level is a write operation, and data stream is from the on-chip SRAM to Flash.
Io_tsize[1:0]: Flash transmits big or small control signal, and 2 ' b00 represents word transmission (32 bit), and 2 ' b10 represents half-word transmission (16 bit), and 2 ' b01 represents byte transmission (8 bit).
Io_data[31:0]: the Flash transmission of data signals.
Signal is selected in bch_select:Flash transmission, and this signal gets from the address decoder that CPU or DMA send, and when the address of sending then enables the BCH function in given scope, otherwise does not enable the BCH function.
The BCH coding-decoding circuit mainly is divided into Code And Decode two parts.Wherein the Code And Decode circuit all is operated in finite field gf (2
13) on, can expand to other finite field gfs (2 simultaneously
n) on, only need to replace position n with 13.
Cataloged procedure: cataloged procedure is the data among the SRAM is written to the process of Flash by the Bose-Chaudhuri-Hocquenghem Code passage, and the transmission size can be word, half-word, byte.The BCH controller transmits big or small control signal io_tsize according to Flash and divides one or more clock period that corresponding byte among the Flash transmission of data signals io_data is delivered to the BCH coding-decoding circuit to encode.As shown in Figure 7, if be transmitted as the byte transmission, then only need a clock period just can be passed to the BCH coding-decoding circuit to the data io_data of needs transmission; If transmission is half-word transmission, then the BCH controller need be divided into two clock period and data are split into two bytes passes to the BCH coding-decoding circuit; If transmission is word transmission, then need to be divided into four clock period data are split into four bytes to pass to the BCH coding-decoding circuit.The most-significant byte XOR of the data redundancy position ecc that each clock period and the 8 Bit data bch_din that are advanced into the BCH coding-decoding circuit obtained with a last clock period respectively by position from high to low, a divider is sent into together divided by generator polynomial g (x) in the remaining position of result and data redundancy position, thereby upgrade data redundancy position ecc_tmp, after 512 required byte transmission are finished, the data redundancy position ecc_tmp of final updating is kept in the BCH controller in the relevant register redundant digit ECC as 512 byte datas, CPU or DMA can visit the redundant digit ECC that these registers are taken 512 byte datas away, are then written among the Flash.
Decode procedure: decode procedure is the data among the Flash is written to the process of SRAM by the BCH decoding channels, and the transmission size can be word, half-word, byte.The BCH controller transmits big or small control signal io_tsize according to Flash and corresponding byte among the Flash transmission of data signals io_data is delivered to the BCH coding-decoding circuit decodes, corresponding transmission byte split mode and above-mentioned cataloged procedure similar.When required 512 data bytes and corresponding data redundancy position ECC transmit finish after, the BCH coding-decoding circuit can provide faultless sign in the data of being transmitted, when wrong, the number of BCH coding-decoding circuit elder generation miscount, when error range in the BCH coding-decoding circuit can the scope of error correction and when the setting of error correction control bit enables, the BCH coding-decoding circuit is searched for by turn and is begun error correction.When the streamline control bit enabled, the BCH coding-decoding circuit can be decoded by above-mentioned streamline control bit mode.The BCH coding-decoding circuit is searched for by turn to 512 the data bytes and the corresponding data redundancy position ECC of transmission during error correction, if discovery mistake, then the BCH controller takes out the error pattern that data and BCH coding-decoding circuit provide and carries out being written back among the SRAM by the BCH controller after the xor operation again from SRAM.After the BCH coding-decoding circuit was corrected all error bits, error correction was finished.When the data number of makeing mistakes of transmission surpassed the error correcting capability of BCH coding-decoding circuit, then the BCH controller provided error correction failure sign.
Decoding comprises the calculating of syndrome syndrome, the calculating of error location polynomial and misaddress search.The concurrent operation circuit that the syndrome syndrome computations is mainly imported simultaneously by 8 Bit data data is finished the calculating of syndrome syndrome; The calculating of error location polynomial iteration is mainly taken turns many bats mode by one in the IBM iterative algorithm and is realized circuit, multiplexing finite field gf (2
13) on a hybrid arithmetic unit, wherein this hybrid arithmetic unit comprises finite field gf (2
13) on two the input multipliers and one two the input totalizer; The pre-search that the misaddress search then adopts 4 bit pre-searching methods of full combinational logic to carry out misaddress is earlier handled, and then sends into the search that the Chien search circuit is finished misaddress.
The foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to allow the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (4)
1, a kind of BCH code controller interface circuit, comprise a system bus interface, this system bus interface is connected between the BCH coding-decoding circuit in embedded type CPU and the BCH code controller, the BCH coding-decoding circuit is made up of BCH parallel encoding circuit and BCH parallel decoding circuit two parts, wherein BCH parallel decoding circuit is by syndrome syndrome computing circuit, error location polynomial iterative circuit and misaddress search circuit are formed, it is characterized in that: be provided with registers group in the described system bus interface, be provided with the wrong test of non-zero control bit in this registers group, the number of times mode bit is finished in zero wrong test control bit and decoding, wherein:
The wrong test of non-zero control bit obtains the first negate signal behind first phase inverter, the enable signal of the first negate signal and misaddress search circuit obtains first control signal through first with door, is used to control the misaddress search circuit; The wrong test of non-zero control bit is enabled when bad piece of Flash is tested by CPU, syndrome syndrome computing circuit in the bad piece test scan of Flash in the BCH parallel decoding circuit and the work of error location polynomial iterative circuit, obtain the number of bits that data are made mistakes in the Flash piece, be used for defining whether corresponding Flash piece is bad piece, and the wrong test of the non-zero after enabling control bit is not worked the misaddress search circuit;
Zero wrong test control bit obtains the second negate signal behind second phase inverter, the enable signal of the second negate signal and error location polynomial iterative circuit obtains second control signal through second with door, is used to control the error location polynomial iterative circuit; The enable signal of the second negate signal and misaddress search circuit obtains the 3rd control signal through the 3rd with door, is used to control the misaddress search circuit; Zero wrong test control bit is enabled when bad piece of Flash is tested by CPU, syndrome syndrome computing circuit work in the bad piece test scan of Flash in the BCH parallel decoding circuit, obtain the result that whether data make mistakes in the Flash piece, be used for defining whether corresponding Flash piece is bad piece, and zero wrong test control bit after enabling is not worked error location polynomial iterative circuit and misaddress search circuit;
It is a counter that the number of times mode bit is finished in decoding, this counter is used to write down BCH parallel decoding circuit and finishes the number of times of Flash sector, this counter provides a kind of than responding BCH parallel decoding circuit interruption signal status signal faster to CPU simultaneously, CPU directly reads the value of this counter, notifies corresponding module to read decoding and finishes later data.
2, BCH code controller interface circuit according to claim 1, it is characterized in that: be provided with Flash form control bit in the described registers group, this control bit becomes " 0 " or " 1 " two states by CPU according to Flash form assignment, wherein a kind of state makes the BCH parallel encoding circuit data that corresponding every sector is 528 bytes Flash forms in coding generate the data redundancy position of 13 bytes, another kind of state makes the BCH parallel encoding circuit data that corresponding every sector is 540 bytes Flash forms in coding generate the data redundancy position of 26 bytes, and the figure place of described data redundancy position determines the error correcting capability of BCH parallel decoding circuit.
3, BCH code controller interface circuit according to claim 1, it is characterized in that: be provided with the streamline control bit in the described registers group, this control bit is enabled by CPU, streamline control bit after enabling makes the syndrome syndrome computing circuit in the BCH parallel decoding circuit produce look-at-me after handling this sector Flash data, notice CPU reads next sector Flash data, and error location polynomial iterative circuit and misaddress search circuit be when handling this sector Flash data, and syndrome syndrome computing circuit is handled next sector Flash data simultaneously.
4, BCH code controller interface circuit according to claim 1, it is characterized in that: be provided with the exceptional reset control bit in the described registers group, according to enabling unusually that the BCH coding-decoding circuit occurs, the exceptional reset control bit after enabling makes BCH coding-decoding circuit forced resetting to this control bit by CPU.
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| CN112099986B (en) * | 2020-08-11 | 2022-02-01 | 西安电子科技大学 | ECC decoding system and method of branch pipeline structure |
| CN116909804A (en) * | 2023-09-13 | 2023-10-20 | 上海云豹创芯智能科技有限公司 | Storage access control system, method, chip and storage medium |
| CN116909804B (en) * | 2023-09-13 | 2023-12-01 | 上海云豹创芯智能科技有限公司 | Storage access control system, method, chip and storage medium |
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