CN111192624A - System and method for testing performance of BCH (broadcast channel) error correcting code - Google Patents
System and method for testing performance of BCH (broadcast channel) error correcting code Download PDFInfo
- Publication number
- CN111192624A CN111192624A CN201911387731.5A CN201911387731A CN111192624A CN 111192624 A CN111192624 A CN 111192624A CN 201911387731 A CN201911387731 A CN 201911387731A CN 111192624 A CN111192624 A CN 111192624A
- Authority
- CN
- China
- Prior art keywords
- bch
- pseudo
- error
- random number
- decoded data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56016—Apparatus features
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56008—Error analysis, representation of errors
Abstract
The invention provides a system and a method for testing the performance of a BCH error correcting code, wherein the system comprises a pseudo-random number generator, a BCH encoder, a BCH decoder, an NAND FLASH controller, a NAND FLASH and an error code counter. The invention realizes the verification of the error correction performance of the BCH error correction code based on a pure hardware mode, and has the advantages of high efficiency and strong portability.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a system and a method for testing the performance of a BCH error correcting code.
Background
NAND FLASH is characterized by the fact that reading after writing data will generate errors, and therefore an error correction code is required. Currently, NAND FLASH of SLC type, MLC type, and partial TLC type all use BCH as error correction code. However, the existing verification method for verifying the error correction performance of the BCH error correction code has the problems of low efficiency and poor portability.
Disclosure of Invention
The invention mainly aims to provide a system and a method for testing the performance of a BCH error correcting code, and aims to solve the problems of low efficiency and poor portability of a verification method for verifying the error correcting performance of the BCH error correcting code in the prior art.
In order to achieve the above object, an embodiment of the present invention provides a system for testing performance of a BCH error correction code, where the system includes a pseudo-random number generator, a BCH encoder, a BCH decoder, an NAND FLASH controller, NAND FLASH, and an error code counter;
the pseudo-random number generator is used for generating pseudo-random numbers;
the BCH encoder is used for encoding the pseudo random number to generate check information;
the NAND FLASH controller is to write the check information to the NAND FLASH;
the NAND FLASH controller is also used for reading the check information from the NAND FLASH and sending the check information to the BCH decoder;
the BCH decoder is used for decoding the check information to generate decoded data, detecting whether the decoded data has errors or not, if the decoded data has errors, performing error correction processing and correction processing on the decoded data, and sending the data obtained after the error correction processing and the correction processing to the error code counter; if the decoded data has no error, sending the decoded data to the error code counter;
the error code counter is used for comparing the pseudo random number with the data from the BCH decoder to obtain statistical information, and sending the statistical information to a preset terminal, wherein the statistical information comprises the number of error codes and/or the error code rate.
Optionally, the pseudo-random number generator includes 16 sets of cyclic shift registers with different feedback modes, and the pseudo-random number generator generates pseudo-random numbers by using the 16 sets of cyclic shift registers with different feedback modes, where the pseudo-random numbers are 16-bit data.
Optionally, the BCH encoder is configured to encode the pseudo random number by using a parallel 16-bit encoding manner, so as to generate check information.
Optionally, the BCH decoder is configured to decode the check information by using a parallel 16-bit decoding manner, so as to generate decoded data.
In addition, to achieve the above object, an embodiment of the present invention further provides a method for testing performance of a BCH error correction code, which is applied to a system for testing performance of a BCH error correction code, the system including a pseudo-random number generator, a BCH encoder, a BCH decoder, an NAND FLASH controller, NAND FLASH, and an error code counter, the method including:
the pseudo-random number generator generates a pseudo-random number;
the BCH encoder encodes the pseudo random number to generate check information;
the NAND FLASH controller writing the check information to the NAND FLASH;
the NAND FLASH controller reads the check information from the NAND FLASH and sends it to the BCH decoder;
the BCH decoder decodes the check information to generate decoded data, detects whether the decoded data has errors or not, performs error correction and correction on the decoded data if the decoded data has errors, and sends the data obtained after the error correction and correction to the error code counter; if the decoded data has no error, sending the decoded data to the error code counter;
and the error code statistics device compares the pseudo random number with the data from the BCH decoder to obtain statistical information, and sends the statistical information to a preset terminal, wherein the statistical information comprises the number of error codes and/or the error code rate.
Optionally, the pseudo-random number generator includes 16 sets of cyclic shift registers with different feedback modes, and the pseudo-random number generator generates pseudo-random numbers including:
the pseudo-random number generator generates pseudo-random numbers by adopting 16 groups of cyclic shift registers with different feedback modes, and the pseudo-random numbers are 16-bit data.
Optionally, the BCH encoder encodes the pseudo random number, and generating the check information includes:
the BCH encoder is used for encoding the pseudo random number by adopting a parallel 16-bit encoding mode to generate check information.
Optionally, the decoding, by the BCH decoder, the check information, and generating decoded data includes:
and the BCH decoder is used for decoding the check information by adopting a parallel 16-bit decoding mode to generate decoded data.
In the present invention, a pseudo-random number generator is used to generate pseudo-random numbers; the BCH encoder is used for encoding the pseudo random number to generate check information; NAND FLASH controller for writing NAND FLASH the verification information; the NANDFLASH controller is also used for reading the check information from the NAND FLASH and sending the check information to the BCH decoder; the BCH decoder is used for decoding the check information to generate decoded data, detecting whether the decoded data has errors or not, if the decoded data has errors, performing error correction processing and correction processing on the decoded data, and sending the data obtained after the error correction processing and the correction processing to the error code counter; if the decoded data has no error, sending the decoded data to the error code counter; and the error code counter is used for comparing the pseudo random number with the data from the BCH decoder to obtain statistical information and sending the statistical information to a preset terminal, wherein the statistical information comprises the number of error codes and/or the error code rate. The invention realizes the verification of the error correction performance of the BCH error correction code based on a pure hardware mode, and has the advantages of high efficiency and strong portability.
Drawings
FIG. 1 is a schematic diagram of a system in an embodiment of a system for testing the performance of BCH error correction codes according to the present invention;
FIG. 2 is a schematic diagram of the pseudo-random number generator in an embodiment of the system for testing the performance of BCH error correction codes of the present invention;
FIG. 3 is a block diagram of a BCH decoder in an embodiment of the system for testing the performance of BCH error correction codes according to the present invention;
FIG. 4 is a flowchart illustrating an embodiment of a method for testing the performance of a BCH error correction code according to the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to FIG. 1, FIG. 1 is a schematic structural diagram of a system in an embodiment of a system for testing performance of BCH error correction codes according to the present invention. As shown in FIG. 1, in one embodiment, a system for testing the performance of a BCH error correction code includes a pseudo-random number generator, a BCH encoder, a BCH decoder, an NAND FLASH controller, a module NAND FLASH, and an error counter; wherein:
the pseudo-random number generator is used for generating pseudo-random numbers;
in this embodiment, a pseudo-random number generator is used to generate pseudo-random numbers.
In an alternative embodiment, the pseudo-random number generator comprises 16 sets of cyclic shift registers with different feedback modes, and the pseudo-random number generator generates pseudo-random numbers by adopting the 16 sets of cyclic shift registers with different feedback modes, wherein the pseudo-random numbers are 16-bit data.
In this embodiment, the pseudo-random number generator generates pseudo-random numbers by using 16 sets of cyclic shift registers with different feedback modes, and each clock generates a 16-bit data pseudo-random number.
Referring to FIG. 2, FIG. 2 is a schematic diagram of the pseudo-random number generator in the embodiment of the system for testing the performance of BCH error correction code of the present invention. As shown in fig. 2, the pseudo random number generator includes 16 sets of cyclic shift registers with different feedback modes, the length of each set of cyclic shift registers can be configured, and any data length required can be generated, that is, the value of n is set according to actual needs.
The BCH encoder is used for encoding the pseudo random number to generate check information;
in this embodiment, the BCH encoder is configured to encode the pseudo random number and generate the check information.
In an optional embodiment, the BCH encoder is configured to encode the pseudo random number by using a parallel 16-bit encoding manner, and generate the check information.
In this embodiment, the BCH encoder encodes the pseudo random number generated by the pseudo random number generator, generates the check information, and sends the check information to the NAND FLASH controller. The conventional method is a method using a linear feedback shift register, but the linear feedback shift register is serial, and each clock can only process one bit of data. In this embodiment, the structure of the linear feedback shift register is changed to 16-bit parallel processing, that is, the BCH encoder adopts a parallel 16-bit encoding mode, a pseudo-random number from the pseudo-random number generator is processed each time, the pseudo-random number is 16-bit data, and after all data are processed, check information is generated.
The NAND FLASH controller is to write the check information to the NAND FLASH;
the NAND FLASH controller is also used for reading the check information from the NAND FLASH and sending the check information to the BCH decoder;
in the present embodiment, the NAND FLASH controller includes a write control unit, a read control unit, and an erase control unit. NAND FLASH, determines that an erase operation must be performed before writing. The read control unit reads out the data from NAND FLASH and sends the data to the decoder for decoding. The writing control unit writes the data sent by the encoder into the NANDFLASH. The erase unit is the erase operation NAND FLASH.
The BCH decoder is used for decoding the check information to generate decoded data, detecting whether the decoded data has errors or not, if the decoded data has errors, performing error correction processing and correction processing on the decoded data, and sending the data obtained after the error correction processing and the correction processing to the error code counter; if the decoded data has no error, sending the decoded data to the error code counter;
in this embodiment, the BCH decoding module decodes the check information from the NAND FLASH controller to generate decoded data.
In an embodiment, the BCH decoder is configured to decode the check information by using a parallel 16-bit decoding manner, so as to generate decoded data.
In this embodiment, when the pseudo-random number is 16-bit data, the check information is also 16-bit data, so the BCH decoder is configured to decode the check information by adopting a parallel 16-bit decoding manner, and generate decoded data.
In this embodiment, the BCH decoder calculates the check information from the NAND FLASH controller and corrects errors if errors are found. After the error correction is completed, correction is performed by a correction circuit. And sends the corrected data to an error counter. If no error is found, the data sent from the NAND FLASH controller is sent directly to the error counter. Referring to FIG. 3, FIG. 3 is a schematic diagram of a BCH decoder in an embodiment of the system for testing the performance of BCH error-correcting codes according to the present invention. As shown in FIG. 3, the BCH decoder includes a syndrome polynomial, a Chien search circuit and an error correction circuit.
The error code counter is used for comparing the pseudo random number with the data from the BCH decoder to obtain statistical information, and sending the statistical information to a preset terminal, wherein the statistical information comprises the number of error codes and/or the error code rate.
In this embodiment, the error code counter compares the data sent by the pseudo-random generator with the data sent by the decoder, counts the number of error codes and/or the error rate to obtain statistical information, and then sends the statistical information to a preset terminal, for example, sends the statistical information to a PC terminal through a UART (Universal Asynchronous Receiver/Transmitter).
In the present embodiment, the pseudo random number generator is used to generate pseudo random numbers; the BCH encoder is used for encoding the pseudo random number to generate check information; NAND FLASH controller for writing NAND FLASH the verification information; the NANDFLASH controller is also used for reading the check information from the NAND FLASH and sending the check information to the BCH decoder; the BCH decoder is used for decoding the check information to generate decoded data, detecting whether the decoded data has errors or not, if the decoded data has errors, performing error correction processing and correction processing on the decoded data, and sending the data obtained after the error correction processing and the correction processing to the error code counter; if the decoded data has no error, sending the decoded data to the error code counter; and the error code counter is used for comparing the pseudo random number with the data from the BCH decoder to obtain statistical information and sending the statistical information to a preset terminal, wherein the statistical information comprises the number of error codes and/or the error code rate. Through the embodiment, the verification of the error correction performance of the BCH error correction code is realized based on a pure hardware mode, and the method has the advantages of high efficiency and strong portability.
Referring to FIG. 4, FIG. 4 is a flowchart illustrating a method for testing the performance of BCH error-correcting codes according to an embodiment of the present invention. In one embodiment, the method for testing the performance of a BCH error correcting code is applied to a system for testing the performance of a BCH error correcting code, the system comprising a pseudo-random number generator, a BCH encoder, a BCH decoder, an NAND FLASH controller, NAND FLASH and an error code counter, the method comprising:
a step S10 of the pseudo random number generator generating a pseudo random number;
step S20, the BCH encoder encodes the pseudo random number to generate check information;
step S30, the NAND FLASH controller writing the check information to the NAND FLASH;
step S40, the NAND FLASH controller reads the check information from the NAND FLASH and sends the check information to the BCH decoder;
step S50, the BCH decoder decodes the check information to generate decoded data, detects whether the decoded data has errors, if so, performs error correction and correction on the decoded data, and sends the data obtained after error correction and correction to the error code counter; if the decoded data has no error, sending the decoded data to the error code counter;
and step S60, the error code counter compares the pseudo random number with the data from the BCH decoder to obtain statistical information, and sends the statistical information to a preset terminal, wherein the statistical information comprises the number of error codes and/or the error rate.
Further, in an embodiment, the pseudo-random number generator includes 16 sets of cyclic shift registers with different feedback modes, and step S10 includes:
the pseudo-random number generator generates pseudo-random numbers by adopting 16 groups of cyclic shift registers with different feedback modes, and the pseudo-random numbers are 16-bit data.
Further, in one embodiment, step S20 includes:
the BCH encoder is used for encoding the pseudo random number by adopting a parallel 16-bit encoding mode to generate check information.
Further, in an embodiment, the BCH decoder decodes the check information, and generating decoded data includes:
and the BCH decoder is used for decoding the check information by adopting a parallel 16-bit decoding mode to generate decoded data.
The specific embodiment of the method for testing the performance of the BCH error correction code of the present invention is basically the same as each embodiment of the system for testing the performance of the BCH error correction code, and details are not repeated herein.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.
The various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functionality of some or all of the components in accordance with embodiments of the present invention. The present invention may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present invention may be stored on computer-readable media or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (8)
1. A system for testing the performance of BCH error correcting codes is characterized by comprising a pseudo-random number generator, a BCH encoder, a BCH decoder, an NAND FLASH controller, a module NAND FLASH and an error code counter;
the pseudo-random number generator is used for generating pseudo-random numbers;
the BCH encoder is used for encoding the pseudo random number to generate check information;
the NAND FLASH controller is to write the check information to the NAND FLASH;
the NAND FLASH controller is also used for reading the check information from the NAND FLASH and sending the check information to the BCH decoder;
the BCH decoder is used for decoding the check information to generate decoded data, detecting whether the decoded data has errors or not, if the decoded data has errors, performing error correction processing and correction processing on the decoded data, and sending the data obtained after the error correction processing and the correction processing to the error code counter; if the decoded data has no error, sending the decoded data to the error code counter;
the error code counter is used for comparing the pseudo random number with the data from the BCH decoder to obtain statistical information, and sending the statistical information to a preset terminal, wherein the statistical information comprises the number of error codes and/or the error code rate.
2. The system for testing the performance of a BCH error correcting code according to claim 1, wherein the pseudo-random number generator includes 16 sets of cyclic shift registers with different feedback modes, the pseudo-random number generator generates pseudo-random numbers with 16 sets of cyclic shift registers with different feedback modes, and the pseudo-random numbers are 16-bit data.
3. The system for testing performance of a BCH error correction code of claim 2 wherein the BCH encoder is configured to encode the pseudo-random number using a parallel 16-bit encoding to generate the check information.
4. The system for testing performance of a BCH error correcting code of claim 2 wherein the BCH decoder is configured to decode the check information using 16-bit decoding in parallel to produce decoded data.
5. A method of testing performance of BCH error correction code, wherein the method of testing performance of BCH error correction code is applied to a system of testing performance of BCH error correction code, the system comprising a pseudo-random number generator, a BCH encoder, a BCH decoder, an NAND FLASH controller, NAND FLASH and an error code counter, the method comprising:
the pseudo-random number generator generates a pseudo-random number;
the BCH encoder encodes the pseudo random number to generate check information;
the NAND FLASH controller writing the check information to the NAND FLASH;
the NAND FLASH controller reads the check information from the NAND FLASH and sends it to the BCH decoder;
the BCH decoder decodes the check information to generate decoded data, detects whether the decoded data has errors or not, performs error correction and correction on the decoded data if the decoded data has errors, and sends the data obtained after the error correction and correction to the error code counter; if the decoded data has no error, sending the decoded data to the error code counter;
and the error code statistics device compares the pseudo random number with the data from the BCH decoder to obtain statistical information, and sends the statistical information to a preset terminal, wherein the statistical information comprises the number of error codes and/or the error code rate.
6. The method of testing the performance of a BCH error correcting code of claim 5, wherein the pseudo-random number generator includes 16 sets of cyclic shift registers having different feedback modes, the pseudo-random number generator generating pseudo-random numbers comprising:
the pseudo-random number generator generates pseudo-random numbers by adopting 16 groups of cyclic shift registers with different feedback modes, and the pseudo-random numbers are 16-bit data.
7. The method of testing performance of a BCH error correction code of claim 6, wherein the BCH encoder encodes the pseudo-random number, generating the check information includes:
the BCH encoder is used for encoding the pseudo random number by adopting a parallel 16-bit encoding mode to generate check information.
8. The method of testing performance of a BCH error correcting code of claim 6, wherein said BCH decoder decodes the check information, generating decoded data includes:
and the BCH decoder is used for decoding the check information by adopting a parallel 16-bit decoding mode to generate decoded data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911387731.5A CN111192624A (en) | 2019-12-30 | 2019-12-30 | System and method for testing performance of BCH (broadcast channel) error correcting code |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911387731.5A CN111192624A (en) | 2019-12-30 | 2019-12-30 | System and method for testing performance of BCH (broadcast channel) error correcting code |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111192624A true CN111192624A (en) | 2020-05-22 |
Family
ID=70707768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911387731.5A Pending CN111192624A (en) | 2019-12-30 | 2019-12-30 | System and method for testing performance of BCH (broadcast channel) error correcting code |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111192624A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101488369A (en) * | 2009-02-20 | 2009-07-22 | 苏州国芯科技有限公司 | Interface circuit for BCH code controller |
| US20100281341A1 (en) * | 2009-05-04 | 2010-11-04 | National Tsing Hua University | Non-volatile memory management method |
| CN103401566A (en) * | 2013-08-06 | 2013-11-20 | 河海大学 | Parameterization BCH (broadcast channel) error-correcting code parallel encoding method and device |
| CN105553485A (en) * | 2015-12-08 | 2016-05-04 | 西安电子科技大学 | FPGA-based BCH encoding and decoding device and encoding and decoding method thereof |
| CN106708654A (en) * | 2017-01-10 | 2017-05-24 | 电子科技大学 | Circuit structure for BCH error correcting code of NAND flash |
| CN108564983A (en) * | 2018-04-10 | 2018-09-21 | 南京扬贺扬微电子科技有限公司 | A kind of LDPC test platforms for NAND FLASH |
| CN109756235A (en) * | 2018-12-07 | 2019-05-14 | 天津津航计算技术研究所 | A kind of configurable parallel BCH error correction/encoding method |
-
2019
- 2019-12-30 CN CN201911387731.5A patent/CN111192624A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101488369A (en) * | 2009-02-20 | 2009-07-22 | 苏州国芯科技有限公司 | Interface circuit for BCH code controller |
| US20100281341A1 (en) * | 2009-05-04 | 2010-11-04 | National Tsing Hua University | Non-volatile memory management method |
| CN103401566A (en) * | 2013-08-06 | 2013-11-20 | 河海大学 | Parameterization BCH (broadcast channel) error-correcting code parallel encoding method and device |
| CN105553485A (en) * | 2015-12-08 | 2016-05-04 | 西安电子科技大学 | FPGA-based BCH encoding and decoding device and encoding and decoding method thereof |
| CN106708654A (en) * | 2017-01-10 | 2017-05-24 | 电子科技大学 | Circuit structure for BCH error correcting code of NAND flash |
| CN108564983A (en) * | 2018-04-10 | 2018-09-21 | 南京扬贺扬微电子科技有限公司 | A kind of LDPC test platforms for NAND FLASH |
| CN109756235A (en) * | 2018-12-07 | 2019-05-14 | 天津津航计算技术研究所 | A kind of configurable parallel BCH error correction/encoding method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102017425B (en) | System and method for performing concatenated error correction | |
| CN111628780B (en) | Data encoding and decoding method and data processing system | |
| US9054742B2 (en) | Error and erasure decoding apparatus and method | |
| CN1146116C (en) | Shortened fire code error-trapping decoding method and apparatus | |
| US9454426B2 (en) | Codes of length tn invariant under rotations of order n | |
| CN101800560B (en) | Method for expanding error correcting capability of BCH (Broadcast Channel) encoding and decoding in Flash controller | |
| US10567003B2 (en) | List decode circuits | |
| TW202019100A (en) | Flash memory controller and encoding circuit and decoding circuit within flash memory controller | |
| US10956259B2 (en) | Error correction code memory device and codeword accessing method thereof | |
| CA2940789C (en) | Method of synchronizing a fountain code transmitting end and receiving end | |
| US8365054B2 (en) | Soft reed-solomon decoder based on error-and-erasure reed-solomon decoder | |
| CN111124741A (en) | Enhanced type checking and error correcting device facing memory characteristics | |
| US9252815B2 (en) | Extension of product codes with applications to tape and parallel channels | |
| US9141466B2 (en) | Correcting double-bit burst errors using a low density parity check technique | |
| CN101938280A (en) | Coding and decoding method and codec of error correction code | |
| US7490285B1 (en) | Marking unreliable symbols in a hard disk drive read back signal | |
| CN111192624A (en) | System and method for testing performance of BCH (broadcast channel) error correcting code | |
| CN105790882A (en) | Method and device for reducing false detection rate | |
| CN116527062A (en) | Test device and method for verifying RS (Reed-Solomon) encoding and decoding circuit function | |
| CN111224741B (en) | BCH code decoding method and decoder for satellite navigation and satellite navigation receiver | |
| CN112286716A (en) | 1024-byte storage system error control module | |
| US8024645B2 (en) | Method for error detection in a decoded digital signal stream | |
| CN101957782A (en) | Method and controller for avoiding data shift error of data storage device | |
| CN112004112A (en) | Verification method and device of hardware video encoder, electronic equipment and storage medium | |
| CN113626249B (en) | Soft decoding method, device and equipment of solid state disk and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200522 |
|
| RJ01 | Rejection of invention patent application after publication |