CN109756235A - A kind of configurable parallel BCH error correction/encoding method - Google Patents

Abstract

The present invention relates to a kind of configurable parallel BCH error correction/encoding methods, wherein include: that pretreatment comprises determining that coding configuration: information digit k verifies digit r, code word size n, error correction digit t and primitive polynomial f (x)；Calculating parameter: generator polynomial g (x)；Generator polynomial matrix T_g, verify calculating matrix T_g ^(p‑1)；Generate calculation processing circuit.Carry out coding calculating, comprising: the input of information bit data parallel；Calculate check bit data；Judge whether that input finishes, if it is, output information position data M (x), otherwise output verification position data S (x).This coding method realizes the parallelization input of data and output, the time loss for reducing process flow of equal proportion significantly improve coded treatment efficiency.

Description

A kind of configurable parallel BCH error correction/encoding method

Technical field

The invention belongs to field of data correction, the configurable parallelization BCH error correction/encoding method of specifically a kind of parameter and Hardware realization.

Background technique

BCH code is a kind of encoding and decoding algorithm that can effectively correct error in data, is calculated by coding and adds check bit Carrying out data transmission on original information position, recipient is decoded to the data of acquisition and corrects if necessary error message, The algorithm be usually used in correcting the error code of transmission that the data in communication system send and receive or data storage into Row data are written and the correcting data error during reading back.BCH code belongs to linear block codes, to the multiple mistakes occurred at random Bit error correction ability is strong, and performance is close to theoretical value especially under short or medium code length, and it is opposite to construct convenience, coding Simply, it is suitble to hardware circuit to realize.

In concrete operations, Bose-Chaudhuri-Hocquenghem Code algorithm is to generate r by the transformation of generator polynomial G (x) to k information bit M (x) Then information bit and check bit are grouped together into the process of n bit word C (x), wherein n=k+r by bit check position S (x). It for ease of description and calculates, in block code, each code word is generally represented as associated polynomial form.Want The codeword polynome of Bose-Chaudhuri-Hocquenghem Code is obtained, key is exactly to find out check polynomial, basic calculating process are as follows: first will be former Beginning message polynomial:

M (x)=m_k-1x^k-1+m_k-2x^k-2+…+m₂x²+m₁x+m₀ m_i∈{0,1}

Multiplied by x^n-kPower becomes x^n-k×M(x)；Then, x^n-k× M (x) is divided by generator polynomial

G (x)=g_rx^r+g_r-1x^r-1+…+g₂x²+g₁x+g₀ g_i∈{0,1}

Quotient q (x) and remainder polynomid S (x) are obtained, i.e.,

x^n-k× M (x)=q (x) × G (x)+S (x),

Finally obtain codeword polynome are as follows:

C (x)=x^n-k× m (x)+S (x)=c₀+c₁x+c₂x²+…+c_n-1x^n-1。

Fig. 1 show the linear feedback shift register schematic diagram realized according to the prior art, as shown in Figure 1, existing It is the side using linear feedback shift register (LFSR) as shown in Figure 1 based on generator polynomial calculation code check bit Formula.S1 and S3 is enabled to be closed, S2 is got at a, initial data m (x) is inputted to calculating one by one, while exporting to C (x)；It is then turned off S1 and S3, S2 are got at b, and being exported again to the n-k data of C (x) is coding checkout position.

Above method simple possible, but can only step-by-step computation, therefore computational efficiency is very low, is not able to satisfy high-speed data The requirement of processing.

Summary of the invention

Of the invention is designed to provide a kind of configurable parallel BCH error correction/encoding method, above-mentioned existing for solving There is the problem of technology.

A kind of configurable parallel BCH error correction/encoding method of the present invention, wherein include: using p as parallel computation data Bit wide, set information position k can be divided exactly by p, i.e. kmodp=0；Second is that p is less than verification bit length r；

Original message polynomial M (x) is divided into p group with the following methods, is obtained:

M (x)=M₀(x)+M₁(x)+...+M_p-1(x),

Wherein

It further calculates:

Wherein

G (x)=g_rx^r+g_r-1x^r-1+…+g₂x²+g₁x+g₀ g_i∈ { 0,1 }

Coding checkout position S (x) is indicated are as follows:

Overall calculation channel is divided into the input of the road p, corresponds respectively to M '_i(x), i=0~p, for per input M ' all the way_i (x), with coefficient of correspondence g_nMould is carried out with the knot D of last register storage and adds operation, and result is temporarily stored in corresponding post In storage.

This coding method realizes the parallelization input and output of data, the time for reducing process flow of equal proportion Consumption, significantly improves coded treatment efficiency.

Detailed description of the invention

Fig. 1 show the linear feedback shift register schematic diagram realized according to the prior art；

Fig. 2 show the realization schematic diagram of the calculating operation of S (x)；

Fig. 3 show the structure chart after computing block diagram variation；

Fig. 4 show a flow chart of this method of the present invention；

Fig. 5 is the structure chart for the specific example that the method for the present invention is realized.

Specific embodiment

To keep the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to of the invention Specific embodiment is described in further detail.

A kind of configurable parallel BCH error correction/encoding method of the present invention includes: to realize parallel to promote computational efficiency It calculates, algorithm below is using p as parallel computation data bit width.2 settings are provided first: first is that information bit k can be whole by p It removes, i.e. kmodp=0；Second is that p is less than verification bit length r.

Original message polynomial M (x) is divided into p group with the following methods first, is obtained:

M (x)=M₀(x)+M₁(x)+...+M_p-1(x),

Wherein

It further calculates:

Wherein

Then, coding checkout position S (x) can be indicated are as follows:

Fig. 2 show the realization schematic diagram of the calculating operation of S (x), and as indicated with 2, overall calculation channel is divided into the input of the road p, Correspond respectively to M '_i(x), i=0~p.For per input M ' all the way_i(x) for, with coefficient of correspondence g_nWith last deposit The result D of device storage carries out mould and adds operation, and result is temporarily stored in corresponding register D.Due in each effective input There is the input of (p-1) a data 0 between data, (p-1) a 0 disposed of in its entirety of data is further considered to calculate to reduce Number.The calculating operation of S (x) can be realized with Fig. 2 mode.

It is available, when input is data 0, the NextState D (t+1) and current state D of the register in circuit (t) there are following matrix operation relationships between:

It is available when input organizes data 0 with continuous (p-1) for one group of valid data I (t):

Wherein

Fig. 3 show the structure chart after computing block diagram variation, as shown in figure 3, in this way, g in above-mentioned calculation process_nSystem Number array can be usedIt indicates, then computing block diagram is further change in realize input data p road parallel processing shown in Fig. 3 Meanwhile calculation times scaled-back is 1/p times.

Fig. 4 show a flow chart of this method of the present invention, as shown in figure 4, the process of this method specifically includes: pre- place Reason and coding calculate；

Pretreatment comprises determining that coding configuration includes: information digit k, verifies digit r, code word size n, error correction digit t And primitive polynomial f (x)；

Calculating parameter: generator polynomial g (x)；Generator polynomial matrix T_g, verify calculating matrix T_g ^(p-1)；It generates and calculates Processing circuit；

Carry out coding calculating, comprising: the input of information bit data parallel；

Calculate check bit data；

Judge whether that input finishes, if it is, output information position data M (x), otherwise output verification position data S (x).

Fig. 5 be the method for the present invention realize specific example structure chart, as shown in figure 5, present invention determine that encoding scheme It is configured that using 32byte data as input information, actual information position is k=256bit=32x8bit, carries out BCH code to it Coded treatment selects GF (2⁹) as finite field calculating space.Error correcting capability is set as t=4bit, available verification digit For r=36bit, total code word size is n=292bit, therefore realizes and be based on binary system BCH (292,256,4) block code.Choosing Selecting primitive polynomial is f (x)=1+x⁴+x⁹, realize the processing of p=8 parallel-by-bit.

It calculates relevant parameter and obtains generator polynomial

G (x)=g₃₆x³⁶+g₃₅x³⁵+g₃₄x³⁴+g₃₁x³¹+g₃₀x³⁰+g₂₅x²⁵+g₂₃x²³+g₂₁x²¹+ g₂₀x²⁰+g₁₉x¹⁹+g₁₆x¹⁶+ g₁₅x¹⁵+g₁₁x¹¹+g₈x⁸+g₇x⁷+g₅x⁵+g₀

, wherein g_nFor finite field gf (2⁹) in corresponding element.To obtain matrix T_g, further calculate check bit calculating Matrix obtains:

Based on above-mentioned pre-processed results, structure such as Fig. 5 that the hardware circuit of calculating is realized is encoded, initial data 256bit information bit gradually enters coder module with 8 data bit widths parallel, and each clock cycle calculating matrix are to information bit It is handled, is stored the result into register, the also output as current circuit simultaneously of primary data information (pdi) position.When all After information bit input, stop the calculating that mould removes functional unit, switches the channel MUX using selection signal, it will be in actual registers Data gradually output in a manner of 8 parallel-by-bits to get to check bit data.

Compared with the prior art, the beneficial effects of the present invention are:

The structure of this method is simple, is easy to hardware realization, can support the different realization sides such as FPGA or chip design Formula.This structure realizes that framework effect is obvious, can quickly form corresponding scheme by the different configurations of parameter.This coding staff Method realizes the parallelization input of data and output, the time loss for reducing process flow of equal proportion significantly improve volume Code treatment effeciency.

The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improve and become Shape also should be regarded as protection scope of the present invention.

Claims (7)

1. a kind of configurable parallel BCH error correction/encoding method characterized by comprising using p as parallel computation data bit Width, set information position k can be divided exactly by p, i.e. kmodp=0；Second is that p is less than verification bit length r；

Original message polynomial M (x) is divided into p group with the following methods, is obtained:

M (x)=M₀(x)+M₁(x)+...+M_p-1(x),

Wherein

It further calculates:

Wherein

G (x)=g_rx^r+g_r-1x^r-1+…+g₂x²+g₁x+g₀ g_i∈{0,1}

Coding checkout position S (x) is indicated are as follows:

Overall calculation channel is divided into the input of the road p, corresponds respectively to M '_i(x), i=0~p, for per input M ' all the way_i(x), with it is right Answer coefficient g_nMould is carried out with the knot D of last register storage and adds operation, and result is temporarily stored in corresponding register.

2. the parallel BCH error correction/encoding method that can configure as described in claim 1, which is characterized in that due to each effective Input data between exist (p-1) a data 0 input, (p-1) a 0 disposed of in its entirety of data, to reduce calculation times.

3. the parallel BCH error correction/encoding method that can configure as described in claim 1, which is characterized in that further include: pretreatment packet It includes:

Determine coding configuration: information digit k verifies digit r, code word size n, error correction digit t and primitive polynomial f (x)；

Calculating parameter: generator polynomial g (x)；Generator polynomial matrix T_g, verify calculating matrix T_g ^(p-1)；Generate calculation processing electricity Road.

4. the parallel BCH error correction/encoding method that can configure as described in claim 1, which is characterized in that carry out coding calculating, wrap It includes: the input of information bit data parallel；Calculate check bit data；Judge whether that input finishes, if it is, output information position data M (x), otherwise output verification position data S (x).

5. the parallel BCH error correction/encoding method that can configure as described in claim 1, which is characterized in that with 32byte data work To input information, actual information position is k=256bit=32x8bit, and BCH code coded treatment is carried out to it, selects GF (2⁹) make Space is calculated for finite field, sets error correcting capability as t=4bit, obtaining verification digit is r=36bit, and total code word size is n= 292bit realizes and is based on binary system BCH (292,256,4) block code, selects primitive polynomial for f (x)=1+x⁴+x⁹, realize p The processing of=8 parallel-by-bits.

6. the parallel BCH error correction/encoding method that can configure as claimed in claim 5, which is characterized in that calculate relevant parameter and obtain Include: to generator polynomial

G (x)=g₃₆x³⁶+g₃₅x³⁵+g₃₄x³⁴+g₃₁x³¹+g₃₀x³⁰+g₂₅x²⁵+g₂₃x²³+g₂₁x²¹+g₂₀x²⁰+g₁₉x¹⁹+g₁₆x¹⁶+g₁₅x¹⁵ +g₁₁x¹¹+g₈x⁸+g₇x⁷+g₅x⁵+g₀,

Wherein g_nFor finite field gf (2⁹) in corresponding element, to obtain matrix T_g, it further calculates check bit calculating matrix and obtains:

7. the parallel BCH error correction/encoding method that can configure as described in claim 1, which is characterized in that when input is data 0 When, there are following matrix operation relationships between the NextState D (t+1) and current state D (t) of the register in circuit:

It is available when input organizes data 0 with continuous (p-1) for one group of valid data I (t):

Wherein