CN101296053A - Method and system for calculating cyclic redundancy check code - Google Patents

Abstract

The invention relates to a method and a system for calculating cyclic redundancy check code. Firstly, the cyclic redundancy check code is calculated directly according to the segments of received information; next, a first code is generated, comprising the cyclic redundancy check code of the segments and a plurality of zero-bytes; finally, the cyclic redundancy check code after adjustment is calculated according to the first code. Therefore, the system and method of the invention can directly calculate a part of the CRC check code of received sub-information and the cyclic redundancy check code after adjustment. After all sub-information of the information is received, all cyclic redundancy check codes of the sub-information after adjustment are combined to obtain the final cyclic redundancy check code of the information after adjustment. The system and the method of the invention can be verified quickly and applied in various computer systems.

Description

The method and system of calculating cyclic redundancy check code

Technical field

The present invention relates to a kind of method and system of calculating cyclic redundancy check code.

Background technology

Cyclic redundancy check (CRC) code (Cyclic Redundancy Check; Hereinafter to be referred as CRC) all implement to add the strong error checking ability that provides quite easily because of its Code And Decode, so be the most general check code on the present computer network, common application has data file (Archive), Magnetic Disk Controler (disk controller), Ethernet (Ethernet) and iSCSI etc.The retransmission mechanism of computer network widespread usage CRC technology collocation at present is to guarantee the correctness of data.

In some network application, for instance, iSCSI (Internet Small Computer System Interface) layer will be to be transmitted data add that its corresponding CRC check sign indicating number forms a message (message, or be called Protocol DataUnit:PDU) after give tcp/ip layer the transmission end, the TCP/IP transmission end is according to maximum segment size (the Maximum Segment Size that goes out with TCP/IP receiving terminal agreement; MSS) can be cut into several fragments (segment) to this iSCSI message sends away.When the TCP/IP receiving terminal is received fragment, can be temporarily stored in them in the memory earlier, up to all fragments of described iSCSI message all collect complete after, the iSCSI layer of described iSCSI message being given receiving terminal carries out CRC check again, and this moment, the iSCSI of receiving terminal must go to read in the memory described iSCSI message again to carry out CRC check.Because in this example, the CRC computing must all be collected in all fragments of described iSCSI message and just can be carried out after complete, has therefore produced one period time of delay; In addition, because the iSCSI layer of receiving terminal must go reading of data in the memory again, therefore increase the burden of memory bus again, and then influence the usefulness of system.Above-mentioned is the CRC check method of the conventional receiving terminal of the first kind.

The CRC check method of the conventional receiving terminal of second class, when receiving, immediately the fragment that receives is carried out the CRC computing, and the intermediate object program after the computing (intermediate result) is accumulated in the receive logic, when waiting to receive further fragments, continue described further fragments is carried out computing with described intermediate object program again.Like this mode, treat that all fragments all are received after, the intermediate object program in the receive logic is exactly last CRC operation result.The second class conventional method can be with reference to U.S. Patent Publication case US2006/0114909 number, though these class methods have been avoided long time of delay and extra storage access, its greatest problem is that all fragments must be received in order.Because the many employings of route (Routing) mode of network packet do not guarantee the principle (as the IP agreement) of order at present, therefore its application is had a greatly reduced quality, add second class methods aspect " intermediate object program " of each network connectivity of management, as long as therefore the many slightly complexities that will significantly increase in its design of network connectivity number are unfavorable for implementing.

The CRC check method of the conventional receiving terminal of the 3rd class is carried out the CRC computing to the fragment that receives immediately when receiving, obtain portion C RC check code, and can adjust the CRC check sign indicating number of its pairing sub-message by portion C RC check code, after waiting to obtain the CRC check sign indicating number of all sub-message, merging can draw end product together again.But the open case of the 3rd class conventional method referenced patent cooperation treaty international patent application WO03/084078 number, United States Patent (USP) US6,904, No. 558, U.S. Patent Publication case US2003/0167440 number and U.S. Patent Publication case US2006/0009952 number.Its characteristic that is primarily aimed at modulus (modulo) is disassembled, and utilizes finite field multiplier to cooperate and table look-up to adjust the CRC check sign indicating number of sub-message.

The invention provides a kind of method and system of innovating and having the calculating cyclic redundancy check code of progressive.

Summary of the invention

The invention provides a kind of method of calculating cyclic redundancy check code, it may further comprise the steps: according to the fragment computations fragment cyclic redundancy check (CRC) code of message; Produce first yard, described first yard has described fragment cyclic redundancy check (CRC) code, and other described first yard position is set at zero; With calculate adjusted cyclic redundancy check (CRC) code according to described first yardage.

The invention provides a kind of system of calculating cyclic redundancy check code, it comprises: first calculation element, first yard generation device, second calculation element.Described first calculation element is in order to the fragment computations fragment cyclic redundancy check (CRC) code according to message.Described first yard generation device is in order to produce first yard, and described first yard has described fragment cyclic redundancy check (CRC) code, and other described first yard position is set at zero.Described second calculation element is in order to calculate adjusted cyclic redundancy check (CRC) code according to described first yardage.

Utilize system and method for the present invention, allow receiving terminal when the reception of each fragment of carrying out certain message, can directly calculate the CRC check sign indicating number and the adjusted cyclic redundancy check (CRC) code of described fragment.All fragments for the treatment of described message all be collected complete after, remerge the described adjusted cyclic redundancy check (CRC) code of being calculated, to obtain the adjusted final cyclic redundancy check (CRC) code of described message.Because second calculation element can utilize multiple look-up table to finish, thereby system and method for the present invention can be verified apace, be implemented in the various computer systems.

Description of drawings

Fig. 1 is the schematic flow sheet of conventional CRC operation method;

Fig. 2 is cut into the schematic diagram of a plurality of fragments for whole message;

Fig. 3 is the schematic diagram of a plurality of sub-message;

Fig. 4 shows the schematic diagram that respectively a plurality of sub-message is carried out the CRC computing;

But Fig. 5 shows the schematic diagram of three message step-by-step-XOR amalgamation results of first sub-message generate;

Fig. 6 A and Fig. 6 B are the schematic diagram of the method for calculating cyclic redundancy check code of the present invention;

Fig. 7 is the schematic diagram of the system of calculating cyclic redundancy check code of the present invention;

Fig. 8 shows portion C RC check code of the present invention, first yard and a plurality of second yard schematic diagrames;

Fig. 9 shows the configuration schematic diagram of the memory of first embodiment of the invention;

Figure 10 shows the schematic diagram of second calculation element of first embodiment of the invention;

Figure 11 shows the schematic diagram of another enforcement aspect of first embodiment of the invention second calculation element;

Figure 12 shows the decomposing schematic representation of second yard of the present invention's the first exponent number value;

Figure 13 shows the configuration schematic diagram of the memory of second embodiment of the invention;

Figure 14 shows a plurality of second yard schematic diagram of second embodiment of the invention;

Figure 15 shows the schematic diagram of second calculation element of second embodiment of the invention;

Figure 16 A is the computing schematic diagram of second embodiment of the invention to 16G;

Figure 17 shows the schematic diagram of numerical value decomposer of the present invention;

Figure 18 shows a plurality of second yard schematic diagram of third embodiment of the invention; With

Figure 19 shows the schematic diagram of second calculation element of third embodiment of the invention.

Embodiment

The calculating of CRC check sign indicating number can directly obtain with polynomial division traditionally, the high power that data that at first will be to be transmitted are regarded a multinomial d (x) as with binary representation and big-endian is first in the coefficient (c0efficients) that hangs down power unit, so the coefficient of each power unit of d (x) is two-symbol 1 or 0 (being equivalent to the element of finite field gf (2)).Obtain one according to the specification of using (specification) then and produce multinomial (generating polynomial) g (x), by g (x) its high order number formulary (degree) m as can be known.D (x) is multiplied by x ^mThe back can obtain a remainder polynomid (remainder polynomial) r (x), shown in formula one divided by g (x).The coefficient of described remainder polynomid is the CRC check sign indicating number of desiring to try to achieve.

D (x) * x ^m=c (x) * g (x)+r (x) formula one

Because addition is equal to subtraction in finite field gf (2), thus can by formula one derive formula two.

D (x) * x ^m+ r (x)=c (x) * g (x) formula two

Left side represented meaning in the formula two is the CRC check sign indicating number that will calculate gained and places the data end, i.e. CRC coded system traditionally is that the multinomial coefficient with formula two is sent to receiving terminal when therefore transmitting.The multinomial coefficient of formula two is called the code word (codeword) of CRC again, and just as shown in the right item of formula two, promptly " is the multinomial that coefficient is formed with the code word " must be times formula that produces multinomial g (x) to its characteristic.Whether characteristic thus, receiving terminal can be when receiving the data that have the CRC check sign indicating number, need only the described data of verification be whether times formula of g (x) is can judgment data correct, quite easy on the implementation.

Though above-mentioned conventional method is easy on the implementation, problem is arranged greatly on usefulness.For example when the CRC encoding and decoding are used in the application of internet, because adding the message of CRC check sign indicating number also must transmit as the TCP/IP procotol by other, if message is crossed stool and can be segmented into several fragments by the TCP/IP procotol and send, therefore the application program of receiving terminal (applications) must just can be carried out above-mentioned multinomial long division after the TCP/IP procotol collects described message traditionally.Because most use (as iSCSI) can be accumulated to data volume to be transmitted a degree and (just can carry out the CRC coding as behind the 8KB～14KB), therefore data volume is also quite consuming time when decoding like this, add because the CRC computing of this mode must just can be carried out after all message fragments, therefore what can not be done for some time to collecting from receiving first fragment; In addition, follow-up checkout action must go to read in the memory (as 8KB～14KB size) message again again, therefore increases the burden of memory bus again, and then influences the usefulness of system.

For fear of the problems referred to above, can utilize the linear characteristic in the CRC computing, CRC is calculated receive in fragment in advance (as receiving the stage) time to be carried out, and after all fragments of message all collect, adjust (adjusting) and merging (merge) again at TCP/IP.

With reference to figure 1, conventional CRC operation method at first receives whole message (message) m, shown in step S11, calculate the CRC check sign indicating number of described message again, shown in step S12, the CRC check sign indicating number that is calculated is called as final CRC check sign indicating number (Final-CRC), shown in step S13.

But because the message of many network applications all surpasses maximum segment size (the Maximum Segment Size of transport layer; MSS), just send out after being cut to several fragments so can be transmitted layer earlier, as shown in Figure 2, message m is cut into a plurality of fragments (segment), for example message be cut into the 0th fragment, the 1st fragment ..., a n-2 fragment and n-1 fragment.

With reference to figure 3, before and after each fragment, respectively fill zero of correct number and can obtain sub-message sm _i, i=0～n-1.For example: the 0th sub-message is to add Z after the 0th fragment ₀Individual 0, the 1 sub-message is to add Z after the 1st fragment ₁Individual 0 and before the 1st fragment, add fragment length 0.The pass of message and each sub-message is

$m=\mathrm{<figure-callout\; id="0"\; label="s\; m"\; filenames="A20071009796600431.png,A20071009796600441.png"\; state="\{\{state\}\}">s</figure-callout>}{m}_{}{}_0\&CirclePlus;s{\mathrm{<figure-callout\; id="1"\; label="m"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">m</figure-callout>}}_1\&CirclePlus;...\&CirclePlus;s{m}_{n-2}\&CirclePlus;s{m}_{n-1}$ Formula three

Wherein

Be step-by-step-XOR (XOR).Because the characteristic of linear transformation (linear transformation) is satisfied in the CRC computing, therefore can derive again and obtain formula four by formula three.

$\mathrm{CRC}\left(m\right)=\mathrm{CRC}(\mathrm{<figure-callout\; id="0"\; label="s\; m"\; filenames="A20071009796600431.png,A20071009796600441.png"\; state="\{\{state\}\}">s</figure-callout>}{m}_{}{}_0\&CirclePlus;s{\mathrm{<figure-callout\; id="1"\; label="m"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">m</figure-callout>}}_1\&CirclePlus;...\&CirclePlus;s{m}_{n-2}\&CirclePlus;s{m}_{n-1})$

$=\mathrm{CRC}\left(s{m}_0\right)\&CirclePlus;\mathrm{CRC}\left(s{m}_1\right)\&CirclePlus;...\&CirclePlus;\mathrm{CRC}\left(s{m}_{n-2}\right)\&CirclePlus;\mathrm{CRC}\left(s{m}_{n-1}\right)$ Formula four

By formula four as can be known, the result who sub-message is distinctly carried out the CRC computing merges with step-by-step-XOR and promptly is equivalent to the result who whole message is carried out the CRC computing.Because the characteristic that this is important, so can just calculate the check code of each sub-message earlier when receiving each sub-message, the present invention is referred to as " adjusted CRC check sign indicating number (Adjusted-CRC) ".By finding in the formula four, because step-by-step-XOR itself satisfies law of communication, even therefore the order of sub-message sink can not influence result of calculation according to the order in the former message yet.

Based on above-mentioned discussion, carry out the CRC computing with reference to the message of antithetical phrase respectively shown in Figure 4 and draw " adjusted CRC check sign indicating number ", last again " the adjusted CRC check sign indicating number " of each sub-message merged the CRC check sign indicating number that can obtain former message with step-by-step-XOR, be final CRC check sign indicating number.

By Fig. 4 and formula four as can be known, when receiving fragment, can before and after described fragment, fill the form that zero of correct number makes it to become sub-message in advance, just can needless to say whole fragments collect promptly and try to achieve " adjusted CRC check sign indicating number " earlier.Further specify just before dawn with reference to figure 5 and formula,, can try to achieve " adjusted CRC check sign indicating number " in advance as long as after fragment, fill zero of correct number.In Fig. 5, we are example with first fragment (Segment 1), and first fragment can be launched into the step-by-step-XOR amalgamation result of three message, and for example shown in the formula five, the first sub-message is carried out the CRC computing only be equivalent to fragment (sm to the first sub-message ₁`) carry out the CRC computing.Therefore, as long as after fragment, fill zero of correct number, can try to achieve " adjusted CRC check sign indicating number ".

$\mathrm{CRC}\left(s{m}_1\right)=\mathrm{CRC}(0\&CirclePlus;\mathrm{<figure-callout\; id="1"\; label="s\; m"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">s</figure-callout>}{m_{}}^{}{{}_1}^{`}\&CirclePlus;0)$

$=\mathrm{CRC}\left(0\right)\&CirclePlus;\mathrm{CRC}\left(\mathrm{<figure-callout\; id="1"\; label="s\; m"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">s</figure-callout>}{m_{}}^{}{{}_1}^{`}\right)\&CirclePlus;\mathrm{CRC}\left(0\right)$

$=0\&CirclePlus;\mathrm{CRC}\left(\mathrm{<figure-callout\; id="1"\; label="s\; m"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">s</figure-callout>}{m_{}}^{}{{}_1}^{`}\right)\&CirclePlus;0$

$=\mathrm{CRC}\left({{\mathrm{<figure-callout\; id="1"\; label="sm"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">sm</figure-callout>}}_1}^{`}\right)$ Formula five

According to formula five, as long as fill the zero of correct number fragment after, promptly generally CRC circuit (as LFSR) directly carries out computing and obtains " adjusted CRC check sign indicating number " when receiving fragment.Yet in the express network, the speed of reception fragment is quite important, reaches the speed that bag is poured into if receive the speed of fragment, just can cause bag to damage or loss.If computing is carried out in direct zero padding when receiving fragment, so can be excessive because of zero quantity, make that operation time is long and significantly reduce the speed that receives fragment, finally cause subsequent packet to damage or lose.

Because the CRC computing is the computing that long division is got remainder, therefore suppose that the binary representation method of certain message m sg is shown msg (x) with polynomial table, just can define the CRC computings as formula six:

CRC (msg)=(msg (x) * x ^m) modg (x) formula six

The result of formula five derived according to the definition of formula six again can obtain formula seven.

$\mathrm{CRC}\left(\mathrm{<figure-callout\; id="1"\; label="sm"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">sm</figure-callout>}{1}^{`}\right)=(\mathrm{<figure-callout\; id="1"\; label="sm"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">sm</figure-callout>}{1}^{`}\left(x\right)\&times;x^m)\mathrm{mod}g\left(x\right)$

$=({\mathrm{seg}}_1\left(x\right)\&times;{\mathrm{<figure-callout\; id="1"\; label="x\; z"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">x</figure-callout>}}^{z_{}}\&times;x^m)\mathrm{mod}g\left(x\right)$

$=({\mathrm{seg}}_1\left(x\right)\&times;x^m\&times;x^{z_1})\mathrm{mod}g\left(x\right)$

$=\left((({\mathrm{seg}}_1\left(x\right)\&times;x^m\mathrm{mod}g\left(x\right))\&times;(x^{{\mathrm{<figure-callout\; id="1"\; label="z"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">z</figure-callout>}}_1}\mathrm{mod}g\left(x\right))\right)\mathrm{mod}g\left(x\right)$ Formula seven

Because (seg ₁(x) * x ^m) modg (x) is seg ₁Get the CRC check sign indicating number, if so (seg ₁(x) * x ^m) separating of modg (x) be crc ₁(x), so formula seven can push away again formula eight.

$\mathrm{CRC}\left(s{{\mathrm{<figure-callout\; id="1"\; label="m"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">m</figure-callout>}}_1}^{`}\right)=({\mathrm{crc}}_1\left(x\right)\&times;\left({\mathrm{<figure-callout\; id="1"\; label="x\; z"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">x</figure-callout>}}^{z_{}}\mathrm{mod}g\left(x\right)\right))\mathrm{mod}g\left(x\right)$

$=(\left({\mathrm{crc}}_1\left(x\right)\mathrm{mod}g\left(x\right)\right)\&times;\left({\mathrm{<figure-callout\; id="1"\; label="x\; z"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">x</figure-callout>}}^{z_{}}\mathrm{mod}g\left(x\right)\right))\mathrm{mod}g\left(x\right)$

$=({\mathrm{crc}}_1\left(x\right)\&times;x^{z_1})\mathrm{mod}g\left(x\right)$

$=({\mathrm{crc}}_1\left(x\right)\&times;x^{z_1-m}\&times;x^m)\mathrm{mod}g\left(x\right)$

$=({\mathrm{crc}}_1\left(x\right)\&times;x^{z_{1a}}\&times;x^m)\mathrm{mod}g\left(x\right)$

$=\mathrm{CRC}(\mathrm{<figure-callout\; id="1"\; label="crc"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">crc</figure-callout>}1\_\mathrm{pad}\_z1a)$ Formula eight

Z wherein _1a=z ₁-m, and crc1_pad_z1a is at crc ₁Fill z afterwards _1aData after individual zero.

With reference to figure 6A and 6B, the method for calculating cyclic redundancy check code of the present invention, at first (for example: (for example: portion C RC check code 0), the described stage is an operation stages the 0th fragment) to calculate the fragment cyclic redundancy check (CRC) code by the fragment of message.In addition as can be known by formula seven and formula eight, when receiving message, only must be to the fragment computations its " portion C RC check code " of message (as the crc in the formula eight ₁(x)), need not whole message is done the cyclic redundancy check (CRC) code computing.

Produce first yard again, described first yard has described fragment cyclic redundancy check (CRC) code (as the crc in the formula eight ₁(x)), and described fragment cyclic redundancy check (CRC) code is in described first yard high bit, and other described first yard position is set at zero, promptly fills suitable length than low level (as the z in the formula eight described first yard _1a) individual zero.Can utilize any method (comprising conventional method or the method for following examples of the present invention) to calculate adjusted cyclic redundancy check (CRC) code (A djusted-CRC n) at last by described first yardage.The described stage is the adjusting stage.Utilize said method can calculate the adjusted cyclic redundancy check (CRC) code of each sub-message.

With reference to figure 7, it shows the system schematic of calculating cyclic redundancy check code of the present invention.The system 10 of calculating cyclic redundancy check code of the present invention comprises: first calculation element 11, first yard generation device 12 and second calculation element 13.Described first calculation element 11 is in order to the fragment computations fragment cyclic redundancy check (CRC) code according to message.Described first yard generation device 12 is in order to produce first yard, and described first yard has described fragment cyclic redundancy check (CRC) code, and other described first yard position is set at zero.That is, described fragment cyclic redundancy check (CRC) code is in described first yard high bit, and other described first yard position is set at zero, promptly fills suitable length than low level (as the z in the formula eight described first yard _1a) individual zero.

Described second calculation element 13 is in order to calculate adjusted cyclic redundancy check (CRC) code according to described first yardage.Described second calculation element 13 can utilize any method (comprising conventional method or the method for following examples of the present invention) to calculate adjusted cyclic redundancy check (CRC) code by described first yardage.

With reference to figure 6A and 6B, after the adjusted cyclic redundancy check (CRC) code of each reception fragment all calculated, promptly available step-by-step-XOR merged the final CRC check sign indicating number that draws whole message again.The described stage is a merging phase.Therefore, utilize method of the present invention, process for the CRC computing of whole message is divided into three phases, is divided into operation stages (Computation Phase), adjusting stage (Adjusting Phase) and merging phase (Merging Phase) shown in Fig. 6 A and 6B in regular turn.

The enforcement of CRC computing is common 1 processing, the processing of 8 parallel-by-bits, the processing of 16 parallel-by-bits, 32 parallel-by-bit processing etc., and wherein degree of parallelism is healed, and then usefulness is better for height.The present invention utilizes tabling look-up as an example of 8 parallel-by-bits processing, proposes method of adjustment, and describes by following three embodiment.

Because present most CRC uses the check code that all adopts 32 (promptly adopting high order number formulary is 31 g (x)), therefore following three embodiment illustrate that with this how adjusting " portion C RC check code " becomes " adjusted CRC check sign indicating number ".

First embodiment:

With reference to figure 8, it shows that certain fragment k through after the operation stages, calculates a portion C RC check code (Partial-CRC _k), in the present embodiment, described portion C RC check code is 32, therefore can be regarded as 4 bytes, big-endian is respectively the first sub-byte B ₀, the second sub-byte B ₁, the 3rd sub-byte B ₂With the 4th sub-byte B ₃According to described portion C RC check code (Partial-CRC _k), produce first yard (pz) again, described first yard has described fragment cyclic redundancy check (CRC) code, and described fragment cyclic redundancy check (CRC) code is in described first yard high bit, other described first yard position is set at zero, promptly fills suitable length zero byte described first yard than low level.In the present embodiment, be at described portion C RC check code (B ₀B ₁B ₂B ₃) rear end fills described z _KaIndividual zero byte (Zeroed-Byte) is to produce described first yard (pz).

The computational methods of described first yard zero byte quantity are, calculate the pairing sub-message of described fragment k earlier, and its back segment is zero byte (Byte) quantity z _k, again with z _kDeduct (m/8) and can obtain z _Ka(can with reference to above-mentioned formula eight).

Be launched into a plurality of second yard by described first yard (pz) again, described fragment cyclic redundancy check (CRC) code has a plurality of sub-bytes, and it is deployed into described second yard highest byte respectively, and other described second yard byte is zero.In the present embodiment, be launched into four second yard (pz by described first yard (pz) ₀, pz ₁, pz ₂And pz ₃), and four sub-byte (B of described fragment cyclic redundancy check (CRC) code ₀B ₁B ₂B ₃), it is deployed into described second yard highest byte respectively, and other described second yard byte is zero.Because CRC has the characteristic of linear transformation, therefore can push away formula nine.

$\mathrm{CRC}\left(\mathrm{pz}\right)=\mathrm{CRC}(\mathrm{<figure-callout\; id="0"\; label="p\; z"\; filenames="A20071009796600431.png,A20071009796600441.png"\; state="\{\{state\}\}">p</figure-callout>}{z}_{}{}_0\&CirclePlus;\mathrm{<figure-callout\; id="1"\; label="p\; z"\; filenames="A20071009796600431.png,A20071009796600501.png"\; state="\{\{state\}\}">p</figure-callout>}{z}_{}{}_1\&CirclePlus;\mathrm{<figure-callout\; id="2"\; label="p\; z"\; filenames="A20071009796600361.png,A20071009796600371.png"\; state="\{\{state\}\}">p</figure-callout>}{z}_{}{}_2\&CirclePlus;p{z}_3)$

$=\mathrm{CRC}\left(p{z}_0\right)\&CirclePlus;\mathrm{CRC}\left(p{z}_1\right)\&CirclePlus;\mathrm{CRC}\left(p{z}_2\right)\&CirclePlus;\mathrm{CRC}\left(p{z}_3\right)$ Formula nine

Shown in formula nine, can obtain described second yard (pz respectively ₀, pz ₁, pz ₂And pz ₃) the CRC check sign indicating number after, merge the CRC check sign indicating number that can calculate described first yard (pz) with step-by-step-XOR again, the CRC check sign indicating number of described first yard (pz) be exactly described fragment k " the adjusted CRC check sign indicating number " of corresponding sub-message.

Because described second yard (pz ₀, pz ₁, pz ₂And pz ₃) respectively have only first byte (for example: sub-byte B ₀, B ₁, B ₂, B ₃) value is arranged, what connect later all is zero byte, therefore can utilize memory, and described memory comprises a plurality of, and each piece is stored a plurality of cyclic redundancy check (CRC) operation results of corresponding sub-byte, as shown in Figure 9.In the present embodiment, it is 8192 pieces that the memory of Fig. 9 is divided into, and it is respectively LUT ₁～LUT ₈₁₉₂, each piece records 256 kinds through the CRC calculated result at 256 kinds of variations (0～255) of a sub-byte in advance.As LUT ₁1 zero CRC operation result, the LUT after the byte filled in record ₂2 the zero CRC operation results after the byte filled in record ..., LUT ₈₁₉₂8192 the zero CRC operation results after the byte filled in record.Represent with mathematical formulae, then LUT ₁, LUT ₂..., LUT ₈₁₉₂Table look-up to be respectively applied for and find separating in the following formula ten.

LUT ₁(B)＝(B(x)×x ^1×8)modg(x)

LUT ₂(B)＝(B(x)×x ^2×8)modg(x)

...

LUT ₈₁₉₂(B)=(B (x) * x ^{8192 * 8}) modg (x) formula ten

Promptly be equivalent to following formula 11:

LUT _p(B)=(B (x) * x ^8p) modg (x) formula 11

Wherein the B in formula ten and the formula 11 is 8 data.

Because described second yard (pz ₀) rear end has z _Ka+ 3 zero bytes, in therefore tabling look-up by the memory of Fig. 9,

The B of piece ₀Locational 32 are CRC (pz ₀) separate.Described second yard (pz ₁) rear end has z _Ka+ 2 zero bytes, in therefore tabling look-up by the memory of Fig. 9, The B of piece ₁Locational 32 are CRC (pz ₁) separate.Described second yard (pz ₂) rear end has z _Ka+ 1 zero byte, in therefore tabling look-up by the memory of Fig. 9,

The B of piece ₂Locational 32 are CRC (pz ₂) separate.Described second yard (pz ₃) there is z the rear end _KaIndividual zero byte, in therefore tabling look-up by the memory of figure eight,

The B of piece ₃Locational 32 are CRC (pz ₃) separate.Table look-up at the memory that utilizes Fig. 9 and to obtain CRC (pz ₀), CRC (pz ₁), CRC (pz ₂) and CRC (pz ₃) separate after, just can as following formula 12 with step-by-step-XOR merge with fragment k as described in obtaining " the adjusted CRC check sign indicating number " of corresponding sub-message.

$\mathrm{CRC}\left(\mathrm{pz}\right)=\mathrm{CRC}\left(p{z}_0\right)\&CirclePlus;\mathrm{CRC}\left(p{z}_1\right)\&CirclePlus;\mathrm{CRC}\left(p{z}_2\right)\&CirclePlus;\mathrm{CRC}\left(p{z}_3\right)$

$=\mathrm{LU}{T}_{z_{\mathrm{ka}}+3}\left(B_0\right)\&CirclePlus;{\mathrm{LUT}}_{z_{\mathrm{ka}}+2}\left(B_1\right)\&CirclePlus;{\mathrm{LUT}}_{z_{\mathrm{ka}}+1}\left(B_2\right)\&CirclePlus;{\mathrm{LUT}}_{z_{\mathrm{ka}}}\left(B_3\right)$ Formula 12

Therefore in first embodiment, can finish tabling look-up of a 8MB memory as shown in Figure 9 in advance,, calculate " adjusted CRC check sign indicating number " to carry out the action of adjusting stage fast for the iSCSI message of 16KB.

With reference to Figure 10, it shows the schematic diagram of second calculation element of first embodiment of the invention.Second calculation element 20 of first embodiment of the invention comprises expanding unit 21, the 3rd calculation element 22 and XOR device 23.Described expanding unit 21 is in order to be launched into a plurality of second yard by described first yard, and described fragment cyclic redundancy check (CRC) code has a plurality of sub-bytes, and it is deployed into described second yard highest byte respectively, and other described second yard byte is zero.

Described the 3rd calculation element 22 carries out the cyclic redundancy check (CRC) code computing respectively for described second yard in order to foundation, to obtain a plurality of trigrams.Described XOR device 23 is in order to the described trigram of XOR, to calculate described adjusted cyclic redundancy check (CRC) code.

With reference to Figure 11, it shows the schematic diagram of second calculation element of another enforcement aspect of first embodiment of the invention.Second calculation element 30 of another enforcement aspect of first embodiment of the invention comprises expanding unit 31, memory 32 and XOR device 33.Described expanding unit 31 is in order to be launched into a plurality of second yard by described first yard, and described fragment cyclic redundancy check (CRC) code has a plurality of sub-bytes, and it is deployed into described second yard highest byte respectively, and other described second yard byte is zero.

According to described second yard, correspondingly at described memory 32 places obtain a plurality of trigrams, described trigram is corresponding to described second yard cyclic redundancy check (CRC) operation result; Described XOR device 33 is in order to the described trigram of XOR, to calculate described adjusted cyclic redundancy check (CRC) code.

The method of above-mentioned first embodiment can be finished with 4 cpu bus access actions (local bus transaction) under the situation of not using cache memory (cache) fast, needs bigger storage space to set up in advance and tables look-up.

Second embodiment:

The first embodiment utilization is than the large memories action of directly tabling look-up, and is limited because of general its memory resource of embedded system (embedded systems) though that it is regulated the speed is quite fast, and so big storage space possibly can't be provided.Yet identical method but has more economical implementation method, and second embodiment uses repeatedly lookup table mode instead to finish, because the storage space of its demand is little, therefore is fit to major applications.

Cooperation is with reference to figure 8 and Figure 12, if second yard (second yard pz for example ₃) have z than low byte _KaIndividual zero byte, z _KaBe called the first exponent number value, the described first exponent number value is disassembled according to the number of combinations of 2 power power, can split into a plurality of 2 power power and, can split into a plurality of second exponent number values.With Figure 12 is the example explanation, described second yard (pz ₃) at highest byte B ₃Have 25 zero bytes afterwards, the promptly described first exponent number value is 25, and 25 of the described first exponent number values are complied with the number of combinations of 2 power power and disassembled, and can split into 16 (2 ⁴) individual zero byte and last 8 (2 ³) individual zero byte and last 1 (2 ⁰) individual zero byte, promptly 25=16 (2 ⁴)+8 (2 ³)+1 (2 ⁰).Three the second exponent number values that the described first exponent number value 25 is disassembled are 16,8 and 1 from high to low.

Therefore, if need the described second yard (pz of computation of table lookup ₃) the CRC operation result, when tabling look-up in principle as long as find earlier at byte B ₃A CRC operation result that has 16 zero bytes afterwards; According to a described CRC operation result, find the 2nd CRC operation result that after a described CRC operation result, has 8 zero bytes again; Again according to described the 2nd CRC operation result, find the 3rd CRC operation result that has 1 zero byte after described the 2nd CRC operation result at last, then described the 3rd CRC operation result is described second yard (pz ₃) the CRC operation result.

Utilize mentioned above principle to obtain described second yard (pz for example with lookup table mode repeatedly ₃) the CRC operation result, only must keep the piece that belongs to 2 power power among above-mentioned first embodiment, other piece does not then need, therefore, only need the storage space of 14KB just can finish the function that is basically the same as those in the first embodiment in the present embodiment, the memory of 14KB as shown in figure 13.

Yet, because of general CRC check sign indicating number is 32 positions (4 bytes), so 1 byte (B for example ₃) add a plurality of zero bytes afterwards, by obtaining 4 bytes after tabling look-up, must (be above-mentioned B to 4 bytes because of each iteration (Iteration) in the gradation adjustment again ₀, B ₁, B ₂And B ₃) table look-up respectively, can obtain 4 group of 4 byte data after therefore 4 bytes being tabled look-up, implement this 4 group of 4 byte data to be merged earlier and carry out next iteration adjustment action again, be difficult to merge to avoid checking result to disperse (divergent).In the present embodiment, be 16,8 and 1 from high to low because the described first exponent number value 25 is disassembled into three second exponent number values, thereby need carry out the iteration computation of table lookup three times.Each iteration can utilize four clock cycle to finish.

With reference to Figure 14, it shows a plurality of second yard schematic diagram of second embodiment of the invention.Get second rank from the described second exponent number value from high to low and handle numerical value, in the present embodiment, it is 16,8 and 1 from high to low that the described first exponent number value 25 is disassembled into three second exponent number values, thereby during first iteration (Iteration 1), it is 16 (2 that numerical value is handled on described second rank ⁴), a in Figure 14 is 4, and by described fragment cyclic redundancy check (CRC) code (B ₀B ₁B ₂B ₃) be launched into a plurality of second yard, described fragment cyclic redundancy check (CRC) code (B ₀B ₁B ₂B ₃) having four sub-bytes, it is deployed into described second yard highest byte respectively, and other described second yard byte is zero, and the byte number of described zero byte is that numerical value is handled on described second rank.In the present embodiment, have four second yard and be respectively the tool first sub-byte (B ₀) second yard 41, the tool second sub-byte (B ₁) second yard 42, tool the 3rd sub-byte (B ₂) second yard 43 and tool the 4th sub-byte (B ₃) second yard 44.

Order in first clock cycle (C1) according to described sub-byte obtains the tool first sub-byte (B from described second yard ₀) second yard 41, according to the described tool first sub-byte (B ₀) second yard 41, locate the corresponding trigram of obtaining at least one memory (with reference to Figure 13), described trigram is corresponding to the described tool first sub-byte (B ₀) second yard 41 cyclic redundancy check (CRC) operation result.

Cooperation illustrates the embodiment of the computational methods of second embodiment with the hardware circuit realization with reference to Figure 14 and Figure 15.Second calculation element 50 of second embodiment of the invention comprises: numerical value decomposer 60, first multiplexer 51, second multiplexer 52, at least one memory 53, the 3rd multiplexer 54, first register 55, zero padding byte operation device 56, exclusive-OR operator 57 and second register 58.

Described numerical value decomposer 60 is in order to decompose described first yard a plurality of zero bytes, and the byte number of described zero byte is the first exponent number value, and it is a plurality of second exponent number values that the number of combinations of the power power according to 2 is decomposed the described first exponent number value.In the present embodiment, to disassemble into three second exponent number values be 16,8 and 1 to the described first exponent number value 25 from high to low.

Described first multiplexer 51 is in order to receive described fragment cyclic redundancy check (CRC) code and iteration result, select signal (load 1) according to first, described fragment cyclic redundancy check (CRC) code of switching controls or described iteration result are to the output of described first multiplexer 51, and described fragment cyclic redundancy check (CRC) code and described iteration result all have a plurality of sub-bytes.In the present embodiment, described fragment cyclic redundancy check (CRC) code and described iteration result all have four sub-bytes.

Second multiplexer 52 is in order to receive described sub-byte, and according to the second selection signal (b_sel), one in the described sub-byte of switching controls is to the output of described second multiplexer 52.

Described memory 53 is in order to store a plurality of trigrams, described trigram is corresponding to a plurality of second yard cyclic redundancy check (CRC) operation results, described second yard highest byte is respectively described sub-byte, and other described second yard byte is zero, and the byte number of described zero byte is the described second exponent number value.

Described the 3rd multiplexer 54 is in order to receive described trigram and XOR result, according to the 3rd selection signal (new), described trigram of switching controls or described XOR result are the first stage casing cyclic redundancy check (CRC) operation result to the output of described the 3rd multiplexer 54.

First register 55 is in order to store the described first stage casing cyclic redundancy check (CRC) operation result.Described zero padding byte operation device 56 is mended the cyclic redundancy check (CRC) operation result of one zero byte afterwards in order to be performed on the described first stage casing cyclic redundancy check (CRC) operation result, and computing gets the second stage casing cyclic redundancy check (CRC) operation result.

Described exclusive-OR operator 57 is in order to described trigram of XOR and the described second stage casing cyclic redundancy check (CRC) operation result, calculating described XOR result, and outputs to described the 3rd multiplexer 54.Described second register 58 is in order to storing the described first stage casing cyclic redundancy check (CRC) operation result, and whether outputs to described first multiplexer 51 through enable signal control and be described iteration result.

Below describe the computational methods of second embodiment in detail:

When first iteration (Iteration 1), (C1) locates in first clock cycle, and through the calculating of described numerical value decomposer 60, it is 16 (2 that numerical value is handled on described second rank ⁴), first control signal (tbl_idx) is made as a, and wherein a is 4, and numerical value (16=2 is handled on promptly above-mentioned second rank ⁴) the inferior number formulary of 2 power power.First of described first multiplexer 51 selects signal (load 1) to be made as 1, makes portion C RC check code be input to the output of first multiplexer 51, and is sent to second multiplexer 52.Select signal (b_sel) to be made as B second of second multiplexer 52 again ₀So that the first sub-byte (B of portion C RC check code ₀) be input to memory 53.

Memory 53 is according to the described first sub-byte (B ₀) and described first control signal (tbl_idx) (being that numerical value 16 is handled on described second rank), can be equal to and learn the above-mentioned tool first sub-byte (B ₀) second yard 41, and the corresponding above-mentioned trigram 81 (with reference to figure 16A) of obtaining of tabling look-up, described trigram 81 is corresponding to the described tool first sub-byte (B ₀) second yard 41 cyclic redundancy check (CRC) operation result.

Select signal (new) to be made as 1 the 3rd of the 3rd multiplexer 54 again, with the next clock cycle then, make described trigram 81 store described first register 55 into by 54 inputs of described the 3rd multiplexer.

Locate in second clock cycle (C2), obtain the tool second sub-byte (B from described second yard ₁) second yard 42, according to the described tool second sub-byte (B ₁) second yard 42, correspondingly at described memory 53 places obtain the 4th yard 82 (with reference to figure 16B), described the 4th yard 82 corresponding to the described tool second sub-byte (B ₁) second yard 42 cyclic redundancy check (CRC) operation result.

With reference to figure 16A, can calculate the 5th yard 83 simultaneously again, described the 5th yard 83 lowest byte is one zero byte, and other described the 5th yard 83 byte is described trigram 81, calculates described the 5th yard 83 cyclic redundancy check (CRC) operation result again, is the 6th yard 84.With reference to figure 16C, XOR is described the 4th yard 82 and described the 6th yard 84 again, calculates the 7th yard 85.

Cooperate again with reference to Figure 14 and Figure 16 A, calculate the described the 5th yard 83 and the 6th yards 84 mean, because the described tool first sub-byte (B ₀) second yard 41 after should add one zero byte, the cyclic redundancy check (CRC) operation result that it calculated could with the described tool second sub-byte (B ₁) second yard 42 do XOR.Therefore, calculating the described tool first sub-byte (B ₀) second yard 41 cyclic redundancy check (CRC) operation result (trigram 81) after, must calculate the described the 5th yard 83 and the 6th yards 84 again, to obtain at the described tool first sub-byte (B ₀) second yard 41 after add one zero byte, the cyclic redundancy check (CRC) operation result that it calculated (the 6th yard 84).At last, described the 6th yard 84 again with the described tool second sub-byte (B ₁) second yard 42 cyclic redundancy check (CRC) operation result (the 4th yard 82) do XOR.

Cooperate again with reference to Figure 15,16A to 16C, the computing of implementing the second clock cycle with circuit is described.At second clock cycle place, select signal (b_sel) to be made as B second of second multiplexer 52 ₁So that the second sub-byte (B of portion C RC check code ₁) be input to memory 53.Memory 53 is according to the described second sub-byte (B ₁) and described first control signal (tbl_idx) (being that numerical value 16 is handled on described second rank), can be equal to and learn the above-mentioned tool second sub-byte (B ₁) second yard 42, and table look-up and correspondingly obtain above-mentioned the 4th yard, described the 4th yard 82 corresponding to the described tool second sub-byte (B ₁) second yard 42 cyclic redundancy check (CRC) operation result.Described the 4th yard 82 is input to exclusive-OR operator 57.

At this moment, the trigram 81 that zero padding byte operation device 56 is stored according to described first register 55 calculates described the 5th yard 83 and described the 6th yard 84.That is, described zero padding byte operation device 56 is in order to calculate the cyclic redundancy check (CRC) operation result of mending one zero byte after described trigram 81.Described the 6th yard 84 is input to exclusive-OR operator 57, and exclusive-OR operator 57 carries out described the 4th yard 82 and described the 6th yard 84 XOR, to calculate described the 7th yard 85.At this moment, select signal (new) to be made as 0 the 3rd of the 3rd multiplexer 54, with the next clock cycle then, make the described first stage casing cyclic redundancy code operation result (described the 7th yard 85) store described first register 55 into by described the 3rd multiplexer 54 input.

The 3rd clock cycle (C3) obtained tool the 3rd sub-byte (B from described second yard ₂) second yard 43, according to described tool the 3rd sub-byte (B ₂) second yard 43, corresponding the 8th yard 86 (with reference to figure 16D), described the 8th yard 86 second yard 43 the cyclic redundancy check (CRC) operation result obtained at described memory place corresponding to described tool the 3rd sub-byte.

With reference to figure 16E, can calculate the 9th yard 87 simultaneously, described the 9th yard 87 lowest byte is zero byte, other described the 9th yard 87 byte is described the 7th yard 85, calculates described the 9th yard 87 cyclic redundancy check (CRC) operation result, is the tenth yard 88.XOR is the described the 8th yard 86 and the described ten yards 88 again, calculates the 11 yard 89.

Similarly, calculate the described the 9th yard 87 and the tenth yards 88 mean, because the described tool second sub-byte (B ₁) second yard 42 after should be described add one zero byte, the cyclic redundancy check (CRC) operation result that it calculated could with described tool the 3rd sub-byte (B ₂) second yard 43 do XOR.Therefore, after calculating described the 7th yard 85, the described the 9th yard 87 and the tenth yards 88 be must calculate again, one zero byte, the cyclic redundancy check (CRC) operation result that it calculated (the tenth yard 88) added to obtain at described the 7th yard 85.At last, the described ten yard 88 again with described tool the 3rd sub-byte (B ₂) second yard 43 cyclic redundancy check (CRC) operation result (the 8th yard 86) do XOR.

Cooperate again with reference to Figure 15,16D and 16E, the computing of implementing for the 3rd clock cycle with circuit is described.At the 3rd clock cycle place, select signal (b_sel) to be made as B second of second multiplexer 52 ₂So that the 3rd sub-byte (B of portion C RC check code ₂) be input to memory 53.Memory 53 is according to the described the 3rd sub-byte (B ₂) and described first control signal (tbl_idx) (being that numerical value 16 is handled on described second rank), can be equal to and learn above-mentioned tool the 3rd sub-byte (B ₂) second yard 43, and table look-up and correspondingly obtain above-mentioned the 8th yard 86, described the 8th yard 86 corresponding to described tool the 3rd sub-byte (B ₂) second yard 43 cyclic redundancy check (CRC) operation result.Described the 8th yard 86 is input to described exclusive-OR operator 57.

At this moment, the 7th yard 85 of being stored according to described first register 55 of zero padding byte operation device 56 calculates the described the 9th yard 87 and the described ten yards 88.That is, described zero padding byte operation device 56 is in order to calculate the cyclic redundancy check (CRC) operation result of mending one zero byte after described the 7th yard 85.Be input to exclusive-OR operator 57 for the described ten yard 88, exclusive-OR operator 57 carries out the described the 8th yard 86 and the described ten yards 88 XOR, to calculate described the 11 yard 89.At this moment, select signal (new) to be made as 0 the 3rd of the 3rd multiplexer 54, with the next clock cycle then, make the described first stage casing cyclic redundancy code operation result (described the 11 yard 89) store described first register 55 into by described the 3rd multiplexer 54 input.

The 4th clock cycle (C4) obtained tool the 4th sub-byte (B from described second yard ₃) second yard 44, according to described tool the 4th sub-byte (B ₃) second yard 44, correspondingly at described memory place obtain the 12 yard 91 (with reference to figure 16F), described the 12 yard 91 corresponding to described tool the 4th sub-byte (B ₃) second yard 44 cyclic redundancy check (CRC) operation result.

With reference to figure 16G, calculate simultaneously the tenth trigram 92 again, the lowest byte of described the tenth trigram 92 is zero byte, other byte of described the tenth trigram 92 is described the 11 yard 89, calculate the cyclic redundancy check (CRC) operation result of described the tenth trigram 92, be the 14 yard 93, XOR is described the 12 yard 91 and described the 14 yard 93 again, calculates the 15 yard 94.Described the 15 yard 94 is first iteration, is 16 adjusted cyclic redundancy check (CRC) code at described second rank processing numerical value.

Cooperate again with reference to Figure 15,16F and 16G, the computing of implementing the second clock cycle with circuit is described.At the 4th clock cycle place, select signal (b_sel) to be made as B second of second multiplexer 52 ₃So that the 4th sub-byte (B of portion C RC check code ₃) be input to memory 53.Memory 53 is according to the described the 4th sub-byte (B ₃) and described first control signal (tbl_idx) (being that numerical value 16 is handled on described second rank), can be equal to and learn above-mentioned tool the 4th sub-byte (B ₃) second yard 44, and table look-up and correspondingly obtain above-mentioned the 12 yard, described the 12 yard 91 corresponding to described tool the 4th sub-byte (B ₃) second yard 44 cyclic redundancy check (CRC) operation result.Described the 12 yard 91 is input to exclusive-OR operator 57.

At this moment, the 11 yard 89 of being stored according to described first register 55 of zero padding byte operation device 56 calculates described the tenth trigram 92 and described the 14 yard 93.That is, described zero padding byte operation device 56 is in order to calculate the cyclic redundancy check (CRC) operation result of mending one zero byte after described the 11 yard 89.Described the 14 yard 93 is input to exclusive-OR operator 57, and exclusive-OR operator 57 carries out described the 12 yard 91 and described the 14 yard 93 XOR, to calculate described the 15 yard 94.At this moment, select signal (new) to be made as 0 the 3rd of the 3rd multiplexer 54, and the enable signal of described second register 58 (en_b) is made as 1, with the next clock cycle then, make the described first stage casing cyclic redundancy code operation result (described the 15 yard 94) store described second register 58 into by 54 inputs of described the 3rd multiplexer, make described the 15 yard 94 can be input to first multiplexer 51, use for next iteration.

In the present embodiment, be 16,8 and 1 from high to low because the described first exponent number value 25 is disassembled into three second exponent number values, thereby need carry out iteration three times.Therefore, handle after numerical value is 16 adjusted cyclic redundancy check (CRC) code calculating described second rank, replace fragment cyclic redundancy check (CRC) code originally with described the 15 yard 94, carrying out secondary iteration, this moment, to handle numerical value be 8 (2 on described second rank ³), a in Figure 14 is 3, repeats the computing in above-mentioned four cycles, to calculate described the 15 yard, described the 15 yard is secondary iteration at this moment, is 8 adjusted cyclic redundancy check (CRC) code at described second rank processing numerical value.

The 15 yard 94 that secondary iteration is drawn replaces fragment cyclic redundancy check (CRC) code originally again, and to carry out the 3rd iteration, described second rank processing this moment numerical value is 1 (2 ⁰), a in Figure 14 is 1, repeats the computing in above-mentioned four cycles, to calculate described the 15 yard, described the 15 yard of this moment is the 3rd iteration, handles numerical value on described the 3rd rank and be 1 adjusted cyclic redundancy check (CRC) code, is final adjusted cyclic redundancy check (CRC) code.

Again with reference to Figure 15, it is postorder iteration (Following Iterations), thereby afterwards in first iteration (Iteration 1), select signal (load) to be made as 0 first of first multiplexer 51, make the 15 yard to import first multiplexer 51 and be sent to second multiplexer 52.And first control signal (tbl_idx) is made as a, and wherein a is 3, promptly numerical value (8=2 is handled on second rank of described secondary iteration ³) the inferior number formulary of 2 power power.With the 15 yard after first iteration and first control signal (tbl_idx) is 3 situation, repeats the computing in above-mentioned four cycles, obtains described the 15 yard to recomputate, and described the 15 yard of this moment is the result of secondary iteration.

In secondary iteration (Iteration 2) afterwards, select signal (load) to be made as 0 first of first multiplexer 51 again, make the 15 yard to import first multiplexer 51 and be sent to second multiplexer 52.And first control signal (tbl_idx) is made as a, and wherein a is 0, numerical value (1=2 is handled on described second rank of promptly described the 3rd iteration ⁰) the inferior number formulary of 2 power power.It with the 15 yard after the secondary iteration and first control signal (tbl_idx) 0 situation, repeat the computing in above-mentioned four cycles, obtain described the 15 yard to recomputate, described the 15 yard is the result of the 3rd iteration at this moment, is final adjusted cyclic redundancy check (CRC) code.

With reference to Figure 17, it shows the schematic diagram of numerical value decomposer of the present invention.Described numerical value decomposer 60 comprises the 4th multiplexer 61, the 3rd register 62, subtracter 63, inferior number formulary calculator 64 and determining device 65.Described the 4th multiplexer 61 is in order to receive numerical value (z to be decomposed _Ka) and the stage casing decomposition value, in the present embodiment, described numerical value (z to be decomposed _Ka) be the described first exponent number value 25.When first iteration, the 4th of described the 4th multiplexer 61 selects signal (load 4) to be made as 1, makes described numerical value (z to be decomposed _Ka) be the output of described the 4th multiplexer, for handling numerical value, described processing numerical value is input to number formulary calculator 64 described time by described the 4th multiplexer 61.

Described number formulary calculator 64 is in order to obtain described numerical value (z to be decomposed _Ka) inferior number formulary a and its value 2 of the highest 2 power power ^a, inferior number formulary a is directly as described first control signal (tbl_idx) and be input to described memory 53 (with reference to Figure 15).In the present embodiment, described numerical value (z to be decomposed _Ka) be 25, thereby the inferior number formulary a of its power power of the highest 2 is 4 and its value 2 ^aBe 16, it is second rank processing numerical value of above-mentioned first iteration.Second rank of described first iteration are handled numerical value and are input to described subtracter 63, and described subtracter 63 is in order to described numerical value (z to be decomposed _Ka=25) numerical value (16) is handled on second rank that deduct first iteration, calculates the stage casing decomposition value.In the present embodiment, when first iteration, the stage casing decomposition value of described subtracter 63 computings is 9.Described stage casing decomposition value is sent to described determining device 65 and described the 3rd register 62.

Described determining device 65 is in order to judging that whether described stage casing decomposition value is zero, if be zero expression decompose and finish; If non-vanishing then expression must continue to decompose.Described the 3rd register 62 is in order to store described stage casing decomposition value.

When secondary iteration, the 4th of described the 4th multiplexer 61 selects signal (load 4) to be made as 0, making the stage casing decomposition value of described the 3rd register 62 storages is the output of described the 4th multiplexer 61, and be to handle numerical value, described processing numerical value is input to number formulary calculator 64 described time by described the 4th multiplexer 61.

Described number formulary calculator 64 is in order to inferior number formulary a and its value 2 of the highest 2 power power of the stage casing decomposition value of obtaining 62 storages of described the 3rd register ^aAt this moment, described processing numerical value is 9, so the inferior number formulary a of its power power of the highest 2 is 3, and its value 2 ^a Be 8, it is second rank processing numerical value of above-mentioned secondary iteration.Repeat above-mentioned computing, (a is 0, and its value 2 to handle numerical value with second rank that calculate above-mentioned the 3rd iteration ^aBe 1), and judge that up to described determining device 65 described operation result is zero, then decomposes and finishes.The result of calculation of above-mentioned numerical value decomposer 60 is then exported described first control signal (tbl_idx) respectively to described memory 53 (with reference to Figure 15) when first iteration, secondary iteration and the 3rd iteration.

By the explanation of above-mentioned second embodiment, can learn if the memory that the message total length when 16KB is following, need only use 14KB for tabling look-up usefulness, can be that 16383 (its binary coding is 11111111111111 in zero padding (byte) quantity just ₂) worst condition (worst case) under finish the action of whole adjustment cyclic redundancy check (CRC) code with the individual clock cycle of 56 (4 * 14).

The 3rd embodiment:

In first embodiment, utilize than the large memories action of directly tabling look-up, but the limited system of memory resource be owing to possibly can't provide the storage space of described size, so the mode with second embodiment of can changing is significantly to reduce the demand of memory.Yet, if the system resource permission can utilize the 3rd embodiment further to quicken the usefulness that second embodiment adjusts.

With reference to Figure 18, it shows a plurality of second yard schematic diagram of third embodiment of the invention.As described in above-mentioned second embodiment, the 3rd embodiment also need decompose described first yard a plurality of zero bytes, and the byte number of described zero byte is the first exponent number value (z for example _Ka=25), decomposing the described first exponent number value according to the number of combinations of 2 power power is a plurality of second exponent number values.Get second rank from the described second exponent number value from high to low and handle numerical value, in the present embodiment, it is 16,8 and 1 from high to low that the described first exponent number value 25 is disassembled into three second exponent number values, thereby when first iteration (Iteration 1), it is 16 (2 that numerical value is handled on described second rank ⁴), a is 4 in Figure 14, and by described fragment cyclic redundancy check (CRC) code (B ₀B ₁B ₂B ₃) be launched into a plurality of second yard, described fragment cyclic redundancy check (CRC) code (B ₀B ₁B ₂B ₃) having four sub-bytes, it is deployed into described second yard highest byte respectively, and other described second yard byte is zero, and the byte number of described zero byte is that described second rank processing numerical value adds set point.

In the present embodiment, four second yard is respectively the tool first sub-byte (B ₀) second yard 45, the tool second sub-byte (B ₁) second yard 46, tool the 3rd sub-byte (B ₂) second yard 47 and tool the 4th sub-byte (B ₃) second yard 48.The described tool first sub-byte (B ₀) the byte number of second yard 45 its zero byte be that second rank are handled numerical value and added three (2 ^a+ 3).The described tool second sub-byte (B ₁) the byte number of second yard 46 its zero byte be that second rank are handled numerical value and added two (2 ^a+ 2).Described tool the 3rd sub-byte (B ₂) the byte number of second yard 47 its zero byte be that second rank are handled numerical value and added (2 ^a+ 1).Described tool the 4th sub-byte (B ₃) the byte number of second yard 48 its zero byte be that second rank are handled numerical value and added zero (2 ^a).

Therefore, the memory of the 3rd embodiment is except keeping 2 of second embodiment ^aOutside the memory of the 14KB size that (0≤a≤13) are required (with reference to the memory 53 of Figure 12), need increase the memory of three 14KB sizes again.With reference to Figure 19, second calculation element 70 of third embodiment of the invention comprises four memories 72,73,74,75.Wherein, with respect to described second yard 45 cyclic redundancy check (CRC) code, promptly first memory 72 can be in order to table look-up at the described first sub-byte (B in order to storage for first memory 72 ₀) have second rank afterwards and handle numerical value and add three (2 ^aThe cyclic redundancy check (CRC) code of zero byte number+3).

Second memory 73 can be in order to table look-up at the described second sub-byte (B ₁) have second rank afterwards and handle numerical value and add two (2 ^aThe cyclic redundancy check (CRC) code of zero byte number+2).The 3rd memory 74 can be in order to table look-up at the described the 3rd sub-byte (B ₂) have second rank afterwards and handle numerical value and add (2 ^aThe cyclic redundancy check (CRC) code of zero byte number+1).The 4th memory 75 can be in order to table look-up at the described the 4th sub-byte (B ₃) have second rank afterwards and handle numerical value (2 ^a) the cyclic redundancy check (CRC) code of zero byte number.Because the cyclic redundancy check (CRC) code adjusting device 70 of present embodiment has four memories, thereby can be in each iteration that gradation is adjusted, as long as a clock cycle can be finished the action that cyclic redundancy check (CRC) code is adjusted.

With reference to Figure 19, it shows the schematic diagram of second calculation element of third embodiment of the invention again.Second calculation element 70 of third embodiment of the invention comprises: numerical value decomposer 60, first multiplexer 71, a plurality of memory 72,73,74,75, exclusive-OR operator 76 and first register 77.Described numerical value decomposer 60 is in order to decompose described first yard a plurality of zero bytes, and the byte number of described zero byte is the first exponent number value, and it is a plurality of second exponent number values that the number of combinations of the power power according to 2 is decomposed the described first exponent number value.Described numerical value decomposer 60 can be with reference to above-mentioned Figure 17, does not add at this and gives unnecessary details.

Described first multiplexer 71 is in order to receive described fragment cyclic redundancy check (CRC) code and iteration result, select signal according to first, described fragment cyclic redundancy check (CRC) code of switching controls or described iteration result are to the output of described first multiplexer, and described fragment cyclic redundancy check (CRC) code and described iteration result all have a plurality of sub-bytes.

Described memory 72,73,74,75 is in order to store a plurality of trigrams, described trigram is corresponding to a plurality of second yard cyclic redundancy check (CRC) operation results, described second yard highest byte is respectively described sub-byte, other described second yard byte is zero, the byte number of described zero byte is that described second rank processing numerical value adds set point, according to described second yard, correspondingly obtain a plurality of trigrams.

Described exclusive-OR operator 76 is in order to the trigram of the described memory output of XOR, to calculate described iteration result.Described first register 77 is in order to storing described iteration result, and outputs to described first multiplexer 71.

Cooperation illustrates the computing of implementing the 3rd embodiment with circuit with reference to Figure 18 and Figure 19.When first iteration (Iteration 1), at first select signal (load 1) to be made as 1 first of first multiplexer 71, make portion C RC check code import first multiplexer 71, and with four sub-byte (B of portion C RC check code ₀B ₁B ₂B ₃) be sent to four memories 72,73,74,75 respectively.First control signal (tbl_idx) by 60 outputs of numerical value decomposer is a, and wherein a is 4, and numerical value (16=2 is handled on promptly above-mentioned second rank ⁴) the inferior number formulary of 2 power power.

Four memories 72,73,74,75 are respectively according to the first sub-byte (B ₀), the second sub-byte (B ₁), the 3rd sub-byte (B ₂) the 4th sub-byte (B ₃) and first control signal (tbl_idx), can be equal to and learn the above-mentioned tool first sub-byte (B ₀) second yard 45, the tool second sub-byte (B ₁) second yard 46, tool the 3rd sub-byte (B ₂) second yard 47 and tool the 4th sub-byte (B ₃) second yard 48, and corresponding four trigrams of obtaining of tabling look-up, described trigram is corresponding to described second yard 45,46,47,48 cyclic redundancy check (CRC) operation result.

Four trigrams are input to described exclusive-OR operator 76 respectively, and to carry out the XOR of four trigrams, its operation result is first iteration, are 16 adjusted cyclic redundancy check (CRC) code at second rank processing numerical value.Therefore, in the present embodiment, as long as clock cycle can finish the action that the first iterative cycles redundancy check code is adjusted.

The result of calculation of described exclusive-OR operator 76 is input to described first register 77, and described first register 77 is input to described first multiplexer 71 with the first iteration result.When secondary iteration (Iteration 2), select signal (load 1) to be made as 0 first of first multiplexer 71, make the iteration result that wins import first multiplexer 71, and four sub-bytes of the first iteration result are sent to four memories 72,73,74,75 respectively.At this moment, described first control signal (tbl_idx) is made as a, and wherein a is 3, and numerical value (8=2 is handled on promptly above-mentioned second rank ³) the inferior number formulary of 2 power power.Repeat above-mentioned table look-up step and XOR step, to calculate the result of the adjusted cyclic redundancy check (CRC) code of secondary iteration at four memory places.

When the 3rd iteration (Iteration 3), select signal (load 1) to be made as 0 first of first multiplexer 71, make the secondary iteration result import first multiplexer 51, and four sub-bytes of secondary iteration result are sent to four memories 72,73,74,75 respectively.At this moment, a of described first control signal (tbl_idx) is 0, and numerical value (1=2 is handled on promptly above-mentioned second rank ⁰) the inferior number formulary of 2 power power.Repeat above-mentioned table look-up step and XOR step,, be final adjusted cyclic redundancy check (CRC) code to calculate the result of the ring redundancy check code that follows after the 3rd iteration adjustment at four memory places.

Described first control signal (tbl_idx) can be by numerical value decomposer 60 control of Figure 17, can be with reference to the explanation of above-mentioned numerical value decomposer 60, and do not add at this and to give unnecessary details.Therefore, in the explanation by above-mentioned the 3rd embodiment, can learn the memory that need only use four 14KB (altogether 56KB) for tabling look-up usefulness, can be that 16383 (its binary coding is 11111111111111 in zero padding byte quantity just ₂) worst condition (worst case) under finish the action of whole adjustment cyclic redundancy check (CRC) code with 14 clock cycle.

And implementing on the usefulness, method of the present invention (as the 3rd embodiment) can be finished in 14 clock cycle (clock cycles) and adjust action, but therefore carry in the bus of microprocessor and collocation system soft/firmware design, also be fit to use CRC with on the highspeed network applications of guaranteeing data correctness.

Wish that the foregoing description only is explanation principle of the present invention and its effect, and be not in order to restriction the present invention.Therefore, the those skilled in the art can make amendment to the foregoing description under the situation of spirit of the present invention and change.Interest field of the present invention should be cited as appended claims.

Claims (32)

1. the method for a calculating cyclic redundancy check code, it may further comprise the steps:

Fragment computations fragment cyclic redundancy check (CRC) code according to message;

Produce first yard, described first yard has described fragment cyclic redundancy check (CRC) code, and other described first yard position is set at zero; With

Calculate adjusted cyclic redundancy check (CRC) code according to described first yardage.

2. method according to claim 1, it comprises deployment step in addition, is launched into a plurality of second yard by described first yard, and described fragment cyclic redundancy check (CRC) code has a plurality of sub-bytes, it is deployed into described second yard highest byte respectively, and other described second yard byte is zero.

3. method according to claim 2, it comprises cyclic redundancy check (CRC) code calculation step and XOR step in addition, according to described second yard, carries out the cyclic redundancy check (CRC) code computing respectively, to obtain a plurality of trigrams; The described trigram of XOR is to calculate described adjusted cyclic redundancy check (CRC) code.

4. method according to claim 2, it comprises table look-up step and XOR step in addition, according to described second yard, correspondingly at least one memory place obtains a plurality of trigrams, described trigram is corresponding to described second yard cyclic redundancy check (CRC) operation result; The described trigram of XOR is to calculate described adjusted cyclic redundancy check (CRC) code.

5. method according to claim 4, wherein said memory comprises a plurality of, each piece is stored a plurality of cyclic redundancy check (CRC) operation results of corresponding sub-byte.

6. method according to claim 1, it may further comprise the steps in addition:

Decompose described first yard a plurality of zero bytes, the byte number of described zero byte is the first exponent number value, and the number of combinations of the power power according to 2 is decomposed into a plurality of second exponent number values with the described first exponent number value;

Get second rank from the described second exponent number value from high to low and handle numerical value, and be launched into a plurality of second yard by described fragment cyclic redundancy check (CRC) code, described fragment cyclic redundancy check (CRC) code has a plurality of sub-bytes, it is deployed into described second yard highest byte respectively, other described second yard byte is zero, and the byte number of described zero byte is that described second rank processing numerical value adds set point;

According to described second yard, correspondingly at least one memory place obtain a plurality of trigrams, described trigram is corresponding to described second yard cyclic redundancy check (CRC) operation result;

The described trigram of XOR to calculate the iteration result, replaces described fragment cyclic redundancy check (CRC) code with described iteration result; With

Repeat above-mentioned deployment step, the step of tabling look-up and XOR step, handle numerical value up to the second minimum rank, described iteration result is described adjusted cyclic redundancy check (CRC) code.

7. method according to claim 6, wherein said fragment cyclic redundancy check (CRC) code has four sub-bytes, it is deployed into four second yard highest byte respectively, the byte number of four second yard described zero byte is respectively that described second rank handle that numerical value adds three, described second rank handle that numerical value adds two, described second rank handle numerical value add one and described second rank handle numerical value and add zero.

8. method according to claim 7 is wherein utilized four memories in the step of tabling look-up, described four memories are stored the cyclic redundancy check (CRC) operation result corresponding to four second yard respectively.

9. method according to claim 1, it may further comprise the steps in addition:

Decompose described first yard a plurality of zero bytes, the byte number of described zero byte is the first exponent number value, and it is a plurality of second exponent number values that the number of combinations of the power power according to 2 is decomposed the described first exponent number value;

Get second rank from the described second exponent number value from high to low and handle numerical value;

According to the first selection signal, switching controls obtains described fragment cyclic redundancy check (CRC) code or iteration result, and described fragment cyclic redundancy check (CRC) code and described iteration result all have a plurality of sub-bytes;

According to the second selection signal, switching controls obtains one in the described sub-byte;

Handle numerical value according to described sub-byte and described second rank, obtain trigram at least one memory place, described trigram is corresponding to second yard cyclic redundancy check (CRC) operation result, described second yard highest byte is described sub-byte, other described second yard byte is zero, and the byte number of described zero byte is the described second exponent number value;

According to the 3rd selection signal, described trigram of switching controls or XOR result are the first stage casing cyclic redundancy check (CRC) operation result;

The cyclic redundancy check (CRC) operation result of one zero byte is mended in computing after the described first stage casing cyclic redundancy check (CRC) operation result, to obtain the second stage casing cyclic redundancy check (CRC) operation result;

Described trigram of XOR and the described second stage casing cyclic redundancy check (CRC) operation result are to calculate described XOR result; With

According to enable signal, control the described first stage casing cyclic redundancy check (CRC) operation result and whether be output as described iteration result;

Repeat above-mentioned switching controls obtain after the sub-byte wherein institute in steps, big-endian is up to the minimum sub-byte that obtains described sub-byte; With

Repeat above-mentioned get described second rank handle after the numerical value institute in steps, to low numerical value, up to the minimum value that obtains the described second exponent number value, described iteration result is described adjusted cyclic redundancy check (CRC) code by high numerical value.

10. method according to claim 9, iterative value is calculated in the number decision of the wherein said second exponent number value, and when first iteration, described first selects the signal switching controls to obtain described fragment cyclic redundancy check (CRC) code; When other iteration, described first selects the signal switching controls to obtain described iteration result.

11. method according to claim 10, wherein said fragment cyclic redundancy check (CRC) code and described iteration result all have four sub-bytes, big-endian, and at first clock cycle place, described second selects the signal switching controls to obtain the first sub-byte; At second clock cycle place, described second selects the signal switching controls to obtain the second sub-byte; At the 3rd clock cycle place, described second selects the signal switching controls to obtain the 3rd sub-byte; At the 4th clock cycle place, described second selects the signal switching controls to obtain the 4th sub-byte.

12. method according to claim 11, wherein at first clock cycle place of each iteration, the described first stage casing cyclic redundancy check (CRC) operation result of described the 3rd selection signal switching controls is described trigram; Other clock cycle in each iteration is located, and the described first stage casing cyclic redundancy check (CRC) operation result of described the 3rd selection signal switching controls is described XOR result.

13. method according to claim 12, wherein at the 4th clock cycle place of each iteration, described enable signal is controlled the described first stage casing cyclic redundancy check (CRC) operation result and is output as described iteration result.

14. method according to claim 1, it may further comprise the steps in addition:

Decompose described first yard a plurality of zero bytes, the byte number of described zero byte is the first exponent number value, and the number of combinations of the power power according to 2 is decomposed into a plurality of second exponent number values with the described first exponent number value;

Get second rank from the described second exponent number value from high to low and handle numerical value, and be launched into a plurality of second yard by described fragment cyclic redundancy check (CRC) code, described fragment cyclic redundancy check (CRC) code has a plurality of sub-bytes, it is deployed into described second yard highest byte respectively, other described second yard byte is zero, and the byte number of described zero byte is that numerical value is handled on described second rank;

Order according to described sub-byte, from described second yard second yard of obtaining the tool first sub-byte, according to second yard of the described tool first sub-byte, at the corresponding trigram of obtaining at least one memory place, described trigram is corresponding to second yard cyclic redundancy check (CRC) operation result of the described tool first sub-byte;

From described second yard second yard of obtaining the tool second sub-byte, according to second yard of the described tool second sub-byte, correspondingly at described memory place obtain the 4th yard, described the 4th yard second yard cyclic redundancy check (CRC) operation result corresponding to the described tool second son position, calculate the 5th yard, described the 5th yard lowest byte is zero byte, other described the 5th yard byte is described trigram, calculate described the 5th yard cyclic redundancy check (CRC) operation result, it is the 6th yard, described the 4th yard and described the 6th yard of XOR calculates the 7th yard;

From described second yard second yard of obtaining tool the 3rd sub-byte, according to second yard of described tool the 3rd sub-byte, correspondingly at described memory place obtain the 8th yard, described the 8th yard second yard cyclic redundancy check (CRC) operation result corresponding to described tool the 3rd sub-byte, calculate the 9th yard, described the 9th yard lowest byte is zero byte, other described the 9th yard byte is described the 7th yard, calculate described the 9th yard cyclic redundancy check (CRC) operation result, it is the tenth yard, described the 8th yard and the described ten yard of XOR calculates the 11 yard;

From described second yard second yard of obtaining tool the 4th sub-byte, according to second yard of described tool the 4th sub-byte, obtain the 12 yard in that described memory place is corresponding, described the 12 yard second yard cyclic redundancy check (CRC) operation result corresponding to described tool the 4th son position, calculate the tenth trigram, the lowest byte of described the tenth trigram is zero byte, other byte of described the tenth trigram is described the 11 yard, calculate the cyclic redundancy check (CRC) operation result of described the tenth trigram, be the 14 yard, described the 12 yard and described the 14 yard of XOR calculates the 15 yard, replaces described fragment cyclic redundancy check (CRC) code with described the 15 yard; With

Repeat above-mentioned deployment step, the step of tabling look-up and XOR step, handle numerical value up to the second minimum rank, described the 15 yard is described adjusted cyclic redundancy check (CRC) code.

15. the system of a calculating cyclic redundancy check code, it comprises:

First calculation element is in order to the fragment computations fragment cyclic redundancy check (CRC) code according to message;

First yard generation device, in order to produce first yard, described first yard has described fragment cyclic redundancy check (CRC) code, and other described first yard position is set at zero; With

Second calculation element is in order to calculate adjusted cyclic redundancy check (CRC) code according to described first yardage.

16. system according to claim 15, it comprises expanding unit in addition, and in order to be launched into a plurality of second yard by described first yard, described fragment cyclic redundancy check (CRC) code has a plurality of sub-bytes, it is deployed into described second yard highest byte respectively, and other described second yard byte is zero.

17. system according to claim 16, wherein said second calculation element comprises the 3rd calculation element and XOR device in addition, described the 3rd calculation element carries out the cyclic redundancy check (CRC) code computing respectively for described second yard in order to foundation, to obtain a plurality of trigrams; Described XOR device is in order to the described trigram of XOR, to calculate described adjusted cyclic redundancy check (CRC) code.

18. system according to claim 16, wherein said second calculation element comprises at least one memory and XOR device in addition, according to described second yard, correspondingly at described memory place obtain a plurality of trigrams, described trigram is corresponding to described second yard cyclic redundancy check (CRC) operation result; Described XOR device is in order to the described trigram of XOR, to calculate described adjusted cyclic redundancy check (CRC) code.

19. system according to claim 18, wherein said memory comprises a plurality of, and each piece is stored a plurality of cyclic redundancy check (CRC) operation results of corresponding sub-byte.

20. system according to claim 15, wherein said second calculation element comprises:

The numerical value decomposer, in order to decompose described first yard a plurality of zero bytes, the byte number of described zero byte is the first exponent number value, the number of combinations of the power power according to 2 is decomposed into a plurality of second exponent number values with the described first exponent number value;

First multiplexer, in order to receive described fragment cyclic redundancy check (CRC) code and iteration result, select signal according to first, described fragment cyclic redundancy check (CRC) code of switching controls or described iteration result are to the output of described first multiplexer, and described fragment cyclic redundancy check (CRC) code and described iteration result all have a plurality of sub-bytes;

A plurality of memories, in order to store a plurality of trigrams, described trigram is corresponding to a plurality of second yard cyclic redundancy check (CRC) operation results, described second yard highest byte is respectively described sub-byte, other described second yard byte is zero, the byte number of described zero byte is that described second rank are handled numerical value and added set point, according to described second yard, correspondingly obtains a plurality of trigrams;

Exclusive-OR operator is in order to the described trigram of the described memory output of XOR, to calculate described iteration result; With

First register in order to storing described iteration result, and outputs to described first multiplexer.

21. system according to claim 20, wherein said fragment cyclic redundancy check (CRC) code and described iteration result all have four sub-bytes, it is deployed into four second yard highest byte respectively, the byte number of described four second yard described zero byte is respectively that described second rank handle that numerical value adds three, described second rank handle that numerical value adds two, described second rank handle numerical value add one and described second rank handle numerical value and add zero.

22. system according to claim 21, wherein said second calculation element comprises four memories, and described four memories are stored the cyclic redundancy check (CRC) operation result corresponding to described four second yard respectively.

23. system according to claim 20, iterative value is calculated in the number decision of the wherein said second exponent number value, when first iteration, the described output of described first multiplexer of the described first selection signal switching controls is described fragment cyclic redundancy check (CRC) code; During other iteration, the described output of described first multiplexer of the described first selection signal switching controls is described iteration result.

24. system according to claim 20, wherein said numerical value decomposer comprises:

The 4th multiplexer, in order to receive described first exponent number value and stage casing decomposition value, according to the 4th selection signal, described first exponent number value of switching controls or described stage casing decomposition value are processing numerical value to the output of described the 4th multiplexer;

Inferior number formulary calculator, in order to inferior number formulary and its value of the highest 2 the power power of obtaining described processing numerical value, described value is that numerical value is handled on second rank;

Subtracter is handled numerical value in order to deduct described second rank from described processing numerical value, calculates described stage casing decomposition value;

Whether determining device is zero in order to judge described stage casing decomposition value; With

The 3rd register in order to storing described stage casing decomposition value, and outputs to described the 4th multiplexer.

25. system according to claim 24, iterative value is calculated in the number decision of the wherein said second exponent number value, and when first iteration, the described processing numerical value of described the 4th selection signal switching controls is the described first exponent number value; During other iteration, the described processing numerical value of described the 4th selection signal switching controls is described stage casing decomposition value.

26. system according to claim 15, wherein said second calculation element comprises:

The numerical value decomposer, in order to decompose described first yard a plurality of zero bytes, the byte number of described zero byte is the first exponent number value, the number of combinations of the power power according to 2 is decomposed into a plurality of second exponent number values with the described first exponent number value;

First multiplexer, in order to receive described fragment cyclic redundancy check (CRC) code and iteration result, select signal according to first, described fragment cyclic redundancy check (CRC) code of switching controls or described iteration result are to the output of described first multiplexer, and described fragment cyclic redundancy check (CRC) code and described iteration result all have a plurality of sub-bytes;

Second multiplexer, in order to receive described sub-byte, according to the second selection signal, one in the described sub-byte of switching controls is to the output of described second multiplexer;

At least one memory, in order to store a plurality of trigrams, described trigram is corresponding to a plurality of second yard cyclic redundancy check (CRC) operation results, described second yard highest byte is respectively described sub-byte, other described second yard byte is zero, and the byte number of described zero byte is the described second exponent number value;

The 3rd multiplexer, in order to receive described trigram and XOR result, according to the 3rd selection signal, described trigram of switching controls or described XOR result are the first stage casing cyclic redundancy check (CRC) operation result to the output of described the 3rd multiplexer;

First register is in order to store the described first stage casing cyclic redundancy check (CRC) operation result;

Zero padding byte operation device is mended the cyclic redundancy check (CRC) operation result of one zero byte in order to computing after the described first stage casing cyclic redundancy check (CRC) operation result, computing obtains the second stage casing cyclic redundancy check (CRC) operation result;

Exclusive-OR operator in order to described trigram of XOR and the described second stage casing cyclic redundancy check (CRC) operation result, calculating described XOR result, and outputs to described the 3rd multiplexer; With

Second register, in order to storing the described first stage casing cyclic redundancy check (CRC) operation result, and whether to output to described first multiplexer by enable signal control be described iteration result.

27. system according to claim 26, wherein said numerical value decomposer comprises:

The 4th multiplexer, in order to receive described first exponent number value and stage casing decomposition value, according to the 4th selection signal, described first exponent number value of switching controls or described stage casing decomposition value are processing numerical value to the output of described the 4th multiplexer;

Inferior number formulary calculator, in order to inferior number formulary and its value of the highest 2 the power power of obtaining described processing numerical value, described value is that numerical value is handled on second rank;

Subtracter is handled numerical value in order to deduct described second rank from described processing numerical value, calculates described stage casing decomposition value;

Whether determining device is zero in order to judge described stage casing decomposition value; With

The 3rd register in order to storing described stage casing decomposition value, and outputs to described the 4th multiplexer.

28. system according to claim 27, iterative value is calculated in the number decision of the wherein said second exponent number value, and when first iteration, the described processing numerical value of described the 4th selection signal switching controls is the described first exponent number value; When other iteration, the described processing numerical value of described the 4th selection signal switching controls is described stage casing decomposition value.

29. system according to claim 26, iterative value is calculated in the number decision of the wherein said second exponent number value, when first iteration, the described output of described first multiplexer of the described first selection signal switching controls is described fragment cyclic redundancy check (CRC) code; When other iteration, the described output of described first multiplexer of the described first selection signal switching controls is described iteration result.

30. system according to claim 29, wherein said fragment cyclic redundancy check (CRC) code and described iteration result all have four sub-bytes, it outputs to described second multiplexer, at first clock cycle place, the described output of described second multiplexer of the described second selection signal switching controls is the first sub-byte; At second clock cycle place, the described output of described second multiplexer of the described second selection signal switching controls is the second sub-byte; At the 3rd clock cycle place, the described output of described second multiplexer of the described second selection signal switching controls is the 3rd sub-byte; At the 4th clock cycle place, the described output of described second multiplexer of the described second selection signal switching controls is the 4th sub-byte.

31. system according to claim 30, wherein at first clock cycle place of each iteration, the described first stage casing cyclic redundancy check (CRC) operation result of described the 3rd multiplexer of described the 3rd selection signal switching controls is described trigram; Other clock cycle in each iteration is located, and the described first stage casing cyclic redundancy check (CRC) operation result of described the 3rd multiplexer of described the 3rd selection signal switching controls is described XOR result.

32. system according to claim 31, wherein at the 4th clock cycle of each iteration place, described enable signal is controlled the described first stage casing cyclic redundancy check (CRC) operation result, and to output to described first multiplexer be described iteration result.

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