CN114884517A - CRC hardware computing system and chip - Google Patents

CRC hardware computing system and chip Download PDF

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CN114884517A
CN114884517A CN202210419560.5A CN202210419560A CN114884517A CN 114884517 A CN114884517 A CN 114884517A CN 202210419560 A CN202210419560 A CN 202210419560A CN 114884517 A CN114884517 A CN 114884517A
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selection control
crc
control module
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程旭帆
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Zhuhai Amicro Semiconductor Co Ltd
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Zhuhai Amicro Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/091—Parallel or block-wise CRC computation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/093—CRC update after modification of the information word
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing

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  • Theoretical Computer Science (AREA)
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Abstract

The invention discloses a CRC hardware computing system and a chip, wherein the CRC hardware computing system comprises i selective processing arrays; each selective processing array comprises m selective control modules, and each bit of information value of the information field has a corresponding selective processing array in a CRC hardware computing system; in the generator polynomial, except for the coefficient of the highest power of the generator polynomial, each power term has a corresponding selection control module in each selection processing array; each selection control module is used for selecting an XOR result of the information value of the corresponding bit in the information field and the associated numerical value or a CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generating polynomial under the trigger of a clock signal, and transmitting the result to the associated selection control modules except the selection processing array where the selection control module is located so as to output CRC codes in parallel after a plurality of clock cycles.

Description

CRC hardware computing system and chip
Technical Field
The invention belongs to the technical field of cyclic redundancy check circuits, and particularly relates to a CRC hardware computing system and a chip.
Background
Cyclic Redundancy Check (CRC) is used to Check the correctness and integrity of data transmission, CRC operation has strong error detection capability, and is easily implemented by an encoder or a detection circuit, such as a Linear Feedback Shift Register (LFSR), an initial value of the LFSR is called a seed of a pseudo-random sequence, and a last flip-flop outputs a periodically repeated pseudo-random sequence. The CRC8 serial shift circuit disclosed in the conventional art can calculate a CRC check code by a shift method, and the corresponding determined generator polynomial is: g ═ G 8 X 8 +g 7 X 7 +...+g 1 X 1 +1。
The conventional techniques have at least the following problems: in the CRC circuit, each time a multi-bit information code value is processed in parallel to perform a check, a long clock cycle is required, and an exclusive-or gate circuit and a multiplier are correspondingly configured for each bit of information code value to be processed in one clock cycle, so that a large amount of time is required to configure and process coefficients of each power of the generator polynomial, and multiplication operation is required to be performed for each coefficient and the associated information code, which results in a relatively long CRC check time and an excessively high hardware resource overhead.
Disclosure of Invention
In order to overcome the technical defects, the invention discloses a CRC hardware computing system and a chip, and the specific technical scheme is as follows:
a CRC hardware computing system is used for obtaining configuration information and information fields, determining a generator polynomial according to the configuration information, and providing a clock signal, coefficients of powers in the generator polynomial and the information fields for each selection processing array; the CRC hardware computing system comprises i select processing arrays; each selection processing array is configured to be controlled by coefficients of a corresponding power of the generator polynomial other than a highest power term; each selection processing array comprises m selection control modules, and each selection control module is used for inputting the information value of the corresponding bit of the information field; wherein, each bit information value of the information field has a corresponding selection processing array in the CRC hardware computing system; in the generator polynomial, except for the coefficient of the highest power of the generator polynomial, each power term has a corresponding selection control module in each selection processing array; each selection control module is used for selecting an XOR result of an information value of a corresponding bit in the information field and an associated numerical value or a CRC initial value associated with the corresponding power according to a coefficient of the corresponding power in a generating polynomial under the triggering of a clock signal, and transmitting the result to a related selection control module except for a selection processing array where the selection control module is located; wherein m is configured to be equal to the number of bits of a CRC initial value, and m is equal to the degree of the highest-order term in the generator polynomial; i is configured as the number of bits of an information field, which is a binary sequence that is input into the CRC hardware computing system in one clock cycle.
Furthermore, the CRC hardware computing system comprises m and i multiplied selection control modules, and all the selection control modules form an arrangement mode of m rows and i columns, so that the CRC hardware computing system has a selection processing array of i columns; each selection processing array comprises m rows of selection control modules; each selection control module comprises an exclusive-or calculation unit, a storage unit and a selector, so that the exclusive-or calculation unit, the storage unit and the selector are arranged in the CRC hardware calculation system in an arrangement of m rows and i columns.
Further, each selection control module is configured to select, according to the coefficient corresponding to the power in the generator polynomial, an xor result of the information value of the corresponding bit of the information field and the associated numerical value or a CRC initial value associated with the corresponding power, transmit the xor result to the selection processing array corresponding to the information value of the relatively lower bit of the information field, and output the CRC initial value to the selection processing array corresponding to the coefficient corresponding to the relatively higher power, except for all the selection control modules corresponding to the coefficients of the higher power and the selection processing array corresponding to the lowest-order information value of the information field.
Furthermore, the XOR calculation unit in the jth row and the jth column is used for carrying out XOR on the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (p-1) th power and the information value of the (i-j-1) th bit of the information field, outputting the XOR result of the XOR calculation unit in the jth row and the jth column, and determining the XOR result as the XOR result of the information value of the corresponding bit of the information field and the associated value; the storage unit of the jth column of the p-th row is used for storing a CRC initial value corresponding to the power of (p-1), wherein the CRC initial value corresponding to the power of (p-1) is a CRC initial value associated with the corresponding power; the p row and j column selector is used for selecting the XOR result of the XOR calculation unit in the p row and j column or the CRC initial value corresponding to the (p-1) power stored by the storage unit in the p row and j column to output according to the coefficient of the p power in the generator polynomial, and configuring the output result of the p row and j column selector as the output value of the selection control module in the p row and j column; the selection control module of the p row and the j column comprises an exclusive OR calculation unit of the p row and the j column, a selector of the p row and the j column and a storage unit of the p row and the j column, and the selection control module of the p row and the j column is positioned in the selection processing array of the j column; the selection control module of the p row and the j column is used for transmitting the output result of the selector of the p row and the j column to the exclusive OR calculation unit of the (p +1) row and the (j +1) column and the storage unit of the (p +1) row and the (j +1) column, and updating the output result to a CRC initial value corresponding to the p power under the triggering of the clock signal; the selection control module of the (p +1) th row and the (j +1) th column comprises an exclusive-or calculation unit of the (p +1) th row and the (j +1) th column and a storage unit of the (p +1) th row and the (j +1) th column, and the selection control module of the (p +1) th row and the (j +1) th column is positioned in the selection processing array of the (j +1) th column; wherein p is less than m-1, p is greater than 0, m is greater than 2, j is greater than or equal to 0, j is less than i-1, i is greater than 1, m, i and p are positive integers, and j is an integer; the selection control modules in the p-th row and the j-th column are not all the selection control modules corresponding to the coefficient of the second highest power, and the selection control modules in the p-th row and the j-th column are not positioned in the selection processing array corresponding to the lowest information value of the information field; all the selection control modules corresponding to the coefficients of the second highest power are all the selection control modules corresponding to the coefficients of the second highest power of the generator polynomial; the CRC initial value input by the selection control module in column 0 is configured before the CRC hardware computing system starts processing the information field, and is updated under the trigger of the clock signal.
Further, the xor calculation unit in row 0 and column j is configured to perform xor on the CRC initial value corresponding to the highest bit and the information value of bit (i-j-1) of the information field, output an xor result of the xor calculation unit in row 0 and column j, and determine the xor result as an xor result of the information value of the corresponding bit of the information field and the associated value; the storage unit in the 0 th row and the jth column is used for storing a preset constant, wherein the preset constant is a CRC initial value associated with the corresponding power; the selector in the 0 th row and the jth column is used for selecting the output of the exclusive OR result of the exclusive OR calculation unit in the 0 th row and the jth column or a preset constant stored in the storage unit in the 0 th row and the jth column according to a coefficient of 0 th power in the generator polynomial, and configuring the output result of the selector in the 0 th row and the jth column as an output value of the selection control module in the 0 th row and the jth column; the selection control module of the 0 th row and the jth column comprises an exclusive OR calculation unit of the 0 th row and the jth column, a selector of the 0 th row and the jth column and a storage unit of the 0 th row and the jth column, and the selection control module of the 0 th row and the jth column is positioned in the selection processing array of the jth column; the selection control module in the 0 th row and the j th column is used for transmitting the output result of the selector in the 0 th row and the j th column to the exclusive OR calculation unit in the 1 st row and the (j +1) th column and the storage unit in the 1 st row and the (j +1) th column, and updating the output result to the CRC initial value associated with the corresponding power under the triggering of the clock signal; the selection control module of the 1 st row and the (j +1) th column comprises an exclusive-or calculation unit of the 1 st row and the (j +1) th column and a storage unit of the 1 st row and the (j +1) th column, and the selection control module of the 0 th row and the (j +1) th column is positioned in the selection processing array of the (j +1) th column; wherein j is greater than or equal to 0, j is less than i-1, i is greater than 1, i is a positive integer, j is an integer; the selection control modules in the 0 th row and the j th column are not all the selection control modules corresponding to the coefficient of the highest power, and the selection control modules in the 0 th row and the j th column are not positioned in the selection processing array corresponding to the lowest-order information value of the information field.
Further, in all the selection control modules corresponding to the coefficients of the second power of higher order, except the selection control module in the selection processing array corresponding to the lowest order information value of the information field, each selection control module is configured to select an exclusive or result of the information value of the corresponding bit of the information field and the associated numerical value or a CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial, and transmit the result to all the selection control modules in the selection processing array corresponding to the information value of the relatively lower order of the information field.
Further, the XOR calculation unit in the j (m-1) th row is used for carrying out XOR on the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (m-2) th power and the information value of the (i-j-1) th bit of the information field, outputting the XOR result of the XOR calculation unit in the 0 (m-1) th row, and determining the XOR result as the result of the information value of the corresponding bit of the information field and the associated value; the memory unit in the jth column of the (m-1) th row is used for storing the CRC initial value corresponding to the (m-2) th power, wherein the CRC initial value corresponding to the (m-2) th power is the CRC initial value associated with the corresponding power; the selector in the (m-1) th row and the j column is used for selecting the XOR result of the XOR calculation unit in the (m-1) th row and the j column or the CRC initial value corresponding to the (m-2) th power stored in the storage unit in the (m-1) th row and the j column to output according to the coefficient of the (m-1) th power in the generator polynomial, and configuring the output result of the selector in the (m-1) th row and the j column as the output value of the selection control module in the (m-1) th row and the j column; the selection control module of the (m-1) th row and the jth column comprises an exclusive OR calculation unit of the (m-1) th row and the jth column, a storage unit of the (m-1) th row and the jth column and a selector of the (m-1) th row and the jth column; the selection control module of the jth row and the jth column in the (m-1) th row is used for transmitting the output result of the selector of the jth column in the (m-1) th row to all the XOR calculation units in the (j +1) th column, and updating the CRC initial value corresponding to the highest bit required by the XOR calculation units in the (j +1) th column for XOR under the trigger of the clock signal; wherein, all the exclusive or calculation units in the (j +1) th column are all the selection control modules in the selection processing array corresponding to the information values located at the relatively low bits of the information field; wherein j is greater than or equal to 0, j is less than i-1, i is greater than 1, m and i are both positive integers, and j is an integer; the selection control module in the (m-1) th row and the jth column is a selection control module except for the selection control module in the selection processing array corresponding to the lowest-order information value of the information field, in all the selection control modules corresponding to the coefficients of the second highest power; all the selection control modules corresponding to the coefficients of the second highest power are all the selection control modules corresponding to the coefficients of the second highest power of the generator polynomial.
Further, each selection control module in the selection processing array corresponding to the lowest-order information value of the information field is configured to select, according to the coefficient of the corresponding power in the generator polynomial, an xor result of the information value of the corresponding bit of the information field and the associated data or a CRC initial value associated with the corresponding power, transmit the xor result to the selection processing array corresponding to the highest-order information value of the information field, and output the CRC initial value to the selection control module corresponding to the selection processing array corresponding to the coefficient of the corresponding power.
Further, the xor calculation unit in the p (i-1) th row and the (i-1) th column is configured to xor the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (p-1) th power, and the information value of the lowest bit of the information field, output an xor result of the xor calculation unit in the p (i-1) th row and the (i-1) th column, and determine the xor result as the xor result of the information value of the corresponding bit of the information field and the associated value; the storage unit of the p row and the (i-1) column is used for storing CRC initial values corresponding to (p-1) power, wherein the CRC initial values corresponding to (p-1) power are CRC initial values associated with the corresponding power; the selector of the p row and the (i-1) th column is used for selecting the XOR result of the XOR calculation unit of the p row and the (i-1) th column or the CRC initial value corresponding to the (p-1) th power stored by the storage unit of the p row and the (i-1) th column to output according to the coefficient of the p power in the generator polynomial, and the output result of the selector of the p row and the (i-1) th column is configured as the output value of the selection control module of the p row and the (i-1) th column; the selection control module of the p row and the (i-1) th column comprises an exclusive OR calculation unit of the p row and the (i-1) th column, a storage unit of the p row and the (i-1) th column and a selector of the p row and the (i-1) th column, and the selection control module of the p row and the (i-1) th column is in a selection processing array corresponding to the lowest information value of the information field; wherein p is less than or equal to m-1, p is greater than 0, m is greater than 1, and i and m are positive integers; the selection control module of the p-th row and the (i-1) -th column is the selection control module in the selection processing array corresponding to the lowest-order information value of the information field except the selection control module of the 0-th row.
Further, the xor calculation unit in row 0 and column (i-1) is configured to xor the CRC initial value corresponding to the highest bit with the lowest information value of the information field, output an xor result of the xor calculation unit in row 0 and column j, and determine the xor result as an xor result of the information value of the corresponding bit of the information field and the associated value; the storage unit at the 0 th row and the (i-1) th column is used for storing a preset constant, wherein the preset constant is a CRC initial value associated with the corresponding power; the selector of the 0 th row and the (i-1) th column is used for selecting the exclusive OR result of the exclusive OR calculation unit of the 0 th row and the (i-1) th column or the preset constant output stored in the storage unit of the 0 th row and the (i-1) th column according to the coefficient of the 0 th power in the generator polynomial, and configuring the output result of the selector of the 0 th row and the (i-1) th column as the output value of the selection control module of the 0 th row and the (i-1) th column; the selection control module of the 0 th row and the (i-1) th column comprises an exclusive OR calculation unit of the 0 th row and the (i-1) th column, a selector of the 0 th row and the (i-1) th column and a storage unit of the 0 th row and the (i-1) th column, and the selection control module of the 0 th row and the (i-1) th column is the selection control module of the 0 th row in the selection processing array corresponding to the lowest information value of the information field.
Furthermore, each selection control module in the 0 th column is connected with a corresponding register, wherein a data input end of one selection control module is correspondingly connected with a data output end of one register, and a data input end of each register is connected with a selector in the (i-1) th column of the same row, so that the selection control module corresponding to the selection processing array in the 0 th column and the selection control module corresponding to the selection processing array in the (i-1) th column are connected through the registers; wherein, the selection processing array of the 0 th column is the selection processing array corresponding to the highest information value of the information field, and the selection processing array of the (i-1) th column is the selection processing array corresponding to the lowest information value of the information field; and the clock end of each register is connected with the clock signal, and each register is used for caching the output result of the selector in the (i-1) th column of the same row under the triggering of the clock signal.
Further, the manner of selecting the xor result of the information value of the corresponding bit of the information field and the associated value or the CRC initial value associated with the corresponding power according to the coefficient corresponding to the power in the generator polynomial includes: when a CRC hardware computing system configures that a coefficient of a corresponding power in the generating polynomial is 1, a gating end of a selector in a corresponding selection control module receives a first level signal, the selector gates an XOR computing unit in the selection control module where the selector is located and outputs an XOR result of the XOR computing unit, wherein the XOR result of an information value of a corresponding bit of the information field and an associated value is the XOR result of the XOR computing unit, and the associated value comprises a CRC initial value corresponding to the highest bit and/or a CRC initial value associated with the corresponding power; the exclusive-or calculation unit is an exclusive-or logic gate circuit with three input ends; the data stored by the memory cell is supported to be refreshed; when the CRC hardware computing system configures that the coefficient of the corresponding power in the generator polynomial is 0, the gating end of the selector in the corresponding selection control module receives a second level signal, and the selector gates the CRC initial value associated with the corresponding power stored in the storage unit in the selection control module where the selector is located to output, wherein the second level signal is different from the first level signal.
Further, the configuration information comprises CRC types, coefficients of generating polynomials and CRC initial values; the CRC hardware computing system is configured to determine a generator polynomial based on the configuration information in a manner comprising: determining the type of the generator polynomial and coefficients of powers in the generator polynomial according to the CRC type and coefficients of the generator polynomial; setting a CRC initial value according to a communication protocol followed by the information field before the CRC hardware computing system starts to process the information field; and the CRC initial value corresponding to the highest bit is the CRC initial value corresponding to the second higher power of the generator polynomial.
Further, when the CRC type is CRC8, m is set to 8, i is set to 4, and the information field is composed of 4-bit information values.
A chip comprises the CRC hardware computing system for cyclic redundancy check.
Furthermore, the CRC hardware computing system comprises m and i multiplied selection control modules, and all the selection control modules form an arrangement mode of m rows and i columns, so that the CRC hardware computing system has a selection processing array of i columns; each selection processing array comprises m rows of selection control modules; each selection control module comprises an exclusive-or calculation unit, a storage unit and a selector, so that the exclusive-or calculation unit, the storage unit and the selector are arranged in the CRC hardware calculation system in an arrangement of m rows and i columns.
Further, each selection control module is configured to select, according to the coefficient corresponding to the power in the generator polynomial, an xor result of the information value of the corresponding bit of the information field and the associated numerical value or a CRC initial value associated with the corresponding power, transmit the xor result to the selection processing array corresponding to the information value of the relatively lower bit of the information field, and output the CRC initial value to the selection processing array corresponding to the coefficient corresponding to the relatively higher power, except for all the selection control modules corresponding to the coefficients of the higher power and the selection processing array corresponding to the lowest-order information value of the information field.
Further, in all the selection control modules corresponding to the coefficients of the second power of higher order, except the selection control module in the selection processing array corresponding to the lowest order information value of the information field, each selection control module is configured to select an exclusive or result of the information value of the corresponding bit of the information field and the associated numerical value or a CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial, and transmit the result to all the selection control modules in the selection processing array corresponding to the information value of the relatively lower order of the information field.
Further, each selection control module in the selection processing array corresponding to the lowest-order information value of the information field is configured to select, according to the coefficient of the corresponding power in the generator polynomial, an xor result of the information value of the corresponding bit of the information field and the associated data or a CRC initial value associated with the corresponding power, transmit the xor result to the selection processing array corresponding to the highest-order information value of the information field, and output the CRC initial value to the selection control module corresponding to the selection processing array corresponding to the coefficient of the corresponding power.
Furthermore, each selection control module in the 0 th column is connected with a corresponding register, wherein a data input end of one selection control module is correspondingly connected with a data output end of one register, and a data input end of each register is connected with a selector in the (i-1) th column of the same row, so that the selection control module corresponding to the selection processing array in the 0 th column and the selection control module corresponding to the selection processing array in the (i-1) th column are connected through the registers; wherein, the selection processing array of the 0 th column is the selection processing array corresponding to the most significant information value of the information field, and the selection processing array of the (i-1) th column is the selection processing array corresponding to the least significant information value of the information field; and the clock end of each register is connected with the clock signal, and each register is used for caching the output result of the selector in the (i-1) th column of the same row under the triggering of the clock signal so as to obtain the iteration result of the CRC hardware computing system.
Compared with the prior art, the CRC hardware computing system disclosed by the invention configures the coefficient of the corresponding power except the highest power item in the specified CRC generating polynomial into the selection control signal, inputs the selection end of the selector of the corresponding row and column in the selection control module so that each selection control module is used for selecting the XOR computation result of the information value of the corresponding bit in the information field and the associated numerical value or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generating polynomial in the current clock period, transmits the information value of the lower bit of the information field to the corresponding selection control module in one selection processing array so that the corresponding selection control module in other selection processing arrays can start the XOR computation of the next clock period on the information values of other bits of the information field, and avoids introducing the number of times of the highest power item 0 after the information field in the process of using the generating polynomial for checking Wherein the XOR operation can advance the CRC check process of the information field bit by bit; not only reduces the iterative processing of constant items such as 0, but also can flexibly configure the coefficients of each power to adapt to various CRC calculation requirements.
On the basis, the invention uses the combinational logic to connect the XOR operation executed by the two adjacent selection control modules under the two adjacent clock cycles in series, and uses the combinational logic to connect the head selection control module and the tail selection control module to form a feedback loop, so that each selection processing array can be controlled to update the CRC initial value in each clock cycle to obtain the CRC code after the corresponding clock cycle, thereby realizing the optimization of the combinational logic circuit by combining the periodic feedback function and the selection circuit and achieving the effect of running the multi-bit CRC operation in a single-beat clock cycle.
Furthermore, when the code corresponding to the generated polynomial is added to the information field of the CRC hardware computing system (to form the CRC code through the CRC operation), since the CRC hardware computing system for cyclic redundancy check according to the present invention abandons the use of the multiplier, and instead uses the selector in cooperation with the xor computing unit, the multiplication operation on 0 is reduced, so that it is not necessary to add 0 to the highest power (the highest power of the polynomial corresponding to the CRC code) after the corresponding bit information value of the information field, nor to directly use the matrix to perform the division operation on hardware, which results in less hardware resources.
Drawings
Fig. 1 is a schematic structural diagram of a CRC hardware computing system according to an embodiment of the present invention.
Fig. 2 is a block diagram of a CRC hardware computing system that employs a CRC8 type and processes four-bit information values, according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention. In the description of the present application, the terms "first", "second", "third", and the like are used only for distinguishing between descriptions and are not intended to indicate relative order of arrangement or to imply relative importance.
As known to those skilled in the art, the CRC check principle is that an R-bit binary check code is appended to a K-bit binary data sequence, thereby forming a binary sequence with a total length of N ═ K + R bits. There is a certain specific relationship between the check code appended to the data sequence and the content of the data sequence. If a certain bit or some bits in the data sequence are wrong due to interference or the like, the specific relationship is destroyed, and therefore, the correctness of the data sequence can be checked through checking the relationship by a CRC (cyclic redundancy check) algorithm or a CRC check circuit. A CRC hardware computing system for cyclic redundancy check disclosed in this embodiment belongs to the CRC check circuit.
In the prior art, when performing CRC check, the sender and the receiver need to agree a divisor in advance, i.e. a generator polynomial, and the highest bit and the lowest bit of the generator polynomial must be 1. In order to perform error checking, an R-bit redundancy code (binary check code) needs to be added after a K-bit information field (K-bit binary data sequence), the codeword length N is equal to the sum of K and R, the sender and the receiver agree in advance on an R-degree polynomial (generator polynomial of CRC), and the highest bit and the lowest bit of the generator polynomial must be 1. The CRC code consists of a K-time information polynomial and an R-1-time check polynomial, specifically, the code corresponding to the R-1-time check polynomial is a redundant code, and the redundant code is added in an original information field to form the CRC code. The calculation mode of the R-1-time check polynomial is as follows: and adding R0 s behind the K-bit information field, and dividing the K-bit information field by the code sequence corresponding to the R-th-order polynomial to obtain a remainder, namely the code corresponding to the R-1-th-order check polynomial.
For example: 1011001 as an information field code; corresponding to m (x) ═ x 6 +x 4 +x 3 +1。
Assume the generator polynomial to be: g (x) x 4 +x 3 + 1; the code corresponding to g (x) is 11001 (corresponding to coefficients to powers).
x 4 m(x)＝x 10 +x 8 +x 7 +x 4 The corresponding code is noted as: 10110010000 (corresponding to coefficients to powers).
Adopting a polynomial division method to obtain a remainder of 1010, namely, codes corresponding to the R-1-order check polynomial are as follows: 1010 (i.e., CRC check code).
The transmission field sent by the sender is: 10110011010 (check field added after information field).
The receiving side: the same generator polynomial corresponding code is used for checking, and if the received field can be divided by the generator polynomial corresponding code (binary division), the check is correct.
In order to improve the cyclic redundancy check speed of a preset generating polynomial on an input information field by using a combinational logic mode and flexibly configure the corresponding generating polynomial according to the requirement of a communication protocol so as to calculate a CRC check code in a hardware mode more quickly or accurately, the embodiment of the invention discloses a CRC hardware calculation system.
Before performing cyclic redundancy check on an input information field, the CRC hardware computing system is configured to obtain configuration information and the information field, determine a generator polynomial of a CRC according to the configuration information, and provide a clock signal, coefficients of powers in the generator polynomial, and the information field to each selected processing array, so that the generator polynomial is configurable; specifically, the configuration information includes a CRC type, coefficients of terms of a generator polynomial, and a CRC initial value; the CRC hardware computing system is configured to determine a generator polynomial based on the configuration information in a manner comprising: determining the type of the generator polynomial and coefficients of various powers in the generator polynomial according to the CRC type and coefficients of various terms of the generator polynomial; before the CRC hardware computing system starts to process the information field, the CRC initial value supports the updating of the XOR result in the subsequent checking process according to the communication protocol setting followed by the information field; in addition, in the present embodiment, the CRC initial value corresponding to the highest bit is the CRC initial value corresponding to the second-order power of the generator polynomial, and is also the CRC initial value corresponding to the second-order power of the generator polynomial. The CRC hardware computing system can determine each coefficient of the generating polynomial according to the CRC type, and then determines the initial CRC value associated with each power according to each coefficient of the generating polynomial customized by a protocol, thereby realizing flexible configuration of the generating polynomial.
The CRC hardware computing system comprises i select processing arrays; each selection processing array is configured to be controlled by a coefficient of a corresponding power other than a highest power term (coefficient of the highest power) in the generator polynomial; each selection processing array comprises m selection control modules, and each selection control module is used for processing the information value of the corresponding bit of the information field; each bit of information value of the information field has a corresponding selection processing array in a CRC hardware computing system, and all selection control modules in one selection processing array correspond to the same bit of information value of the information field; in the generator polynomial, except for the coefficient corresponding to the highest power of the generator polynomial, the coefficient corresponding to each power has a corresponding selection control module in each selection processing array; equivalently, in the generator polynomial, each power term has a corresponding selection control block in each selection processing array except for a coefficient corresponding to the highest power of the generator polynomial, so that each power coefficient has a corresponding selection control block in each selection processing array. In the process of performing cyclic redundancy check by the CRC hardware calculation system according to this embodiment, the coefficient of the highest power of the generator polynomial is not processed, which is equivalent to performing check calculation on the remaining polynomials after deleting the highest term of the generator polynomial. In this embodiment, each selection control module is configured to, under the trigger of a clock signal, select, according to a coefficient corresponding to a power in a generator polynomial, an xor result of an information value of a corresponding bit in the information field and an associated numerical value or a CRC initial value associated with the corresponding power, and transmit the xor result or the CRC initial value to an associated selection control module other than a selection processing array where the selection control module is located, so that one selection control module transmits only a result of selective output thereof to selection control modules in other selection processing arrays, specifically, to selection control modules in other columns of fig. 1, and after a number of clock cycles, the selection control modules in the associated selection processing array output check codes in parallel; the coefficients corresponding to powers in the generator polynomial are configured in the selection control module as selection control signals for selecting the circuit for generating the exclusive-or result of the information value of the corresponding bit in the information field and the associated value, or the circuit for storing the CRC initial value associated to the corresponding power, to be connected to the selection processing array of the other column, in some embodiments, in response to the clock signal, one selection control module transmits the exclusive-or result of the information value of the corresponding bit in the information field and the associated value, or the CRC initial value associated to the corresponding power, to the selection control module for processing the information value of the associated bit of the information field in the next clock cycle under selection of the coefficient corresponding to the power of the generator polynomial, in response to the clock signal, to implement the iterative processing required in performing the cyclic redundancy check, the check code (CRC code) is computed in parallel in hardware.
It should be noted that m is configured to be equal to the number of bits of the CRC initial value, and m is equal to the degree of the highest-order term in the generator polynomial; it is worth noting that i is configured as the bit number of the information field, and the information field is configured as the binary sequence which is input into the CRC hardware computing system in one clock cycle, and the bit number of the input information field in each clock cycle is equal; preferably, each clock cycle may be updated with different information fields, i.e. D [ i-1] to D [0] input from left to right in fig. 1 are refreshed, so as to obtain CRC codes according to the generator polynomial calculation.
In this embodiment, the configuration information is used to instruct the CRC hardware computing system to select an exclusive or result or a CRC initial value associated with a corresponding power to complete CRC check, and also to obtain a latest value iterated by the CRC initial value associated with each power in each clock cycle, where the latest value is preset information, where the CRC initial value is used to initialize the selection processing array, the CRC initial value may be a protocol definition value or may be an output value iterated by the selection control module last time, and the number of bits of the CRC initial value is equal to the number of iteration bits of the selection control module.
CRC types include, but are not limited to, CRC4, CRC7, CRC8, CRC12, CRC16, CRC 32. The generating the polynomial includes generating a polynomial type corresponding to a CRC type of a coefficient corresponding to each power in the generating polynomial, and the user may define the polynomial type corresponding to each power in the generating polynomial according to a protocol or a product requirement. In some embodiments, the CRC type is CRC8, and the generator polynomial corresponding to CRC8 is 1+ X 1 +X 2 +X 8 The CRC hardware computing system selects the generator polynomial corresponding to CRC8 to check and determines g [0]]＝1，g[1]＝1,g[2]＝1,g[3]＝g[4]＝g[5]＝g[6]＝g[7]＝0，g[8]When the CRC8 is equal to 1, the coefficients of the generator polynomial corresponding to the CRC8 can be determined as: the 0-th power coefficient, the 1-th power coefficient, the 2-th power coefficient, and the 8-th power coefficient are all 0, except for the highest power coefficient g [8] that is 0]In addition, there are 8 coefficients accumulated, and the selection processing array in the CRC hardware computing system only utilizes g [0]]To g [7]]To participate in cyclic redundancy checkWherein g is [7]]Is a coefficient of a power of the second higher order, g0]A coefficient that is the lowest power; since the number m of selection control modules included in one selection processing array is equal to the number of times of the highest power term in the generator polynomial and m is configured to be equal to the number of bits of the CRC initial value, m is set to 8 and the CRC initial value is set to C [7: 0]]，C[7:0]Preferably 01010101, the CRC initial value corresponding to the most significant bit is C [7]]The CRC initial value associated with the power (CRC initial value corresponding to the power p, p is an integer between 0 and 7) is C [0] from the lower to the higher order]、C[1]、C[2]、C[3]、C[4]、C[5]And C6]。
On the basis of the foregoing embodiment, the CRC hardware computing system includes m and i multiplied selection control modules, all the selection control modules form an arrangement of m rows and i columns, so that the CRC hardware computing system has i columns of selection processing arrays, each column selection processing array is a selection processing array, each selection processing array has m rows of selection control modules, each selection control module in one selection processing array is a selection control module, and each selection control module in the CRC hardware computing system has i selection control modules; each selection control module comprises an exclusive-or calculation unit, a storage unit and a selector, so that the exclusive-or calculation unit, the storage unit and the selector are all arranged in the CRC hardware calculation system in an arrangement manner of m rows and i columns, and corresponding to fig. 1, row sequence numbers and column sequence numbers where the exclusive-or calculation unit, the storage unit and the selector are located are counted from 0. In some embodiments, the selection control module is further connected to a register, where the register is used to buffer CRC initial values transmitted by other selection control modules in a previous clock cycle or results (iteration results in a cyclic redundancy check process) selectively output by an associated selector, and further, the coefficients of each power of the generator polynomial and the corresponding CRC initial values perform parallel processing on the information field in a selection processing array for multiple clock cycles, and finally, obtain the CRC code in a hardware manner.
Specifically, as shown in fig. 1, the CRC hardware computing system includes i selective processing arrays arranged in a column, and sequentially includes a first selective processing array, a second selective processing array, and an ith selective processing array, where i is a positive integer; the i selection processing arrays are used for processing the information field of i bits shown in fig. 1 in each clock cycle under the trigger of the clock signal CLK, and each selection processing array can process the information value of one bit of the information field (composed of information values of a plurality of bits). The information field is communication data to be checked, which is a binary sequence whose number of bits is i.
In the present embodiment, each selection processing array is configured to be controlled by a corresponding signal of a coefficient of a corresponding power other than the coefficient of the highest power in the generator polynomial, and the selection control block in row 0 of each selection processing array (the selection control block in which the exclusive or calculation unit of row 0 of fig. 1 is located) corresponds to and is controlled by a coefficient g [0] of a power 0 of the generator polynomial; the selection control module in row 1 of each selection processing array (the selection control module where the exclusive-or calculation unit in row 1 of fig. 1 is located) corresponds to and is controlled by the coefficient g [1] of the power of 1 of the generator polynomial; by analogy, the selection control module in the (M-1) th row of each selection processing array (the selection control module in which the exclusive-or calculation unit in the (M-1) th row of fig. 1 is located) corresponds to and is controlled by the coefficient g [ M-1] of the (M-1) th power of the generator polynomial.
Each selection processing array comprises m selection control modules, each selection control module is used for processing the information value of the corresponding bit of the information field under the triggering of a clock signal, so that each bit of information value of the information field has a corresponding selection processing array in the CRC hardware computing system, the specific column serial number of the selection processing array is associated with the bit number of the input information value in the information field, each selection control module in the first selection processing array positioned in the 0 th column of the CRC hardware computing system corresponding to the embodiment in FIG. 1 inputs the (i-1) th bit information value D [ i-1] of the information field, each selection control module in the second selection processing array positioned in the 1 st column of the CRC hardware computing system inputs the (i-2) th bit information value D [ i-2] of the information field, by analogy, each selection control module in the ith selection handling array located in the (i-1) th column of the CRC hardware computation system inputs the 0 th bit information value D [0] of the information field.
It should be added that the selection control modules in the same row in each selection processing array all correspond to the coefficients of the same power in the generator polynomial, so that in the generator polynomial, except for the coefficient of the highest power of the generator polynomial, the coefficient of each power has a corresponding selection control module in each selection processing array, and except for the coefficient of the highest power of the generator polynomial, each power has a corresponding selection control module in each selection processing array; wherein the selection control modules of the same row in each selection processing array are configured to be controlled by coefficients of the same power in the generator polynomial, the row number of the selection control module is equal to the number of times of the power item of the coefficient of the corresponding power of the selection control module, corresponding to FIG. 1, all the selection control modules of row 0 correspond to and are controlled by the coefficient g [0] of the power of 0 of the generator polynomial, all the selection control modules of row 1 correspond to and are controlled by the coefficient g [1] of the power of 1 of the generator polynomial, and so on, all the selection control modules of row (m-1) correspond to and are controlled by the coefficient g [ m-1] of the power of (m-1) of the generator polynomial on the hardware port and are constrained by the corresponding clock period.
It should be noted that Exclusive OR (Exclusive OR), also called Exclusive OR operation, is implemented by the Exclusive OR calculation unit in this embodiment, i.e. the same is 0, and the different is 1, i.e. binary addition and subtraction operation without taking carry and borrow into account, such as: 10011011+11001010 ═ 01010001. The exclusive OR calculation unit disclosed by the invention is an exclusive OR logic gate circuit with three input ends. The data stored by the memory cells support being refreshed, the memory cells may be comprised of registers, or dynamic random access memory.
As an embodiment one, except for all the selection control modules corresponding to the coefficients of the second highest power and the selection processing array corresponding to the lowest information value of the information field, each selection control module is configured to select, according to the coefficient of the second highest power in the generator polynomial, an xor result between the information value of the corresponding bit of the information field and the associated value or a CRC initial value associated with the corresponding second highest power, transmit the selected from the information field to the selection processing array corresponding to the lowest information value of the selected from the information, to be the CRC; one selection control module is connected with the selection control module corresponding to the coefficient of the relatively higher power in the selection processing array corresponding to the information value of the relatively lower order of the information field except for all the selection control modules corresponding to the coefficient of the second higher power and the selection processing array corresponding to the lowest order information value of the information field; and the coefficient corresponding to the power in the generator polynomial corresponds to the selection control module which is selected currently. In this embodiment, the relatively low-order information value of the information field is an information value that is one bit lower than the bit number of the information value corresponding to the selection processing array in which the selection control module that outputs the verification information code is located, and the relatively high-order coefficient is a coefficient that is one time higher than the number of times of the power-order term corresponding to the selection control module that outputs the verification information code.
As an embodiment, the xor calculation unit in the pth row and the jth column is configured to perform xor on the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (p-1) th power, and the information value of the (i-j-1) th bit of the information field, output an xor result of the xor calculation unit in the pth row and the jth column, and determine the xor result as the xor result of the information value of the corresponding bit of the information field and the associated value. In this embodiment, the xor calculation unit in the jth row and jth column inputs the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (p-1) th power, and the information value of the (i-j-1) th bit of the information field, respectively, so that the information value of the (i-j-1) th bit of the information field (actually, the binary number of the (i-j) th bit from right to left) is the information value of the corresponding bit of the information field, and the CRC initial value corresponding to the highest bit and the CRC initial value corresponding to the (p-1) th power are associated values; when the exclusive-OR calculation unit is an exclusive-OR gate circuit with three input ends, a first input end of the exclusive-OR gate circuit is used for inputting the CRC initial value corresponding to the highest bit, a second input end of the exclusive-OR gate circuit is used for inputting the CRC initial value corresponding to the power of (p-1), and a third input end of the exclusive-OR gate circuit is used for inputting the information value of the (i-j-1) th bit of the information field; the CRC initial value corresponding to the input highest bit is updated according to the clock period under the triggering action of the clock information; the CRC initial value input by the selection control module in column 0 is configured before the CRC hardware computing system starts processing the information value of the (i-1) th bit of the information field, and is updated under the trigger of the clock signal, specifically, the CRC initial value is updated to the power of (p-1) according to the clock period, and may be transmitted from the register. It should be noted that, as can be seen from fig. 1, p is less than m-1, p is greater than 0, m is greater than 2, j is greater than or equal to 0, j is less than i-1, i is greater than 1, m, i and p are positive integers, and j is an integer; the selection control modules in the p-th row and the j-th column are not all the selection control modules corresponding to the coefficient of the second highest power, and the selection control modules in the p-th row and the j-th column are not the selection processing array corresponding to the information value at the lowest position of the information field; all selection control modules corresponding to coefficients of the next highest power are all selection control modules corresponding to coefficients of the (m-1) th power of the generator polynomial. The memory cell in the p-th row and the j-th column is used for storing a CRC initial value corresponding to the power of (p-1), wherein the CRC initial value corresponding to the power of (p-1) is a CRC initial value associated with the corresponding power, can be derived from a CRC initial value updated in the last clock cycle, and can be transmitted by the selection control module in the previous column. The p row and j column selector is used for selecting the XOR result of the XOR calculation unit in the p row and j column or the CRC initial value corresponding to the (p-1) power stored by the storage unit in the p row and j column to output according to the coefficient of the p power in the generator polynomial, and configuring the output result of the p row and j column selector as the output value of the selection control module in the p row and j column; the selection control module of the pth row and the pth column comprises an exclusive-or calculation unit of the pth row and the pth column, a selector of the pth row and the pth column, and a storage unit of the pth row and the pth column, one input end of the selector of the pth row and the pth column is connected with an output end of the exclusive-or calculation unit of the pth row and the pth column, the other input end of the selector of the pth row and the pth column is connected with an output end of the storage unit of the pth row and the pth column, and a gating end of the selector of the pth row and the pth column is used for inputting a configurable coefficient (corresponding signal) of the p power in the generator polynomial. The output end of the selector in the p-th row and the j-th column is connected with one input end of the exclusive-or calculation unit in the (p +1) -th row and the (j +1) -th column, and the output end of the selector in the p-th row and the j-th column is connected with one input end of the storage unit in the (p +1) -th row and the (j +1) -th column; and the selection control module in the p row and the j column is used for transmitting the output result of the selector in the p row and the j column to the exclusive-or calculation unit in the (p +1) th row and the (j +1) th column and the storage unit in the (p +1) th row and the (j +1) th column, updating the output result to a CRC initial value corresponding to the p power under the trigger of the clock signal, and using the CRC initial value as a parameter for carrying out exclusive-or in the selection control module in the (p +1) th row and the (j +1) th column in the next clock period, wherein the selection control module in the (p +1) th row and the (j +1) th column comprises the exclusive-or calculation unit in the (p +1) th row and the (j +1) th column and the selection control module in the (p +1) th row and the (j +1) th column is positioned in the selection processing array in the (j +1) th column. When j is larger than 0, one input end of the XOR calculation unit in the jth row and the jth column is connected with the output end of the selector in the (p-1) th row and the (j-1) th column; when j is equal to 0, one input end of the xor calculation unit in the jth row and the jth column of the pth row is configured to input a CRC initial value corresponding to a preconfigured highest bit, where the CRC initial value corresponding to the input highest bit is updated according to a clock cycle under a triggering effect of clock information, and specifically, the CRC initial value is updated and configured by a related configuration module inside the CRC hardware calculation system.
In summary, in this embodiment, only one clock cycle of the clock signal is required to control the information field to complete parallel iterative processing of the coefficients of the power of each of the generator polynomials except for the power of the highest power term, and the power of the lowest order information value of the information field, so as to improve the efficiency of CRC calculation. On the other hand, the method can flexibly configure various types of configuration information to adapt to various CRC calculation requirements.
As can be seen from fig. 1 and fig. 2, on a one-to-one basis, when the CRC type is CRC8, m is set to 8, i is set to 4, so that 4 selective processing arrays sequentially process 4-bit information values under the trigger of the clock signal, wherein the highest bit is processed first, and the lowest bit is processed last; the information field is composed of 4-bit information values; all selection control modules in one selection processing array perform parallel processing on input CRC initial values; the information field is a binary sequence. Since the selection control modules in the p-th row and the j-th column are not all the selection control modules corresponding to the coefficient of the second highest power, the selection control module in the p-th row and the j-th column is not the selection processing array corresponding to the information value at the lowest order of the information field, and p is less than m-1, p is greater than 0, m is greater than 2, j is greater than or equal to 0, j is less than i-1, i is greater than 1, m, i and p are all positive integers, j is an integer, therefore, the selection control modules in the p-th row and the j-th column include a selection control module in the 1 st row and the 0 th column, a selection control module in the 1 st row and the 1 st column, a selection control module in the 1 st row and the 2 nd column, a selection control module in the 2 nd row and the 0 th column, a selection control module in the 2 nd row and the 1 st column, a selection control module in the 2 nd row and the 2 nd column, a selection control module in the 6 th row and the 0 th column, a selection control module in the 6 th row and the 1 st column, and a selection control module in the 6 th row and the 2 nd column.
Corresponding to the second selection processing array in FIG. 2, the selection control module of line 1, line 0 includes XOR calculation unit of line 1, line 0 (the block marked with C [0] < Lambda > C [7] < Lambda > D [3] in FIG. 2), storage unit of line 1, line 0 (the block marked with C [0] in FIG. 2), and selector S1[1] of line 1, line 0, XOR calculation unit of line 1, line 0 respectively obtains CRC initial value C [7] corresponding to the most significant bit, CRC initial value C [0] corresponding to the power of 0 (derived from register REG1), and information value D [3] of bit 3 of the information field (the most significant bit of the information field), and performs C [0] < Lambda > C [7] < Lambda > D [3], and outputs XOR result of these three values; the memory cell of row 1 and column 0 is used to store the CRC initial value C [0] corresponding to the power of 0. The row 1, column 0 selector S1[1] is for selecting the output of the XOR result of the XOR calculation unit of row 1, column 0 when the power-1 coefficient g [1] in the generator polynomial is not equal to 0, or for selecting the output of C [0] stored by the storage unit of row 1, column 0 when the power-1 coefficient g [1] in the generator polynomial is equal to 0. The selection control module in the 1 st row and the 0 th column configures the output result of the selector in the 1 st row and the 0 th column as the output value of the selection control module in the 1 st row and the 0 th column, then transmits the output value to the exclusive OR calculation unit in the 2 nd row and the 1 st column and the storage unit in the 2 nd row and the 1 st column, and updates the output value to a CRC initial value L [1] corresponding to the power of 1 under the triggering of the clock signal. The selection control module of the 2 nd row and the 1 st column comprises an exclusive OR calculation unit of the 2 nd row and the 1 st column and a storage unit of the 2 nd row and the 1 st column. When g [1] is equal to 0, L [1] is equal to C [0], and the CRC initial value corresponding to the power of 1 required by the selection control module of the row 2 and column 1 is not the exclusive OR result of the exclusive OR calculation unit of the row 1 and column 0, but remains as the CRC initial value C [0] corresponding to the power of 0.
Corresponding to the second selection processing array in FIG. 2, the selection control block of line 1 and column 1 includes an XOR calculation unit of line 1 and column 1 (the block marked L [0] L [7] D [2] in FIG. 2), a storage unit of line 1 and column 2 (the block marked L [0] in FIG. 2), and a selector S2[1] of line 1 and column 1, the XOR calculation unit of line 1 and column 1 respectively obtains the CRC initial value L [7] corresponding to the highest bit (derived from the selection control block of line 7 and column 0), the CRC initial value L [0] corresponding to the power of 0 (derived from the selection control block of line 0 and column 0), and the information value D [2] of bit 2 of the information field (the second highest bit of the information field), and then L0 ^ L7 ^ D2, output the XOR result of these three values; the memory cell of the 1 st row and the 1 st column is used for storing a CRC initial value L [0] corresponding to 0 th power (derived from the selection control module of the 0 th row and the 0 th column). The row 1, column 1 selector S2[1] is for selecting the output of the exclusive or result of the exclusive or calculation unit of row 1, column 1 when the power-1 coefficient g [1] in the generator polynomial is not equal to 0, or for selecting the output of L [0] stored by the storage unit of row 1, column 1 when the power-1 coefficient g [1] in the generator polynomial is equal to 0. The selection control module in the 1 st row and the 1 st column configures the output result of the selector in the 1 st row and the 1 st column as the output value of the selection control module in the 1 st row and the 1 st column, then transmits the output value to the exclusive OR calculation unit in the 2 nd row and the 2 nd column and the storage unit in the 2 nd row and the 2 nd column, and updates the output value to a CRC initial value M [1] corresponding to the power of 1 under the triggering of the clock signal. When g [1] is equal to 0, M [1] is equal to L [0], and the CRC initial value corresponding to the power of 1 required by the selection control module of the 2 nd row and 2 nd column is not updated by the XOR result of the XOR calculation unit of the 1 st row and 1 st column, but is retained as the CRC initial value L [0] corresponding to the power of 0. Note that a CRC initial value C [0] raised to the power of 0 and a CRC initial value L [0] raised to the power of 0 are CRC initial values of two adjacent clock cycles, respectively.
As a second embodiment, the xor calculation unit in row 0 and column j is configured to xor the CRC initial value corresponding to the highest bit with the information value in (i-j-1) th bit (counted from 0 in the binary sequence from right to left) of the information field, output the xor result of the xor calculation unit in row 0 and column j, and determine the xor result as the xor result of the information value of the corresponding bit of the information field and the associated value; in this embodiment, the xor calculation unit in the jth row and the jth column of row 0 respectively inputs the CRC initial value corresponding to the highest bit and the information value of the (i-j-1) th bit of the information field, so that the information value of the (i-j-1) th bit of the information field is the information value of the corresponding bit of the information field, and the CRC initial value corresponding to the highest bit is the associated value; when the exclusive-or calculation unit is an exclusive-or gate circuit with three input ends, the first input end of the exclusive-or gate circuit is used for inputting the CRC initial value corresponding to the highest bit, and the third input end of the exclusive-or gate circuit is used for inputting the information value of the (i-j-1) th bit of the information field; the CRC initial value corresponding to the input highest bit is updated according to a clock cycle under the triggering action of clock information, and particularly, a related configuration module in the CRC hardware computing system performs updating configuration; j is greater than or equal to 0, j is less than i-1, i is greater than 1, i is a positive integer, j is an integer, the selection control module in row 0 and column j is not all the selection control modules corresponding to the coefficient of the highest power, nor is the selection control module in row 0 and column j is the selection processing array corresponding to the lowest information value located in (not included in) the information field. The storage unit in row 0 and column j is configured to store a preset constant, where the preset constant is the CRC initial value associated with the corresponding power, and may be stored before the cyclic redundancy check is started, and the preset constant is preferably 0 to mask the influence of feedback of a previous stage (a previous clock cycle). The selector in the 0 th row and the jth column is used for selecting the output of the exclusive OR result of the exclusive OR calculation unit in the 0 th row and the jth column or a preset constant stored in the storage unit in the 0 th row and the jth column according to a coefficient of 0 th power in the generator polynomial, and configuring the output result of the selector in the 0 th row and the jth column as an output value of the selection control module in the 0 th row and the jth column; and the selection control module in the 0 th row and the j th column is used for transmitting the output result of the selector in the 0 th row and the j th column to the XOR calculation unit in the 1 st row and the (j +1) th column and the storage unit in the 1 st row and the (j +1) th column, updating the CRC initial value associated with the corresponding power under the trigger of the clock signal, and updating the CRC initial value corresponding to the power of 0 under the trigger of the clock signal to be used as a parameter for carrying out XOR and selection in the selection control module in the 1 st row and the (j +1) th column in the next clock period. In some embodiments, when the selector in the 0 th row and the jth column selects the preset constant stored in the memory cell in the 0 th row and the jth column to output, the selection control module in the 1 st row and the (j +1) th column can be prevented from being influenced by the xor result generated in the last clock cycle; the selection control module of the 0 th row and the jth column comprises an exclusive OR calculation unit of the 0 th row and the jth column, a selector of the 0 th row and the jth column and a storage unit of the 0 th row and the jth column, and the selection control module of the 0 th row and the jth column is positioned in the selection processing array of the jth column; the selection control module in the 0 th row and the jth column comprises an exclusive-or calculation unit in the 0 th row and the jth column, a selector in the 0 th row and the jth column, and a storage unit in the 0 th row and the jth column, wherein one input end of the selector in the 0 th row and the jth column is connected with an output end of the exclusive-or calculation unit in the 0 th row and the jth column, the other input end of the selector in the 0 th row and the jth column is connected with an output end of the storage unit in the 0 th row and the jth column, and a gating end of the selector in the 0 th row and the jth column is used for inputting a configurable coefficient (corresponding signal) of the 0 th power in the generating polynomial. The selection control module of the 1 st row and the (j +1) th column comprises an exclusive-or calculation unit of the 1 st row and the (j +1) th column and a storage unit of the 1 st row and the (j +1) th column, and the selection control module of the 0 th row and the (j +1) th column is positioned in the selection processing array of the (j +1) th column. The output end of the selector in the 0 th row and the j th column is connected with one input end of the exclusive OR calculation unit in the 1 st row and the (j +1) th column.
As can be seen from fig. 1 and 2, when the CRC type is CRC8, m is set to 8, i is set to 4, and the information field is composed of 4-bit information values. The CRC hardware computing system may also process the information fields, with the information fields being composed of D [3], D [2], D [1] and D [0] in order from left to right, optionally with the CRC hardware computing system inputting D [3] in a first clock cycle, D [2] in a second clock cycle, D [1] in a third clock cycle, and D [0] in a fourth clock cycle. Since the selection control modules in row 0 and column j are not all the selection control modules corresponding to the coefficient of the second highest power, the selection control module in row 0 and column j is not the selection processing array corresponding to the information value D [0] located at the lowest bit of the information field, and j is greater than or equal to 0, j is less than i-1, i is greater than 1, i is a positive integer, and j is an integer, the selection control modules in row 0 and column j include the selection control module in row 0 and column 0, the selection control module in row 0 and column 1, the selection control module in row 0 and column 2, and the selection control module in row 0 and column 3.
Corresponding to FIG. 2, the selection control module in row 0 and column 0 includes the XOR calculation unit in row 0 and column 0 (the block marked with C7 ^ D [3] in FIG. 2), the storage unit in row 0 and column 0 (the block marked with 0 in FIG. 2), and the selector S1[0] in row 0 and column 0, the XOR calculation unit in row 0 and column 0 respectively obtains the CRC initial value C7 corresponding to the most significant bit and the information value D [3] of the 3 rd bit of the information field (the most significant bit of the information field), and carries out C7 ^ D [3], outputs the XOR result of the two values; in some embodiments, the register REG0 is used to buffer the CRC value fed back in the previous clock cycle (corresponding to the check information code output from the previous stage), and transmit the CRC value to the xor calculation unit in the 0 th row and the 0 th column in the current clock cycle, so as to update the CRC initial value C [7] corresponding to the most significant bit. The 0 th row and 0 th column memory cells are used to store a constant of 0. The row 0 and column 0 selector S1[0] is for selecting the output of the exclusive or result of the exclusive or calculation unit of row 0 and column 0 when the coefficient g [0] of the power of 0 in the generator polynomial is not equal to 0, or for selecting the output of the constant 0 stored by the storage unit of column 0 in row 0 when the coefficient g [0] of the power of 0 in the generator polynomial is equal to 0. The selection control module in the 0 th row and the 0 th column configures the output result of the selector S1[0] in the 0 th row and the 0 th column as the output value of the selection control module in the 0 th row and the 0 th column, then transmits the output value to the exclusive OR calculation unit in the 1 st row and the 1 st column and the storage unit in the 1 st row and the 1 st column, and updates the output value to a CRC initial value L [0] corresponding to the 0 th power under the triggering of the clock signal.
Similarly, the selection control module corresponding to row 0 and column 1 in fig. 2 includes an exclusive or calculation unit of row 0 and column 1 (the block marked with L [7] ^ D [2] in fig. 2), a storage unit of row 0 and column 1 (the block marked with 0 in fig. 2), and a selector S2[0] of row 0 and column 1, the exclusive or calculation unit of row 0 and column 1 respectively obtains the CRC initial value L [7] (from the selection control module of row 7 and column 0), and the information value D [2] (next highest bit of the information field) of the 2 nd bit of the information field, and performs L [7] ^ D [2], and outputs the exclusive or result of these two values; the memory cells of row 0 and column 1 are used to store a constant of 0. The row 0, column 1 selector S2[0] is for selecting the output of the exclusive or result of the exclusive or calculation unit of row 0, column 1 when the coefficient g [0] to the power of 0 in the generator polynomial is not equal to 0, or for selecting the output of the constant 0 stored by the storage unit of row 0, column 1 when the coefficient g [0] to the power of 0 in the generator polynomial is equal to 0. The selection control module in the 0 th row and the 1 st column configures the output result of the selector in the 0 th row and the 1 st column as the output value of the selection control module in the 0 th row and the 1 st column, then transmits the output value to the exclusive OR calculation unit in the 1 st row and the 2 nd column and the storage unit in the 1 st row and the 2 nd column, and updates the output value to a CRC initial value M [0] corresponding to the 0 th power under the triggering of the clock signal.
As a second embodiment, in all the selection control modules corresponding to the coefficients of the second highest power, except the selection control module in the selection processing array corresponding to the lowest information value of the information field, each selection control module is configured to select, according to the coefficient of the second lowest power in the generator polynomial, an xor result between the information value of the corresponding bit of the information field and the associated value or a CRC initial value associated with the corresponding second lowest power, as a check information code (which may also be regarded as a result of one hardware iteration and belongs to the CRC initial value) output by the current selection control module, and transmit the check information code to all the selection control modules in the selection processing array corresponding to the information value of the second lowest power in the information field. And the coefficient of the corresponding power in the generating polynomial is used as a selection control signal, and the corresponding power item and the coefficient in the generating polynomial correspond to the selection control module which is selected currently. In this embodiment, the relatively low-order information value of the information field is an information value that is one order lower than the number of bits of the information value corresponding to the selection processing array in which the selection control module that outputs the check information code is located.
As a second embodiment, the xor calculation unit in the j (m-1) th row is configured to xor the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (m-2) th power, and the information value of the (i-j-1) th bit of the information field, output the xor result of the xor calculation unit in the 0 (m-1) th row, and determine the xor result as the xor result of the information value of the corresponding bit of the information field and the associated value; in this embodiment, the xor calculation unit in the jth column of the (m-1) th row inputs the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (m-2) th power, and the information value of the (i-j-1) th bit of the information field, respectively, so that the information value of the (i-j-1) th bit of the information field (actually, the binary number of the (i-j) th bit from right to left) is the information value of the corresponding bit of the information field, and the CRC initial value corresponding to the highest bit and the CRC initial value corresponding to the (m-1) th power are associated values; when the exclusive-OR calculation unit is an exclusive-OR gate circuit with three input ends, a first input end of the exclusive-OR gate circuit is used for inputting the CRC initial value corresponding to the highest bit, a second input end of the exclusive-OR gate circuit is used for inputting the CRC initial value corresponding to the power of (m-2), and a third input end of the exclusive-OR gate circuit is used for inputting the information value of the (i-j-1) th bit of the information field; the CRC initial value corresponding to the input highest bit is updated according to the clock period under the triggering action of clock information; the CRC initial value input by the selection control module in column 0 is configured before the CRC hardware computing system starts processing the information field, and is updated under the trigger of the clock signal, specifically, the CRC initial value is updated to the (m-2) th power according to the clock cycle, and may be transmitted from the register. It should be noted that, as can be seen from fig. 1, j is greater than or equal to 0, j is less than i-1, i is greater than 1, m and i are positive integers, and j is an integer; the selection control module in the (m-1) th row and the j column is the selection control module except the selection control module in the selection processing array corresponding to the lowest information value of the information field in all the selection control modules corresponding to the coefficient of the second highest power; all selection control modules corresponding to coefficients of the next highest power are all selection control modules corresponding to coefficients of the (m-1) th power of the generator polynomial. The memory unit of the jth column of the (m-1) th row is used for storing CRC initial values corresponding to (m-2) th powers, wherein the CRC initial values corresponding to the (m-2) th powers are CRC initial values associated with the corresponding powers; and the selector in the (m-1) th row and the j th column is used for selecting the XOR result of the XOR calculation unit in the (m-1) th row and the j th column or the CRC initial value corresponding to the (m-2) th power stored by the storage unit in the (m-1) th row and the j th column according to the coefficient g [ m-1] of the (m-1) th power in the generating polynomial and outputting the output result of the selector in the (m-1) th row and the j th column as the output value of the selection control module in the (m-1) th row and the j th column. In the embodiment, the selection control module in the (m-1) th row and the j th column comprises an exclusive OR calculation unit in the (m-1) th row and the j th column, a storage unit in the (m-1) th row and the j th column and a selector in the (m-1) th row and the j th column. And the selection control module in the (m-1) th row and the j th column is used for transmitting the output result of the selector in the (m-1) th row and the j th column to all the XOR calculation units in the (j +1) th column, and updating a CRC initial value corresponding to the highest bit required by the XOR calculation units in the (j +1) th column for XOR under the trigger of the clock signal, wherein the CRC initial value is used as a parameter for performing XOR in all the selection control modules in the (j +1) th column in the next clock period. Preferably, the selector in row (M-1) and column 0 outputs L [ M-1] of FIG. 1 in a first clock cycle, the selector in row (M-1) and column 1 corresponds to M [ M-1] of FIG. 1 in a second clock cycle, and the selector in row (M-1) and column (i-2) corresponds to N [ M-1] of FIG. 1 in a (i-1) clock cycle. Wherein, one input end of the selector in the jth row and jth column of the (m-1) th row and jth column is connected with the output end of the XOR calculation unit in the jth column of the (m-1) th row, the other input end of the selector in the jth column of the (m-1) th row is connected with the output end of the storage unit in the jth column of the (m-1) th row, the gating end of the selector in the jth column of the (m-1) th row is used for inputting the coefficient g [ m-1] of the (m-1) th power in the configurable polynomial generator, the output end of the selector in the jth column of the (m-1) th row is connected with the input ends of all the XOR calculation units in the (j +1) th column to obtain the CRC initial value corresponding to the highest bit, one input end of the XOR calculation unit in the (j +1) th row and jth column of the (m-1) th row is connected with the output end of the selector in the jth column of the (m-1) th row, and one input end of the storage unit in the (m-1) th row and the (j +1) th column is connected with the output end of the selector in the (m-1) th row and the j column. The CRC initial value corresponding to the highest bit is the CRC initial value corresponding to the second highest power; all the exclusive-or calculation units in the (j +1) th column are all the selection control modules in the selection processing array corresponding to the information value D [ i-j-1] which is positioned at the relatively low position of the information field. All the exclusive or calculation units of the (j +1) th column are located in the selection processing array of the (j +1) th column. In summary, in addition to the power term corresponding to the lowest-order information value of the information field, the present embodiment only needs a clock signal of one clock cycle to control the information field to complete the parallel iterative processing (checking process) of the coefficient of the second highest power in the generator polynomial, thereby improving the efficiency of CRC calculation on a hardware circuit. On the other hand, various types of configuration information can be flexibly configured according to the protocol so as to adapt to various CRC calculation requirements.
As can be seen from fig. 1 and fig. 2, on the basis of the first embodiment, when the CRC type is CRC8, m is set to 8, and i is set to 4; wherein the information field is a binary sequence of 4 bits. Since the selection control module in the jth column of the (m-1) th row is the selection control module except the selection control module in the selection processing array corresponding to the lowest-order information value of the information field among all the selection control modules corresponding to the coefficients of the second highest power, j is greater than or equal to 0, j is less than i-1, i is greater than 1, m and i are both positive integers, and j is an integer; therefore, the selection control modules in the (m-1) th row and the j th column include the selection control module in the 7 th row and the 0 th column, the selection control module in the 7 th row and the 1 st column, and the selection control module in the 7 th row and the 2 nd column.
The selection control module corresponding to row 7 and column 0 in FIG. 2 comprises XOR calculation unit (the block marked with C6 ^ C7 ^ D3 in FIG. 2) of row 7 and column 0, storage unit (the block marked with C6 in FIG. 2) of row 7 and column 0, and selector S1[7] of row 7 and column 0, wherein the XOR calculation unit of row 7 and column 0 obtains CRC initial value C7 corresponding to the most significant bit, CRC initial value C6 corresponding to the power of 6 (from register REG7) and information value D [3] of bit 3 of the information field (the most significant bit of the information field), and carries out C6 ^ C7 ^ D [3], and outputs the XOR result of the three values; the storage unit of the 7 th row and the 0 th column is used for storing the CRC initial value C [6] corresponding to the power of 6. The row 7, column 0 selector S1[7] is for selecting the output of the XOR result of the XOR calculation unit of row 7, column 0, if the power-of-7 coefficient g [7] in the generator polynomial is not equal to 0, or for selecting the output of C [6] stored by the storage unit of column 0, row 7, if the power-of-7 coefficient g [7] in the generator polynomial is equal to 0. The selection control module in the 7 th row and the 0 th column configures the output result of the selector in the 7 th row and the 0 th column as the output value of the selection control module in the 7 th row and the 0 th column, and transmits the output value to all the exclusive OR calculation units in the 1 st column, wherein the output value sequentially comprises a block marked with L [7] < Lambda > D [2] in the graph 2, a block marked with L [0] < Lambda > L [7] < Lambda > D [2] in the graph 2, and a block marked with L [6] < Lambda > L [7] < Lambda > D [2] in the graph 2; and updating the CRC initial value L [7] corresponding to the most significant bit in the next clock period under the triggering of the clock signal.
The selection control module corresponding to line 7 and column 1 in FIG. 2 comprises XOR calculation unit (marked with L6 ^ L7 ^ D2 in FIG. 2), storage unit (marked with L6 in FIG. 2) of line 7 and column 1 in line 7 and selector S2[7] of line 7 and column 1, the XOR calculation unit of line 7 and column 1 obtains CRC initial value L7 corresponding to the highest order (from the selection control module of line 7 and column 0), CRC initial value L6 corresponding to the power of 6 (from the selection control module of line 6 and column 0 in FIG. 1), and information value D2 of bit 2 of the information field (next highest bit of the information field), and then L6 ^ L7 ^ D2, output the XOR result of these three values; the memory cell of the 7 th row and the 1 st column is used for storing CRC initial values L [6] corresponding to 6 th power (derived from the selection control module of the 6 th row and the 0 th column). The row 7, column 1 selector S2[7] is for selecting the output of the XOR result of the XOR calculation unit of row 7, column 1, when the power-of-7 coefficient g [7] in the generator polynomial is not equal to 0, or for selecting the output of the L [6] stored by the storage unit of row 7, column 1, when the power-of-7 coefficient g [7] in the generator polynomial is equal to 0. And the selection control module in the 7 th row and the 1 st column configures the output result of the selector in the 7 th row and the 1 st column as the output value of the selection control module in the 7 th row and the 1 st column, transmits the output value to all the exclusive OR calculation units in the 2 nd column, and updates the output value to the CRC initial value M [7] corresponding to the highest bit in the next clock cycle under the triggering of the clock signal.
As a third embodiment, each selection control module in the selection processing array corresponding to the lowest order information value of the information field, each selection control module in the ith selection processing array corresponding to the generator polynomial in FIG. 1 is used for selecting the XOR result of the information value of the corresponding bit of the information field and the associated data or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial and transmitting the result to the selection processing array corresponding to the information value of the highest bit of the information field, for example, the information value transmitted to the highest bit of the information field is buffered in the register of the selection processing array corresponding to the information value, and then the register outputs the coefficient of the corresponding power to the selection control module corresponding to the selection processing array, namely, the selection control module outputs the selection control module to the same row of the selection processing array corresponding to the information value of the highest bit of the information field.
As a third embodiment, the xor calculation unit in the p (th) row and the (i-1) th column is configured to xor the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (p-1) th power, and the information value of the lowest bit of the information field, output an xor result of the xor calculation unit in the p (th) row and the (i-1) th column, and determine the xor result as an xor result of the information value of the corresponding bit of the information field and the associated value; in this embodiment, the xor calculation unit in the (i-1) th column of the p-th row inputs the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (p-1) th power, and the information value of the lowest bit of the information field, respectively, so that the information value of the lowest bit of the information field (actually, the binary number of the 0 th bit from the right to the left) is the information value of the corresponding bit of the information field, and the CRC initial value corresponding to the highest bit and the CRC initial value corresponding to the (p-1) th power are associated numerical values; when the exclusive-or calculation unit is an exclusive-or gate circuit with three input ends, a first input end of the exclusive-or gate circuit is used for inputting the CRC initial value corresponding to the highest bit, a second input end of the exclusive-or gate circuit is used for inputting the CRC initial value corresponding to the power of (p-1), and a third input end of the exclusive-or gate circuit is used for inputting the information value of the lowest bit of the information field; the CRC initial value corresponding to the input most significant bit is updated according to a clock cycle under the triggering action of clock information, and specifically updated to N [ m-1] output by the selection control module in the (m-1) th row and the (i-2) th column. P is less than or equal to m-1, p is greater than 0, m is greater than 1, and i and m are positive integers; the selection control module of the p-th row and the (i-1) -th column is the selection control module in the selection processing array corresponding to the lowest-order information value of the information field except the selection control module of the 0-th row. The storage unit of the (i-1) th column of the p-th row is used for storing a CRC initial value corresponding to the (p-1) th power, wherein the CRC initial value corresponding to the (p-1) th power is a CRC initial value associated with the corresponding power, is a CRC initial value updated in the last clock cycle and is transmitted by the selection control module of the (i-2) th column of the (p-1) th row. The selector of the p row and the (i-1) th column is used for selecting the XOR result of the XOR calculation unit of the p row and the (i-1) th column or the CRC initial value corresponding to the (p-1) th power stored by the storage unit of the p row and the (i-1) th column to output according to the coefficient of the p power in the generator polynomial, and the output result of the selector of the p row and the (i-1) th column is configured as the output value of the selection control module of the p row and the (i-1) th column; the selection control module of the p row, the (i-1) th column comprises an XOR calculation unit of the p row, the (i-1) th column, a storage unit of the p row, the (i-1) th column and a selector of the p row, the selection control module of the p row, the (i-1) th column is positioned in the selection processing array corresponding to the lowest information value of the information field, and the selection control module of the p row, the (i-1) th column is used for transmitting the output result of the selector of the p row, the (i-1) th column to the selection control module of the p row, the 0 th column through a register to form a feedback path and can be used as a parameter for carrying out XOR in the selection control module of the p row, the 0 th column in the next clock cycle. One input end of the selector of the (i-1) th column in the p-th row is connected with the output end of the exclusive-or calculation unit of the (i-1) th column in the p-th row, the other input end of the selector of the (i-1) th column in the p-th row is connected with the output end of the storage unit of the (i-1) th column in the p-th row, and the gating end of the selector of the (i-1) th column in the p-th row is used for inputting the configurable coefficient of the p-th power in the generating polynomial. One input end of the XOR calculation unit in the p-th row and the (i-1) -th column is connected with the output end of the selector in the (p-1) -th row and the (i-2) -th column, so that the XOR calculation unit in the p-th row and the (i-1) -th column acquires a CRC initial value corresponding to the power of (p-1); one input end of the storage unit in the p-th row and the (i-1) -th column is connected with the output end of the selector in the (p-1) -th row and the (i-2) -th column, so that the storage unit in the p-th row and the (i-1) -th column acquires a CRC initial value corresponding to the power of (p-1); the output end of the selector of the (i-1) th column in the p-th row is connected with the data input end of the register of the 0 th column in the p-th row.
In summary, the present embodiment controls the lowest-order information value of the information field to perform parallel iterative processing of the coefficients of the powers other than the lowest-order power term in the generator polynomial, thereby improving the efficiency of CRC calculation. On the other hand, the method can flexibly configure various types of configuration information to adapt to various CRC calculation requirements.
As can be seen from the above description of FIGS. 1 and 2, when the CRC type is CRC8, m is set to 8, i is set to 4, wherein the information fields are composed of D [3], D [2], D [1] and D [0] from left to right, D [3] is input to the CRC hardware computing system first, and D [0] is input to the CRC hardware computing system last. Since the selection control module in the (i-1) th row and the (i-1) th column of the information field is the selection control module in the selection processing array corresponding to the lowest information value of the information field except the selection control module in the 0 th row, the selection control module in the (i-1) th row and the (i-1) th column of the p-th row includes the selection control module in the 1 st row and the 3 rd column, the selection control module in the 2 nd row and the 3 rd column, the selection control module in the 3 rd row and the 3 rd column, and the selection control module in the 7 th row and the 3 rd column. The selection control module corresponding to the 1 st row and the 3 rd column in FIG. 2 comprises an XOR calculation unit (the block marked with N0 ^ D [0] ^ N [7] in FIG. 2), a storage unit (the block marked with N [0] in FIG. 2) of the 1 st row and the 3 rd column, and a selector S4[1] (corresponding to Si [1] in FIG. 1) of the 1 st row and the 3 rd column, wherein the XOR calculation unit in the 1 st row and the 3 rd column respectively obtains the CRC initial value N [7] corresponding to the highest bit, the CRC initial value N [0] corresponding to the power of 0, and the lowest information value D [0] of the information field, performs N [0] ^ D [0] ^ N [7], and outputs the XOR result of the three values; the storage unit of the 1 st row and the 3 rd column is used for storing a CRC initial value N [0] corresponding to 0 th power, wherein the CRC initial value N [0] corresponding to 0 th power is from the selection control module of the 0 th row and the 2 nd column; the row 1, column 3 selector S4[1] is for selecting the output of the XOR result of the XOR calculation unit of row 1, column 3 when the power-1 coefficient g [1] in the generator polynomial is not equal to 0, or for selecting the output of N [0] stored by the storage unit of row 1, column 3 when the power-1 coefficient g [1] in the generator polynomial is equal to 0. The selection control module in row 1 and column 3 configures the output result of the selector in row 1 and column 3 as the output value of the selection control module in row 1 and column 3, and then transmits the output value to the register REG1 in row 1, and updates the output value to the CRC initial value O [1] corresponding to the power of 0 under the trigger of the clock signal. When the CRC initial value received by the register REG1 associated with the corresponding power is 0, the register REG1 cannot convey a feedback signal to lock the register, and the selection control module in row 1, column 0 does not receive feedback information of the selection control module in row 1, column 3. In this embodiment, the register REG1 is used to buffer the CRC value fed back in the previous clock cycle (corresponding to the check information code output from the previous stage), and transmit the CRC value to the xor calculation unit in row 1 and column 0 in the current clock cycle, so as to update the CRC initial value C [0] input to the xor calculation unit in row 1 and column 0 to the power of 0.
The selection control module of the 7 th row and the 3 rd column comprises an XOR calculation unit of the 7 th row and the 3 rd column (a box marked with N6 ^ D [0] ^ N [7] in FIG. 2), a storage unit of the 7 th row and the 3 rd column (a box marked with N6 in FIG. 2), and a selector S4[7] (corresponding to Si [ m-1]) of the 7 th row and the 3 rd column, wherein the XOR calculation unit of the 7 th row and the 3 rd column respectively obtains a CRC initial value N [7] (corresponding to N [ m-1] of FIG. 1) corresponding to the most significant bit, a CRC initial value N [6] (corresponding to N [ m-2] of FIG. 1) corresponding to the power of 6, and an information value D [0] of the least significant bit of the information field, and performs N [6] < D [0] ^ N [7], and outputs an XOR result of the three values; the storage unit of the 7 th row and the 3 rd column is used for storing a CRC initial value N [6] corresponding to the power of 6, wherein the CRC initial value N [6] corresponding to the power of 6 is the selection control module from the 6 th row and the 2 nd column; the row 7 column 3 selector S4[7] is for selecting the output of the XOR result of the XOR calculation unit of row 7 column 3 when the power-of-7 coefficient g [7] in the generator polynomial is not equal to 0, or for selecting the output of N [6] stored by the storage unit of row 7 column 3 when the power-of-7 coefficient g [7] in the generator polynomial is equal to 0. The selection control module in row 7 and column 3 configures the output result of the selector in row 7 and column 3 as the output value of the selection control module in row 7 and column 3, and then transmits the output value to the register REG7 in row 7, and updates the output value to the CRC initial value O [7] corresponding to the power of 6 under the trigger of the clock signal. When the CRC initial value received by the register REG7 associated with the corresponding power is 0, the register REG7 cannot convey a feedback signal to lock the register, and the selection control module in row 7, column 0 does not receive feedback information of the selection control module in row 7, column 3. In this embodiment, the register REG7 is used to buffer the CRC value fed back in the previous clock cycle (corresponding to the check information code output from the previous stage), and transmit the CRC value to the xor calculation unit in row 7 and column 0 in the current clock cycle, so as to update the CRC initial value C [6] corresponding to the power of 6 input to the xor calculation unit in row 7 and column 0.
As a second embodiment, the xor calculation unit in row 0 and column (i-1) is configured to xor the CRC initial value corresponding to the highest bit with the lowest information value of the information field, output an xor result of the xor calculation unit in row 0 and column j, and determine the xor result as an xor result of the information value of the corresponding bit of the information field and the associated value; the storage unit in row 0 and column (i-1) is configured to store a preset constant, where the preset constant is a CRC initial value associated with the corresponding power, and may be stored before starting performing cyclic redundancy check, and the preset constant is preferably 0. When the exclusive-or calculation unit is an exclusive-or gate circuit having three input terminals, a first input terminal of the exclusive-or gate circuit is used for inputting the CRC initial value corresponding to the most significant bit, and a third input terminal of the exclusive-or gate circuit is used for inputting the information value of the least significant bit of the information field. In this embodiment, the xor calculation unit in the (i-1) th row and the (0) th column inputs the CRC initial value corresponding to the highest bit and the lowest bit information value of the information field, respectively, and in the xor calculation unit in the (i-1) th row and the (0) th column, the input CRC initial value corresponding to the highest bit is updated according to the clock cycle under the trigger of the clock information, specifically, updated to N [ m-1] output by the selection control module in the (i-2) th row and the (m-1) th column. The selector of the 0 th row and the (i-1) th column is used for selecting the exclusive OR result of the exclusive OR calculation unit of the 0 th row and the (i-1) th column or the numerical value 0 output stored by the storage unit of the 0 th row and the (i-1) th column according to a coefficient g [0] raised to the power of 0 in the generator polynomial, and configuring the output result of the selector of the 0 th row and the (i-1) th column as the output value of the selection control module of the 0 th row and the (i-1) th column; the selection control module of the 0 th row and the (i-1) th column comprises an exclusive OR calculation unit of the 0 th row and the (i-1) th column, a selector of the 0 th row and the (i-1) th column and a storage unit of the 0 th row and the (i-1) th column, and the selection control module of the 0 th row and the (i-1) th column is the selection control module of the 0 th row in the selection processing array corresponding to the lowest information value of the information field. The selection control module in the row 0 and the column (i-1) is used for transmitting the output result of the selector in the row 0 and the column (i-1) to a register in the selection control module in the row 0 and the column 0 to form a feedback path, and can be used as a parameter for carrying out exclusive or in the selection control module in the row 0 and the column 0 as the next clock cycle. One input end of the selector in the (i-1) th row and column 0 is connected with the output end of the exclusive-or calculation unit in the (i-1) th row and column 0, the other input end of the selector in the (i-1) th row and column 0 is connected with the output end of the storage unit in the (i-1) th row and column 0, and the gating end of the selector in the (i-1) th row and column 0 is used for inputting the coefficient of the power 0 in the configurable generating polynomial. The output end of the selector of the (i-1) th column in the 0 th row is connected with the data input end of the register of the (i-1) th column in the 0 th row.
As can be seen from FIG. 1 and FIG. 2, when the CRC type is CRC8, m is set to 8, i is set to 4, and the components of the information field are D [3], D [2], D [1] and D [0] from left to right. Since the selection control module at row 0 and column (i-1) is the selection control module at row 0 in the selection processing array corresponding to the lowest information value of the information field, the selection control module at row 0 and column (i-1) is the selection control module at row 0 and column 3. Corresponding to FIG. 2, the selection control module of the 0 th row and the 3 rd column comprises an XOR calculation unit (the block marked with N7 ^ D [0] in FIG. 2) of the 0 th row and the 3 rd column, a storage unit (the block marked with 0 in FIG. 2) of the 0 th row and the 3 rd column, and a selector S4[0] (corresponding to Si [0] in FIG. 1) of the 0 th row and the 3 rd column, wherein the XOR calculation unit of the 0 th row and the 3 rd column respectively obtains a CRC initial value N7 corresponding to the most significant bit and an information value D [0] of the least significant bit of the information field, performs N7 ^ D [0], and outputs an XOR result of the two values; the storage unit of the 0 th row and the 3 rd column is used for storing a numerical value of 0; the row 0, column 3 selector S4[0] is for selecting the output of the exclusive or result of the exclusive or calculation unit of row 1, column 3 when the coefficient g [0] to the power of 0 in the generator polynomial is not equal to 0, or for selecting the output of 0 stored by the storage unit of row 0, column 3 when the coefficient g [0] to the power of 0 in the generator polynomial is equal to 0. The selection control module in row 0 and column 3 configures the output result of the selector in row 0 and column 3 as the output value of the selection control module in row 0 and column 3, and then transmits the output value to the register REG0 in row 0, and updates the output value to the CRC initial value O [0] corresponding to the power of 0 under the trigger of the clock signal. In some embodiments, the register REG0 is configured to buffer a CRC value fed back in a previous clock cycle (corresponding to a check information code output at a previous stage), and transmit the buffered CRC value to the xor calculation unit in row 1 and column 0 in a current clock cycle, so as to update a CRC initial value C [7] corresponding to a highest bit input to the xor calculation unit in row 1 and column 0, and also to update a CRC initial value C [7] corresponding to a second power of the generator polynomial (a CRC initial value corresponding to a second power of the generator polynomial), where the CRC initial value C [8] corresponding to the second power of the generator polynomial (a CRC initial value corresponding to the second power of the generator polynomial). When the CRC initial value received by the register REG0 associated with the corresponding power is 0, the register REG0 cannot convey a feedback signal to lock the register, and the select control module in row 0 and column 0 does not receive feedback information from the select control module in row 0 and column 3.
On the basis of the third embodiment, in the CRC hardware computing system, each selection control module in the 0 th column is connected to a corresponding register, where the register exists in each row of the selection processing array in the 0 th column (corresponding to the first selection processing array in fig. 1 and 2), the data input terminal of one selection control module is connected to the data output terminal of one register, the data input terminal of each register is connected to the selector in the (i-1) th column in the same row, and in fig. 2, the output terminal of the selector S4[0] in the 0 th row and the 3 rd column is connected to the data input terminal D of the register REG0 in the 0 th row, the output terminal of the selector S4[1] in the 1 st row and the 3 rd column is connected to the data input terminal D of the register REG1 in the 1 st row, ·, the output terminal of the selector S4[7] in the 7 th row and the 3 rd column is connected to the data input terminal D of the register REG7 in the 7 th row, so that the selection control module corresponding to the selection processing array (first selection processing array) in the 0 th column and the selection control module corresponding to the selection processing array (i-1) in the (i-1) th column are connected through a register; wherein, the selection processing array of the 0 th column is the selection processing array corresponding to the most significant information value of the information field, and the selection processing array of the (i-1) th column is the selection processing array corresponding to the least significant information value of the information field. The clock end of each register is connected with the clock signal CLK, and the clock ends of the registers in the 0 th row to the (m-1) th row are connected with the clock signal CLK; each register is used for buffering the output result of the selector in the (i-1) th column of the same row under the triggering of the clock signal, and the corresponding relation to fig. 1 is as follows: the registers in the 0 th row to the (m-1) th row buffer O [0] to O [ m-1] respectively, and update the CRC initial value associated with the corresponding power, so that the m registers in the first selection processing array repeat a combination of some check codes in sequence, and a pseudo-random sequence with a period of m can be formed based on the xor logic circuit units in the foregoing embodiments, and a feedback polynomial of a pseudo-random sequence with a maximum length is correspondingly generated. The CRC code may be obtained after several clock cycles to complete the check of the information field.
On the basis of the foregoing embodiment, the manner of selecting the xor result of the information values of the corresponding bits of the information field and the associated numerical value or the CRC initial value associated to the corresponding power according to the coefficient corresponding to the power in the generator polynomial includes: when a CRC hardware computing system configures that a coefficient of a corresponding power in the generating polynomial is 1, a gating end of a selector in a corresponding selection control module receives a first level signal, the selector gates an XOR computing unit in the selection control module where the selector is located and outputs an XOR result of the XOR computing unit, wherein the XOR result of an information value of a corresponding bit of the information field and an associated value is the XOR result of the XOR computing unit, and the associated value comprises a CRC initial value corresponding to the highest bit and/or a CRC initial value associated with the corresponding power; the exclusive-or calculation unit is an exclusive-or logic gate circuit with three input ends; when the CRC hardware calculation system configures that the coefficient of the corresponding power in the generator polynomial is 0, the gating end of the selector in the corresponding selection control module receives the second level signal, the selector gates the CRC initial value associated with the corresponding power stored in the storage unit in the selection control module in which the selector is located to output, and specifically outputs the CRC initial value to the associated selection control module (the associated selection control module in the selection processing array in the adjacent column) other than the selection processing array in which the selection control module is located, but the CRC initial value associated with the corresponding power received by the selection control module of this class or the CRC initial value corresponding to the highest bit does not change, so that the xor result of the previous stage feedback is masked, and the CRC calculation process is advanced.
Preferably, the second level signal is different from the first level signal, and when the first level signal is configured to be at a high level, the first level signal is configured to be at a low level, and is used as the selection control signal of the selector in the selection control module, and is input to the gate terminal of the selector to change the switching path of the selector.
In the first to third embodiments, the xor operations executed by the two adjacent selection control modules in the two adjacent clock cycles are connected in series by using the combinational logic, and the two head and tail selection control modules are connected by using the combinational logic to form the feedback loop, so that each selection processing array can be controlled to update the CRC initial value in each clock cycle to obtain the CRC code after the corresponding clock cycle, the combinational logic circuit is optimized by combining the periodic feedback function and the selection circuit, and the effect of operating the multi-bit CRC operation in a single-beat clock cycle is also achieved. In addition, when the code corresponding to the generating polynomial is added to the information field (to form the CRC code through the CRC operation) input into the CRC hardware computing system, since the CRC hardware computing system for cyclic redundancy check designed by the present invention abandons the use of the multiplier, instead of using the selector in cooperation with the xor computing unit, and reduces the multiplication operation on 0 in the process of completing the cyclic redundancy check on the information field in each clock cycle, the number of times of the highest power (the number of times of the highest power of the polynomial corresponding to the CRC code) added after the corresponding bit information value of the information field is not required to be 0, and thus less hardware resources are consumed.
In summary of embodiments one to three, the CRC hardware computing system configures a coefficient of a corresponding power except for a highest power term in a generator polynomial of a specified CRC as a selection control signal, inputs a gating end of a selector of a corresponding row and column in a selection control module so that each selection control module is configured to select an xor calculation result of an information value of a corresponding bit in an information field and an associated value or a CRC initial value associated with the corresponding power in accordance with the coefficient of the corresponding power in the generator polynomial in a current clock cycle, transmits an information value of a lower bit of the information field to a corresponding selection control module in a selection processing array so that the corresponding selection control module in other selection processing arrays starts to perform an xor operation of information values of other bits of the information field in a next clock cycle, and avoids introducing the number of times of the highest power term after the information field by 0 in a process of using the generator polynomial for checking, wherein the XOR operation can advance the CRC check process of the information field bit by bit; not only reduces the iterative processing of constant items such as 0, but also can flexibly configure the coefficients of each power to adapt to various CRC calculation requirements.
On the basis, the invention uses the combinational logic to connect the XOR operation executed by the two adjacent selection control modules under the two adjacent clock cycles in series, and uses the combinational logic to connect the head selection control module and the tail selection control module to form a feedback loop, so that each selection processing array can be controlled to update the CRC initial value in each clock cycle to obtain the CRC code after the corresponding clock cycle, thereby realizing the optimization of the combinational logic circuit by combining the periodic feedback function and the selection circuit and achieving the effect of running the multi-bit CRC operation in a single-beat clock cycle.
Furthermore, when the code corresponding to the generated polynomial is added to the information field of the CRC hardware computing system (to form the CRC code through the CRC operation), since the CRC hardware computing system for cyclic redundancy check according to the present invention abandons the use of the multiplier, and instead uses the selector in cooperation with the xor computing unit, the multiplication operation on 0 is reduced, so that it is not necessary to add 0 to the highest power (the highest power of the polynomial corresponding to the CRC code) after the corresponding bit information value of the information field, nor to directly use the matrix to perform the division operation on hardware, which results in less hardware resources.
Based on the foregoing embodiments, an embodiment of the present invention provides a chip including the CRC hardware computing system for cyclic redundancy check as described in the foregoing embodiments. Inside the chip, the CRC hardware computing system comprises i selective processing arrays, namely, the chip integrates the i selective processing arrays; each selection processing array is configured to be controlled by a coefficient of a corresponding power other than a highest power term (coefficient of the highest power) in the generator polynomial; each selection processing array comprises m selection control modules, and each selection control module is used for processing the information value of the corresponding bit of the information field; each bit of information value of the information field has a corresponding selection processing array in a CRC hardware computing system, and all selection control modules in one selection processing array correspond to the same bit of information value of the information field; in the generator polynomial, except for the coefficient corresponding to the highest power of the generator polynomial, the coefficient corresponding to each power has a corresponding selection control module in each selection processing array; equivalently, in the generator polynomial, each power term has a corresponding selection control block in each selection processing array except for a coefficient corresponding to the highest power of the generator polynomial, so that each power coefficient has a corresponding selection control block in each selection processing array. In the process of performing cyclic redundancy check by the CRC hardware computing system according to this embodiment, the coefficient of the highest power of the generator polynomial is not processed, which is equivalent to deleting the highest term of the generator polynomial, and then checking the remaining polynomials. In this embodiment, each selection control module is configured to, under the trigger of a clock signal, select, according to a coefficient corresponding to a power in the generator polynomial, an xor result between an information value of a corresponding bit in the information field and an associated numerical value or a CRC initial value associated with the corresponding power, transmit the xor result or CRC initial value to an associated selection control module other than the selection processing array in which the selection control module is located, one selection control module transmits only the result of its selection output to the selection control modules in the other selection processing arrays, in particular to the selection control modules in the other columns of figure 1, then the selection control module receiving the corresponding selection output result repeatedly executes the exclusive-or operation and the selection operation in the next clock period, after a plurality of clock periods, all the selection control modules in the selection processing array of the (i-1) th column output check codes in parallel; wherein the coefficients corresponding to powers in the generator polynomial are configured in the selection control module as selection control signals for selecting the circuit for generating the exclusive-or result of the information value of the corresponding bit in the information field and the associated value, or the circuit for storing the CRC initial value associated with the corresponding power, to be connected to the selection processing array of the other column, in some embodiments, in response to the clock signal, one selection control module transmits the exclusive-or result of the information value of the corresponding bit in the information field and the associated value, or the CRC initial value associated with the corresponding power, in the current clock cycle to the selection control module for processing the information value of the associated bit of the information field in the next clock cycle, under the selection of the coefficient corresponding power of the generator polynomial, to implement the iterative processing required in performing the cyclic redundancy check, to obtain iteration results corresponding to powers other than the highest power.
On the basis of the foregoing embodiment, the CRC hardware computing system includes m and i multiplied selection control modules, all the selection control modules form an arrangement of m rows and i columns, so that the CRC hardware computing system has i columns of selection processing arrays, each column selection processing array is a selection processing array, each selection processing array has m rows of selection control modules, each selection control module in one selection processing array is a selection control module, and each selection control module in the CRC hardware computing system has i selection control modules; each selection control module comprises an exclusive-or calculation unit, a storage unit and a selector, so that the exclusive-or calculation unit, the storage unit and the selector are all arranged in the CRC hardware calculation system in an arrangement manner of m rows and i columns, and corresponding to fig. 1, row sequence numbers and column sequence numbers where the exclusive-or calculation unit, the storage unit and the selector are located are counted from 0. In some embodiments, the selection control module is further connected to a register for buffering CRC initial values transmitted by other selection control modules in a previous clock cycle or results (iterative results in the cyclic redundancy check process) selectively output by the associated selector, and optionally, the generator polynomial and the code values output by the information field in the m selection control modules of the selection processing array through parallel processing of i clock cycles. The chip is then designed to: configuring coefficients of corresponding powers except a highest power term in a generator polynomial of a specified CRC as selection control signals, then, each selection control module is used for selecting an XOR result of an information value of a corresponding bit in an information field and an associated numerical value or a CRC initial value associated with the corresponding power in a current clock cycle according to the coefficient of the corresponding power in the generator polynomial, transmitting the XOR result to a selection control module corresponding to a lower bit of the information field in a selection processing array, so that the selection control modules corresponding to other selection processing arrays start to carry out XOR operation on information values of other bits of the information field in the next clock cycle, and avoiding introducing the number of times of the highest power term 0 after the information field in the process of using the generator polynomial for checking; not only reduces the iterative processing of constant items such as 0, but also can flexibly configure the coefficients of each power to adapt to various CRC calculation requirements.
It should be added that the chip is a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a single chip, an arm (acorn RISC machine) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. When the external equipment sends communication data to the chip, the CRC hardware computing system included in the chip uses a preset generator polynomial to check and package the communication data, so that the communication data are transmitted more reliably, wherein one piece of communication data received in each clock cycle is the information field.
As an embodiment of the chip, except all the selection control modules corresponding to the coefficients of the second higher power and the selection processing array corresponding to the lowest information value of the information field, each selection control module is used for selecting the XOR result of the information value of the corresponding bit of the information field and the associated numerical value or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial, and transmitting the result as the check information code (which can also be regarded as the result of one iteration and belongs to the CRC initial value) output by the current selection control module to the selection processing array corresponding to the information value of the relatively lower bit of the information field, and output to the corresponding selection control module in the selection processing array of the coefficient of the relative high power, and the coefficient corresponding to the power in the generator polynomial corresponds to the selection control module which is selected currently. In this embodiment, the relatively lower information value of the information field is an information value that is one bit lower than the number of bits of the information value corresponding to the selection processing array in which the selection control module that outputs the verification information code is located, and the relatively higher coefficient is a coefficient that is one time higher than the number of times of the power item corresponding to the selection control module that outputs the verification information code.
In an embodiment of the chip, in all the selection control modules corresponding to the coefficients of the second higher power, except the selection control module in the selection processing array corresponding to the lowest-order information value of the information field, each selection control module is configured to select, according to the coefficient corresponding to the second power in the generator polynomial, an xor result of the information value of the corresponding bit of the information field and the associated value or a CRC initial value associated with the corresponding second power as a check information code (which may also be regarded as a result of one iteration and belongs to the CRC initial value) output by the current selection control module, and transmit the check information code to all the selection control modules in the selection processing array corresponding to the information value of the relatively lower power of the information field. And the coefficient of the corresponding power in the generating polynomial is used as a selection control signal, and the corresponding power item and the coefficient in the generating polynomial correspond to the selection control module which is selected currently. In this embodiment, the relatively low-order information value of the information field is an information value that is one order lower than the number of bits of the information value corresponding to the selection processing array in which the selection control module that outputs the check information code is located.
As an embodiment of the chip, each selection control module in the selection processing array corresponding to the lowest order information value of the information field, each selection control module in the ith selection processing array corresponding to the generator polynomial in FIG. 1 is used for selecting the XOR result of the information value of the corresponding bit of the information field and the associated data or the CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial and transmitting the result to the selection processing array corresponding to the information value of the highest bit of the information field, for example, the information value transmitted to the highest bit of the information field is buffered in the register of the selection processing array corresponding to the information value, and then the register outputs the coefficient of the corresponding power to the selection control module corresponding to the selection processing array, namely, the selection control module outputs the selection control module to the same row of the selection processing array corresponding to the information value of the highest bit of the information field.
On the basis of the above embodiment, in the chip, each selection control module in column 0 is connected to a corresponding register, where the register exists in each row of the selection processing array in column 0 (corresponding to the first selection processing array in fig. 1 and 2), the data input terminal of one selection control module is connected to the data output terminal of one register, the data input terminal of each register is connected to the selector in column (i-1) in the same row, and in fig. 2, the output terminal of the selector S4[0] in column 3 in row 0 is connected to the data input terminal D of the register REG0 in row 0, the output terminal of the selector S4[1] in column 3 in row 1 is connected to the data input terminal D of the register REG1 in row 1., and the output terminal of the selector S4[7] in column 3 in row 7 is connected to the data input terminal D of the register REG7 in row 7, so that the selection control module corresponding to the selection processing array (first selection processing array) in the 0 th column and the selection control module corresponding to the selection processing array (i-1) in the (i-1) th column are connected through a register; the clock end of each register is connected with the clock signal CLK, and the clock ends of the registers in the 0 th row to the (m-1) th row are connected with the clock signal CLK; each register is used for buffering the output result of the selector in the (i-1) th column of the same row under the triggering of the clock signal, and the corresponding relation to fig. 1 is as follows: the registers of line 0 to line (m-1) buffer O0 to O m-1, respectively, and update the CRC initial values associated with the corresponding powers, the m registers of the first selection processing array are sequentially repeated with some combination of check codes, thereby forming a pseudo-random sequence of period i based on the xor logic involved in the previous embodiment, after i clock cycles, the m registers obtain the m-bit check code (CRC code) of the CRC hardware computing system, corresponding to the feedback polynomial that produces the maximal length pseudorandom sequence, as an iteration result, configured in some embodiments as a check result, the chip can directly or through peripheral equipment send out successful verification information after obtaining the verification result, and the information field is encapsulated according to the iteration result, so that the information field of the external communication of the chip is more reliable.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention and not to limit it; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art will understand that: modifications to the specific embodiments of the invention or equivalent substitutions for parts of the technical features may be made; without departing from the spirit of the present invention, it is intended to cover all aspects of the invention as defined by the appended claims.

Claims (20)

1. A CRC hardware computing system is characterized in that the CRC hardware computing system is used for acquiring configuration information and information fields, determining a generator polynomial according to the configuration information, and providing a clock signal, coefficients of powers in the generator polynomial and the information fields for each selection processing array;
the CRC hardware computing system comprises i select processing arrays; each selection processing array is configured to be controlled by coefficients of a corresponding power of the generator polynomial other than a highest power term; each selection processing array comprises m selection control modules, and each selection control module is used for inputting the information value of the corresponding bit of the information field; wherein, each bit information value of the information field has a corresponding selection processing array in a CRC hardware computing system; in the generator polynomial, except for the coefficient of the highest power of the generator polynomial, each power term has a corresponding selection control module in each selection processing array;
each selection control module is used for selecting an XOR result of an information value of a corresponding bit in the information field and an associated numerical value or a CRC initial value associated with the corresponding power according to a coefficient of the corresponding power in a generating polynomial under the triggering of a clock signal, and transmitting the result to a related selection control module except for a selection processing array where the selection control module is located;
wherein m is configured to be equal to the number of bits of a CRC initial value, and m is equal to the degree of the highest-order term in the generator polynomial; i is configured as the number of bits of an information field, which is a binary sequence that is input into the CRC hardware computing system in one clock cycle.
2. The CRC hardware computation system of claim 1, comprising m and i multiplied selection control modules, all of which form an arrangement of m rows and i columns, such that the CRC hardware computation system has i columns of selection processing arrays; each selection processing array comprises m rows of selection control modules;
each selection control module comprises an exclusive-OR calculation unit, a storage unit and a selector, so that the exclusive-OR calculation unit, the storage unit and the selector are arranged in the CRC hardware calculation system in an arrangement of m rows and i columns.
3. The CRC hardware computing system of claim 2, wherein each selection control module is configured to select, based on a coefficient corresponding to a power of the generator polynomial, an xor result of an information value of a corresponding bit of the information field and an associated value or a CRC initial value associated with the corresponding power, transmit to the selection processing array corresponding to an information value of a relatively lower bit of the information field, and output to the selection control module corresponding to the coefficient corresponding to the relatively higher power in the selection processing array, except for all selection control modules corresponding to coefficients of the higher power and the selection processing array corresponding to the lowest bit of the information field.
4. The CRC hardware computation system of claim 3, wherein the XOR computation unit of the jth row and the jth column is configured to XOR the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (p-1) th power, and the information value of the (i-j-1) th bit of the information field, output the XOR result of the XOR computation unit of the jth row and the jth column, and determine the XOR result as the result of the information value of the corresponding bit of the information field and the associated value;
the storage unit of the jth column of the p-th row is used for storing a CRC initial value corresponding to the power of (p-1), wherein the CRC initial value corresponding to the power of (p-1) is a CRC initial value associated with the corresponding power;
the p row and j column selector is used for selecting the XOR result of the XOR calculation unit in the p row and j column or the CRC initial value corresponding to the (p-1) power stored by the storage unit in the p row and j column to output according to the coefficient of the p power in the generator polynomial, and configuring the output result of the p row and j column selector as the output value of the selection control module in the p row and j column; the selection control module of the p row and the j column comprises an exclusive OR calculation unit of the p row and the j column, a selector of the p row and the j column and a storage unit of the p row and the j column, and the selection control module of the p row and the j column is positioned in the selection processing array of the j column;
the selection control module of the p row and the j column is used for transmitting the output result of the selector of the p row and the j column to the exclusive OR calculation unit of the (p +1) row and the (j +1) column and the storage unit of the (p +1) row and the (j +1) column, and updating the output result to a CRC initial value corresponding to the p power under the triggering of the clock signal; the selection control module of the (p +1) th row and the (j +1) th column comprises an exclusive-or calculation unit of the (p +1) th row and the (j +1) th column and a storage unit of the (p +1) th row and the (j +1) th column, and the selection control module of the (p +1) th row and the (j +1) th column is positioned in the selection processing array of the (j +1) th column;
wherein p is less than m-1, p is greater than 0, m is greater than 2, j is greater than or equal to 0, j is less than i-1, i is greater than 1, m, i and p are positive integers, and j is an integer; the selection control modules in the pth row and the jth column are not all the selection control modules corresponding to the coefficient of the second highest power, and the selection control modules in the pth row and the jth column are not positioned in the selection processing array corresponding to the lowest bit information value of the information field; all the selection control modules corresponding to the coefficients of the second highest power are all the selection control modules corresponding to the coefficients of the second highest power of the generator polynomial;
the CRC initial value input by the selection control module in column 0 is configured before the CRC hardware computing system starts processing the information field, and is updated under the trigger of the clock signal.
5. The CRC hardware computation system according to claim 3, wherein the XOR computation unit in the 0 th row and the j th column is configured to XOR the CRC initial value corresponding to the highest bit with the information value of the (i-j-1) th bit of the information field, output the XOR result of the XOR computation unit in the 0 th row and the j th column, and determine the XOR result as the result of the information value of the corresponding bit of the information field and the associated value;
the storage unit in the 0 th row and the jth column is used for storing a preset constant, wherein the preset constant is a CRC initial value associated with the corresponding power;
the selector in the 0 th row and the jth column is used for selecting the output of the exclusive OR result of the exclusive OR calculation unit in the 0 th row and the jth column or a preset constant stored in the storage unit in the 0 th row and the jth column according to a coefficient of 0 th power in the generator polynomial, and configuring the output result of the selector in the 0 th row and the jth column as an output value of the selection control module in the 0 th row and the jth column; the selection control module of the 0 th row and the jth column comprises an exclusive OR calculation unit of the 0 th row and the jth column, a selector of the 0 th row and the jth column and a storage unit of the 0 th row and the jth column, and the selection control module of the 0 th row and the jth column is positioned in the selection processing array of the jth column;
the selection control module in the 0 th row and the jth column is used for transmitting the output result of the selector in the 0 th row and the jth column to the XOR calculation unit in the 1 st row and the (j +1) th column and the storage unit in the 1 st row and the (j +1) th column, and updating the output result to the CRC initial value associated with the corresponding power under the triggering of the clock signal; the selection control module of the 1 st row and the (j +1) th column comprises an exclusive-or calculation unit of the 1 st row and the (j +1) th column and a storage unit of the 1 st row and the (j +1) th column, and the selection control module of the 0 th row and the (j +1) th column is positioned in the selection processing array of the (j +1) th column;
wherein j is greater than or equal to 0, j is less than i-1, i is greater than 1, i is a positive integer, j is an integer; the selection control modules in the 0 th row and the j th column are not all the selection control modules corresponding to the coefficient of the highest power, and the selection control modules in the 0 th row and the j th column are not positioned in the selection processing array corresponding to the lowest-order information value of the information field.
6. The CRC hardware computing system of claim 2, wherein among all selection control modules corresponding to the coefficients of the second highest power, except the selection control module in the selection processing array corresponding to the lowest order information value of the information field, each selection control module is configured to select an exclusive or result of the information value of the corresponding bit of the information field and the associated value or a CRC initial value associated with the corresponding power according to the coefficient of the corresponding power in the generator polynomial, and transmit the result to all selection control modules in the selection processing array corresponding to the information value of the relatively lower order of the information field.
7. The CRC hardware computation system of claim 6, wherein the XOR computation unit of the j (m-1) th column is configured to XOR the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (m-2) th power, and the information value of the (i-j-1) th bit of the information field, output the XOR result of the XOR computation unit of the 0 (m-1) th column, and determine the XOR result as the information value of the corresponding bit of the information field and the associated value;
the memory unit of the jth column of the (m-1) th row is used for storing CRC initial values corresponding to (m-2) th powers, wherein the CRC initial values corresponding to the (m-2) th powers are CRC initial values associated with the corresponding powers;
the selector in the (m-1) th row and the j column is used for selecting the XOR result of the XOR calculation unit in the (m-1) th row and the j column or the CRC initial value corresponding to the (m-2) th power stored in the storage unit in the (m-1) th row and the j column to output according to the coefficient of the (m-1) th power in the generator polynomial, and configuring the output result of the selector in the (m-1) th row and the j column as the output value of the selection control module in the (m-1) th row and the j column; the selection control module of the (m-1) th row and the jth column comprises an exclusive OR calculation unit of the (m-1) th row and the jth column, a storage unit of the (m-1) th row and the jth column and a selector of the (m-1) th row and the jth column;
the selection control module of the jth row and the jth column in the (m-1) th row is used for transmitting the output result of the selector of the jth column in the (m-1) th row to all the XOR calculation units in the (j +1) th column, and updating the CRC initial value corresponding to the highest bit required by the XOR calculation units in the (j +1) th column for XOR under the trigger of the clock signal; wherein, all the exclusive or calculation units in the (j +1) th column are all the selection control modules in the selection processing array corresponding to the information values located at the relatively low bits of the information field;
wherein j is greater than or equal to 0, j is less than i-1, i is greater than 1, m and i are both positive integers, and j is an integer; the selection control module in the (m-1) th row and the j column is the selection control module except the selection control module in the selection processing array corresponding to the lowest information value of the information field in all the selection control modules corresponding to the coefficient of the second highest power; all the selection control modules corresponding to the coefficients of the second highest power are all the selection control modules corresponding to the coefficients of the second highest power of the generator polynomial.
8. The CRC hardware computing system of claim 2, wherein each selection control module in the selection processing array corresponding to the lowest-order information value of the information field is configured to select, according to the coefficient corresponding to the power in the generator polynomial, an xor result of the information value of the corresponding bit of the information field and the associated data or a CRC initial value associated with the corresponding power, transmit the xor result to the selection processing array corresponding to the information value of the highest-order information of the information field, and output the CRC initial value to the selection control module corresponding to the selection processing array corresponding to the coefficient corresponding to the power.
9. The CRC hardware computing system of claim 8, wherein the xor calculation unit of the (i-1) th column of the p-th row is configured to xor the CRC initial value corresponding to the highest bit, the CRC initial value corresponding to the (p-1) th power, and the information value of the lowest bit of the information field, output an xor result of the xor calculation unit of the (i-1) th column of the p-th row, and determine the xor result as the information value of the corresponding bit of the information field and the associated value;
the storage unit of the p row and the (i-1) column is used for storing CRC initial values corresponding to (p-1) power, wherein the CRC initial values corresponding to (p-1) power are CRC initial values associated with the corresponding power;
the selector of the p row and the (i-1) th column is used for selecting the XOR result of the XOR calculation unit of the p row and the (i-1) th column or the CRC initial value corresponding to the (p-1) th power stored by the storage unit of the p row and the (i-1) th column to output according to the coefficient of the p power in the generator polynomial, and the output result of the selector of the p row and the (i-1) th column is configured as the output value of the selection control module of the p row and the (i-1) th column; the selection control module of the p row and the (i-1) th column comprises an exclusive OR calculation unit of the p row and the (i-1) th column, a storage unit of the p row and the (i-1) th column and a selector of the p row and the (i-1) th column, and the selection control module of the p row and the (i-1) th column is in a selection processing array corresponding to the lowest information value of the information field;
wherein p is less than or equal to m-1, p is greater than 0, m is greater than 1, and i and m are positive integers; the selection control module of the p-th row and the (i-1) -th column is the selection control module in the selection processing array corresponding to the lowest-order information value of the information field except the selection control module of the 0-th row.
10. The CRC hardware computing system of claim 8, wherein the xor calculation unit in row 0 and column (i-1) is configured to xor the CRC initial value corresponding to the most significant bit with the information value of the least significant bit of the information field, output an xor result of the xor calculation unit in row 0 and column j, and determine the xor result as the result of the information value of the corresponding bit of the information field and the associated value;
the storage unit at the 0 th row and the (i-1) th column is used for storing a preset constant, wherein the preset constant is a CRC initial value associated with the corresponding power;
the selector of the 0 th row and the (i-1) th column is used for selecting the exclusive OR result of the exclusive OR calculation unit of the 0 th row and the (i-1) th column or the preset constant output stored in the storage unit of the 0 th row and the (i-1) th column according to the coefficient of the 0 th power in the generator polynomial, and configuring the output result of the selector of the 0 th row and the (i-1) th column as the output value of the selection control module of the 0 th row and the (i-1) th column; the selection control module of the 0 th row and the (i-1) th column comprises an exclusive OR calculation unit of the 0 th row and the (i-1) th column, a selector of the 0 th row and the (i-1) th column and a storage unit of the 0 th row and the (i-1) th column, and the selection control module of the 0 th row and the (i-1) th column is the selection control module of the 0 th row in the selection processing array corresponding to the lowest information value of the information field.
11. The CRC hardware computation system of claim 8, wherein each selection control module in the 0 th column is connected with a corresponding register, wherein the data input end of one selection control module is correspondingly connected with the data output end of one register, and the data input end of each register is connected with the selector in the (i-1) th column in the same row, so that the selection control module corresponding to the selection processing array in the 0 th column and the selection control module corresponding to the selection processing array in the (i-1) th column are connected through the register; wherein, the selection processing array of the 0 th column is the selection processing array corresponding to the most significant information value of the information field, and the selection processing array of the (i-1) th column is the selection processing array corresponding to the least significant information value of the information field;
and the clock end of each register is connected with the clock signal, and each register is used for caching the output result of the selector in the (i-1) th column of the same row under the triggering of the clock signal.
12. A CRC hardware computing system according to any of claims 3 to 11, wherein the selection of the xor result of the information values of the respective bits of the information field with the associated value or the initial value of the CRC associated to the corresponding power in dependence on the corresponding power of the coefficients in the generator polynomial comprises:
when a CRC hardware computing system configures that a coefficient of a corresponding power in the generating polynomial is 1, a gating end of a selector in a corresponding selection control module receives a first level signal, the selector gates an XOR computing unit in the selection control module where the selector is located and outputs an XOR result of the XOR computing unit, wherein the XOR result of an information value of a corresponding bit of the information field and an associated value is the XOR result of the XOR computing unit, and the associated value comprises a CRC initial value corresponding to the highest bit and/or a CRC initial value associated with the corresponding power; the exclusive-or calculation unit is an exclusive-or logic gate circuit with three input ends; the data stored by the memory cell is supported to be refreshed;
when the CRC hardware computing system configures that the coefficient of the corresponding power in the generator polynomial is 0, the gating end of the selector in the corresponding selection control module receives a second level signal, and the selector gates the CRC initial value associated with the corresponding power stored in the storage unit in the selection control module where the selector is located to output, wherein the second level signal is different from the first level signal.
13. The CRC hardware computing system of claim 12, wherein the configuration information comprises a CRC type, coefficients of a generator polynomial, and a CRC initial value;
the CRC hardware computing system is configured to determine a generator polynomial based on the configuration information in a manner comprising:
determining the type of the generator polynomial and coefficients of powers in the generator polynomial according to the CRC type and coefficients of the generator polynomial;
before the CRC hardware computing system starts to process the information field, the CRC initial value is set and supported to be updated according to the communication protocol followed by the information field;
and the CRC initial value corresponding to the highest bit is the CRC initial value corresponding to the second higher power of the generator polynomial.
14. The CRC hardware computing system of claim 13, wherein when said CRC type is CRC8, m is set to 8, i is set to 4, and said information field is comprised of 4-bit information values.
15. A chip comprising the CRC hardware computing system of any one of claims 1 to 14.
16. The chip of claim 15, wherein the CRC hardware computing system comprises m multiplied by i select control modules, and all select control modules form an arrangement of m rows and i columns, such that the CRC hardware computing system has i columns of select processing arrays; each selection processing array comprises m rows of selection control modules;
each selection control module comprises an exclusive-or calculation unit, a storage unit and a selector, so that the exclusive-or calculation unit, the storage unit and the selector are arranged in the CRC hardware calculation system in an arrangement of m rows and i columns.
17. The chip of claim 15, wherein each selection control module is configured to select, according to a coefficient corresponding to a power of the generator polynomial, an xor result of an information value of a corresponding bit of the information field and an associated value or a CRC initial value associated with the corresponding power, transmit the xor result to the selection processing array corresponding to an information value of a relatively lower bit of the information field, and output the CRC initial value to the selection processing array corresponding to the coefficient corresponding to the relatively higher power, except for all selection control modules corresponding to coefficients corresponding to the higher power, and the selection processing array corresponding to an information value of a lowest bit of the information field.
18. The chip according to claim 15, wherein among all the selection control modules corresponding to the coefficients of the second highest power, except the selection control module in the selection processing array corresponding to the lowest order information value of the information field, each selection control module is configured to select, according to the coefficient of the generator polynomial corresponding to the second lowest power, an exclusive or result of the information value of the corresponding bit of the information field and the associated value or a CRC initial value associated with the corresponding second lowest power, and transmit the result to all the selection control modules in the selection processing array corresponding to the information value of the information field.
19. The chip according to claim 15, wherein each selection control module in the selection processing array corresponding to the lowest order information value of the information field is configured to select, according to the coefficient of the generator polynomial corresponding to the power, an xor result of the information value of the corresponding bit of the information field and the associated data or a CRC initial value associated with the corresponding power, transmit the result to the selection processing array corresponding to the highest order information value of the information field, and output the result to the selection control module corresponding to the selection processing array corresponding to the coefficient of the corresponding power.
20. The chip of claim 16, wherein each selection control module in column 0 is connected to a corresponding register, wherein a data input terminal of one selection control module is connected to a data output terminal of one register, and a data input terminal of each register is connected to a selector in column (i-1) in the same row, so that the selection control module corresponding to the selection processing array in column 0 and the selection control module corresponding to the selection processing array in column (i-1) are connected through the register; wherein, the selection processing array of the 0 th column is the selection processing array corresponding to the most significant information value of the information field, and the selection processing array of the (i-1) th column is the selection processing array corresponding to the least significant information value of the information field;
and the clock end of each register is connected with the clock signal, and each register is used for caching the output result of the selector in the (i-1) th column of the same row under the triggering of the clock signal.
CN202210419560.5A 2022-04-21 2022-04-21 CRC hardware computing system and chip Pending CN114884517A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117220833A (en) * 2023-11-09 2023-12-12 新华三网络信息安全软件有限公司 CRC (cyclic redundancy check) calculation circuit, chip, message processing method and network security equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117220833A (en) * 2023-11-09 2023-12-12 新华三网络信息安全软件有限公司 CRC (cyclic redundancy check) calculation circuit, chip, message processing method and network security equipment
CN117220833B (en) * 2023-11-09 2024-01-26 新华三网络信息安全软件有限公司 CRC (cyclic redundancy check) calculation circuit, chip, message processing method and network security equipment

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