CN107154836A - A kind of cardiopulmonary bypass in beating heart redundancy CRC check method based on FPGA - Google Patents
A kind of cardiopulmonary bypass in beating heart redundancy CRC check method based on FPGA Download PDFInfo
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- CN107154836A CN107154836A CN201710508875.6A CN201710508875A CN107154836A CN 107154836 A CN107154836 A CN 107154836A CN 201710508875 A CN201710508875 A CN 201710508875A CN 107154836 A CN107154836 A CN 107154836A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/091—Parallel or block-wise CRC computation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/18578—Satellite systems for providing broadband data service to individual earth stations
- H04B7/18586—Arrangements for data transporting, e.g. for an end to end data transport or check
Abstract
The invention discloses a kind of cardiopulmonary bypass in beating heart redundancy CRC check method based on FPGA.This method follows the given CRC algorithm of CRC CCITT codings, cardiopulmonary bypass in beating heart redundancy CRC check code calculating is realized using simple XOR, solve the logic flaw of the multiple parallel-serial conversion based on bit serial, breach the high engineering bottleneck of the BlockRAM resources occupation rates based on look-up table, improve the data throughout of CRC check, reduce simultaneously to hardware resource challenging needs, it is achieved thereby that simplifying logic, improving efficiency and reducing the purpose of resource.
Description
Technical field
The present invention relates to Satellite TT and the communication technology, more particularly to a kind of cardiopulmonary bypass in beating heart redundancy CRC schools based on FPGA
Proved recipe method.
Background technology
In the data frame transfer that satellite remote control, remote measurement, outside sum are passed, it is to examine link to pass to take CRC check purpose
Defeated correctness, reaches correcting data error and error detection purpose, prevents error-logic judgement.
Cyclic redundancy CRC check is subordinate to the cyclic code of packet, and its basic thought is：Information code element sequence of the transmitting terminal in transmission
The supervision code element of some redundancies is added in row, certain relation is formed between these picket codes and information code by coding rule, connects
Receiving end then finds or corrected issuable error code by checking this particular kind of relationship.
CRC check code is theoretical using uniform enconding, in transmitting terminal according to the K to be transmitted positions binary code sequence, with one
Fixed rule produces the picket code (i.e. CRC code) r of a verification, and is attached to information back, constitutes a new binary system
Code sequence, (k+r) position, finally sends altogether.In receiving terminal, then entered according to the rule followed between information code and CRC code
Performing check, to determine error performance and confidence level in data transfer.
Traditional cyclic redundancy CRC check technology is primarily referred to as serial data checking algorithm and byte look-up table checking algorithm
2 major classes.
CRC-CCITT given algorithms are followed strictly based on serial data check code algorithm, based on Memory lookup table algorithms
Simple, intuitive, can obtain the CRC check code of data frame, but these algorithms have the following disadvantages：
(1) the CRC check code algorithm based on bit serial is characterized in needing multiple parallel-serial conversion, system delay big, realizes
Sequential alignment is more complicated, and occupancy hardware resource is more, it is difficult to break through the bottleneck of processing speed；
(2) the byte type lookup table algorithm based on Memory resources is characterized in complicated displacement and XOR computing
Delivery is completed by matlab programs, Slices and LUTs hardware resources are employed in algorithm and are not reduced relatively, and device 96
Block RAM block resources have accounted for 1；
(3) a variety of different modes in CRC-CCITT agreements are directed to, look-up table generation and byte based on Memory resources are adjusted
During, whether the detailed problem such as inverted order does not illustrate clear for register first phase and high low byte, does not provide concrete application
Constraints.
As transmission information rate is improved, the CRC check computational methods based on bit serial or based on Memory look-up tables
The technical requirements such as resources occupation rate is low, system work clock is high, result of calculation delay is small can not already be met.
The content of the invention
The technology of the present invention solves problem：Overcoming the deficiencies in the prior art, there is provided a kind of following parallel based on FPGA
Ring redundancy CRC check method, cardiopulmonary bypass in beating heart redundancy CRC check code calculating is realized using simple XOR, at utmost full
Foot satellite CRC check is calculated efficiently, demand accurately and quickly.
The present invention technical solution be：
A kind of cardiopulmonary bypass in beating heart redundancy CRC check method based on FPGA, comprises the following steps：
Step 1: the data transfer passed according to satellite remote control, remote measurement, exterior measuring or number sets call format framing, number is formed
According to frame；
Step 2: confirm different CRC patterns to input the sequence requirement with output data, initial phase requirement and
Output result whether the requirement with 0xFFFF XORs；
Step 3: the initial phase of different CRC patterns is set, when CRC pattern is XMODEN patterns or TURE patterns,
The initial phase is set to " 0000 ", when CRC pattern is FALSE patterns or X25 patterns, the initial phase set
For " FFFF "；
Step 4: when the logical sequence of data frame to be encoded is frame alignment word part, byte counter adds 1, inputs word
Section is directly assigned to output byte, while shift register is accordingly initialized；
Step 5: when the logical sequence of data frame to be encoded is data to be encoded part, byte counter adds 1, inputs
Byte is directly assigned to output byte, and byte pair has been inputted while directly being calculated according to cyclic redundancy CRC check parallel computation formula
The CRC check code answered；
Step 6: when the logical sequence of data frame to be encoded is CRC check part, byte counter adds 1, according to CRC
The data order of check code, CRC check code is exported.
Further, the frame length of the data frame is Na, wherein the effective byte length for participating in CRC codings is Nb, CRC schools
Yard byte length is tested for Nk；The logical sequence of the data frame includes frame alignment word part, data to be encoded part and CRC
Check part；The sequential length of the frame alignment word part is Na-Nb-Nk, and the sequential length of the data to be encoded part is
Nb, the sequential length of the CRC check part is Nk.
Further, the output result whether the requirement with 0xFFFF XORs, including：
When the specific CRC pattern is X25 patterns, calculated using the cyclic redundancy CRC check parallel computation formula
CRC check code require with 0xFFFF carry out XOR.
Further, the cyclic redundancy CRC check parallel computation is based on CRC-CCITT standards.
Further, the cyclic redundancy CRC check parallel computation formula is：Before the CRC check code of current byte is equal to
One byte CRC register values and the logic XOR of each information bit of current byte；
When the specific CRC pattern is inverted order to inputting with the sequence requirement of output data,
In formula group (1),Represent the CRC that i-th of shift register is inputted after 1 8bite byte
Check bit；Represent the jth position of previous byte CRC check code；mk, k=1,2 ... 8 represent current byte
K-th of bit；
When the specific CRC pattern is positive sequence to inputting with the sequence requirement of output data,
In formula group (2),Represent the CRC that i-th of shift register is inputted after 1 8bite byte
Check bit；Represent the jth position of previous byte CRC check code；mk, k=1,2 ... 8 represent current byte
K-th of bit.
Further, according to the data order of CRC check code, CRC check code is exported, including：
If the data order of CRC check code is inverted order, the CRC check code is first from low bit output；If CRC check code
Data order be positive sequence, then CRC check code is first from higher bit output.
The present invention has the advantages that compared with prior art：
The present invention proposes a kind of cardiopulmonary bypass in beating heart redundancy CRC check method based on FPGA, it then follows CRC-CCITT encode to
Determine CRC algorithm, realize cardiopulmonary bypass in beating heart redundancy CRC check code calculating using simple XOR, solve based on bit serial
The logic flaw of multiple parallel-serial conversion, breaches the high engineering bottleneck of the BlockRAM resources occupation rates based on look-up table, improves
The data throughout of CRC check, while reducing to hardware resource challenging needs, it is achieved thereby that simplifying logic, improving effect
The purpose of rate and reduction resource.
Brief description of the drawings
Fig. 1 is a kind of flow chart of cardiopulmonary bypass in beating heart redundancy CRC check method based on FPGA proposed by the present invention；
Fig. 2 is that the present invention relates to CRC-CCITT coding principle schematic diagrames；
Fig. 3 is a kind of flow chart of cardiopulmonary bypass in beating heart redundancy CRC check method based on FPGA in the embodiment of the present invention.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that described herein
Specific embodiment be used only for explaining the present invention, rather than limitation of the invention.It also should be noted that, for the ease of
Description, part related to the present invention rather than entire infrastructure are illustrate only in accompanying drawing.
Fig. 1 is a kind of flow chart of cardiopulmonary bypass in beating heart redundancy CRC check method based on FPGA proposed by the present invention.With reference to figure
1, a kind of cardiopulmonary bypass in beating heart redundancy CRC check method based on FPGA proposed by the present invention specifically may include steps of：
Step 1: the data transfer passed according to satellite remote control, remote measurement, exterior measuring or number sets call format framing, number is formed
According to frame.
Wherein, the data transfer passed according to satellite remote control, remote measurement, exterior measuring or number sets call format framing, is treated with being formed
Pass the data frame of data.The frame length of the data frame is Na, wherein the effective byte length for participating in CRC codings is Nb, CRC check
Code byte length is Nk；The logical sequence of the data frame includes frame alignment word part, data to be encoded part and CRC schools
Test part；The sequential length of the frame alignment word part is Na-Nb-Nk, and the sequential length of the data to be encoded part is Nb,
The sequential length of the CRC check part is Nk.
Step 2: confirm different CRC patterns to input the sequence requirement with output data, initial phase requirement and
Output result whether the requirement with 0xFFFF XORs.
Wherein, whether CRC pattern is to inputting the sequence requirement with output data, initial phase requirement and output result
Requirement with 0xFFFF XORs is the CRC algorithm demand of background model；The output result whether with 0xFFFF XORs will
Ask, including：
When the specific CRC pattern is X25 patterns, calculated using the cyclic redundancy CRC check parallel computation formula
CRC check code require with 0xFFFF carry out XOR.That is, when the specific CRC pattern is X25 patterns, using described
The CRC check code that cyclic redundancy CRC check parallel computation formula is calculated needs first to carry out after XOR with 0xFFFF, Cai Nengzuo
For final CRC check code to export.
Step 3: the initial phase of different CRC patterns is set, when CRC pattern is XMODEN patterns or TURE patterns,
The initial phase is set to " 0000 ", when CRC pattern is FALSE patterns or X25 patterns, the initial phase set
For " FFFF ".
Step 4: when the logical sequence of data frame to be encoded is frame alignment word part, byte counter adds 1, inputs word
Section is directly assigned to output byte, while shift register is accordingly initialized.
Step 5: when the logical sequence of data frame to be encoded is data to be encoded part, byte counter adds 1, inputs
Byte is directly assigned to output byte, and byte pair has been inputted while directly being calculated according to cyclic redundancy CRC check parallel computation formula
The CRC check code answered.
Wherein, the cyclic redundancy CRC check parallel computation is based on CRC-CCITT standards.The present invention using CRC-CCITT as
Standard carries out the coding and decoding design and emulation of CRC parallel computing, is illustrated in figure 2 that the present invention relates to CRC-CCITT coding principles
Schematic diagram.With reference to Fig. 2, encoded for CRC-CCITT, generator polynomial is g (x)=x16+x12+x5+ 1, corresponding feedback factor
For 0x1021, when data to be transferred is encoded, A/B switch closures, C switch disconnects；When extracting CRC check code, A/B is switched off, and C is opened
Close and close.
It is different according to background model demand CRC check pattern, when the check code for carrying out data frame is calculated, it need to pay close attention to
Whether shift register first phase, input 8bit data bit sequence, output 16bit verification code bit sequences and check code need and 0xFFFF XORs
Deng 4 important steps, several standards are commonly used as shown in table 1 for CRC-CCITT of the present invention.
Table 1CRC-CCITT commonly uses several standards
The core thinking of the CRC parallel computation is：
The CRC remainders and 8 information codes input string by turn inputted simultaneously due to 8 information codes produced by concurrent operation circuit
The CRC remainders that row circuit is produced are identical, it is possible to think that parallel computation circuit and serial computing circuit both circuits are
Effect, so as to derive the logical relation of parallel computation according to the change of each register in serial arithmetic circuit and input information bit
Formula.
Optionally, the cyclic redundancy CRC check parallel computation formula is：The CRC check code of current byte is equal to previous
Byte CRC register values and the logic XOR of each information bit of current byte；
When the specific CRC pattern is inverted order, such as TURE patterns and X25 moulds to the sequence requirement inputted with output data
During formula, the cyclic redundancy CRC check parallel computation formula is：
In formula group (1),Represent the CRC that i-th of shift register is inputted after 1 8bite byte
Check bit；Represent the jth position of previous byte CRC check code；mk, k=1,2 ... 8 represent current byte
K-th of bit.Above-mentioned formula group (1) is also denoted as table 2.
Table 2 inputs CRC parallel computation formula during with output data inverted order
When the specific CRC pattern is positive sequence to inputting with the sequence requirement of output data, for example XMODEN patterns and
During FALSE patterns, the cyclic redundancy CRC check parallel computation formula is：
In formula group (2),Represent the CRC that i-th of shift register is inputted after 1 8bite byte
Check bit；Represent the jth position of previous byte CRC check code；mk, k=1,2 ... 8 represent current byte
K-th of bit.Above-mentioned formula group (2) is also denoted as table 3.
Table 3 inputs CRC parallel computation formula during with output data positive sequence
Step 6: when the logical sequence of data frame to be encoded is CRC check part, byte counter adds 1, according to CRC
The data order of check code, CRC check code is exported.
Wherein, according to the data order of CRC check code, CRC check code is exported, can be included：
If the data order of CRC check code is inverted order, the CRC check code is first from low bit output；If CRC check code
Data order be positive sequence, then CRC check code is first from higher bit output.
Embodiment：
Fig. 3 is a kind of flow chart of cardiopulmonary bypass in beating heart redundancy CRC check method based on FPGA in the embodiment of the present invention.Ginseng
Fig. 3 is examined, the present embodiment proposes a kind of cardiopulmonary bypass in beating heart redundancy CRC check method based on FPGA, and implementation steps are as follows：
Require to complete the AOS of data to be transferred according to data transfer established forms such as satellite remote control, remote measurement, exterior measuring sum biographies
(Advanced Orbiting Systems) framing, whole frame frame length byte number is designated as Na (512 byte), wherein participating in the valid data word of CRC codings
Section length is designated as Nb (506 byte), and (each byte higher bit is designated as m8, low bit be designated as m1), CRC check code length is designated as Nk (2
Byte)；
Confirm the CRC algorithm demand (present context model takes such as TURE patterns) of background model, CRC pattern clear and definite first
It is positive sequence (m to input and output data sequence requirement (being designated as order)8First participate in coding) or inverted order (m1First participate in coding)；
If positive sequence (order=1), on the basis of data positive sequence, further clear and definite CRC pattern is at the beginning of the shift register of checking algorithm
Beginning phase requirements (are designated as Crc_Ini), when it is complete " 0 " to require initial phase, Crc_Ini=0x0000, when requiring initial phase
When complete " 1 " is in position, Crc_Ini=0xFFFF；If inverted order (order=0), on the basis of data inverted order, clear and definite CRC is equally needed
Pattern requires (being designated as Crc_Ini) to the shift register initial phase of checking algorithm, when it is complete " 0 " to require initial phase,
Crc_Ini=0x0000, when it is complete " 1 " to require initial phase, Crc_Ini=0xFFFF；
In each data frame CRC check calculating process, decision logic sequential is needed to include 3 parts, frame alignment word (is designated as
Head=1), data to be encoded (being designated as Check=1) and CRC check code (being designated as Check=0), byte sequential length are right respectively
Answer Na-Nb-Nk (4 byte), Nb and Nk；
When the current sequential of data to be encoded frame is frame alignment word part (0x1ACFFC1D), then byte counter Count
=Count+1, input byte is directly assigned to output byte, while shift register is accordingly initialized (0x0000)；
When the current sequential of data to be encoded frame is data to be encoded part, then byte counter Count=Count+1,
Input byte is directly assigned to output byte, and word has been inputted while directly being calculated according to cyclic redundancy CRC check parallel computation formula
Section correspondence CRC check code；
When the current sequential of data to be encoded frame is CRC check code part, then byte counter Count=Count+1, root
According to the data order of CRC check code, CRC check code is exported, the height of CRC check code is needed if inverted order (order=0)
Bit is exchanged, i.e., first export (Crc_Ini (0)) from low bit；Otherwise, the higher bit first from CRC check code exports (Crc_Ini
(15), background model).
Emphasis of the present invention is to inquire into that a kind of algorithm is simple, resource occupation is low, time delay is small CRC is parallel
Computational methods, it is clear based on serial data CRC check algorithm to solve to meet background model mission requirements, but logical relation
It is excessively loaded down with trivial details and tediously long, and program timing sequence is difficult to control and too many based on byte Memory look-up tables'implementation processes some linkses,
And Block RAM resource consumptions it is big the problem of.Show by the test of unit, system and whole star, apply after the inventive method, it is full
Logic simplifying that foot is encoded to CRC, efficiency improve and resource reduction technical need, effectively ensured that TTC channel is reliable
Set up and data transfer demands.
The present invention follows the given CRC algorithm of CRC-CCITT codings, and cardiopulmonary bypass in beating heart redundancy is realized using simple XOR
CRC check code is calculated, and is solved the logic flaw of the multiple parallel-serial conversion based on bit serial, is breached based on look-up table
The high engineering bottleneck of BlockRAM resources occupation rates, improves the data throughout of CRC check, while reducing to hardware resource
Challenging needs, so as to reach simplified logic, improve efficiency and reduce the purpose of resource.The present invention has adapted to rear class and has been based on byte
Channel coding cascades demand, simplifies and realizes processing procedure, about 8 times of modular system working frequency is improved, in all satellites
Had broad application prospects in terms of realizing the reliability transmissions such as remote control, remote measurement, exterior measuring sum biography.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art it is various it is obvious change,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although the present invention is carried out by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
Other more equivalent embodiments can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (6)
1. a kind of cardiopulmonary bypass in beating heart redundancy CRC check method based on FPGA, it is characterised in that comprise the following steps：
Step 1: the data transfer passed according to satellite remote control, remote measurement, exterior measuring or number sets call format framing, data frame is formed；
Step 2: confirming different CRC patterns to inputting the sequence requirement with output data, initial phase requirement and exporting
As a result whether the requirement with 0xFFFF XORs；
Step 3: the initial phase of different CRC patterns is set, when CRC pattern is XMODEN patterns or TURE patterns, by institute
State initial phase and be set to " 0000 ", when CRC pattern is FALSE patterns or X25 patterns, the initial phase is set to
“FFFF”；
Step 4: when the logical sequence of data frame to be encoded is frame alignment word part, byte counter adds 1, and input byte is straight
Connect and be assigned to output byte, while shift register is accordingly initialized；
Step 5: when the logical sequence of data frame to be encoded is data to be encoded part, byte counter adds 1, inputs byte
Output byte directly is assigned to, while it is corresponding to have inputted byte according to the directly calculating of cyclic redundancy CRC check parallel computation formula
CRC check code；
Step 6: when the logical sequence of data frame to be encoded is CRC check part, byte counter adds 1, according to CRC check
The data order of code, CRC check code is exported.
2. according to the method described in claim 1, it is characterised in that the frame length of the data frame is Na, wherein participating in CRC codings
Effective byte length be Nb, CRC check code byte length be Nk；The logical sequence of the data frame includes frame alignment word portion
Point, data to be encoded part and CRC check part；The sequential length of the frame alignment word part is Na-Nb-Nk, described to treat
The sequential length of encoded data portion is Nb, and the sequential length of the CRC check part is Nk.
3. according to the method described in claim 1, it is characterised in that the output result whether the requirement with 0xFFFF XORs,
Including：
When the specific CRC pattern is X25 patterns, the CRC calculated using the cyclic redundancy CRC check parallel computation formula
Check code requirement carries out XOR with 0xFFFF.
4. according to the method described in claim 1, it is characterised in that the cyclic redundancy CRC check parallel computation is based on CRC-
Ccitt standard.
5. method according to claim 4, it is characterised in that the cyclic redundancy CRC check parallel computation formula is：When
The CRC check code of preceding byte is equal to previous byte CRC register values and the logic XOR of each information bit of current byte；
When the specific CRC pattern is inverted order to inputting with the sequence requirement of output data,
In formula group (1), ri 8, i=0,2 ... 15 represent the CRC schools that i-th of shift register is inputted after 1 8bite byte
Test position；Represent the jth position of previous byte CRC check code；mk, k=1,2 ... 8 represent the kth of current byte
Individual bit；
When the specific CRC pattern is positive sequence to inputting with the sequence requirement of output data,
In formula group (2), ri 8, i=0,2 ... 15 represent the CRC schools that i-th of shift register is inputted after 1 8bite byte
Test position；Represent the jth position of previous byte CRC check code；mk, k=1,2 ... 8 represent the kth of current byte
Individual bit.
6. according to the method described in claim 1, it is characterised in that according to the data order of CRC check code, by the CRC schools
Code output is tested, including：
If the data order of CRC check code is inverted order, the CRC check code is first from low bit output；If the number of CRC check code
It is positive sequence according to order, then the CRC check code is first from higher bit output.
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| CN107733568A (en) * | 2017-09-22 | 2018-02-23 | 烽火通信科技股份有限公司 | The method and device of CRC parallel computations is realized based on FPGA |
| CN107733568B (en) * | 2017-09-22 | 2020-05-12 | 烽火通信科技股份有限公司 | Method and device for realizing CRC parallel computation based on FPGA |
| CN107704335A (en) * | 2017-09-28 | 2018-02-16 | 华南理工大学 | A kind of CRC concurrent operation IP kernels based on FPGA |
| CN107704335B (en) * | 2017-09-28 | 2019-08-20 | 华南理工大学 | A kind of CRC concurrent operation IP kernel based on FPGA |
| CN109936376A (en) * | 2019-01-31 | 2019-06-25 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method of byte-oriented operation cyclic code CRC16-CCITT verification |
| CN110726809A (en) * | 2019-10-19 | 2020-01-24 | 北京工业大学 | Design method of high-reliability combustible gas state monitoring and alarming equipment |
| CN111130695A (en) * | 2019-12-10 | 2020-05-08 | 卡斯柯信号有限公司 | Method for calculating CANOPEN protocol CRC through redundant code words |
| CN111082810A (en) * | 2020-01-07 | 2020-04-28 | 西安电子科技大学 | FPGA-based low-overhead parallel cyclic redundancy check method and application |
| CN111082810B (en) * | 2020-01-07 | 2023-03-31 | 西安电子科技大学 | FPGA-based low-overhead parallel cyclic redundancy check method and application |
| CN114866195A (en) * | 2022-07-07 | 2022-08-05 | 深圳市江元科技(集团)有限公司 | Method for controlling thermal printer by using android system |
| CN115987460A (en) * | 2023-03-21 | 2023-04-18 | 深圳华锐分布式技术股份有限公司 | Data transmission method, device, equipment and medium based on check code |
| CN116861493A (en) * | 2023-08-31 | 2023-10-10 | 上海芯联芯智能科技有限公司 | Verification code generation method, processor and electronic equipment |
| CN116861493B (en) * | 2023-08-31 | 2024-03-29 | 上海芯联芯智能科技有限公司 | Verification code generation method, processor and electronic equipment |
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