CN107154836B - Parallel Cyclic Redundancy Check (CRC) method based on Field Programmable Gate Array (FPGA) - Google Patents
Parallel Cyclic Redundancy Check (CRC) method based on Field Programmable Gate Array (FPGA) Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/091—Parallel or block-wise CRC computation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/18578—Satellite systems for providing broadband data service to individual earth stations
- H04B7/18586—Arrangements for data transporting, e.g. for an end to end data transport or check
Abstract
The invention discloses a parallel Cyclic Redundancy Check (CRC) method based on Field Programmable Gate Array (FPGA). The method follows a CRC-CCITT coding given CRC algorithm, realizes parallel cyclic redundancy CRC code calculation by using simple XOR logic, solves the logic defect of multiple parallel-serial conversion based on bit serial, breaks through the engineering bottleneck of high resource occupancy rate of a Block RAM based on a lookup table, improves the data throughput of CRC, and simultaneously reduces the harsh requirement on hardware resources, thereby realizing the purposes of simplifying logic, improving efficiency and reducing resources.
Description
Technical Field
The invention relates to satellite measurement and control and communication technology, in particular to a parallel Cyclic Redundancy Check (CRC) method based on Field Programmable Gate Array (FPGA).
Background
When data frames of satellite remote control, remote measurement, outside and data transmission are transmitted, CRC is adopted to check the correctness of link transmission, so that the aims of data error correction and error detection are achieved, and the occurrence of wrong logic judgment is prevented.
The cyclic redundancy CRC checks are attached to the cyclic codes of the groups, and the basic idea is as follows: the transmitting end adds some redundant parity code elements in the transmitted information code element sequence, these parity code and information code form a certain relation according to the coding rule, the receiving end finds or corrects the error code which may be generated by checking this specific relation.
The CRC code is a check code (CRC code) r bit generated by a certain rule at the transmitting end according to the K bit binary code sequence to be transmitted by utilizing the linear coding theory, and attached to the back of information to form a new binary code sequence, wherein the number of the bits is (K + r), and finally the new binary code sequence is transmitted. At the receiving end, checking is performed according to the rule followed between the information code and the CRC code to determine the error performance and the confidence coefficient in the data transmission.
The traditional cyclic redundancy CRC (cyclic redundancy check) technology mainly refers to a serial bit check algorithm and a byte lookup table check algorithm 2.
Based on a serial bit check code algorithm, the CRC-CCITT given algorithm is strictly followed, and based on a Memory lookup table algorithm, the CRC check codes of the data frames can be obtained simply and visually, but the algorithms have the following defects:
(1) the CRC algorithm based on bit serial is characterized by multiple parallel-serial conversion, large system delay, complex time sequence alignment, more occupied hardware resources and difficulty in breaking through the bottleneck of processing speed;
(2) the byte type lookup table algorithm based on Memory resources is characterized in that complex shift and XOR logic operation delivery is completed by a matlab program, hardware resources of Slices and LUTs adopted in the algorithm are relatively not reduced, and 96 Block RAM Block resources of devices occupy 1;
(3) for different modes in the CRC-CCITT protocol, details such as whether register initial phases and high and low bytes are in reverse order or not in the process of look-up table generation and byte calling based on Memory resources are not clarified, and no constraint condition of specific application is given.
With the improvement of the transmission information rate, the CRC check calculation method based on bit serial or Memory lookup tables cannot meet the technical requirements of low resource occupancy rate, high system working clock, small calculation result delay and the like.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the parallel cyclic redundancy CRC check method based on the FPGA is provided, the parallel cyclic redundancy CRC check code calculation is realized by utilizing simple XOR logic, and the requirements of satellites on high efficiency, accuracy and rapidness of CRC check calculation are met to the greatest extent.
The technical solution of the invention is as follows:
a parallel cyclic redundancy CRC (cyclic redundancy check) method based on an FPGA (field programmable gate array) comprises the following steps of:
step one, framing according to the data transmission set format requirements of satellite remote control, remote measurement, external measurement or data transmission to form a data frame;
step two, confirming the sequence requirements and the initial phase requirements of different CRC modes on input and output data and the requirements whether the output result is XOR with 0xFFFF or not;
setting initial phases of different CRC modes, setting the initial phases to be 0000 when the CRC mode is an XMODEN mode or a TURE mode, and setting the initial phases to be FFFF when the CRC mode is a FALSE mode or an X25 mode;
step four, when the logic time sequence of the data frame to be coded is a frame synchronous word part, adding 1 to a byte counter, directly assigning input bytes to output bytes, and correspondingly initializing a shift register;
step five, when the logic time sequence of the data frame to be coded is the data part to be coded, adding 1 to a byte counter, directly assigning input bytes to output bytes, and simultaneously directly calculating CRC check codes corresponding to the input bytes according to a cyclic redundancy CRC check parallel calculation formula;
and step six, when the logic time sequence of the data frame to be coded is a CRC check part, adding 1 to a byte counter, and outputting the CRC check code according to the data sequence of the CRC check code.
Further, the frame length of the data frame is Na, wherein the effective byte length participating in CRC coding is Nb, and the byte length of the CRC check code is Nk; the logic time sequence of the data frame comprises a frame synchronization word part, a data part to be coded and a CRC (cyclic redundancy check) part; the time sequence length of the frame synchronization word part is Na-Nb-Nk, the time sequence length of the data part to be coded is Nb, and the time sequence length of the CRC part is Nk.
Further, the requirement of whether the output result is XOR-ed with 0xFFFF includes:
and when the specific CRC mode is an X25 mode, performing exclusive OR operation on the CRC check code calculated by the cyclic redundancy CRC parallel calculation formula and 0 xFFFF.
Further, the cyclic redundancy CRC check parallel computation is based on the CRC-CCITT standard.
Further, the cyclic redundancy CRC check parallel calculation formula is: the CRC check code of the current byte is equal to the logical XOR of the CRC register value of the previous byte and each information bit of the current byte;
when the specific CRC pattern requires the order of input and output data to be in reverse order,
in the formula set (1), the formula is shown in the specification,the CRC check bit after 1 byte of 8 bits is input into the ith shift register is shown;bit j representing the CRC check code of the previous byte; m iskK 1, 2.. 8 denotes the kth bit of the current byte;
when the particular CRC pattern requires positive order for the order of the input and output data,
in the formula set (2), the formula is shown in the specification,the CRC check bit after 1 byte of 8 bits is input into the ith shift register is shown;bit j representing the CRC check code of the previous byte; m iskAnd k is 1, 2.. 8 denotes the kth bit of the current byte.
Further, outputting the CRC check code according to a data order of the CRC check code, including:
if the data sequence of the CRC check code is the reverse sequence, the CRC check code is output from low bits firstly; if the data sequence of the CRC check code is positive sequence, the CRC check code is output from high bits firstly.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a parallel cyclic redundancy CRC (cyclic redundancy check) method based on an FPGA (field programmable gate array), which follows a CRC-CCITT (cyclic redundancy check) algorithm and utilizes simple XOR (exclusive OR) logic to realize parallel cyclic redundancy CRC code calculation, solves the logic defect of multiple parallel-serial conversion based on bit serial, breaks through the engineering bottleneck of high resource occupancy rate of a Block RAM (random access memory) based on a lookup table, improves the data throughput of CRC, and simultaneously reduces the harsh requirement on hardware resources, thereby realizing the purposes of simplifying logic, improving efficiency and reducing resources.
Drawings
FIG. 1 is a flow chart of a parallel Cyclic Redundancy Check (CRC) method based on FPGA according to the present invention;
FIG. 2 is a schematic diagram of the CRC-CCITT encoding principle involved in the present invention;
fig. 3 is a flowchart of a parallel cyclic redundancy check method based on an FPGA in an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a flowchart of a parallel cyclic redundancy check method based on an FPGA according to the present invention. Referring to fig. 1, the parallel cyclic redundancy CRC checking method based on an FPGA provided in the present invention may specifically include the following steps:
step one, framing according to the data transmission set format requirements of satellite remote control, remote measurement, external measurement or data transmission to form a data frame.
The data frame is formed according to the data transmission setting format requirements of satellite remote control, remote measurement, external measurement or data transmission so as to form the data frame of the data to be transmitted. The frame length of the data frame is Na, the effective byte length participating in CRC coding is Nb, and the byte length of the CRC check code is Nk; the logic time sequence of the data frame comprises a frame synchronization word part, a data part to be coded and a CRC (cyclic redundancy check) part; the time sequence length of the frame synchronization word part is Na-Nb-Nk, the time sequence length of the data part to be coded is Nb, and the time sequence length of the CRC part is Nk.
And step two, confirming the sequence requirements, the initial phase requirements and the requirements of the different CRC modes on the input and output data and whether the output result is XOR-ed with 0 xFFFF.
The sequence requirement, the initial phase requirement and the requirement whether the output result is XOR with 0xFFFF of the CRC mode on the input and output data are the requirements of the CRC algorithm of the background model; the requirement of whether the output result is XOR-ed with 0xFFFF comprises:
and when the specific CRC mode is an X25 mode, performing exclusive OR operation on the CRC check code calculated by the cyclic redundancy CRC parallel calculation formula and 0 xFFFF. That is, when the specific CRC pattern is the X25 pattern, the CRC check code calculated by the CRC parallel calculation formula needs to be xor-ed with 0xFFFF before being output as the final CRC check code.
And step three, setting initial phases of different CRC modes, setting the initial phases to be '0000' when the CRC mode is the XMODEN mode or the TURE mode, and setting the initial phases to be 'FFFF' when the CRC mode is the FALSE mode or the X25 mode.
And step four, when the logic time sequence of the data frame to be coded is a frame synchronous word part, adding 1 to a byte counter, directly assigning input bytes to output bytes, and correspondingly initializing a shift register.
And step five, when the logic time sequence of the data frame to be coded is the data part to be coded, adding 1 to a byte counter, directly assigning input bytes to output bytes, and simultaneously, directly calculating the CRC check code corresponding to the input bytes according to a cyclic redundancy CRC check parallel calculation formula.
Wherein the cyclic redundancy CRC check parallel computation is based on the CRC-CCITT standard. The invention uses CRC-CCITT as standard to carry out coding and decoding design and simulation of parallel CRC check, and fig. 2 is a schematic diagram of the CRC-CCITT coding principle of the invention. Referring to fig. 2, for CRC-CCITT encoding, the generator polynomial is g (x) x16+x12+x5+1, the corresponding feedback coefficient is 0x1021, when the data to be transmitted is coded, the A/B switch is closed, and the C switch is opened; lifting deviceAnd when the CRC check code is taken, the A/B switch is switched off, and the C switch is switched on.
According to different CRC check modes required by background models, 4 important links such as shift register initial phase, 8-bit data bit sequence input, 16-bit check code bit sequence output and whether the check code needs to be XOR-ed with 0xFFFF or not are focused when the check code of a data frame is calculated, and as shown in Table 1, the CRC-CCITT common standards related to the invention are provided.
TABLE 1CRC-CCITT commonly used several criteria
The core thought of the cyclic redundancy check parallel computation is as follows:
since the CRC remainder generated when the 8-bit information code is simultaneously input to the parallel operation circuit is the same as the CRC remainder generated when the 8-bit information code is input to the serial circuit bit by bit, it can be considered that the two circuits of the parallel calculation circuit and the serial calculation circuit are equivalent, and thus the logical relationship of the parallel calculation is derived from the changes of the registers and the input information bits in the serial operation circuit.
Optionally, the cyclic redundancy CRC check parallel calculation formula is: the CRC check code of the current byte is equal to the logical XOR of the CRC register value of the previous byte and each information bit of the current byte;
when the specific CRC pattern requires the order of the input and output data to be the reverse order, such as the tune pattern and the X25 pattern, the CRC check calculation formula is:
in the formula set (1), the formula is shown in the specification,the CRC check bit after 1 byte of 8 bits is input into the ith shift register is shown;bit j representing the CRC check code of the previous byte; m iskAnd k is 1, 2.. 8 denotes the kth bit of the current byte. The above formula (1) can also be expressed as table 2.
TABLE 2 CRC parallel calculation formula for reverse order of input and output data
When the sequence requirement of the specific CRC mode on the input and output data is positive, such as XMODEN mode and FALSE mode, the CRC check parallel calculation formula is:
in the formula set (2), the formula is shown in the specification,the CRC check bit after 1 byte of 8 bits is input into the ith shift register is shown;bit j representing the CRC check code of the previous byte; m iskAnd k is 1, 2.. 8 denotes the kth bit of the current byte. The above formula (2) can also be expressed as table 3.
TABLE 3 CRC parallel calculation formula for positive sequence of input and output data
And step six, when the logic time sequence of the data frame to be coded is a CRC check part, adding 1 to a byte counter, and outputting the CRC check code according to the data sequence of the CRC check code.
The outputting the CRC check code according to the data sequence of the CRC check code may include:
if the data sequence of the CRC check code is the reverse sequence, the CRC check code is output from low bits firstly; if the data sequence of the CRC check code is positive sequence, the CRC check code is output from high bits firstly.
Example (b):
fig. 3 is a flowchart of a parallel cyclic redundancy check method based on an FPGA in an embodiment of the present invention. Referring to fig. 3, the embodiment provides a parallel cyclic redundancy check method based on an FPGA, which includes the following steps:
completing the framing of AOS (advanced on-orbit System) of data to be transmitted according to the established format requirements of data transmission such as satellite remote control, remote measurement, external measurement and data transmission, wherein the length byte number of the frame of the whole frame is recorded as Na (512 bytes), the length of the effective data byte participating in CRC encoding is recorded as Nb (506 bytes) (the high bit of each byte is recorded as m8And a low bit is represented as m1) The CRC length is recorded as Nk (2 bytes);
to identify the CRC algorithm requirement for the background model (this background model assumes, for example, a TURE mode), it is first clear that the CRC mode requires (in order) that the input and output data sequence be positive (m)8First participating in encoding) or in reverse order (m)1First participate in encoding); if the order is 1, on the basis of the data positive sequence, further explicitly determining that the CRC mode requires the initial phase of the shift register of the check algorithm (recorded as Crc _ Ini), when the required initial phase is all "0", Crc _ Ini is 0x0000, and when the required initial phase is all "1", Crc _ Ini is 0 xFFFF; if the order is reversed (order is 0), on the basis of data reverse order, the requirement (marked as Crc _ Ini) of the CRC mode on the initial phase of the shift register of the check algorithm needs to be clarified, when the required initial phase is all "0", Crc _ Ini is 0x0000, and when the required initial phase is all "1", Crc _ Ini is 0 xFFFF;
in the CRC Check calculation process of each data frame, the logical timing to be determined includes 3 parts, a frame synchronization word (denoted as Head ═ 1), data to be encoded (denoted as Check ═ 1), and a CRC Check code (denoted as Check ═ 0), and the byte timing lengths respectively correspond to Na-Nb-Nk (4 bytes), Nb, and Nk;
when the current timing of the data frame to be encoded is the frame sync word portion (0x1ACFFC1D), the byte counter Count is Count +1, the input byte is directly assigned to the output byte, and the shift register is initialized accordingly (0x 0000);
when the current time sequence of the data frame to be coded is the data part to be coded, the byte counter Count is equal to Count +1, the input byte is directly assigned to the output byte, and meanwhile, the CRC check code corresponding to the input byte is directly calculated according to a cyclic redundancy CRC check parallel calculation formula;
when the current time sequence of the data frame to be coded is a CRC (cyclic redundancy check) code part, outputting the CRC code according to the data sequence of the CRC code, and if the order is 0, exchanging the high bit and the low bit of the CRC code, namely outputting the low bit (Crc _ Ini (0)); otherwise, the high bit of the CRC check code is output first (Crc _ Ini (15), background model).
The invention focuses on discussing a cyclic redundancy check parallel computing method which is simple in algorithm, low in resource occupation and small in time delay, so as to meet the requirements of background model tasks and solve the problems that a serial bit CRC (cyclic redundancy check) based check algorithm is clear, but the logic relation is too complicated and long, the programming time sequence is difficult to control, the realization process based on a byte Memory lookup table is too many in attention links, and the consumption of Block RAM resources is large. The single machine, system and whole satellite tests show that the method meets the technical requirements of simplifying the logic of CRC coding, improving the efficiency and reducing the resources, and effectively ensures the reliable establishment of the measurement and control link and the data transmission requirement.
The invention follows the CRC-CCITT coding given CRC algorithm, realizes the calculation of the parallel cyclic redundancy CRC code by utilizing simple XOR logic, solves the logic defect of multiple parallel-serial conversion based on bit serial, breaks through the engineering bottleneck of high resource occupancy rate of Block RAM based on a lookup table, improves the data throughput of CRC, and simultaneously reduces the harsh requirement on hardware resources, thereby achieving the purposes of simplifying logic, improving efficiency and reducing resources. The invention meets the requirement of the later-stage byte-based channel coding cascade, simplifies the implementation process, improves the working frequency of a module system by about 8 times, and has wide application prospect in the aspects of realizing the reliable transmission of remote control, remote measurement, external measurement, data transmission and the like of all satellites.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (1)
1. A parallel cyclic redundancy CRC (cyclic redundancy check) method based on an FPGA (field programmable gate array) is characterized by comprising the following steps of:
step one, framing according to the data transmission setting format requirements of satellite remote control, remote measurement, external measurement or data transmission to form a data frame, wherein:
the frame length of the data frame is Na, the effective byte length participating in CRC coding is Nb, and the byte length of the CRC check code is Nk; the logic time sequence of the data frame comprises a frame synchronization word part, a data part to be coded and a CRC (cyclic redundancy check) part; the time sequence length of the frame synchronization word part is Na-Nb-Nk, the time sequence length of the data part to be coded is Nb, and the time sequence length of the CRC part is Nk;
step two, confirming the sequence requirement and the initial phase requirement of different CRC modes on input and output data and the requirement whether an output result is XOR with 0xFFFF, wherein:
the requirement of whether the output result is XOR-ed with 0xFFFF comprises:
when the specific CRC mode is an X25 mode, performing exclusive OR operation on the CRC check code requirement calculated by the cyclic redundancy CRC parallel calculation formula and 0 xFFFF;
the cyclic redundancy CRC check parallel calculation is based on a CRC-CCITT standard, and the cyclic redundancy CRC check parallel calculation formula specifically comprises: the CRC check code of the current byte is equal to the logical XOR of the CRC register value of the previous byte and each information bit of the current byte;
when the specific CRC pattern requires the order of input and output data to be in reverse order,
in the formula set (1), the formula is shown in the specification,the CRC check bit after 1 byte of 8 bits is input into the ith shift register is shown;bit j representing the CRC check code of the previous byte; m iskK 1, 2.. 8 denotes the kth bit of the current byte;
when the particular CRC pattern requires positive order for the order of the input and output data,
in the formula set (2), the formula is shown in the specification,the CRC check bit after 1 byte of 8 bits is input into the ith shift register is shown;bit j representing the CRC check code of the previous byte; m iskK 1, 2.. 8 denotes the kth bit of the current byte;
setting initial phases of different CRC modes, setting the initial phases to be 0000 when the CRC mode is an XMODEN mode or a TURE mode, and setting the initial phases to be FFFF when the CRC mode is a FALSE mode or an X25 mode;
step four, when the logic time sequence of the data frame to be coded is a frame synchronous word part, adding 1 to a byte counter, directly assigning input bytes to output bytes, and correspondingly initializing a shift register;
step five, when the logic time sequence of the data frame to be coded is the data part to be coded, adding 1 to a byte counter, directly assigning input bytes to output bytes, and simultaneously directly calculating CRC check codes corresponding to the input bytes according to a cyclic redundancy CRC check parallel calculation formula;
step six, when the logic time sequence of the data frame to be coded is a CRC check part, adding 1 to a byte counter, and outputting the CRC check code according to the data sequence of the CRC check code, wherein:
outputting the CRC check code according to the data sequence of the CRC check code, comprising:
if the data sequence of the CRC check code is the reverse sequence, the CRC check code is output from low bits firstly; if the data sequence of the CRC check code is positive sequence, the CRC check code is output from high bits firstly.
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