CN117914444A - Hardware implementation method and device for CRC calculation of IB network data packet - Google Patents
Hardware implementation method and device for CRC calculation of IB network data packet Download PDFInfo
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Abstract
The invention provides a hardware implementation method and a device for calculating CRC of an IB network data packet, wherein the method comprises the following steps: acquiring a packet header field of an IB network data packet, and analyzing packet length information in the packet header field; filling bits into the IB network data packet according to the packet length information of the data packet, so that the packet length of the filled data packet in each clock period is equal to the single-period data bit width; and performing CRC check calculation on the IB network data packet after bit filling. The technical scheme of the invention can calculate CRC check codes of data packets with different lengths only by instantiating a set of CRC calculation circuit by on-chip hardware.
Description
Technical Field
The invention belongs to the field of network data verification, and particularly relates to a hardware implementation method and device for computing CRC of an IB network data packet.
Background
In high-speed data switching networks, the InfiniBand (IB) protocol occupies a high share in computing systems with the advantages of high bandwidth, low latency, etc. To discover bad packets in a high-speed communication network as early as possible, and to ensure the integrity and reliability of the data packets, the IB protocol uses two Cyclic Redundancy Check (CRC) algorithms to check and check the data packets, known as fixed CRC (ICRC) and variable CRC (VCRC), respectively.
The ICRC corresponds to a CRC32 algorithm, the polynomial is 0x04C11DB7, the initial value is 0 xFFFFFFFFFF, and the field of the message, which is unchanged across subnets, is covered. VCRC corresponds to a CRC16 algorithm, the polynomial is 0x100B, the initial value is 0xFFFF, and all fields and ICRC fields of the message are covered. Both the ICRC field and VCRC field of the IB network packet are located at the end of the packet, and the format of the packet is shown in fig. 1.
The packet length of the IB network data packet is not fixed, the range of the packet length supported by the protocol is 6 DW-1055 DW (Double Word), and the gradient is 1DW. In the network communication chip, the data width of transmission and reception per clock cycle is fixed. When performing CRC check on the streaming data packet, the traditional hardware implementation method needs to instantiate CRC hardware calculation modules with different data widths according to the length variation range of the data packet, so as to realize CRC calculation and check of the data packets with different lengths.
Taking the chip transmission data bit width of 32DW as an example, for IB CRC32 check, the conventional hardware method is shown in fig. 2. When the CRC32 calculation of the pipelined packet is performed, if the received packet is a short packet with a single clock cycle, different CRC32 hardware circuits are selected according to the packet length, and the CRC32 check code of the packet can be obtained with a single clock cycle. If the received packet is a long packet spanning multiple clock cycles, a 32DW CRC32 hardware circuit is used in the packet header and in the middle of the packet, and a different CRC32 hardware circuit is selected in the end of the packet clock cycle based on the remaining packet length, so that the CRC32 check code of the packet is obtained in the end of the packet clock cycle. The short packet and the long packet require a plurality of CRC32 calculation unit circuits of which the on-chip hardware-exemplified data bit widths are 1DW to 32DW, respectively, each CRC32 calculation unit circuit including a large number of logic gate units.
The IB CRC16 conventional hardware approach is similar to the CRC32 conventional hardware approach, and also requires CRC hardware circuitry that instantiates different data bit widths.
Because the hardware in the chip needs to instantiate the hardware calculation circuits of CRC32 and CRC16 with different data bit widths when the traditional CRC calculation method processes the pipelined IB data, a large number of logic gate units are introduced to occupy a large amount of on-chip hardware expenditure, so that a large amount of physical area is occupied when the chip is realized at the rear end of the chip, congestion and time sequence problems are extremely easy to introduce, the realization difficulty is high, and the development period of the chip and the improvement of the product performance are greatly influenced.
Disclosure of Invention
The invention aims to provide a hardware implementation method and a hardware implementation device for calculating CRC of an IB network data packet, which aim to calculate CRC check codes of data packets with different lengths by only instantiating a set of calculation circuit modules of CRC32 or CRC 16.
According to a first aspect of the present invention, there is provided a hardware implementation method for calculating a CRC of an IB network packet, including:
acquiring a packet header field of an IB network data packet, and analyzing packet length information in the packet header field;
filling bits into the IB network data packet according to the packet length information of the data packet, so that the packet length of the filled data packet in each clock period is equal to the single-period data bit width;
And performing CRC check calculation on the IB network data packet after bit filling.
Preferably, the CRC check is calculated as a CRC32 check, and the supplementing bits to the IB network data packet according to packet length information of the data packet further includes:
When the single-period data bit width is 32 double words, for a data packet with a single clock period, supplementing x 32' h9D0AD96D bits in the front of a packet head, and splicing the data packet into 32 double words, wherein:
x＝32-(pktlen-1)，
pktlen is the packet length of the data packet.
Preferably, for a packet spanning multiple clock cycles, x 32' h9d0 d96d are appended in front of the header, the first clock cycle data is concatenated into 32 doublewords, starting from the first clock cycle, the remaining x doublewords of the current clock cycle data are concatenated with the next clock cycle front part data into 32 doublewords, until all clock cycles are concatenated into 32 doublewords, wherein:
x＝32-(pktlen-1)％32。
Preferably, the CRC check is calculated as a CRC16 check, and the supplementing bits to the IB network data packet according to packet length information of the data packet further includes:
When the single-period data bit width is 32 double words, for a data packet with a single clock period, y 32' h 719987198 are complemented at the front part of the packet head, and the data packet is spliced into 32 double words, wherein:
y＝32-pktlen，
pktlen is the packet length of the data packet.
Preferably, for a packet spanning multiple clock cycles, y 32' h 719987198 are appended in front of the header, the first clock cycle data is concatenated into 32 doublewords, starting from the first clock cycle, the remaining y doublewords of data for the current clock cycle are concatenated with the next clock cycle front part data into 32 doublewords, until all clock cycles are concatenated into 32 doublewords, where:
y＝32-pktlen％32。
According to a second aspect of the present invention, there is provided a circuit for implementing a IB network packet CRC calculation, comprising:
The packet analysis unit is used for acquiring the packet header field of the IB network data packet and analyzing the packet length information in the packet header field;
The bit filling unit is used for filling bits into the IB network data packet according to the packet length information of the data packet so that the packet length of the data packet after bit filling in each clock period is equal to the single-period data bit width;
and the checking unit is used for performing CRC check calculation on the IB network data packet after bit filling.
Compared with the prior art, the technical scheme of the invention has the following advantages:
The hardware implementation scheme of the CRC calculation of the IB network data packet is more suitable for a direct-through data forwarding mode, the CRC check result can be kept consistent with the data flow time sequence, the hardware implementation scheme is also suitable for a data storage forwarding mode, and the design scheme can be simplified; for the transmission of the IB network data packet with the single-port high data bit width, only one set of CRC calculation circuit is needed in the chip, the difference of packet lengths of the IB network data packet is compatible, the chip is more friendly to physical realization, the CRC hardware circuit resources in the chip are reduced, and the risks of winding congestion, timing sequence convergence and the like of the design of the rear end of the chip are reduced. In addition, the method has lower power consumption and is beneficial to the improvement of the performance of chip products.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure and process particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of an IB packet according to the prior art.
Fig. 2 is a flow chart of a method of IB network packet CRC calculation in accordance with the prior art.
Fig. 3 is a schematic diagram of CRC polynomial computation using CRC complement data.
Fig. 4 is a general flow chart of a hardware implementation method of IB network packet CRC calculation in accordance with the present invention.
Fig. 5 is a flow chart of a method of calculating a CRC32 for an IB network packet having a single cycle data bit width of 32DW, in accordance with the present invention.
Fig. 6 is a schematic diagram of an IB network packet before and after bit-filling, for example, a single cycle data bit-width of 32DW, according to the invention.
Fig. 7 is a flow chart of a method of calculating a CRC16 for an IB network packet having a single cycle data bit width of 32DW, in accordance with the present invention.
Fig. 8 is a schematic diagram of IB network packets before and after bit-filling, for example, a single cycle data bit-width of 32DW, according to the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, reference will be made to the accompanying drawings in which embodiments of the present invention are illustrated, the technical solutions in the embodiments of the present invention are clearly and completely described, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which are derived by a person skilled in the art from the embodiments according to the invention without creative efforts, fall within the protection scope of the invention.
The main problem of high bit width IB network packets for CRC checking is that on-chip CRC checking circuits of various bit widths need to be instantiated according to the variation of the data bit width. Based on the analysis, the invention provides a hardware implementation method and a device for calculating CRC of an IB network data packet, which are used for carrying out the complementary bit calculation of CRC32 or CRC16 on the IB network data packet, and can calculate CRC check codes of data packets with different lengths only by using on-chip hardware to instantiate a set of calculation circuit modules of CRC32 or CRC 16.
After the CRC bit-filling data is calculated by the CRC polynomial, if the xor value is the same as the initial value, the bit-filling data does not affect the final CRC result according to the CRC algorithm, as shown in fig. 3. Complementary data 32'h9d0ad96d corresponding to the IB network packet CRC32 and complementary data 32' h 719987198 corresponding to the CRC 16. And (3) supplementing the data packet by using bit supplementing data, splicing the data of each clock period into a fixed length (maximum single-period data bit width), and only needing to instantiate a set of single-period maximum data bit width CRC32 or CRC16 calculation circuit module in a chip to realize calculation check of the CRC32 or CRC16 of the data packets of different IB networks. Specifically, the invention checks CRC32 or CRC16 of IB network data packet, supplements bits of the data packet according to the packet length and single period data bit width of the data packet, and calculates CRC.
Referring to the flowchart of fig. 4, the hardware implementation method for calculating the CRC of the IB network packet according to the present invention includes:
Step 101: and acquiring a packet header field of the IB network data packet, and analyzing packet length information in the packet header field.
In the following, a single-cycle data bit width of 32DW is taken as an example, and the processing flow of the IB network packet CRC32 according to the present invention is shown in fig. 5.
The header field of the IB network packet includes packet length information for the packet, available during the first clock cycle of the packet, and the ICRC field is included within the packet length.
Step 102: and filling bits into the IB network data packet according to the packet length information of the data packet, so that the packet length of the filled data packet in each clock period is equal to the single-period data bit width.
The on-chip CRC32 hardware calculation circuit only exemplifies one set of 32DW check circuits, so that calculation data of each clock cycle needs to be spliced into 32DW, the spliced data is 32' h9D0AD96D, and a splicing schematic diagram is shown in FIG. 6.
For a short packet with a single clock period, the calculation formula of the number x of the 32' h9D0AD96D complementary bits at the front part of the packet head is as follows: x=32- (pktlen-1), concatenating the data packets into 32dw, pktlen being the packet length of the data packet, as shown in fig. 6 at datapkt.
For a long packet crossing a clock period, the number x of the complementary bits 32' h9D0AD96D at the front part of the packet head has the following calculation formula: x=32- (pktlen-1)% 32, splice the first clock cycle data into 32DW,% is the remainder operator, and splice the remaining xDW data of the first clock cycle and the partial data before the second clock cycle into 32DW, and splice the data of the remaining clock cycles in the same manner, as shown in fig. 6 as datapkt and datapkt.
Step 103: and performing CRC check calculation on the IB network data packet after bit filling.
After the splicing step, the data of each clock period are spliced into 32DW, so that the CRC32 check of all packet length data packets can be completed by only one set of CRC32 calculation circuit module for the spliced data. Specifically, the CRC code value calculated by the current circuit is compared with the CRC code value in the IB network data packet, if the CRC code value is consistent with the IB network data packet, the CRC check is passed, and otherwise, the CRC check is not passed.
In another embodiment, the process flow of the IB network packet CRC16 of the present invention is shown in fig. 7, taking a single cycle data bit width of 32DW as an example.
The VCRC check of the IB network data packet comprises all fields (including ICRC fields) of the packet length, and by adopting a CRC16 algorithm, only one set of CRC16 hardware calculation circuit with the data bit width of 32DW needs to be instantiated in a chip, similar to the calculation method of CRC32, calculation data of each clock cycle needs to be spliced into 32DW, the spliced data is 32' h71987198, and the splicing schematic diagram is shown in fig. 7.
For a short packet with a single clock period, the calculation formula of the number y of the 32' h 719987198 of the complementary bits at the front part of the packet head is as follows: y=32-pktlen, concatenating the packets into 32DW, as shown by datapkt0 in fig. 8.
For a long packet crossing a clock period, the calculation formula of the number y of the complementary bits 32' h 719987198 at the front part of the packet head is as follows: y=32-pktlen%, and the data of the first clock cycle is spliced into 32DW, and the remaining yDW data of the first clock cycle and the partial data before the second clock cycle are spliced into 32DW, and the data of the remaining clock cycles are spliced in the same manner, as shown in datapkt1 and datapkt in fig. 8.
After the splicing step, the data of each clock period are spliced into 32DW, so that the CRC16 check of all packet length data packets can be completed by only one set of CRC16 calculation circuit module for the spliced data.
The two embodiments above illustrate the calculation method of the CRC32 or CRC16 IB network data packet according to the invention, taking a single period data bit width of 32DW as an example. Furthermore, those skilled in the art will appreciate that the method is applicable to other data bit wide data stream scenarios. For data streams with different data bit widths, the data splice bit width of each cycle is adjusted according to the maximum data bit width of a single cycle, and the on-chip hardware instantiates a CRC hardware circuit with the maximum data bit width.
Compared with the prior art, the hardware implementation method for calculating the CRC of the IB network data packet is more suitable for a straight-through data forwarding mode, the CRC check result can be consistent with the data flow time sequence, the hardware implementation method is also suitable for a data storage forwarding mode, and the design scheme can be simplified; for the transmission of the IB network data packet with the single-port high data bit width, only one set of CRC calculation circuit is needed in the chip, the difference of packet lengths of the IB network data packet is compatible, the chip is more friendly to physical realization, the CRC hardware circuit resources in the chip are reduced, and the risks of winding congestion, timing sequence convergence and the like of the design of the rear end of the chip are reduced. In addition, the method has lower power consumption and is beneficial to the improvement of the performance of chip products.
Accordingly, the present invention provides in a second aspect a circuit for performing a CRC calculation for an IB network packet, comprising:
The packet analysis unit is used for acquiring the packet header field of the IB network data packet and analyzing the packet length information in the packet header field;
The bit filling unit is used for filling bits into the IB network data packet according to the packet length information of the data packet so that the packet length of the data packet after bit filling in each clock period is equal to the single-period data bit width;
and the checking unit is used for performing CRC check calculation on the IB network data packet after bit filling.
The above circuit may be implemented by a hardware implementation method for calculating a CRC of an IB network packet provided by the embodiment of the first aspect, and specific implementation manners may be referred to the description in the embodiment of the first aspect, which is not repeated herein.
It is understood that the circuit structures, names and parameters described in the above embodiments are only examples. Those skilled in the art may also make and adjust the structural features of the above embodiments as desired without limiting the inventive concept to the specific details of the examples described above.
While the invention has been described in detail with reference to the foregoing embodiments, it will be appreciated by those skilled in the art that variations may be made in the techniques described in the foregoing embodiments, or equivalents may be substituted for elements thereof; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A hardware implementation method for calculating a CRC of an IB network packet, comprising:
acquiring a packet header field of an IB network data packet, and analyzing packet length information in the packet header field;
filling bits into the IB network data packet according to the packet length information of the data packet, so that the packet length of the filled data packet in each clock period is equal to the single-period data bit width;
And performing CRC check calculation on the IB network data packet after bit filling.
2. The hardware implementation method of IB network packet CRC calculation according to claim 1, wherein said CRC calculation is a CRC32 calculation, said supplementing said IB network packet according to packet length information of the packet, further comprising:
When the single-period data bit width is 32 double words, for a data packet with a single clock period, supplementing x 32' h9D0AD96D bits in the front of a packet head, and splicing the data packet into 32 double words, wherein:
x＝32-(pktlen-1)，
pktlen is the packet length of the data packet.
3. The hardware implemented method of IB network packet CRC calculation of claim 2, further comprising:
For a packet spanning multiple clock cycles, x 32' h9d0ad96d bits are appended in front of the header, the first clock cycle data is concatenated into 32 doublewords, starting with the first clock cycle, the remaining x doublewords of the current clock cycle data are concatenated with the next clock cycle front part data into 32 doublewords, until all clock cycles are concatenated into 32 doublewords, wherein:
x＝32-(pktlen-1)％32。
4. the hardware implementation method of IB network packet CRC calculation according to claim 1, wherein said CRC calculation is a CRC16 calculation, said supplementing said IB network packet according to packet length information of the packet, further comprising:
When the single-period data bit width is 32 double words, for a data packet with a single clock period, y 32' h 719987198 are complemented at the front part of the packet head, and the data packet is spliced into 32 double words, wherein:
y＝32-pktlen，
pktlen is the packet length of the data packet.
5. The hardware implemented method of IB network packet CRC calculation of claim 4, further comprising:
For a packet spanning multiple clock cycles, y 32' h 719987198 are appended at the front of the header, the first clock cycle data is concatenated into 32 doublewords, starting from the first clock cycle, the remaining y doublewords of data for the current clock cycle are concatenated with the next clock cycle front part data into 32 doublewords, until all clock cycles are concatenated into 32 doublewords, where:
y＝32-pktlen％32。
6. a circuit for performing a CRC calculation on an IB network packet, comprising:
The packet analysis unit is used for acquiring the packet header field of the IB network data packet and analyzing the packet length information in the packet header field;
The bit filling unit is used for filling bits into the IB network data packet according to the packet length information of the data packet so that the packet length of the data packet after bit filling in each clock period is equal to the single-period data bit width;
and the checking unit is used for performing CRC check calculation on the IB network data packet after bit filling.
7. The circuit for performing IB network packet CRC calculation as claimed in claim 6, wherein said CRC check calculation is a CRC32 check, and said bit-filling unit is further configured to:
When the single-period data bit width is 32 double words, for a data packet with a single clock period, supplementing x 32' h9D0AD96D bits in the front of a packet head, and splicing the data packet into 32 double words, wherein:
x＝32-(pktlen-1)，
pktlen is the packet length of the data packet.
8. The circuit for performing IB network packet CRC calculation as claimed in claim 7, wherein said bit-filling unit is further configured to:
For a packet spanning multiple clock cycles, x 32' h9d0ad96d bits are appended in front of the header, the first clock cycle data is concatenated into 32 doublewords, starting with the first clock cycle, the remaining x doublewords of the current clock cycle data are concatenated with the next clock cycle front part data into 32 doublewords, until all clock cycles are concatenated into 32 doublewords, wherein:
x＝32-(pktlen-1)％32。
9. The circuit for performing IB network packet CRC calculation as claimed in claim 6, wherein said CRC check calculation is a CRC16 check, and said bit-filling unit is further configured to:
When the single-period data bit width is 32 double words, for a data packet with a single clock period, y 32' h 719987198 are complemented at the front part of the packet head, and the data packet is spliced into 32 double words, wherein:
y＝32-pktlen，
pktlen is the packet length of the data packet.
10. The circuit for performing IB network packet CRC calculation as claimed in claim 9, wherein said bit-filling unit is further configured to:
For a packet spanning multiple clock cycles, y 32' h 719987198 are appended at the front of the header, the first clock cycle data is concatenated into 32 doublewords, starting from the first clock cycle, the remaining y doublewords of data for the current clock cycle are concatenated with the next clock cycle front part data into 32 doublewords, until all clock cycles are concatenated into 32 doublewords, where:
y＝32-pktlen％32。
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